machsystm.h revision 12908:80a39220b451 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25#ifndef _SYS_MACHSYSTM_H
26#define	_SYS_MACHSYSTM_H
27
28/*
29 * Numerous platform-dependent interfaces that don't seem to belong
30 * in any other header file.
31 *
32 * This file should not be included by code that purports to be
33 * platform-independent.
34 */
35
36#ifndef _ASM
37#include <sys/types.h>
38#include <sys/scb.h>
39#include <sys/varargs.h>
40#include <sys/machparam.h>
41#include <sys/thread.h>
42#include <vm/seg_enum.h>
43#include <sys/processor.h>
44#include <sys/sunddi.h>
45#include <sys/memlist.h>
46#endif /* _ASM */
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#ifdef _KERNEL
53
54#ifndef _ASM
55/*
56 * The following enum types determine how interrupts are distributed
57 * on a sun4u system.
58 */
59enum intr_policies {
60	/*
61	 * Target interrupt at the CPU running the add_intrspec
62	 * thread. Also used to target all interrupts at the panicing
63	 * CPU.
64	 */
65	INTR_CURRENT_CPU = 0,
66
67	/*
68	 * Target all interrupts at the boot cpu
69	 */
70	INTR_BOOT_CPU,
71
72	/*
73	 * Flat distribution of all interrupts
74	 */
75	INTR_FLAT_DIST,
76
77	/*
78	 * Weighted distribution of all interrupts
79	 */
80	INTR_WEIGHTED_DIST
81};
82
83
84/*
85 * Structure that defines the interrupt distribution list. It contains
86 * enough info about the interrupt so that it can callback the parent
87 * nexus driver and retarget the interrupt to a different CPU.
88 */
89struct intr_dist {
90	struct intr_dist *next;	/* link to next in list */
91	void (*func)(void *);	/* Callback function */
92	void *arg;		/* Nexus parent callback arg 1 */
93};
94
95/*
96 * Miscellaneous cpu_state changes
97 */
98extern void power_down(const char *);
99extern void do_shutdown(void);
100
101/*
102 * Number of seconds until power is shut off
103 */
104extern int thermal_powerdown_delay;
105
106
107/*
108 * prom-related
109 */
110extern int obpdebug;
111extern int forthdebug_supported;
112extern uint_t tba_taken_over;
113extern void forthdebug_init(void);
114extern void init_vx_handler(void);
115extern void kern_preprom(void);
116extern void kern_postprom(void);
117
118/*
119 * externally (debugger or prom) initiated panic
120 */
121extern struct regs sync_reg_buf;
122extern uint64_t sync_tt;
123extern void sync_handler(void);
124
125/*
126 * Trap-related
127 */
128struct regs;
129extern void trap(struct regs *rp, caddr_t addr, uint32_t type,
130    uint32_t mmu_fsr);
131extern void *get_tba(void);
132extern void *set_tba(void *);
133extern caddr_t set_trap_table(void);
134extern struct scb trap_table;
135
136struct panic_trap_info {
137	struct regs *trap_regs;
138	uint_t	trap_type;
139	caddr_t trap_addr;
140	uint_t	trap_mmu_fsr;
141};
142
143/*
144 * misc. primitives
145 */
146#define	PROM_CFGHDL_TO_CPUID(x)	 (x  & ~(0xful << 28))
147
148extern void debug_flush_windows(void);
149extern void flush_windows(void);
150extern int getprocessorid(void);
151extern void reestablish_curthread(void);
152
153extern void stphys(uint64_t physaddr, int value);
154extern int ldphys(uint64_t physaddr);
155extern void stdphys(uint64_t physaddr, uint64_t value);
156extern uint64_t lddphys(uint64_t physaddr);
157
158extern void stphysio(u_longlong_t physaddr, uint_t value);
159extern uint_t ldphysio(u_longlong_t physaddr);
160extern void sthphysio(u_longlong_t physaddr, ushort_t value);
161extern ushort_t ldhphysio(u_longlong_t physaddr);
162extern void stbphysio(u_longlong_t physaddr, uchar_t value);
163extern uchar_t ldbphysio(u_longlong_t physaddr);
164extern void stdphysio(u_longlong_t physaddr, u_longlong_t value);
165extern u_longlong_t lddphysio(u_longlong_t physaddr);
166
167extern int pf_is_dmacapable(pfn_t);
168
169extern int dip_to_cpu_id(dev_info_t *dip, processorid_t *cpu_id);
170
171extern void set_cmp_error_steering(void);
172
173/*
174 * SPARCv9 %ver register and field definitions
175 */
176
177#define	ULTRA_VER_MANUF(x)	((x) >> 48)
178#define	ULTRA_VER_IMPL(x)	(((x) >> 32) & 0xFFFF)
179#define	ULTRA_VER_MASK(x)	(((x) >> 24) & 0xFF)
180
181extern uint64_t ultra_getver(void);
182
183/*
184 * bootup-time
185 */
186extern void segnf_init(void);
187extern void kern_setup1(void);
188extern void startup(void);
189extern void post_startup(void);
190extern void install_va_to_tte(void);
191extern void setwstate(uint_t);
192extern void create_va_to_tte(void);
193extern int memscrub_init(void);
194
195extern void kcpc_hw_init(void);
196extern void kcpc_hw_startup_cpu(ushort_t);
197extern int kcpc_hw_load_pcbe(void);
198
199/*
200 * Interrupts
201 */
202struct cpu;
203extern struct cpu cpu0;
204extern struct scb *set_tbr(struct scb *);
205
206extern uint_t disable_vec_intr(void);
207extern void enable_vec_intr(uint_t);
208extern void setintrenable(int);
209
210extern void intr_dist_add(void (*f)(void *), void *);
211extern void intr_dist_rem(void (*f)(void *), void *);
212extern void intr_dist_add_weighted(void (*f)(void *, int32_t, int32_t), void *);
213extern void intr_dist_rem_weighted(void (*f)(void *, int32_t, int32_t), void *);
214
215extern uint32_t intr_dist_cpuid(void);
216extern uint32_t intr_dist_mycpuid(void);
217
218void intr_dist_cpuid_add_device_weight(uint32_t cpuid, dev_info_t *dip,
219		int32_t weight);
220void intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip);
221
222extern void intr_redist_all_cpus(void);
223extern void intr_redist_all_cpus_shutdown(void);
224
225extern void send_dirint(int, int);
226extern void setsoftint(uint64_t);
227extern void setsoftint_tl1(uint64_t, uint64_t);
228extern void siron(void);
229extern void sir_on(int);
230extern void intr_enqueue_req(uint_t pil, uint64_t inum);
231extern void intr_dequeue_req(uint_t pil, uint64_t inum);
232extern void wr_clr_softint(uint_t);
233
234/*
235 * Time- and %tick-related
236 */
237extern hrtime_t rdtick(void);
238extern void tick_write_delta(uint64_t);
239extern void tickcmpr_set(uint64_t);
240extern void tickcmpr_reset(void);
241extern void tickcmpr_disable(void);
242extern int tickcmpr_disabled(void);
243extern uint64_t cbe_level14_inum;
244
245/*
246 * contiguous memory
247 */
248extern void *contig_mem_alloc(size_t);
249extern void *contig_mem_alloc_align(size_t, size_t);
250extern void contig_mem_free(void *, size_t);
251
252/*
253 * Caches
254 */
255extern int vac;
256extern int cache;
257extern int use_mp;
258extern uint_t vac_mask;
259extern uint64_t ecache_flushaddr;
260extern int ecache_alignsize;	/* Maximum ecache linesize for struct align */
261extern int ecache_setsize;	/* Maximum ecache setsize possible */
262extern int cpu_setsize;		/* Maximum ecache setsize of configured cpus */
263
264/*
265 * VM
266 */
267extern int do_pg_coloring;
268extern int use_page_coloring;
269extern uint_t vac_colors_mask;
270
271extern caddr_t get_mmfsa_scratchpad(void);
272extern void set_mmfsa_scratchpad(caddr_t);
273extern int ndata_alloc_mmfsa(struct memlist *);
274extern int ndata_alloc_page_freelists(struct memlist *, int);
275extern int ndata_alloc_dmv(struct memlist *);
276extern int ndata_alloc_tsbs(struct memlist *, pgcnt_t);
277extern int ndata_alloc_hat(struct memlist *);
278extern int ndata_alloc_kpm(struct memlist *, pgcnt_t);
279extern int ndata_alloc_page_mutexs(struct memlist *ndata);
280
281extern size_t calc_pp_sz(pgcnt_t);
282extern size_t calc_kpmpp_sz(pgcnt_t);
283extern size_t calc_hmehash_sz(pgcnt_t);
284extern size_t calc_pagehash_sz(pgcnt_t);
285extern size_t calc_free_pagelist_sz(void);
286
287extern caddr_t alloc_hmehash(caddr_t);
288extern caddr_t alloc_page_freelists(caddr_t);
289
290extern size_t page_ctrs_sz(void);
291extern caddr_t page_ctrs_alloc(caddr_t);
292extern void page_freelist_coalesce_all(int);
293extern void ppmapinit(void);
294extern void hwblkpagecopy(const void *, void *);
295extern void hw_pa_bcopy32(uint64_t, uint64_t);
296
297extern int pp_slots;
298extern int pp_consistent_coloring;
299
300/*
301 * ppcopy/hwblkpagecopy interaction.  See ppage.c.
302 */
303#define	PPAGE_STORE_VCOLORING	0x1 /* use vcolors to maintain consistency */
304#define	PPAGE_LOAD_VCOLORING	0x2 /* use vcolors to maintain consistency */
305#define	PPAGE_STORES_POLLUTE	0x4 /* stores pollute VAC */
306#define	PPAGE_LOADS_POLLUTE	0x8 /* loads pollute VAC */
307
308/*
309 * VIS-accelerated copy/zero
310 */
311extern int use_hw_bcopy;
312extern uint_t hw_copy_limit_1;
313extern uint_t hw_copy_limit_2;
314extern uint_t hw_copy_limit_4;
315extern uint_t hw_copy_limit_8;
316extern int use_hw_bzero;
317
318#ifdef CHEETAH
319#define	VIS_COPY_THRESHOLD 256
320#else
321#define	VIS_COPY_THRESHOLD 900
322#endif
323
324/*
325 * MP
326 */
327extern void idle_other_cpus(void);
328extern void resume_other_cpus(void);
329extern void stop_other_cpus(void);
330extern void idle_stop_xcall(void);
331extern void set_idle_cpu(int);
332extern void unset_idle_cpu(int);
333extern void mp_cpu_quiesce(struct cpu *);
334extern int stopcpu_bycpuid(int);
335
336/*
337 * Panic at TL > 0
338 */
339extern uint64_t cpu_pa[];
340extern void ptl1_init_cpu(struct cpu *);
341
342/*
343 * Constants which define the "hole" in the 64-bit sfmmu address space.
344 * These are set to specific values by the CPU module code.
345 */
346extern caddr_t	hole_start, hole_end;
347
348/* kpm mapping window */
349extern size_t	kpm_size;
350extern uchar_t	kpm_size_shift;
351extern caddr_t	kpm_vbase;
352
353#define	INVALID_VADDR(a)	(((a) >= hole_start && (a) < hole_end))
354#define	VA_ADDRESS_SPACE_BITS		64
355#define	RA_ADDRESS_SPACE_BITS		56
356#define	MAX_REAL_ADDRESS		(1ull << RA_ADDRESS_SPACE_BITS)
357#define	DEFAULT_VA_ADDRESS_SPACE_BITS	48	/* def. Niagara (broken MD) */
358#define	PAGESIZE_MASK_BITS		16
359#define	MAX_PAGESIZE_MASK		((1<<PAGESIZE_MASK_BITS) - 1)
360
361extern void adjust_hw_copy_limits(int);
362
363struct kdi;
364
365void	cpu_kdi_init(struct kdi *);
366
367/*
368 * flush instruction and data caches
369 */
370void	kdi_flush_caches(void);
371
372struct async_flt;
373
374/*
375 * take pending fp traps if fpq present
376 * this function is also defined in fpusystm.h
377 */
378void	syncfpu(void);
379
380void	cpu_faulted_enter(struct cpu *);
381void	cpu_faulted_exit(struct cpu *);
382
383int	cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar,
384	    char *buf, int buflen, int *lenp);
385int	cpu_get_mem_info(uint64_t synd, uint64_t afar,
386	    uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep,
387	    int *segsp, int *banksp, int *mcidp);
388size_t	cpu_get_name_bufsize();
389
390/*
391 * ecache scrub operations
392 */
393void cpu_init_cache_scrub(void);
394
395/*
396 * clock/tick register operations
397 */
398void	cpu_init_tick_freq(void);
399
400/*
401 * stick synchronization
402 */
403void	sticksync_slave(void);
404void	sticksync_master(void);
405
406#endif /* _ASM */
407
408/*
409 * Actions for set_error_enable_tl1
410 */
411#define	EER_SET_ABSOLUTE	0x0
412#define	EER_SET_SETBITS		0x1
413#define	EER_SET_CLRBITS		0x2
414
415/*
416 * HVDUMP_SIZE_MAX set as 64k due to limitiation by intrq_alloc()
417 */
418
419#define	HVDUMP_SIZE_MAX		0x10000
420#define	HVDUMP_SIZE_DEFAULT	0x8000
421
422/*
423 * HV TOD service retry in usecs
424 */
425
426#define	HV_TOD_RETRY_THRESH	100
427#define	HV_TOD_WAIT_USEC	5
428
429/*
430 * Interrupt Queues and Error Queues
431 */
432
433#define	INTR_CPU_Q	0x3c
434#define	INTR_DEV_Q	0x3d
435#define	CPU_RQ		0x3e
436#define	CPU_NRQ		0x3f
437#define	DEFAULT_CPU_Q_ENTRIES	0x100
438#define	DEFAULT_DEV_Q_ENTRIES	0x100
439#define	INTR_REPORT_SIZE	64
440
441#ifndef	_ASM
442extern uint64_t cpu_q_entries;
443extern uint64_t dev_q_entries;
444extern uint64_t cpu_rq_entries;
445extern uint64_t cpu_nrq_entries;
446extern uint64_t ncpu_guest_max;
447#endif /* _ASM */
448
449#endif /* _KERNEL */
450
451#ifdef __cplusplus
452}
453#endif
454
455#endif	/* _SYS_MACHSYSTM_H */
456