hypervisor_api.h revision 459:a7351c54713f
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _SYS_HYPERVISOR_API_H 28#define _SYS_HYPERVISOR_API_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32/* 33 * sun4v Hypervisor API 34 * 35 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 36 * io-api.txt version 1.11 dated 10/19/2004 37 */ 38 39#ifdef __cplusplus 40extern "C" { 41#endif 42 43/* 44 * Trap types 45 */ 46#define FAST_TRAP 0x80 /* Function # in %o5 */ 47#define CPU_TICK_NPT 0x81 48#define CPU_STICK_NPT 0x82 49#define MMU_MAP_ADDR 0x83 50#define MMU_UNMAP_ADDR 0x84 51 52/* 53 * Error returns in %o0. 54 * (Additional result is returned in %o1.) 55 */ 56#define H_EOK 0 /* Successful return */ 57#define H_ENOCPU 1 /* Invalid CPU id */ 58#define H_ENORADDR 2 /* Invalid real address */ 59#define H_ENOINTR 3 /* Invalid interrupt id */ 60#define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 61#define H_EBADTSB 5 /* Invalid TSB description */ 62#define H_EINVAL 6 /* Invalid argument */ 63#define H_EBADTRAP 7 /* Invalid function number */ 64#define H_EBADALIGN 8 /* Invalid address alignment */ 65#define H_EWOULDBLOCK 9 /* Cannot complete operation */ 66 /* without blocking */ 67#define H_ENOACCESS 10 /* No access to resource */ 68#define H_EIO 11 /* I/O error */ 69#define H_ECPUERROR 12 /* CPU is in error state */ 70#define H_ENOTSUPPORTED 13 /* Function not supported */ 71#define H_ENOMAP 14 /* Mapping is not valid, */ 72 /* no translation exists */ 73 74#define H_BREAK -1 /* Console Break */ 75#define H_HUP -2 /* Console Break */ 76/* 77 * Function numbers for FAST_TRAP. 78 */ 79#define HV_MACH_EXIT 0x00 80#define HV_MACH_DESC 0x01 81#define HV_CPU_YIELD 0x12 82#define CPU_QCONF 0x14 83#define HV_CPU_STATE 0x17 84#define MMU_TSB_CTX0 0x20 85#define MMU_TSB_CTXNON0 0x21 86#define MMU_DEMAP_PAGE 0x22 87#define MMU_DEMAP_CTX 0x23 88#define MMU_DEMAP_ALL 0x24 89#define MAP_PERM_ADDR 0x25 90#define MMU_SET_INFOPTR 0x26 91#define UNMAP_PERM_ADDR 0x28 92#define HV_MEM_SCRUB 0x31 93#define HV_MEM_SYNC 0x32 94#define HV_INTR_SEND 0x42 95#define TOD_GET 0x50 96#define TOD_SET 0x51 97#define CONS_READ 0x60 98#define CONS_WRITE 0x61 99 100#define SVC_SEND 0x80 101#define SVC_RECV 0x81 102#define SVC_GETSTATUS 0x82 103#define SVC_SETSTATUS 0x83 104#define SVC_CLRSTATUS 0x84 105 106#define TTRACE_BUF_CONF 0x90 107#define TTRACE_BUF_INFO 0x91 108#define TTRACE_ENABLE 0x92 109#define TTRACE_FREEZE 0x93 110 111#define DUMP_BUF_UPDATE 0x94 112 113#define HVIO_INTR_DEVINO2SYSINO 0xa0 114#define HVIO_INTR_GETVALID 0xa1 115#define HVIO_INTR_SETVALID 0xa2 116#define HVIO_INTR_GETSTATE 0xa3 117#define HVIO_INTR_SETSTATE 0xa4 118#define HVIO_INTR_GETTARGET 0xa5 119#define HVIO_INTR_SETTARGET 0xa6 120 121#define HVIO_IOMMU_MAP 0xb0 122#define HVIO_IOMMU_DEMAP 0xb1 123#define HVIO_IOMMU_GETMAP 0xb2 124#define HVIO_IOMMU_GETBYPASS 0xb3 125 126#define HVIO_CONFIG_GET 0xb4 127#define HVIO_CONFIG_PUT 0xb5 128 129#define HVIO_PEEK 0xb6 130#define HVIO_POKE 0xb7 131 132#define HVIO_DMA_SYNC 0xb8 133 134#define HVIO_MSIQ_CONF 0xc0 135#define HVIO_MSIQ_INFO 0xc1 136#define HVIO_MSIQ_GETVALID 0xc2 137#define HVIO_MSIQ_SETVALID 0xc3 138#define HVIO_MSIQ_GETSTATE 0xc4 139#define HVIO_MSIQ_SETSTATE 0xc5 140#define HVIO_MSIQ_GETHEAD 0xc6 141#define HVIO_MSIQ_SETHEAD 0xc7 142#define HVIO_MSIQ_GETTAIL 0xc8 143 144#define HVIO_MSI_GETVALID 0xc9 145#define HVIO_MSI_SETVALID 0xca 146#define HVIO_MSI_GETMSIQ 0xcb 147#define HVIO_MSI_SETMSIQ 0xcc 148#define HVIO_MSI_GETSTATE 0xcd 149#define HVIO_MSI_SETSTATE 0xce 150 151#define HVIO_MSG_GETMSIQ 0xd0 152#define HVIO_MSG_SETMSIQ 0xd1 153#define HVIO_MSG_GETVALID 0xd2 154#define HVIO_MSG_SETVALID 0xd3 155 156#ifdef SET_MMU_STATS 157#define MMU_STAT_AREA 0xfc 158#endif /* SET_MMU_STATS */ 159 160#define HV_NCS_REQUEST 0x110 161 162/* 163 * Bits for MMU functions flags argument: 164 * arg3 of MMU_MAP_ADDR 165 * arg3 of MMU_DEMAP_CTX 166 * arg2 of MMU_DEMAP_ALL 167 */ 168#define MAP_DTLB 0x1 169#define MAP_ITLB 0x2 170 171 172/* 173 * Interrupt state manipulation definitions. 174 */ 175 176#define HV_INTR_IDLE_STATE 0 177#define HV_INTR_RECEIVED_STATE 1 178#define HV_INTR_DELIVERED_STATE 2 179 180#define HV_INTR_NOTVALID 0 181#define HV_INTR_VALID 1 182 183#ifndef _ASM 184 185/* 186 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 187 */ 188typedef struct hv_tsb_info { 189 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 190 uint16_t hvtsb_assoc; /* TSB associativity */ 191 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 192 uint32_t hvtsb_ctx_index; /* context reg index */ 193 uint32_t hvtsb_pgszs; /* sizes in use */ 194 uint64_t hvtsb_pa; /* real address of TSB base */ 195 uint64_t hvtsb_rsvd; /* reserved */ 196} hv_tsb_info_t; 197 198#define HVTSB_SHARE_INDEX ((uint32_t)-1) 199 200#ifdef SET_MMU_STATS 201#ifndef TTE4V_NPGSZ 202#define TTE4V_NPGSZ 8 203#endif /* TTE4V_NPGSZ */ 204/* 205 * MMU statistics structure for MMU_STAT_AREA 206 */ 207struct mmu_stat_one { 208 uint64_t hit_ctx0[TTE4V_NPGSZ]; 209 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 210 uint64_t tsb_miss; 211 uint64_t tlb_miss; /* miss, no TSB set */ 212 uint64_t map_ctx0[TTE4V_NPGSZ]; 213 uint64_t map_ctxn0[TTE4V_NPGSZ]; 214}; 215 216struct mmu_stat { 217 struct mmu_stat_one immu_stat; 218 struct mmu_stat_one dmmu_stat; 219 uint64_t set_ctx0; 220 uint64_t set_ctxn0; 221}; 222#endif /* SET_MMU_STATS */ 223 224#endif /* _ASM */ 225 226/* 227 * CPU States 228 */ 229#define CPU_STATE_INVALID 0x0 230#define CPU_STATE_IDLE 0x1 /* cpu not started */ 231#define CPU_STATE_GUEST 0x2 /* cpu running guest code */ 232#define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 233#define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 234 235/* 236 * MMU fault status area 237 */ 238 239#define MMFSA_TYPE_ 0x00 /* fault type */ 240#define MMFSA_ADDR_ 0x08 /* fault address */ 241#define MMFSA_CTX_ 0x10 /* fault context */ 242 243#define MMFSA_I_ 0x00 /* start of fields for I */ 244#define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 245#define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 246#define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 247 248#define MMFSA_D_ 0x40 /* start of fields for D */ 249#define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 250#define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 251#define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 252 253#define MMFSA_F_FMISS 1 /* fast miss */ 254#define MMFSA_F_FPROT 2 /* fast protection */ 255#define MMFSA_F_MISS 3 /* mmu miss */ 256#define MMFSA_F_INVRA 4 /* invalid RA */ 257#define MMFSA_F_PRIV 5 /* privilege violation */ 258#define MMFSA_F_PROT 6 /* protection violation */ 259#define MMFSA_F_NFO 7 /* NFO access */ 260#define MMFSA_F_SOPG 8 /* so page */ 261#define MMFSA_F_INVVA 9 /* invalid VA */ 262#define MMFSA_F_INVASI 10 /* invalid ASI */ 263#define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 264#define MMFSA_F_PRVACT 12 /* privileged action */ 265#define MMFSA_F_WPT 13 /* watchpoint hit */ 266#define MMFSA_F_UNALIGN 14 /* unaligned access */ 267#define MMFSA_F_INVPGSZ 15 /* invalid page size */ 268 269#define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 270 271/* 272 * MMU fault status - MMFSA_IFS and MMFSA_DFS 273 */ 274#define MMFS_FV 0x00000001 275#define MMFS_OW 0x00000002 276#define MMFS_W 0x00000004 277#define MMFS_PR 0x00000008 278#define MMFS_CT 0x00000030 279#define MMFS_E 0x00000040 280#define MMFS_FT 0x00003f80 281#define MMFS_ME 0x00004000 282#define MMFS_TM 0x00008000 283#define MMFS_ASI 0x00ff0000 284#define MMFS_NF 0x01000000 285 286/* 287 * DMA sync parameter definitions 288 */ 289#define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 290#define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 291 292#ifndef _ASM 293 294extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 295extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 296extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 297extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 298#ifdef SET_MMU_STATS 299extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 300#endif /* SET_MMU_STATS */ 301 302extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 303extern uint64_t hv_cpu_yield(); 304 305extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 306extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 307 uint64_t *scrubbed_len); 308extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 309 uint64_t *flushed_len); 310 311extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 312 uint64_t size, uint64_t *recv_bytes); 313extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 314 uint64_t size, uint64_t *send_bytes); 315extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 316extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 317extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 318 319extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 320 321extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 322extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 323extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 324extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 325extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 326 327extern int64_t hv_cnputchar(uint8_t); 328extern int64_t hv_cngetchar(uint8_t *); 329 330extern uint64_t hv_tod_get(uint64_t *seconds); 331extern uint64_t hv_tod_set(uint64_t); 332 333extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 334 uint64_t *sysino); 335extern uint64_t hvio_intr_getvalid(uint64_t sysino, 336 int *intr_valid_state); 337extern uint64_t hvio_intr_setvalid(uint64_t sysino, 338 int intr_valid_state); 339extern uint64_t hvio_intr_getstate(uint64_t sysino, 340 int *intr_state); 341extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 342extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 343extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 344#endif 345 346#ifdef __cplusplus 347} 348#endif 349 350#endif /* _SYS_HYPERVISOR_API_H */ 351