cmp.c revision 3434:5142e1d7d0bc 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#pragma ident	"%Z%%M%	%I%	%E% SMI"
27
28#include <sys/types.h>
29#include <sys/machsystm.h>
30#include <sys/cmp.h>
31#include <sys/pghw.h>
32
33/*
34 * Note: For now assume the chip ID as 0 for all the cpus until additional
35 * information is available via machine description table
36 */
37
38/*
39 * Returns 1 if cpuid is CMP-capable, 0 otherwise.
40 */
41/*ARGSUSED*/
42int
43cmp_cpu_is_cmp(processorid_t cpuid)
44{
45	return (0);
46}
47
48/*
49 * Indicate that this core (cpuid) resides on the chip indicated by chipid.
50 * Called during boot and DR add.
51 */
52/*ARGSUSED*/
53void
54cmp_add_cpu(chipid_t chipid, processorid_t cpuid)
55{
56}
57
58/*
59 * Indicate that this core (cpuid) is being DR removed.
60 */
61/*ARGSUSED*/
62void
63cmp_delete_cpu(processorid_t cpuid)
64{
65}
66
67/*
68 * Called when cpuid is being onlined or offlined.  If the offlined
69 * processor is CMP-capable then current target of the CMP Error Steering
70 * Register is set to either the lowest numbered on-line sibling core, if
71 * one exists, or else to this core.
72 */
73/*ARGSUSED*/
74void
75cmp_error_resteer(processorid_t cpuid)
76{
77}
78
79/*
80 * Return 0, shortterm workaround until MD table is updated
81 * to provide cpu-chip mapping
82 */
83
84/*ARGSUSED*/
85chipid_t
86cmp_cpu_to_chip(processorid_t cpuid)
87{
88	return (0);
89}
90
91/*ARGSUSED*/
92int
93pg_plat_hw_shared(cpu_t *cp, pghw_type_t hw)
94{
95	switch (hw) {
96	case PGHW_IPIPE:
97		return (1);
98	case PGHW_FPU:
99		return (1);
100	case PGHW_CHIP:
101		return (1);
102	}
103	return (0);
104}
105
106int
107pg_plat_cpus_share(cpu_t *cpu_a, cpu_t *cpu_b, pghw_type_t hw)
108{
109	if (pg_plat_hw_shared(cpu_a, hw) == 0 ||
110	    pg_plat_hw_shared(cpu_b, hw) == 0)
111		return (0);
112
113	return (pg_plat_hw_instance_id(cpu_a, hw) ==
114	    pg_plat_hw_instance_id(cpu_b, hw));
115}
116
117id_t
118pg_plat_hw_instance_id(cpu_t *cpu, pghw_type_t hw)
119{
120	switch (hw) {
121	case PGHW_IPIPE:
122		return (cpu->cpu_m.cpu_ipipe);
123	case PGHW_CHIP:
124		return (cmp_cpu_to_chip(cpu->cpu_id));
125	case PGHW_FPU:
126		return (cpu->cpu_m.cpu_fpu);
127	default:
128		return (-1);
129	}
130}
131
132/*
133 * Order the relevant hw sharing relationships
134 * from least, to greatest physical scope.
135 *
136 * The hierarchy *must* be defined for all hw that
137 * pg_plat_hw_shared() returns non-zero.
138 */
139int
140pg_plat_hw_level(pghw_type_t hw)
141{
142	int i;
143	static pghw_type_t hw_hier[] = {
144		PGHW_IPIPE,
145		PGHW_FPU,
146		PGHW_CHIP,
147		PGHW_NUM_COMPONENTS
148	};
149
150	for (i = 0; hw_hier[i] != PGHW_NUM_COMPONENTS; i++) {
151		if (hw_hier[i] == hw)
152			return (i);
153	}
154	return (-1);
155}
156
157id_t
158pg_plat_get_core_id(cpu_t *cpu)
159{
160	return (cpu->cpu_m.cpu_core);
161}
162
163void
164cmp_set_nosteal_interval(void)
165{
166	nosteal_nsec = 0;
167}
168