hcall.s revision 1991:f29baf5bf770
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37 38#if defined(lint) || defined(__lint) 39 40/*ARGSUSED*/ 41uint64_t 42hv_mach_exit(uint64_t exit_code) 43{ return (0); } 44 45uint64_t 46hv_mach_sir(void) 47{ return (0); } 48 49/*ARGSUSED*/ 50uint64_t 51hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 52{ return (0); } 53 54/*ARGSUSED*/ 55uint64_t 56hv_cpu_stop(uint64_t cpuid) 57{ return (0); } 58 59/*ARGSUSED*/ 60uint64_t 61hv_cpu_set_rtba(uint64_t *rtba) 62{ return (0); } 63 64/*ARGSUSED*/ 65int64_t 66hv_cnputchar(uint8_t ch) 67{ return (0); } 68 69/*ARGSUSED*/ 70int64_t 71hv_cngetchar(uint8_t *ch) 72{ return (0); } 73 74/*ARGSUSED*/ 75uint64_t 76hv_tod_get(uint64_t *seconds) 77{ return (0); } 78 79/*ARGSUSED*/ 80uint64_t 81hv_tod_set(uint64_t seconds) 82{ return (0);} 83 84/*ARGSUSED*/ 85uint64_t 86hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 87{ return (0); } 88 89/*ARGSUSED */ 90uint64_t 91hv_mmu_fault_area_conf(void *raddr) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 102{ return (0); } 103 104/*ARGSUSED*/ 105uint64_t 106hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 107{ return (0); } 108 109#ifdef SET_MMU_STATS 110/*ARGSUSED*/ 111uint64_t 112hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 113{ return (0); } 114#endif /* SET_MMU_STATS */ 115 116/*ARGSUSED*/ 117uint64_t 118hv_cpu_qconf(int queue, uint64_t paddr, int size) 119{ return (0); } 120 121/*ARGSUSED*/ 122uint64_t 123hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 124{ return (0); } 125 126/*ARGSUSED*/ 127uint64_t 128hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 129{ return (0); } 130 131/*ARGSUSED*/ 132uint64_t 133hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_intr_getstate(uint64_t sysino, int *intr_state) 139{ return (0); } 140 141/*ARGSUSED*/ 142uint64_t 143hvio_intr_setstate(uint64_t sysino, int intr_state) 144{ return (0); } 145 146/*ARGSUSED*/ 147uint64_t 148hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 149{ return (0); } 150 151/*ARGSUSED*/ 152uint64_t 153hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 154{ return (0); } 155 156uint64_t 157hv_cpu_yield(void) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 168{ return (0); } 169 170/*ARGSUSED*/ 171uint64_t 172hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 173{ return (0); } 174 175/*ARGSUSED*/ 176uint64_t 177hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 178{ return (0); } 179 180/*ARGSUSED*/ 181uint64_t 182hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 183{ return (0); } 184 185/*ARGSUSED*/ 186uint64_t 187hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 198{ return (0); } 199 200/*ARGSUSED*/ 201uint64_t 202hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 203{ return (0); } 204 205/*ARGSUSED*/ 206uint64_t 207hv_ra2pa(uint64_t ra) 208{ return (0); } 209 210/*ARGSUSED*/ 211uint64_t 212hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 213{ return (0); } 214 215/*ARGSUSED*/ 216uint64_t 217hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 218{ return (0); } 219 220/*ARGSUSED*/ 221uint64_t 222hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hv_ldc_tx_get_state(uint64_t channel, 228 uint64_t *headp, uint64_t *tailp, uint64_t *state) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 234{ return (0); } 235 236/*ARGSUSED*/ 237uint64_t 238hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 239{ return (0); } 240 241/*ARGSUSED*/ 242uint64_t 243hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 244{ return (0); } 245 246/*ARGSUSED*/ 247uint64_t 248hv_ldc_rx_get_state(uint64_t channel, 249 uint64_t *headp, uint64_t *tailp, uint64_t *state) 250{ return (0); } 251 252/*ARGSUSED*/ 253uint64_t 254hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 255{ return (0); } 256 257/*ARGSUSED*/ 258uint64_t 259hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 260{ return (0); } 261 262/*ARGSUSED*/ 263uint64_t 264hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 270 uint64_t raddr, uint64_t length, uint64_t *lengthp) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 276{ return (0); } 277 278/*ARGSUSED*/ 279uint64_t 280hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 281{ return (0); } 282 283/*ARGSUSED*/ 284uint64_t 285hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 286{ return (0); } 287 288/*ARGSUSED*/ 289uint64_t 290hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 291{ return (0); } 292 293/*ARGSUSED*/ 294uint64_t 295hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 296{ return (0); } 297 298/*ARGSUSED*/ 299uint64_t 300hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 301{ return (0); } 302 303/*ARGSUSED*/ 304uint64_t 305hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 306{ return (0); } 307 308/*ARGSUSED*/ 309uint64_t 310hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 321 uint64_t *supported_minor) 322{ return (0); } 323 324#else /* lint || __lint */ 325 326 /* 327 * int hv_mach_exit(uint64_t exit_code) 328 */ 329 ENTRY(hv_mach_exit) 330 mov HV_MACH_EXIT, %o5 331 ta FAST_TRAP 332 retl 333 nop 334 SET_SIZE(hv_mach_exit) 335 336 /* 337 * uint64_t hv_mach_sir(void) 338 */ 339 ENTRY(hv_mach_sir) 340 mov HV_MACH_SIR, %o5 341 ta FAST_TRAP 342 retl 343 nop 344 SET_SIZE(hv_mach_sir) 345 346 /* 347 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 348 * uint64_t arg) 349 */ 350 ENTRY(hv_cpu_start) 351 mov HV_CPU_START, %o5 352 ta FAST_TRAP 353 retl 354 nop 355 SET_SIZE(hv_cpu_start) 356 357 /* 358 * hv_cpu_stop(uint64_t cpuid) 359 */ 360 ENTRY(hv_cpu_stop) 361 mov HV_CPU_STOP, %o5 362 ta FAST_TRAP 363 retl 364 nop 365 SET_SIZE(hv_cpu_stop) 366 367 /* 368 * hv_cpu_set_rtba(uint64_t *rtba) 369 */ 370 ENTRY(hv_cpu_set_rtba) 371 mov %o0, %o2 372 ldx [%o2], %o0 373 mov HV_CPU_SET_RTBA, %o5 374 ta FAST_TRAP 375 stx %o1, [%o2] 376 retl 377 nop 378 SET_SIZE(hv_cpu_set_rtba) 379 380 /* 381 * int64_t hv_cnputchar(uint8_t ch) 382 */ 383 ENTRY(hv_cnputchar) 384 mov CONS_PUTCHAR, %o5 385 ta FAST_TRAP 386 retl 387 nop 388 SET_SIZE(hv_cnputchar) 389 390 /* 391 * int64_t hv_cngetchar(uint8_t *ch) 392 */ 393 ENTRY(hv_cngetchar) 394 mov %o0, %o2 395 mov CONS_GETCHAR, %o5 396 ta FAST_TRAP 397 brnz,a %o0, 1f ! failure, just return error 398 nop 399 400 cmp %o1, H_BREAK 401 be 1f 402 mov %o1, %o0 403 404 cmp %o1, H_HUP 405 be 1f 406 mov %o1, %o0 407 408 stb %o1, [%o2] ! success, save character and return 0 409 mov 0, %o0 4101: 411 retl 412 nop 413 SET_SIZE(hv_cngetchar) 414 415 ENTRY(hv_tod_get) 416 mov %o0, %o4 417 mov TOD_GET, %o5 418 ta FAST_TRAP 419 retl 420 stx %o1, [%o4] 421 SET_SIZE(hv_tod_get) 422 423 ENTRY(hv_tod_set) 424 mov TOD_SET, %o5 425 ta FAST_TRAP 426 retl 427 nop 428 SET_SIZE(hv_tod_set) 429 430 /* 431 * Map permanent address 432 * arg0 vaddr (%o0) 433 * arg1 context (%o1) 434 * arg2 tte (%o2) 435 * arg3 flags (%o3) 0x1=d 0x2=i 436 */ 437 ENTRY(hv_mmu_map_perm_addr) 438 mov MAP_PERM_ADDR, %o5 439 ta FAST_TRAP 440 retl 441 nop 442 SET_SIZE(hv_mmu_map_perm_addr) 443 444 /* 445 * hv_mmu_fault_area_conf(void *raddr) 446 */ 447 ENTRY(hv_mmu_fault_area_conf) 448 mov %o0, %o2 449 ldx [%o2], %o0 450 mov MMU_SET_INFOPTR, %o5 451 ta FAST_TRAP 452 stx %o1, [%o2] 453 retl 454 nop 455 SET_SIZE(hv_mmu_fault_area_conf) 456 457 /* 458 * Unmap permanent address 459 * arg0 vaddr (%o0) 460 * arg1 context (%o1) 461 * arg2 flags (%o2) 0x1=d 0x2=i 462 */ 463 ENTRY(hv_mmu_unmap_perm_addr) 464 mov UNMAP_PERM_ADDR, %o5 465 ta FAST_TRAP 466 retl 467 nop 468 SET_SIZE(hv_mmu_unmap_perm_addr) 469 470 /* 471 * Set TSB for context 0 472 * arg0 ntsb_descriptor (%o0) 473 * arg1 desc_ra (%o1) 474 */ 475 ENTRY(hv_set_ctx0) 476 mov MMU_TSB_CTX0, %o5 477 ta FAST_TRAP 478 retl 479 nop 480 SET_SIZE(hv_set_ctx0) 481 482 /* 483 * Set TSB for context non0 484 * arg0 ntsb_descriptor (%o0) 485 * arg1 desc_ra (%o1) 486 */ 487 ENTRY(hv_set_ctxnon0) 488 mov MMU_TSB_CTXNON0, %o5 489 ta FAST_TRAP 490 retl 491 nop 492 SET_SIZE(hv_set_ctxnon0) 493 494#ifdef SET_MMU_STATS 495 /* 496 * Returns old stat area on success 497 */ 498 ENTRY(hv_mmu_set_stat_area) 499 mov MMU_STAT_AREA, %o5 500 ta FAST_TRAP 501 retl 502 nop 503 SET_SIZE(hv_mmu_set_stat_area) 504#endif /* SET_MMU_STATS */ 505 506 /* 507 * CPU Q Configure 508 * arg0 queue (%o0) 509 * arg1 Base address RA (%o1) 510 * arg2 Size (%o2) 511 */ 512 ENTRY(hv_cpu_qconf) 513 mov HV_CPU_QCONF, %o5 514 ta FAST_TRAP 515 retl 516 nop 517 SET_SIZE(hv_cpu_qconf) 518 519 /* 520 * arg0 - devhandle 521 * arg1 - devino 522 * 523 * ret0 - status 524 * ret1 - sysino 525 */ 526 ENTRY(hvio_intr_devino_to_sysino) 527 mov HVIO_INTR_DEVINO2SYSINO, %o5 528 ta FAST_TRAP 529 brz,a %o0, 1f 530 stx %o1, [%o2] 5311: retl 532 nop 533 SET_SIZE(hvio_intr_devino_to_sysino) 534 535 /* 536 * arg0 - sysino 537 * 538 * ret0 - status 539 * ret1 - intr_valid_state 540 */ 541 ENTRY(hvio_intr_getvalid) 542 mov %o1, %o2 543 mov HVIO_INTR_GETVALID, %o5 544 ta FAST_TRAP 545 brz,a %o0, 1f 546 stuw %o1, [%o2] 5471: retl 548 nop 549 SET_SIZE(hvio_intr_getvalid) 550 551 /* 552 * arg0 - sysino 553 * arg1 - intr_valid_state 554 * 555 * ret0 - status 556 */ 557 ENTRY(hvio_intr_setvalid) 558 mov HVIO_INTR_SETVALID, %o5 559 ta FAST_TRAP 560 retl 561 nop 562 SET_SIZE(hvio_intr_setvalid) 563 564 /* 565 * arg0 - sysino 566 * 567 * ret0 - status 568 * ret1 - intr_state 569 */ 570 ENTRY(hvio_intr_getstate) 571 mov %o1, %o2 572 mov HVIO_INTR_GETSTATE, %o5 573 ta FAST_TRAP 574 brz,a %o0, 1f 575 stuw %o1, [%o2] 5761: retl 577 nop 578 SET_SIZE(hvio_intr_getstate) 579 580 /* 581 * arg0 - sysino 582 * arg1 - intr_state 583 * 584 * ret0 - status 585 */ 586 ENTRY(hvio_intr_setstate) 587 mov HVIO_INTR_SETSTATE, %o5 588 ta FAST_TRAP 589 retl 590 nop 591 SET_SIZE(hvio_intr_setstate) 592 593 /* 594 * arg0 - sysino 595 * 596 * ret0 - status 597 * ret1 - cpu_id 598 */ 599 ENTRY(hvio_intr_gettarget) 600 mov %o1, %o2 601 mov HVIO_INTR_GETTARGET, %o5 602 ta FAST_TRAP 603 brz,a %o0, 1f 604 stuw %o1, [%o2] 6051: retl 606 nop 607 SET_SIZE(hvio_intr_gettarget) 608 609 /* 610 * arg0 - sysino 611 * arg1 - cpu_id 612 * 613 * ret0 - status 614 */ 615 ENTRY(hvio_intr_settarget) 616 mov HVIO_INTR_SETTARGET, %o5 617 ta FAST_TRAP 618 retl 619 nop 620 SET_SIZE(hvio_intr_settarget) 621 622 /* 623 * hv_cpu_yield(void) 624 */ 625 ENTRY(hv_cpu_yield) 626 mov HV_CPU_YIELD, %o5 627 ta FAST_TRAP 628 retl 629 nop 630 SET_SIZE(hv_cpu_yield) 631 632 /* 633 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 634 */ 635 ENTRY(hv_cpu_state) 636 mov %o1, %o4 ! save datap 637 mov HV_CPU_STATE, %o5 638 ta FAST_TRAP 639 brz,a %o0, 1f 640 stx %o1, [%o4] 6411: 642 retl 643 nop 644 SET_SIZE(hv_cpu_state) 645 646 /* 647 * HV state dump zone Configure 648 * arg0 real adrs of dump buffer (%o0) 649 * arg1 size of dump buffer (%o1) 650 * ret0 status (%o0) 651 * ret1 size of buffer on success and min size on EINVAL (%o1) 652 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 653 */ 654 ENTRY(hv_dump_buf_update) 655 mov DUMP_BUF_UPDATE, %o5 656 ta FAST_TRAP 657 retl 658 stx %o1, [%o2] 659 SET_SIZE(hv_dump_buf_update) 660 661 662 /* 663 * For memory scrub 664 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 665 * uint64_t *scrubbed_len); 666 * Retun %o0 -- status 667 * %o1 -- bytes scrubbed 668 */ 669 ENTRY(hv_mem_scrub) 670 mov %o2, %o4 671 mov HV_MEM_SCRUB, %o5 672 ta FAST_TRAP 673 retl 674 stx %o1, [%o4] 675 SET_SIZE(hv_mem_scrub) 676 677 /* 678 * Flush ecache 679 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 680 * uint64_t *flushed_len); 681 * Retun %o0 -- status 682 * %o1 -- bytes flushed 683 */ 684 ENTRY(hv_mem_sync) 685 mov %o2, %o4 686 mov HV_MEM_SYNC, %o5 687 ta FAST_TRAP 688 retl 689 stx %o1, [%o4] 690 SET_SIZE(hv_mem_sync) 691 692 /* 693 * TTRACE_BUF_CONF Configure 694 * arg0 RA base of buffer (%o0) 695 * arg1 buf size in no. of entries (%o1) 696 * ret0 status (%o0) 697 * ret1 minimum size in no. of entries on failure, 698 * actual size in no. of entries on success (%o1) 699 */ 700 ENTRY(hv_ttrace_buf_conf) 701 mov TTRACE_BUF_CONF, %o5 702 ta FAST_TRAP 703 retl 704 stx %o1, [%o2] 705 SET_SIZE(hv_ttrace_buf_conf) 706 707 /* 708 * TTRACE_BUF_INFO 709 * ret0 status (%o0) 710 * ret1 RA base of buffer (%o1) 711 * ret2 size in no. of entries (%o2) 712 */ 713 ENTRY(hv_ttrace_buf_info) 714 mov %o0, %o3 715 mov %o1, %o4 716 mov TTRACE_BUF_INFO, %o5 717 ta FAST_TRAP 718 stx %o1, [%o3] 719 retl 720 stx %o2, [%o4] 721 SET_SIZE(hv_ttrace_buf_info) 722 723 /* 724 * TTRACE_ENABLE 725 * arg0 enable/ disable (%o0) 726 * ret0 status (%o0) 727 * ret1 previous enable state (%o1) 728 */ 729 ENTRY(hv_ttrace_enable) 730 mov %o1, %o2 731 mov TTRACE_ENABLE, %o5 732 ta FAST_TRAP 733 retl 734 stx %o1, [%o2] 735 SET_SIZE(hv_ttrace_enable) 736 737 /* 738 * TTRACE_FREEZE 739 * arg0 enable/ freeze (%o0) 740 * ret0 status (%o0) 741 * ret1 previous freeze state (%o1) 742 */ 743 ENTRY(hv_ttrace_freeze) 744 mov %o1, %o2 745 mov TTRACE_FREEZE, %o5 746 ta FAST_TRAP 747 retl 748 stx %o1, [%o2] 749 SET_SIZE(hv_ttrace_freeze) 750 751 /* 752 * MACH_DESC 753 * arg0 buffer real address 754 * arg1 pointer to uint64_t for size of buffer 755 * ret0 status 756 * ret1 return required size of buffer / returned data size 757 */ 758 ENTRY(hv_mach_desc) 759 mov %o1, %o4 ! save datap 760 ldx [%o1], %o1 761 mov HV_MACH_DESC, %o5 762 ta FAST_TRAP 763 retl 764 stx %o1, [%o4] 765 SET_SIZE(hv_mach_desc) 766 767 /* 768 * hv_ra2pa(uint64_t ra) 769 * 770 * MACH_DESC 771 * arg0 Real address to convert 772 * ret0 Returned physical address or -1 on error 773 */ 774 ENTRY(hv_ra2pa) 775 mov HV_RA2PA, %o5 776 ta FAST_TRAP 777 cmp %o0, 0 778 move %xcc, %o1, %o0 779 movne %xcc, -1, %o0 780 retl 781 nop 782 SET_SIZE(hv_ra2pa) 783 784 /* 785 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 786 * 787 * MACH_DESC 788 * arg0 OS function to call 789 * arg1 First arg to OS function 790 * arg2 Second arg to OS function 791 * arg3 Third arg to OS function 792 * ret0 Returned value from function 793 */ 794 795 ENTRY(hv_hpriv) 796 mov HV_HPRIV, %o5 797 ta FAST_TRAP 798 retl 799 nop 800 SET_SIZE(hv_hpriv) 801 802 /* 803 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 804 * uint64_t nentries); 805 */ 806 ENTRY(hv_ldc_tx_qconf) 807 mov LDC_TX_QCONF, %o5 808 ta FAST_TRAP 809 retl 810 nop 811 SET_SIZE(hv_ldc_tx_qconf) 812 813 814 /* 815 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 816 * uint64_t *nentries); 817 */ 818 ENTRY(hv_ldc_tx_qinfo) 819 mov %o1, %g1 820 mov %o2, %g2 821 mov LDC_TX_QINFO, %o5 822 ta FAST_TRAP 823 stx %o1, [%g1] 824 retl 825 stx %o2, [%g2] 826 SET_SIZE(hv_ldc_tx_qinfo) 827 828 829 /* 830 * hv_ldc_tx_get_state(uint64_t channel, 831 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 832 */ 833 ENTRY(hv_ldc_tx_get_state) 834 mov LDC_TX_GET_STATE, %o5 835 mov %o1, %g1 836 mov %o2, %g2 837 mov %o3, %g3 838 ta FAST_TRAP 839 stx %o1, [%g1] 840 stx %o2, [%g2] 841 retl 842 stx %o3, [%g3] 843 SET_SIZE(hv_ldc_tx_get_state) 844 845 846 /* 847 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 848 */ 849 ENTRY(hv_ldc_tx_set_qtail) 850 mov LDC_TX_SET_QTAIL, %o5 851 ta FAST_TRAP 852 retl 853 SET_SIZE(hv_ldc_tx_set_qtail) 854 855 856 /* 857 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 858 * uint64_t nentries); 859 */ 860 ENTRY(hv_ldc_rx_qconf) 861 mov LDC_RX_QCONF, %o5 862 ta FAST_TRAP 863 retl 864 nop 865 SET_SIZE(hv_ldc_rx_qconf) 866 867 868 /* 869 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 870 * uint64_t *nentries); 871 */ 872 ENTRY(hv_ldc_rx_qinfo) 873 mov %o1, %g1 874 mov %o2, %g2 875 mov LDC_RX_QINFO, %o5 876 ta FAST_TRAP 877 stx %o1, [%g1] 878 retl 879 stx %o2, [%g2] 880 SET_SIZE(hv_ldc_rx_qinfo) 881 882 883 /* 884 * hv_ldc_rx_get_state(uint64_t channel, 885 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 886 */ 887 ENTRY(hv_ldc_rx_get_state) 888 mov LDC_RX_GET_STATE, %o5 889 mov %o1, %g1 890 mov %o2, %g2 891 mov %o3, %g3 892 ta FAST_TRAP 893 stx %o1, [%g1] 894 stx %o2, [%g2] 895 retl 896 stx %o3, [%g3] 897 SET_SIZE(hv_ldc_rx_get_state) 898 899 900 /* 901 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 902 */ 903 ENTRY(hv_ldc_rx_set_qhead) 904 mov LDC_RX_SET_QHEAD, %o5 905 ta FAST_TRAP 906 retl 907 SET_SIZE(hv_ldc_rx_set_qhead) 908 909 /* 910 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 911 * uint64_t tbl_entries) 912 */ 913 ENTRY(hv_ldc_set_map_table) 914 mov LDC_SET_MAP_TABLE, %o5 915 ta FAST_TRAP 916 retl 917 nop 918 SET_SIZE(hv_ldc_set_map_table) 919 920 921 /* 922 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 923 * uint64_t *tbl_entries) 924 */ 925 ENTRY(hv_ldc_get_map_table) 926 mov %o1, %g1 927 mov %o2, %g2 928 mov LDC_GET_MAP_TABLE, %o5 929 ta FAST_TRAP 930 stx %o1, [%g1] 931 retl 932 stx %o2, [%g2] 933 SET_SIZE(hv_ldc_get_map_table) 934 935 936 /* 937 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 938 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 939 */ 940 ENTRY(hv_ldc_copy) 941 mov %o5, %g1 942 mov LDC_COPY, %o5 943 ta FAST_TRAP 944 retl 945 stx %o1, [%g1] 946 SET_SIZE(hv_ldc_copy) 947 948 949 /* 950 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 951 * uint64_t *perm) 952 */ 953 ENTRY(hv_ldc_mapin) 954 mov %o2, %g1 955 mov %o3, %g2 956 mov LDC_MAPIN, %o5 957 ta FAST_TRAP 958 stx %o1, [%g1] 959 retl 960 stx %o2, [%g2] 961 SET_SIZE(hv_ldc_mapin) 962 963 964 /* 965 * hv_ldc_unmap(uint64_t raddr) 966 */ 967 ENTRY(hv_ldc_unmap) 968 mov LDC_UNMAP, %o5 969 ta FAST_TRAP 970 retl 971 nop 972 SET_SIZE(hv_ldc_unmap) 973 974 975 /* 976 * hv_ldc_revoke(uint64_t raddr) 977 */ 978 ENTRY(hv_ldc_revoke) 979 mov LDC_REVOKE, %o5 980 ta FAST_TRAP 981 retl 982 nop 983 SET_SIZE(hv_ldc_revoke) 984 985 986 /* 987 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 988 * uint64_t *cookie); 989 */ 990 ENTRY(hvldc_intr_getcookie) 991 mov %o2, %g1 992 mov VINTR_GET_COOKIE, %o5 993 ta FAST_TRAP 994 retl 995 stx %o1, [%g1] 996 SET_SIZE(hvldc_intr_getcookie) 997 998 /* 999 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1000 * uint64_t cookie); 1001 */ 1002 ENTRY(hvldc_intr_setcookie) 1003 mov VINTR_SET_COOKIE, %o5 1004 ta FAST_TRAP 1005 retl 1006 nop 1007 SET_SIZE(hvldc_intr_setcookie) 1008 1009 1010 /* 1011 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1012 * int *intr_valid_state); 1013 */ 1014 ENTRY(hvldc_intr_getvalid) 1015 mov %o2, %g1 1016 mov VINTR_GET_VALID, %o5 1017 ta FAST_TRAP 1018 retl 1019 stuw %o1, [%g1] 1020 SET_SIZE(hvldc_intr_getvalid) 1021 1022 /* 1023 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1024 * int intr_valid_state); 1025 */ 1026 ENTRY(hvldc_intr_setvalid) 1027 mov VINTR_SET_VALID, %o5 1028 ta FAST_TRAP 1029 retl 1030 nop 1031 SET_SIZE(hvldc_intr_setvalid) 1032 1033 /* 1034 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1035 * int *intr_state); 1036 */ 1037 ENTRY(hvldc_intr_getstate) 1038 mov %o2, %g1 1039 mov VINTR_GET_STATE, %o5 1040 ta FAST_TRAP 1041 retl 1042 stuw %o1, [%g1] 1043 SET_SIZE(hvldc_intr_getstate) 1044 1045 /* 1046 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1047 * int intr_state); 1048 */ 1049 ENTRY(hvldc_intr_setstate) 1050 mov VINTR_SET_STATE, %o5 1051 ta FAST_TRAP 1052 retl 1053 nop 1054 SET_SIZE(hvldc_intr_setstate) 1055 1056 /* 1057 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1058 * uint32_t *cpuid); 1059 */ 1060 ENTRY(hvldc_intr_gettarget) 1061 mov %o2, %g1 1062 mov VINTR_GET_TARGET, %o5 1063 ta FAST_TRAP 1064 retl 1065 stuw %o1, [%g1] 1066 SET_SIZE(hvldc_intr_gettarget) 1067 1068 /* 1069 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1070 * uint32_t cpuid); 1071 */ 1072 ENTRY(hvldc_intr_settarget) 1073 mov VINTR_SET_TARGET, %o5 1074 ta FAST_TRAP 1075 retl 1076 nop 1077 SET_SIZE(hvldc_intr_settarget) 1078 1079 /* 1080 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1081 * uint64_t *minorp) 1082 * 1083 * API_GET_VERSION 1084 * arg0 API group 1085 * ret0 status 1086 * ret1 major number 1087 * ret2 minor number 1088 */ 1089 ENTRY(hv_api_get_version) 1090 mov %o1, %o3 1091 mov %o2, %o4 1092 mov API_GET_VERSION, %o5 1093 ta CORE_TRAP 1094 stx %o1, [%o3] 1095 retl 1096 stx %o2, [%o4] 1097 SET_SIZE(hv_api_get_version) 1098 1099 /* 1100 * hv_api_set_version(uint64_t api_group, uint64_t major, 1101 * uint64_t minor, uint64_t *supported_minor) 1102 * 1103 * API_SET_VERSION 1104 * arg0 API group 1105 * arg1 major number 1106 * arg2 requested minor number 1107 * ret0 status 1108 * ret1 actual minor number 1109 */ 1110 ENTRY(hv_api_set_version) 1111 mov %o3, %o4 1112 mov API_SET_VERSION, %o5 1113 ta CORE_TRAP 1114 retl 1115 stx %o1, [%o4] 1116 SET_SIZE(hv_api_set_version) 1117 1118#endif /* lint || __lint */ 1119