generic.c revision 3434:5142e1d7d0bc 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#pragma ident	"%Z%%M%	%I%	%E% SMI"
27
28#include <sys/types.h>
29#include <sys/systm.h>
30#include <sys/archsystm.h>
31#include <sys/machparam.h>
32#include <sys/machsystm.h>
33#include <sys/cpu.h>
34#include <sys/elf_SPARC.h>
35#include <vm/hat_sfmmu.h>
36#include <vm/page.h>
37#include <sys/cpuvar.h>
38#include <sys/async.h>
39#include <sys/cmn_err.h>
40#include <sys/debug.h>
41#include <sys/dditypes.h>
42#include <sys/sunddi.h>
43#include <sys/cpu_module.h>
44#include <sys/prom_debug.h>
45#include <sys/vmsystm.h>
46#include <sys/prom_plat.h>
47#include <sys/sysmacros.h>
48#include <sys/intreg.h>
49#include <sys/machtrap.h>
50#include <sys/ontrap.h>
51#include <sys/ivintr.h>
52#include <sys/atomic.h>
53#include <sys/panic.h>
54#include <sys/dtrace.h>
55#include <vm/seg_spt.h>
56#include <sys/simulate.h>
57#include <sys/fault.h>
58
59
60uint_t root_phys_addr_lo_mask = 0xffffffffU;
61
62void
63cpu_setup(void)
64{
65	extern int mmu_exported_pagesize_mask;
66	char *generic_isa_set[] = {
67	    "sparcv9+vis",
68	    "sparcv8plus+vis",
69	    NULL
70	};
71
72	/*
73	 * The setup common to all CPU modules is done in cpu_setup_common
74	 * routine.
75	 */
76	cpu_setup_common(generic_isa_set);
77
78	cache |= (CACHE_PTAG | CACHE_IOCOHERENT);
79
80	if (broken_md_flag) {
81		/*
82		 * Turn on the missing bits supported by sun4v architecture in
83		 * MMU pagesize mask returned by MD.
84		 */
85		mmu_exported_pagesize_mask |= DEFAULT_SUN4V_MMU_PAGESIZE_MASK;
86	} else {
87		/*
88		 * According to sun4v architecture each processor must
89		 * support 8K, 64K and 4M page sizes. If any of the page
90		 * size is missing from page size mask, then panic.
91		 */
92		if ((mmu_exported_pagesize_mask &
93		    DEFAULT_SUN4V_MMU_PAGESIZE_MASK) !=
94		    DEFAULT_SUN4V_MMU_PAGESIZE_MASK)
95			cmn_err(CE_PANIC, "machine description"
96			    " does not have required sun4v page sizes"
97			    " 8K, 64K and 4M: MD mask is 0x%x",
98			    mmu_exported_pagesize_mask);
99	}
100
101	/*
102	 * If processor supports the subset of full 64-bit virtual
103	 * address space, then set VA hole accordingly.
104	 */
105	if (va_bits < VA_ADDRESS_SPACE_BITS) {
106		hole_start = (caddr_t)(1ull << (va_bits - 1));
107		hole_end = (caddr_t)(0ull - (1ull << (va_bits - 1)));
108	} else {
109		hole_start = hole_end = 0;
110	}
111}
112
113void
114cpu_fiximp(struct cpu_node *cpunode)
115{
116	/*
117	 * The Cache node is optional in MD. Therefore in case "Cache"
118	 * does not exists in MD, set the default L2 cache associativity,
119	 * size, linesize for generic CPU module.
120	 */
121	if (cpunode->ecache_size == 0)
122		cpunode->ecache_size = 0x100000;
123	if (cpunode->ecache_linesize == 0)
124		cpunode->ecache_linesize = 64;
125	if (cpunode->ecache_associativity == 0)
126		cpunode->ecache_associativity = 1;
127}
128
129void
130dtrace_flush_sec(uintptr_t addr)
131{
132	pfn_t pfn;
133	proc_t *procp = ttoproc(curthread);
134	page_t *pp;
135	caddr_t va;
136
137	pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr);
138	if (pfn != -1) {
139		ASSERT(pf_is_memory(pfn));
140		pp = page_numtopp_noreclaim(pfn, SE_SHARED);
141		if (pp != NULL) {
142			va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr);
143			/* sparc needs 8-byte align */
144			doflush((caddr_t)((uintptr_t)va & -8l));
145			ppmapout(va);
146			page_unlock(pp);
147		}
148	}
149}
150
151void
152cpu_init_private(struct cpu *cp)
153{
154	/*
155	 * The cpu_ipipe and cpu_fpu fields are initialized based on
156	 * the execution unit sharing information from the Machine
157	 * Description table. They default to the CPU id in the
158	 * absence of such information.
159	 */
160	cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping;
161	if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND)
162		cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
163
164	cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping;
165	if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND)
166		cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id);
167
168	cp->cpu_m.cpu_core = (id_t)(cp->cpu_id);
169}
170
171void
172cpu_uninit_private(struct cpu *cp)
173{
174}
175
176/*
177 * Invalidate a TSB. Since this needs to work on all sun4v
178 * architecture compliant processors, we use the old method of
179 * walking the TSB, setting each tag to TSBTAG_INVALID.
180 */
181void
182cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
183{
184	struct tsbe *tsbaddr;
185
186	for (tsbaddr = (struct tsbe *)tsb_base;
187	    (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes);
188	    tsbaddr++) {
189		tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID;
190	}
191}
192
193/*
194 * Sun4v kernel must emulate code a generic sun4v processor may not support
195 * i.e. VIS1 and VIS2.
196 */
197#define	IS_FLOAT(i) (((i) & 0x1000000) != 0)
198#define	IS_IBIT_SET(x)	(x & 0x2000)
199#define	IS_VIS1(op, op3)(op == 2 && op3 == 0x36)
200#define	IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi)		\
201		(op == 3 && (op3 == IOP_V8_LDDFA ||		\
202		op3 == IOP_V8_STDFA) &&	asi > ASI_SNFL)
203int
204vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault)
205{
206	char *badaddr;
207	int instr;
208	uint_t	optype, op3, asi;
209	uint_t	rd, ignor;
210
211	if (!USERMODE(rp->r_tstate))
212		return (-1);
213
214	instr = fetch_user_instr((caddr_t)rp->r_pc);
215
216	rd = (instr >> 25) & 0x1f;
217	optype = (instr >> 30) & 0x3;
218	op3 = (instr >> 19) & 0x3f;
219	ignor = (instr >> 5) & 0xff;
220	if (IS_IBIT_SET(instr)) {
221		asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) &
222		    TSTATE_ASI_MASK);
223	} else {
224		asi = ignor;
225	}
226
227	if (!IS_VIS1(optype, op3) &&
228	    !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) {
229		return (-1);
230	}
231	switch (simulate_unimp(rp, &badaddr)) {
232	case SIMU_RETRY:
233		break;	/* regs are already set up */
234		/*NOTREACHED*/
235
236	case SIMU_SUCCESS:
237		/*
238		 * skip the successfully
239		 * simulated instruction
240		 */
241		rp->r_pc = rp->r_npc;
242		rp->r_npc += 4;
243		break;
244		/*NOTREACHED*/
245
246	case SIMU_FAULT:
247		siginfo->si_signo = SIGSEGV;
248		siginfo->si_code = SEGV_MAPERR;
249		siginfo->si_addr = badaddr;
250		*fault = FLTBOUNDS;
251		break;
252
253	case SIMU_DZERO:
254		siginfo->si_signo = SIGFPE;
255		siginfo->si_code = FPE_INTDIV;
256		siginfo->si_addr = (caddr_t)rp->r_pc;
257		*fault = FLTIZDIV;
258		break;
259
260	case SIMU_UNALIGN:
261		siginfo->si_signo = SIGBUS;
262		siginfo->si_code = BUS_ADRALN;
263		siginfo->si_addr = badaddr;
264		*fault = FLTACCESS;
265		break;
266
267	case SIMU_ILLEGAL:
268	default:
269		siginfo->si_signo = SIGILL;
270		op3 = (instr >> 19) & 0x3F;
271		if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) ||
272		    (op3 == IOP_V8_STDFA)))
273			siginfo->si_code = ILL_ILLADR;
274		else
275			siginfo->si_code = ILL_ILLOPC;
276		siginfo->si_addr = (caddr_t)rp->r_pc;
277		*fault = FLTILL;
278		break;
279	}
280	return (0);
281}
282
283/*
284 * Trapstat support for generic sun4v processor
285 */
286int
287cpu_trapstat_conf(int cmd)
288{
289	int status;
290
291	switch (cmd) {
292	case CPU_TSTATCONF_INIT:
293	case CPU_TSTATCONF_FINI:
294	case CPU_TSTATCONF_ENABLE:
295	case CPU_TSTATCONF_DISABLE:
296		status = ENOTSUP;
297		break;
298
299	default:
300		status = EINVAL;
301		break;
302	}
303	return (status);
304}
305
306/*ARGSUSED*/
307void
308cpu_trapstat_data(void *buf, uint_t tstat_pgszs)
309{
310}
311