envctrl_targets.c revision 1341:6d7c4f090a72
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 1997 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Low level environmental control routines. 31 * These routines implement the I2C bus protocol. 32 */ 33 34#define EHC_SUCCESS 0 35#define EHC_FAILURE (-1) 36#define EHC_NO_SLAVE_ACK 3 37 38#define EHC_MAX_WAIT 100 /* decimal */ 39 40#define EHC_S1_PIN 0x80 41#define EHC_S1_ES1 0x20 42#define EHC_S1_ES0 0x40 43#define EHC_S1_NBB 0x01 44#define EHC_S1_ACK 0x01 45#define EHC_S1_STA 0x04 46#define EHC_S1_STO 0x02 47#define EHC_S1_LRB 0x08 48#define EHC_S1_BER 0x10 49#define EHC_S1_LAB 0x02 50#define EHC_S1_AAS 0x04 51#define EHC_S1_AD0 0x08 52#define EHC_S1_STS 0x20 53 54#define EHC_S0_OWN 0x55 55#define EHC_S0_CLK 0x1d 56 57#define EHC_BYTE_READ 0x01 58 59#define EHC_LONGEST_MSG 200000 /* 200 ms */ 60 61#define DUMMY_WRITE_ADDR 0x20 62#define DUMMY_WRITE_DATA 0x00 63 64/* 65 * PCF8591 Chip Used for temperature sensors 66 * 67 * Addressing Register definition. 68 * A0-A2 valid range is 0-7 69 * 70 * ------------------------------------------------ 71 * | 1 | 0 | 0 | 1 | A2 | A1 | A0 | R/W | 72 * ------------------------------------------------ 73 */ 74 75 76#define EHC_PCF8591_MAX_DEVS 0x08 77 78#define EHC_DEV0 0x00 79#define EHC_DEV1 0x02 80#define EHC_DEV2 0x04 81#define EHC_DEV3 0x06 82#define EHC_DEV4 0x08 83#define EHC_DEV5 0x0A 84#define EHC_DEV6 0x0C 85#define EHC_DEV7 0x0E 86 87 88/* 89 * CONTROL OF CHIP 90 * PCF8591 Temp sensing control register definitions 91 * 92 * --------------------------------------------- 93 * | 0 | AOE | X | X | 0 | AIF | X | X | 94 * --------------------------------------------- 95 * AOE = Analog out enable.. not used on out implementation 96 * 5 & 4 = Analog Input Programming.. see data sheet for bits.. 97 * 98 * AIF = Auto increment flag 99 * bits 1 & 0 are for the Chennel number. 100 */ 101 102#define EHC_PCF8591_ANALOG_OUTPUT_EN 0x40 103#define EHC_PCF8591_ANALOG_INPUT_EN 0x00 104#define EHC_PCF8591_READ_BIT 0x01 105 106 107#define EHC_PCF8591_AUTO_INCR 0x04 108#define EHC_PCF8591_OSCILATOR 0x40 109 110#define EHC_PCF8591_MAX_PORTS 0x04 111 112#define EHC_PCF8591_CH_0 0x00 113#define EHC_PCF8591_CH_1 0x01 114#define EHC_PCF8591_CH_2 0x02 115#define EHC_PCF8591_CH_3 0x03 116 117 118/* 119 * PCF8574 Fan Fail, Power Supply Fail Detector 120 * This device is driven by interrupts. Each time it interrupts 121 * you must look at the CSR to see which ports caused the interrupt 122 * they are indicated by a 1. 123 * 124 * Address map of this chip 125 * 126 * ------------------------------------------- 127 * | 0 | 1 | 1 | 1 | A2 | A1 | A0 | 0 | 128 * ------------------------------------------- 129 * 130 */ 131 132#define EHC_PCF8574_PORT0 0x01 133#define EHC_PCF8574_PORT1 0x02 134#define EHC_PCF8574_PORT2 0x04 135#define EHC_PCF8574_PORT3 0x08 136#define EHC_PCF8574_PORT4 0x10 137#define EHC_PCF8574_PORT5 0x20 138#define EHC_PCF8574_PORT6 0x40 139#define EHC_PCF8574_PORT7 0x80 140 141/* 142 * Defines for the PCF8583 Clock Calendar Chip. 143 */ 144#define EHC_PCF8583_READ_BIT 0x01 145 146struct ehc_pcd8584_regs { 147 uint8_t s0; /* Own Address S0' */ 148 uint8_t s1; /* Control Status register */ 149 uint8_t clock_s2; /* Clock programming register */ 150}; 151 152struct ehc_envcunit { 153 struct ehc_pcd8584_regs *bus_ctl_regs; 154 ddi_acc_handle_t ctlr_handle; 155 kmutex_t umutex; 156}; 157 158int ehc_debug = 0; 159 160#define DCMN_ERR if (ehc_debug & 0x1) cmn_err 161#define DCMN2_ERR if (ehc_debug & 0x2) cmn_err 162 163/* 164 * Prototypes for routines used in other modules. 165 */ 166 167void ehc_init_pcf8584(struct ehc_envcunit *); 168int ehc_read_tda8444(struct ehc_envcunit *ehcp); 169int ehc_write_tda8444(struct ehc_envcunit *, int, int, int, uint8_t *, int); 170int ehc_write_pcf8591(struct ehc_envcunit *, int, int, int, int, int, 171 uint8_t *, int); 172int ehc_read_pcf8591(struct ehc_envcunit *, int, int, int, int, int, 173 uint8_t *, int); 174int ehc_read_pcf8574a(struct ehc_envcunit *, int, uint8_t *, int); 175int ehc_write_pcf8574a(struct ehc_envcunit *, int, uint8_t *, int); 176int ehc_read_pcf8574(struct ehc_envcunit *, int, uint8_t *, int); 177int ehc_write_pcf8574(struct ehc_envcunit *, int, uint8_t *, int); 178int ehc_read_lm75(struct ehc_envcunit *, int, uint8_t *, int); 179int ehc_write_pcf8583(struct ehc_envcunit *, int, uint8_t *, int); 180 181/* 182 * Prototypes for routines used only in this source module. 183 */ 184 185static int ehc_start_pcf8584(struct ehc_envcunit *, uint8_t); 186static void ehc_stop_pcf8584(struct ehc_envcunit *); 187static int ehc_read_pcf8584(struct ehc_envcunit *, uint8_t *); 188static int ehc_write_pcf8584(struct ehc_envcunit *, uint8_t); 189static int ehc_after_read_pcf8584(struct ehc_envcunit *, uint8_t *); 190 191/* 192 * put host interface into master mode 193 */ 194static int 195ehc_start_pcf8584(struct ehc_envcunit *ehcp, uint8_t byteaddress) 196{ 197 uint8_t poll_status; 198 uint8_t discard; 199 int i; 200 201 /* wait if bus is busy */ 202 203 i = 0; 204 do { 205 drv_usecwait(1000); 206 poll_status = 207 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 208 i++; 209 } while (((poll_status & EHC_S1_NBB) == 0) && i < EHC_MAX_WAIT); 210 211 if (i == EHC_MAX_WAIT) { 212 DCMN_ERR(CE_WARN, "ehc_start_pcf8584(): busy bit clear failed"); 213 return (EHC_FAILURE); 214 } 215 216 if (poll_status & EHC_S1_BER) { 217 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()1: Bus error"); 218 ehc_init_pcf8584(ehcp); 219 return (EHC_FAILURE); 220 } 221 222 if (poll_status & EHC_S1_LAB) { 223 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()1: Lost Arbitration"); 224 ehc_init_pcf8584(ehcp); 225 return (EHC_FAILURE); 226 } 227 228 /* 229 * This is a dummy arbitration using the lowest unused address 230 * possible. This step allows the PCF8584 to always win arbitration 231 * except in the case of "general call" being issued by the other 232 * master. 233 */ 234 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, DUMMY_WRITE_ADDR); 235 236 /* generate the "start condition" and clock out the slave address */ 237 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, 238 EHC_S1_PIN | EHC_S1_ES0 | EHC_S1_STA | EHC_S1_ACK); 239 240 /* wait for completion of transmission */ 241 i = 0; 242 do { 243 drv_usecwait(1000); 244 poll_status = 245 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 246 i++; 247 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 248 249 if (i == EHC_MAX_WAIT) { 250 DCMN_ERR(CE_WARN, "ehc_start_pcf8584_5(): read of S1 failed"); 251 return (EHC_FAILURE); 252 } 253 254 if (poll_status & EHC_S1_BER) { 255 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()5: Bus error"); 256 ehc_init_pcf8584(ehcp); 257 return (EHC_FAILURE); 258 } 259 260 if (poll_status & EHC_S1_LAB) { 261 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()5: Lost Arbitration"); 262 ehc_init_pcf8584(ehcp); 263 return (EHC_FAILURE); 264 } 265 266 /* dummy write */ 267 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, DUMMY_WRITE_DATA); 268 269 /* wait for completion of transmission */ 270 i = 0; 271 do { 272 drv_usecwait(1000); 273 poll_status = 274 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 275 i++; 276 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 277 278 if (i == EHC_MAX_WAIT) { 279 DCMN_ERR(CE_WARN, "ehc_start_pcf8584(): read of S1 failed"); 280 return (EHC_FAILURE); 281 } 282 283 if (poll_status & EHC_S1_BER) { 284 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()4: Bus error"); 285 ehc_init_pcf8584(ehcp); 286 return (EHC_FAILURE); 287 } 288 289 if (poll_status & EHC_S1_LAB) { 290 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()4: Lost Arbitration"); 291 ehc_init_pcf8584(ehcp); 292 return (EHC_FAILURE); 293 } 294 295 /* 296 * generate the repeated "start condition" and 297 * clock out the slave address 298 */ 299 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, 300 EHC_S1_ES0 | EHC_S1_STA | EHC_S1_ACK); 301 302 /* load the slave address */ 303 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, byteaddress); 304 305 /* wait for completion of transmission */ 306 i = 0; 307 do { 308 drv_usecwait(1000); 309 poll_status = 310 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 311 i++; 312 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 313 314 if (i == EHC_MAX_WAIT) { 315 DCMN_ERR(CE_WARN, "ehc_start_pcf8584(): read of S1 failed"); 316 return (EHC_FAILURE); 317 } 318 319 if (poll_status & EHC_S1_BER) { 320 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()2: Bus error"); 321 ehc_init_pcf8584(ehcp); 322 return (EHC_FAILURE); 323 } 324 325 if (poll_status & EHC_S1_LAB) { 326 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()2: Lost Arbitration"); 327 ehc_init_pcf8584(ehcp); 328 return (EHC_FAILURE); 329 } 330 331 if (poll_status & EHC_S1_LRB) { 332 DCMN_ERR(CE_WARN, "ehc_start_pcf8584(): No slave ACK"); 333 return (EHC_NO_SLAVE_ACK); 334 } 335 336 /* 337 * If this is a read we are setting up for (as indicated by 338 * the least significant byte being set), read 339 * and discard the first byte off the bus - this 340 * is the slave address. 341 */ 342 343 i = 0; 344 if (byteaddress & EHC_BYTE_READ) { 345 discard = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 346#ifdef lint 347 discard = discard; 348#endif 349 350 /* wait for completion of transmission */ 351 do { 352 drv_usecwait(1000); 353 poll_status = 354 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 355 i++; 356 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 357 358 if (i == EHC_MAX_WAIT) { 359 DCMN_ERR(CE_WARN, 360 "ehc_start_pcf8584(): read of S1 failed"); 361 return (EHC_FAILURE); 362 } 363 364 if (poll_status & EHC_S1_BER) { 365 DCMN2_ERR(CE_WARN, "ehc_start_pcf8584()3: Bus error"); 366 ehc_init_pcf8584(ehcp); 367 return (EHC_FAILURE); 368 } 369 if (poll_status & EHC_S1_LAB) { 370 DCMN2_ERR(CE_WARN, 371 "ehc_start_pcf8584()3: Lost Arbitration"); 372 ehc_init_pcf8584(ehcp); 373 return (EHC_FAILURE); 374 } 375 376 } 377 378 return (EHC_SUCCESS); 379} 380 381/* 382 * put host interface into slave/receiver mode 383 */ 384static void 385ehc_stop_pcf8584(struct ehc_envcunit *ehcp) 386{ 387 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, 388 EHC_S1_PIN | EHC_S1_ES0 | EHC_S1_STO | EHC_S1_ACK); 389} 390 391static int 392ehc_read_pcf8584(struct ehc_envcunit *ehcp, uint8_t *data) 393{ 394 uint8_t poll_status; 395 int i = 0; 396 397 /* Read the byte of interest */ 398 *data = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 399 400 /* wait for completion of transmission */ 401 do { 402 drv_usecwait(1000); 403 poll_status = 404 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 405 i++; 406 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 407 408 if (i == EHC_MAX_WAIT) { 409 DCMN_ERR(CE_WARN, "ehc_read_pcf8584(): read of S1 failed"); 410 return (EHC_FAILURE); 411 } 412 413 if (poll_status & EHC_S1_BER) { 414 DCMN2_ERR(CE_WARN, "ehc_read_pcf8584(): Bus error"); 415 ehc_init_pcf8584(ehcp); 416 return (EHC_FAILURE); 417 } 418 419 if (poll_status & EHC_S1_LAB) { 420 DCMN2_ERR(CE_WARN, "ehc_read_pcf8584(): Lost Arbitration"); 421 ehc_init_pcf8584(ehcp); 422 return (EHC_FAILURE); 423 } 424 425 return (EHC_SUCCESS); 426} 427 428/* 429 * host interface is in transmitter state, thus mode is master/transmitter 430 * NOTE to Bill: this check the LRB bit (only done in transmit mode). 431 */ 432 433static int 434ehc_write_pcf8584(struct ehc_envcunit *ehcp, uint8_t data) 435{ 436 uint8_t poll_status; 437 int i = 0; 438 439 /* send the data, EHC_S1_PIN should go to "1" immediately */ 440 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, data); 441 442 /* wait for completion of transmission */ 443 do { 444 drv_usecwait(1000); 445 poll_status = 446 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 447 i++; 448 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 449 450 if (i == EHC_MAX_WAIT) { 451 DCMN_ERR(CE_WARN, "ehc_write_pcf8584(): read of S1 failed"); 452 return (EHC_FAILURE); 453 } 454 455 if (poll_status & EHC_S1_BER) { 456 DCMN2_ERR(CE_WARN, "ehc_write_pcf8584(): Bus error"); 457 ehc_init_pcf8584(ehcp); 458 return (EHC_FAILURE); 459 } 460 461 if (poll_status & EHC_S1_LAB) { 462 DCMN2_ERR(CE_WARN, "ehc_write_pcf8584(): Lost Arbitration"); 463 ehc_init_pcf8584(ehcp); 464 return (EHC_FAILURE); 465 } 466 467 if (poll_status & EHC_S1_LRB) { 468 DCMN_ERR(CE_WARN, "ehc_write_pcf8584(): No slave ACK"); 469 return (EHC_NO_SLAVE_ACK); 470 } 471 472 return (EHC_SUCCESS); 473} 474 475static int 476ehc_after_read_pcf8584(struct ehc_envcunit *ehcp, uint8_t *data) 477{ 478 uint8_t discard; 479 uint8_t poll_status; 480 int i = 0; 481 482 /* set ACK in register S1 to 0 */ 483 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, EHC_S1_ES0); 484 485 /* 486 * Read the "byte-before-the-last-byte" - sets PIN bit to '1' 487 */ 488 489 *data = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 490 491 /* wait for completion of transmission */ 492 do { 493 drv_usecwait(1000); 494 poll_status = 495 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 496 i++; 497 } while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 498 499 if (i == EHC_MAX_WAIT) { 500 DCMN_ERR(CE_WARN, "ehc_after_rd_pcf8584(): read of S1 failed"); 501 return (EHC_FAILURE); 502 } 503 504 if (poll_status & EHC_S1_BER) { 505 DCMN2_ERR(CE_WARN, "ehc_after_rd_pcf8584(): Bus error"); 506 ehc_init_pcf8584(ehcp); 507 return (EHC_FAILURE); 508 } 509 510 if (poll_status & EHC_S1_LAB) { 511 DCMN2_ERR(CE_WARN, "ehc_after_rd_pcf8584(): Lost Arbitration"); 512 ehc_init_pcf8584(ehcp); 513 return (EHC_FAILURE); 514 } 515 516 /* 517 * Generate the "stop" condition. 518 */ 519 ehc_stop_pcf8584(ehcp); 520 521 /* 522 * Read the "last" byte. 523 */ 524 discard = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 525#ifdef lint 526 discard = discard; 527#endif 528 529 return (EHC_SUCCESS); 530} 531 532/* 533 * Below this comment are the externally visible routines comprising the API 534 */ 535 536/* 537 * Initialize the 8584 chip 538 */ 539 540void 541ehc_init_pcf8584(struct ehc_envcunit *ehcp) 542{ 543 /* 544 * Writing PIN bit of S1 causes software reset. 545 * The next write to S0 will be S0' "own address". 546 */ 547 548 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, EHC_S1_PIN); 549 550 /* 551 * Write the address which the controller chip will use 552 * (when addressed as a slave) on the I2C bus. 553 * DAF - should own address be passed as argument? 554 */ 555 556 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, EHC_S0_OWN); 557 558 /* 559 * Writing PIN bit and ES1 bit of S1 causes software 560 * reset and selects the S2 register for writing. 561 * Now, the next write to S0 will be the S2 clock 562 * control register. 563 */ 564 565 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, 566 EHC_S1_PIN | EHC_S1_ES1); 567 568 /* 569 * Write the value into register that sets internal system clock 570 * to 12 Mhz, and the I2C bus rate (SCL) to 9 Khz. 571 * DAF - should these be parameters? 572 */ 573 574 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, EHC_S0_CLK); 575 576 /* 577 * Writing PIN bit causes software reset and the ES0 bit 578 * selects the (S0) register for reading/writing. The ACK 579 * bit being set causes controller to send ACK after each 580 * byte. 581 */ 582 583 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, 584 EHC_S1_PIN | EHC_S1_ES0 | EHC_S1_ACK); 585 586 /* 587 * Multi-Master: Wait for a period of time equal to the 588 * longest I2C message. This accounts for the case 589 * where multiple controllers and, if this particular one 590 * is "lagging", misses the BB (bus busy) condition. 591 * DAF - What does this need? 592 * We wait 200 ms since the longest transaction at this time 593 * on the i2c bus is a 256 byte read from the seprom which takes 594 * about 75 ms. Some additional buffer does no harm to the driver. 595 */ 596 597 drv_usecwait(EHC_LONGEST_MSG); 598 599} 600 601int 602ehc_read_tda8444(struct ehc_envcunit *ehcp) 603{ 604#ifdef lint 605 ehcp = ehcp; 606#endif 607 return (EHC_FAILURE); 608} 609 610/* 611 * Write to the TDA8444 chip. 612 * byteaddress = chip type base address | chip offset address. 613 */ 614int 615ehc_write_tda8444(struct ehc_envcunit *ehcp, int byteaddress, int instruction, 616 int subaddress, uint8_t *buf, int size) 617{ 618 uint8_t control; 619 int i, status; 620 621 ASSERT((byteaddress & 0x1) == 0); 622 ASSERT(subaddress < 8); 623 ASSERT(instruction == 0xf || instruction == 0x0); 624 ASSERT(MUTEX_HELD(&ehcp->umutex)); 625 626 control = (instruction << 4) | subaddress; 627 628 if ((status = ehc_start_pcf8584(ehcp, byteaddress)) != EHC_SUCCESS) { 629 if (status == EHC_NO_SLAVE_ACK) { 630 /* 631 * Send the "stop" condition. 632 */ 633 ehc_stop_pcf8584(ehcp); 634 } 635 return (EHC_FAILURE); 636 } 637 638 if ((status = ehc_write_pcf8584(ehcp, control)) != EHC_SUCCESS) { 639 if (status == EHC_NO_SLAVE_ACK) { 640 /* 641 * Send the "stop" condition. 642 */ 643 ehc_stop_pcf8584(ehcp); 644 } 645 return (EHC_FAILURE); 646 } 647 648 for (i = 0; i < size; i++) { 649 if ((status = ehc_write_pcf8584(ehcp, (buf[i] & 0x3f))) != 650 EHC_SUCCESS) { 651 if (status == EHC_NO_SLAVE_ACK) 652 ehc_stop_pcf8584(ehcp); 653 return (EHC_FAILURE); 654 } 655 } 656 657 ehc_stop_pcf8584(ehcp); 658 659 return (EHC_SUCCESS); 660} 661 662/* 663 * Read from PCF8574A chip. 664 * byteaddress = chip type base address | chip offset address. 665 */ 666int 667ehc_read_pcf8574a(struct ehc_envcunit *ehcp, int byteaddress, uint8_t *buf, 668 int size) 669{ 670 int i; 671 int status; 672 uint8_t discard; 673 674 ASSERT((byteaddress & 0x1) == 0); 675 ASSERT(MUTEX_HELD(&ehcp->umutex)); 676 677 /* 678 * Put the bus into the start condition 679 */ 680 if ((status = ehc_start_pcf8584(ehcp, EHC_BYTE_READ | byteaddress)) != 681 EHC_SUCCESS) { 682 if (status == EHC_NO_SLAVE_ACK) { 683 /* 684 * Send the "stop" condition. 685 */ 686 ehc_stop_pcf8584(ehcp); 687 /* 688 * Read the last byte - discard it. 689 */ 690 discard = 691 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 692#ifdef lint 693 discard = discard; 694#endif 695 } 696 return (EHC_FAILURE); 697 } 698 699 for (i = 0; i < size - 1; i++) { 700 if ((status = ehc_read_pcf8584(ehcp, &buf[i])) != EHC_SUCCESS) { 701 return (EHC_FAILURE); 702 } 703 } 704 705 /* 706 * Handle the part of the bus protocol which comes 707 * after a read, including reading the last byte. 708 */ 709 710 if (ehc_after_read_pcf8584(ehcp, &buf[i]) != EHC_SUCCESS) { 711 return (EHC_FAILURE); 712 } 713 714 return (EHC_SUCCESS); 715} 716 717/* 718 * Write to the PCF8574A chip. 719 * byteaddress = chip type base address | chip offset address. 720 */ 721int 722ehc_write_pcf8574a(struct ehc_envcunit *ehcp, int byteaddress, uint8_t *buf, 723 int size) 724{ 725 int i; 726 int status; 727 728 ASSERT((byteaddress & 0x1) == 0); 729 ASSERT(MUTEX_HELD(&ehcp->umutex)); 730 731 /* 732 * Put the bus into the start condition (write) 733 */ 734 if ((status = ehc_start_pcf8584(ehcp, byteaddress)) != EHC_SUCCESS) { 735 if (status == EHC_NO_SLAVE_ACK) { 736 /* 737 * Send the "stop" condition. 738 */ 739 ehc_stop_pcf8584(ehcp); 740 } 741 return (EHC_FAILURE); 742 } 743 744 /* 745 * Send the data - poll as needed. 746 */ 747 for (i = 0; i < size; i++) { 748 if ((status = ehc_write_pcf8584(ehcp, buf[i])) != EHC_SUCCESS) { 749 if (status == EHC_NO_SLAVE_ACK) 750 ehc_stop_pcf8584(ehcp); 751 return (EHC_FAILURE); 752 } 753 } 754 755 /* 756 * Transmission complete - generate stop condition and 757 * put device back into slave receiver mode. 758 */ 759 ehc_stop_pcf8584(ehcp); 760 761 return (EHC_SUCCESS); 762} 763 764/* 765 * Read from the PCF8574 chip. 766 * byteaddress = chip type base address | chip offset address. 767 */ 768int 769ehc_read_pcf8574(struct ehc_envcunit *ehcp, int byteaddress, uint8_t *buf, 770 int size) 771{ 772 int i; 773 int status; 774 uint8_t discard; 775 776 ASSERT((byteaddress & 0x1) == 0); 777 ASSERT(MUTEX_HELD(&ehcp->umutex)); 778 779 /* 780 * Put the bus into the start condition 781 */ 782 if ((status = ehc_start_pcf8584(ehcp, EHC_BYTE_READ | byteaddress)) != 783 EHC_SUCCESS) { 784 if (status == EHC_NO_SLAVE_ACK) { 785 /* 786 * Send the "stop" condition. 787 */ 788 ehc_stop_pcf8584(ehcp); 789 /* 790 * Read the last byte - discard it. 791 */ 792 discard = 793 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 794#ifdef lint 795 discard = discard; 796#endif 797 } 798 return (EHC_FAILURE); 799 } 800 801 for (i = 0; i < size - 1; i++) { 802 if ((status = ehc_read_pcf8584(ehcp, &buf[i])) != EHC_SUCCESS) { 803 return (EHC_FAILURE); 804 } 805 } 806 807 /* 808 * Handle the part of the bus protocol which comes 809 * after a read. 810 */ 811 812 if (ehc_after_read_pcf8584(ehcp, &buf[i]) != EHC_SUCCESS) { 813 return (EHC_FAILURE); 814 } 815 816 return (EHC_SUCCESS); 817} 818 819/* 820 * Write to the PCF8574 chip. 821 * byteaddress = chip type base address | chip offset address. 822 */ 823int 824ehc_write_pcf8574(struct ehc_envcunit *ehcp, int byteaddress, uint8_t *buf, 825 int size) 826{ 827 int i; 828 int status; 829 830 ASSERT((byteaddress & 0x1) == 0); 831 ASSERT(MUTEX_HELD(&ehcp->umutex)); 832 833 /* 834 * Put the bus into the start condition (write) 835 */ 836 if ((status = ehc_start_pcf8584(ehcp, byteaddress)) != EHC_SUCCESS) { 837 if (status == EHC_NO_SLAVE_ACK) { 838 /* 839 * Send the "stop" condition. 840 */ 841 ehc_stop_pcf8584(ehcp); 842 } 843 return (EHC_FAILURE); 844 } 845 846 /* 847 * Send the data - poll as needed. 848 */ 849 for (i = 0; i < size; i++) { 850 if ((status = ehc_write_pcf8584(ehcp, buf[i])) != EHC_SUCCESS) { 851 if (status == EHC_NO_SLAVE_ACK) 852 ehc_stop_pcf8584(ehcp); 853 return (EHC_FAILURE); 854 } 855 } 856 /* 857 * Transmission complete - generate stop condition and 858 * put device back into slave receiver mode. 859 */ 860 ehc_stop_pcf8584(ehcp); 861 862 return (EHC_SUCCESS); 863} 864 865/* 866 * Read from the LM75 867 * byteaddress = chip type base address | chip offset address. 868 */ 869int 870ehc_read_lm75(struct ehc_envcunit *ehcp, int byteaddress, uint8_t *buf, 871 int size) 872{ 873 int i; 874 int status; 875 uint8_t discard; 876 877 ASSERT((byteaddress & 0x1) == 0); 878 ASSERT(MUTEX_HELD(&ehcp->umutex)); 879 880 /* 881 * Put the bus into the start condition 882 */ 883 if ((status = ehc_start_pcf8584(ehcp, EHC_BYTE_READ | byteaddress)) != 884 EHC_SUCCESS) { 885 if (status == EHC_NO_SLAVE_ACK) { 886 /* 887 * Send the stop condition. 888 */ 889 ehc_stop_pcf8584(ehcp); 890 /* 891 * Read the last byte - discard it. 892 */ 893 discard = 894 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 895#ifdef lint 896 discard = discard; 897#endif 898 } 899 return (EHC_FAILURE); 900 } 901 902 for (i = 0; i < size - 1; i++) { 903 if ((status = ehc_read_pcf8584(ehcp, &buf[i])) != EHC_SUCCESS) { 904 return (EHC_FAILURE); 905 } 906 } 907 908 /* 909 * Handle the part of the bus protocol which comes 910 * after a read. 911 */ 912 if (ehc_after_read_pcf8584(ehcp, &buf[i]) != EHC_SUCCESS) { 913 return (EHC_FAILURE); 914 } 915 916 return (EHC_SUCCESS); 917} 918 919/* 920 * Write to the PCF8583 chip. 921 * byteaddress = chip type base address | chip offset address. 922 */ 923int 924ehc_write_pcf8583(struct ehc_envcunit *ehcp, int byteaddress, uint8_t *buf, 925 int size) 926{ 927 int i; 928 int status; 929 930 ASSERT((byteaddress & 0x1) == 0); 931 ASSERT(MUTEX_HELD(&ehcp->umutex)); 932 933 if ((status = ehc_start_pcf8584(ehcp, byteaddress)) != EHC_SUCCESS) { 934 if (status == EHC_NO_SLAVE_ACK) { 935 /* 936 * Send the "stop" condition. 937 */ 938 ehc_stop_pcf8584(ehcp); 939 } 940 return (EHC_FAILURE); 941 } 942 943 /* 944 * Send the data - poll as needed. 945 */ 946 for (i = 0; i < size; i++) { 947 if ((status = ehc_write_pcf8584(ehcp, buf[i])) != EHC_SUCCESS) { 948 if (status == EHC_NO_SLAVE_ACK) 949 ehc_stop_pcf8584(ehcp); 950 return (EHC_FAILURE); 951 } 952 } 953 954 /* 955 * Transmission complete - generate stop condition and 956 * put device back into slave receiver mode. 957 */ 958 ehc_stop_pcf8584(ehcp); 959 960 return (EHC_SUCCESS); 961} 962 963/* 964 * Read from the PCF8591 chip. 965 */ 966int 967ehc_read_pcf8591(struct ehc_envcunit *ehcp, int byteaddress, int channel, 968 int autoinc, int amode, int aenable, uint8_t *buf, int size) 969{ 970 int i; 971 int status; 972 register uint8_t control; 973 uint8_t discard; 974 975 ASSERT((byteaddress & 0x1) == 0); 976 ASSERT(channel < 4); 977 ASSERT(amode < 4); 978 ASSERT(MUTEX_HELD(&ehcp->umutex)); 979 980 /* 981 * Write the control word to the PCF8591. 982 * Follow the control word with a repeated START byte 983 * rather than a STOP so that reads can follow without giving 984 * up the bus. 985 */ 986 987 control = ((aenable << 6) | (amode << 4) | (autoinc << 2) | channel); 988 989 if ((status = ehc_start_pcf8584(ehcp, byteaddress)) != EHC_SUCCESS) { 990 if (status == EHC_NO_SLAVE_ACK) { 991 ehc_stop_pcf8584(ehcp); 992 } 993 return (EHC_FAILURE); 994 } 995 996 if ((status = ehc_write_pcf8584(ehcp, control)) != EHC_SUCCESS) { 997 if (status == EHC_NO_SLAVE_ACK) 998 ehc_stop_pcf8584(ehcp); 999 return (EHC_FAILURE); 1000 } 1001 1002 /* 1003 * The following two operations, 0x45 to S1, and the byteaddress 1004 * to S0, will result in a repeated START being sent out on the bus. 1005 * Refer to Fig.8 of Philips Semiconductors PCF8584 product spec. 1006 */ 1007 1008 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, 1009 EHC_S1_ES0 | EHC_S1_STA | EHC_S1_ACK); 1010 1011 ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, 1012 EHC_BYTE_READ | byteaddress); 1013 1014 i = 0; 1015 1016 do { 1017 drv_usecwait(1000); 1018 status = 1019 ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1); 1020 i++; 1021 } while ((status & EHC_S1_PIN) && i < EHC_MAX_WAIT); 1022 1023 if (i == EHC_MAX_WAIT) { 1024 DCMN_ERR(CE_WARN, "ehc_read_pcf8591(): read of S1 failed"); 1025 return (EHC_FAILURE); 1026 } 1027 1028 if (status & EHC_S1_BER) { 1029 DCMN2_ERR(CE_WARN, "ehc_read_pcf8591(): Bus error"); 1030 ehc_init_pcf8584(ehcp); 1031 return (EHC_FAILURE); 1032 } 1033 1034 if (status & EHC_S1_LAB) { 1035 DCMN2_ERR(CE_WARN, "ehc_read_pcf8591(): Lost Arbitration"); 1036 ehc_init_pcf8584(ehcp); 1037 return (EHC_FAILURE); 1038 } 1039 1040 if (status & EHC_S1_LRB) { 1041 DCMN_ERR(CE_WARN, "ehc_read_pcf8591(): No slave ACK"); 1042 /* 1043 * Send the stop condition. 1044 */ 1045 ehc_stop_pcf8584(ehcp); 1046 /* 1047 * Read the last byte - discard it. 1048 */ 1049 discard = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0); 1050#ifdef lint 1051 discard = discard; 1052#endif 1053 return (EHC_FAILURE); 1054 } 1055 1056 /* 1057 * Discard first read as per PCF8584 master receiver protocol. 1058 * This is normally done in the ehc_start_pcf8584() routine. 1059 */ 1060 if ((status = ehc_read_pcf8584(ehcp, &discard)) != EHC_SUCCESS) { 1061 return (EHC_FAILURE); 1062 } 1063 1064 /* Discard second read as per PCF8591 protocol */ 1065 if ((status = ehc_read_pcf8584(ehcp, &discard)) != EHC_SUCCESS) { 1066 return (EHC_FAILURE); 1067 } 1068 1069 for (i = 0; i < size - 1; i++) { 1070 if ((status = ehc_read_pcf8584(ehcp, &buf[i])) != EHC_SUCCESS) { 1071 return (EHC_FAILURE); 1072 } 1073 } 1074 1075 if (ehc_after_read_pcf8584(ehcp, &buf[i]) != EHC_SUCCESS) { 1076 return (EHC_FAILURE); 1077 } 1078 1079 return (EHC_SUCCESS); 1080} 1081 1082/* 1083 * Write to the PCF8591 chip. 1084 * byteaddress = chip type base address | chip offset address. 1085 */ 1086int 1087ehc_write_pcf8591(struct ehc_envcunit *ehcp, int byteaddress, int channel, 1088 int autoinc, int amode, int aenable, uint8_t *buf, int size) 1089{ 1090 int i, status; 1091 register uint8_t control; 1092 1093 ASSERT((byteaddress & 0x1) == 0); 1094 ASSERT(MUTEX_HELD(&ehcp->umutex)); 1095 1096 control = ((aenable << 6) | (amode << 4) | (autoinc << 2) | channel); 1097 1098 status = ehc_start_pcf8584(ehcp, byteaddress); 1099 if (status != EHC_SUCCESS) { 1100 if (status == EHC_NO_SLAVE_ACK) { 1101 /* 1102 * Send the "stop" condition. 1103 */ 1104 ehc_stop_pcf8584(ehcp); 1105 } 1106 return (EHC_FAILURE); 1107 } 1108 1109 if ((status = ehc_write_pcf8584(ehcp, control)) != EHC_SUCCESS) { 1110 if (status == EHC_NO_SLAVE_ACK) 1111 ehc_stop_pcf8584(ehcp); 1112 return (EHC_FAILURE); 1113 } 1114 1115 for (i = 0; i < size; i++) { 1116 status = ehc_write_pcf8584(ehcp, buf[i]); 1117 if (status != EHC_SUCCESS) { 1118 if (status == EHC_NO_SLAVE_ACK) 1119 ehc_stop_pcf8584(ehcp); 1120 return (EHC_FAILURE); 1121 } 1122 } 1123 1124 ehc_stop_pcf8584(ehcp); 1125 1126 return (EHC_SUCCESS); 1127} 1128