1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_SIMULATE_H 27#define _SYS_SIMULATE_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33/* SPARC instruction simulator return codes. */ 34 35#define SIMU_SUCCESS 1 /* simulation worked */ 36#define SIMU_ILLEGAL 2 /* tried to simulate an illegal instuction */ 37#define SIMU_FAULT 3 /* simulation generated an illegal access */ 38#define SIMU_DZERO 4 /* simulation generated divide by zero */ 39#define SIMU_UNALIGN 5 /* simulation generated an unaligned access */ 40#define SIMU_RETRY 6 /* fixed up instruction, now retry it */ 41 42 43/* 44 * Opcode types. 45 */ 46#define OP_V8_BRANCH 0 47#define OP_V8_CALL 1 48#define OP_V8_ARITH 2 /* includes control xfer (e.g. JMPL) */ 49#define OP_V8_LDSTR 3 50 51/* 52 * Relevant instruction opcodes. 53 */ 54 55/* OP_V8_LDSTR */ 56#define IOP_V8_LD 0x00 57#define IOP_V8_LDA 0x10 58#define IOP_V8_LDUBA 0x11 59#define IOP_V8_LDUHA 0x12 60#define IOP_V8_LDDA 0x13 61#define IOP_V8_STA 0x14 62#define IOP_V8_STBA 0x15 63#define IOP_V8_STHA 0x16 64#define IOP_V8_STDA 0x17 65#define IOP_V8_LDSBA 0x19 66#define IOP_V8_LDSHA 0x1a 67#define IOP_V8_LDSTUBA 0x1d 68#define IOP_V8_SWAPA 0x1f 69#define IOP_V8_LDFSR 0x21 70#define IOP_V8_LDQF 0x22 71#define IOP_V8_STFSR 0x25 72#define IOP_V8_STQF 0x26 73#define IOP_V8_LDQFA 0x32 74#define IOP_V8_LDDFA 0x33 75#define IOP_V8_STQFA 0x36 76#define IOP_V8_STDFA 0x37 77 78/* OP_V8_ARITH */ 79#define IOP_V8_ADD 0x00 80#define IOP_V8_AND 0x01 81#define IOP_V8_OR 0x02 82#define IOP_V8_XOR 0x03 83#define IOP_V8_SUB 0x04 84#define IOP_V8_ANDN 0x05 85#define IOP_V8_ORN 0x06 86#define IOP_V8_XNOR 0x07 87#define IOP_V8_ADDC 0x08 88#define IOP_V8_UMUL 0x0a 89#define IOP_V8_SMUL 0x0b 90#define IOP_V8_SUBC 0x0c 91#define IOP_V8_UDIV 0x0e 92#define IOP_V8_SDIV 0x0f 93#define IOP_V8_ADDcc 0x10 94#define IOP_V8_ANDcc 0x11 95#define IOP_V8_ORcc 0x12 96#define IOP_V8_XORcc 0x13 97#define IOP_V8_SUBcc 0x14 98#define IOP_V8_ANDNcc 0x15 99#define IOP_V8_ORNcc 0x16 100#define IOP_V8_XNORcc 0x17 101#define IOP_V8_ADDCcc 0x18 102#define IOP_V8_UMULcc 0x1a 103#define IOP_V8_SMULcc 0x1b 104#define IOP_V8_SUBCcc 0x1c 105#define IOP_V8_UDIVcc 0x1e 106#define IOP_V8_SDIVcc 0x1f 107#define IOP_V8_TADDcc 0x20 108#define IOP_V8_TSUBcc 0x21 109#define IOP_V8_TADDccTV 0x22 110#define IOP_V8_TSUBccTV 0x23 111#define IOP_V8_MULScc 0x24 112#define IOP_V8_SLL 0x25 113#define IOP_V8_SRL 0x26 114#define IOP_V8_SRA 0x27 115#define IOP_V8_RDASR 0x28 116#define IOP_V8_POPC 0x2e 117#define IOP_V8_WRASR 0x30 118#define IOP_V8_FCMP 0x35 119#define IOP_V8_JMPL 0x38 120#define IOP_V8_RETT 0x39 121#define IOP_V8_TCC 0x3a 122#define IOP_V8_FLUSH 0x3b 123#define IOP_V8_SAVE 0x3c 124#define IOP_V8_RESTORE 0x3d 125 126/* 127 * Check for a load/store to alternate space. All other ld/st 128 * instructions should have bits 12-5 clear, if the i-bit is 0. 129 */ 130#define IS_LDST_ALT(x) \ 131 (((x) == IOP_V8_LDA || (x) == IOP_V8_LDDA || \ 132 (x) == IOP_V8_LDSBA || (x) == IOP_V8_LDSHA || \ 133 (x) == IOP_V8_LDSTUBA || (x) == IOP_V8_LDUBA || \ 134 (x) == IOP_V8_LDUHA || (x) == IOP_V8_STA || \ 135 (x) == IOP_V8_STBA || (x) == IOP_V8_STDA || \ 136 (x) == IOP_V8_STHA || (x) == IOP_V8_SWAPA) ? 1 : 0) 137 138 139#ifndef _ASM 140 141#include <vm/seg_enum.h> 142 143extern int32_t fetch_user_instr(caddr_t); 144extern int simulate_unimp(struct regs *, caddr_t *); 145extern int simulate_lddstd(struct regs *, caddr_t *); 146extern int simulate_rdtick(struct regs *); 147extern int do_unaligned(struct regs *, caddr_t *); 148extern int calc_memaddr(struct regs *, caddr_t *); 149extern int is_atomic(struct regs *); 150extern int instr_size(struct regs *, caddr_t *, enum seg_rw); 151extern int getreg(struct regs *, uint_t, uint64_t *, caddr_t *); 152extern int putreg(uint64_t *, struct regs *, uint_t, caddr_t *); 153extern int extended_asi_size(int asi); 154 155#endif /* _ASM */ 156 157#ifdef __cplusplus 158} 159#endif 160 161#endif /* _SYS_SIMULATE_H */ 162