x86_archext.h revision 7656:2621e50fdf4a
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_X86_ARCHEXT_H 27#define _SYS_X86_ARCHEXT_H 28 29#if !defined(_ASM) 30#include <sys/regset.h> 31#include <sys/processor.h> 32#include <vm/seg_enum.h> 33#include <vm/page.h> 34#endif /* _ASM */ 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40/* 41 * cpuid instruction feature flags in %edx (standard function 1) 42 */ 43 44#define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 45#define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 46#define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 47#define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 48#define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 49#define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 50#define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 51#define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 52#define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 53#define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 54 /* 0x400 - reserved */ 55#define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 56#define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 57#define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 58#define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 59#define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 60#define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 61#define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 62#define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 63#define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 64 /* 0x100000 - reserved */ 65#define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 66#define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 67#define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 68#define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 69#define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 70#define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 71#define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 72#define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 73#define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 74#define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 75#define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 76 77#define FMT_CPUID_INTC_EDX \ 78 "\20" \ 79 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 80 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 81 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 82 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 83 84/* 85 * cpuid instruction feature flags in %ecx (standard function 1) 86 */ 87 88#define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 89 /* 0x00000002 - reserved */ 90 /* 0x00000004 - reserved */ 91#define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 92#define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 93#define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 94#define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 95#define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 96#define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 97#define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 98#define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 99 /* 0x00000800 - reserved */ 100 /* 0x00001000 - reserved */ 101#define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 102#define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 103 /* 0x00008000 - reserved */ 104 /* 0x00010000 - reserved */ 105 /* 0x00020000 - reserved */ 106#define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 107#define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 108#define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 109#define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 110 111#define FMT_CPUID_INTC_ECX \ 112 "\20" \ 113 "\30popcnt\25sse4.2\24sse4.1\23dca" \ 114 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 115 "\10est\7smx\6vmx\5dscpl\4mon\1sse3" 116 117/* 118 * cpuid instruction feature flags in %edx (extended function 0x80000001) 119 */ 120 121#define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 122#define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 123#define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 124#define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 125#define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 126#define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 127#define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 128#define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 129#define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 130#define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 131 /* 0x00000400 - sysc on K6m6 */ 132#define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 133#define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 134#define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 135#define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 136#define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 137#define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 138#define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 139#define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 140 /* 0x00040000 - reserved */ 141 /* 0x00080000 - reserved */ 142#define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 143 /* 0x00200000 - reserved */ 144#define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 145#define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 146#define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 147#define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 148#define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 149#define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 150 /* 0x10000000 - reserved */ 151#define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 152#define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 153#define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 154 155#define FMT_CPUID_AMD_EDX \ 156 "\20" \ 157 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 158 "\30mmx\27mmxext\25nx\22pse\21pat" \ 159 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 160 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 161 162#define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 163#define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 164#define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 165#define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 166#define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 167#define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 168#define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 169#define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 170#define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 171#define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 172#define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 173#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 174#define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 175#define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 176 177#define FMT_CPUID_AMD_ECX \ 178 "\20" \ 179 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 180 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 181 182/* 183 * Intel now seems to have claimed part of the "extended" function 184 * space that we previously for non-Intel implementors to use. 185 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 186 * is available in long mode i.e. what AMD indicate using bit 0. 187 * On the other hand, everything else is labelled as reserved. 188 */ 189#define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 190 191 192#define P5_MCHADDR 0x0 193#define P5_CESR 0x11 194#define P5_CTR0 0x12 195#define P5_CTR1 0x13 196 197#define K5_MCHADDR 0x0 198#define K5_MCHTYPE 0x01 199#define K5_TSC 0x10 200#define K5_TR12 0x12 201 202#define REG_PAT 0x277 203 204#define REG_MC0_CTL 0x400 205#define REG_MC5_MISC 0x417 206#define REG_PERFCTR0 0xc1 207#define REG_PERFCTR1 0xc2 208 209#define REG_PERFEVNT0 0x186 210#define REG_PERFEVNT1 0x187 211 212#define REG_TSC 0x10 /* timestamp counter */ 213#define REG_APIC_BASE_MSR 0x1b 214#define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 215 216#define MSR_DEBUGCTL 0x1d9 217 218#define DEBUGCTL_LBR 0x01 219#define DEBUGCTL_BTF 0x02 220 221/* Intel P6, AMD */ 222#define MSR_LBR_FROM 0x1db 223#define MSR_LBR_TO 0x1dc 224#define MSR_LEX_FROM 0x1dd 225#define MSR_LEX_TO 0x1de 226 227/* Intel P4 (pre-Prescott, non P4 M) */ 228#define MSR_P4_LBSTK_TOS 0x1da 229#define MSR_P4_LBSTK_0 0x1db 230#define MSR_P4_LBSTK_1 0x1dc 231#define MSR_P4_LBSTK_2 0x1dd 232#define MSR_P4_LBSTK_3 0x1de 233 234/* Intel Pentium M */ 235#define MSR_P6M_LBSTK_TOS 0x1c9 236#define MSR_P6M_LBSTK_0 0x040 237#define MSR_P6M_LBSTK_1 0x041 238#define MSR_P6M_LBSTK_2 0x042 239#define MSR_P6M_LBSTK_3 0x043 240#define MSR_P6M_LBSTK_4 0x044 241#define MSR_P6M_LBSTK_5 0x045 242#define MSR_P6M_LBSTK_6 0x046 243#define MSR_P6M_LBSTK_7 0x047 244 245/* Intel P4 (Prescott) */ 246#define MSR_PRP4_LBSTK_TOS 0x1da 247#define MSR_PRP4_LBSTK_FROM_0 0x680 248#define MSR_PRP4_LBSTK_FROM_1 0x681 249#define MSR_PRP4_LBSTK_FROM_2 0x682 250#define MSR_PRP4_LBSTK_FROM_3 0x683 251#define MSR_PRP4_LBSTK_FROM_4 0x684 252#define MSR_PRP4_LBSTK_FROM_5 0x685 253#define MSR_PRP4_LBSTK_FROM_6 0x686 254#define MSR_PRP4_LBSTK_FROM_7 0x687 255#define MSR_PRP4_LBSTK_FROM_8 0x688 256#define MSR_PRP4_LBSTK_FROM_9 0x689 257#define MSR_PRP4_LBSTK_FROM_10 0x68a 258#define MSR_PRP4_LBSTK_FROM_11 0x68b 259#define MSR_PRP4_LBSTK_FROM_12 0x68c 260#define MSR_PRP4_LBSTK_FROM_13 0x68d 261#define MSR_PRP4_LBSTK_FROM_14 0x68e 262#define MSR_PRP4_LBSTK_FROM_15 0x68f 263#define MSR_PRP4_LBSTK_TO_0 0x6c0 264#define MSR_PRP4_LBSTK_TO_1 0x6c1 265#define MSR_PRP4_LBSTK_TO_2 0x6c2 266#define MSR_PRP4_LBSTK_TO_3 0x6c3 267#define MSR_PRP4_LBSTK_TO_4 0x6c4 268#define MSR_PRP4_LBSTK_TO_5 0x6c5 269#define MSR_PRP4_LBSTK_TO_6 0x6c6 270#define MSR_PRP4_LBSTK_TO_7 0x6c7 271#define MSR_PRP4_LBSTK_TO_8 0x6c8 272#define MSR_PRP4_LBSTK_TO_9 0x6c9 273#define MSR_PRP4_LBSTK_TO_10 0x6ca 274#define MSR_PRP4_LBSTK_TO_11 0x6cb 275#define MSR_PRP4_LBSTK_TO_12 0x6cc 276#define MSR_PRP4_LBSTK_TO_13 0x6cd 277#define MSR_PRP4_LBSTK_TO_14 0x6ce 278#define MSR_PRP4_LBSTK_TO_15 0x6cf 279 280#define MCI_CTL_VALUE 0xffffffff 281 282#define MTRR_TYPE_UC 0 283#define MTRR_TYPE_WC 1 284#define MTRR_TYPE_WT 4 285#define MTRR_TYPE_WP 5 286#define MTRR_TYPE_WB 6 287#define MTRR_TYPE_UC_ 7 288 289/* 290 * For Solaris we set up the page attritubute table in the following way: 291 * PAT0 Write-Back 292 * PAT1 Write-Through 293 * PAT2 Unchacheable- 294 * PAT3 Uncacheable 295 * PAT4 Write-Back 296 * PAT5 Write-Through 297 * PAT6 Write-Combine 298 * PAT7 Uncacheable 299 * The only difference from h/w default is entry 6. 300 */ 301#define PAT_DEFAULT_ATTRIBUTE \ 302 ((uint64_t)MTRR_TYPE_WB | \ 303 ((uint64_t)MTRR_TYPE_WT << 8) | \ 304 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 305 ((uint64_t)MTRR_TYPE_UC << 24) | \ 306 ((uint64_t)MTRR_TYPE_WB << 32) | \ 307 ((uint64_t)MTRR_TYPE_WT << 40) | \ 308 ((uint64_t)MTRR_TYPE_WC << 48) | \ 309 ((uint64_t)MTRR_TYPE_UC << 56)) 310 311#define X86_LARGEPAGE 0x00000001 312#define X86_TSC 0x00000002 313#define X86_MSR 0x00000004 314#define X86_MTRR 0x00000008 315#define X86_PGE 0x00000010 316#define X86_DE 0x00000020 317#define X86_CMOV 0x00000040 318#define X86_MMX 0x00000080 319#define X86_MCA 0x00000100 320#define X86_PAE 0x00000200 321#define X86_CX8 0x00000400 322#define X86_PAT 0x00000800 323#define X86_SEP 0x00001000 324#define X86_SSE 0x00002000 325#define X86_SSE2 0x00004000 326#define X86_HTT 0x00008000 327#define X86_ASYSC 0x00010000 328#define X86_NX 0x00020000 329#define X86_SSE3 0x00040000 330#define X86_CX16 0x00080000 331#define X86_CMP 0x00100000 332#define X86_TSCP 0x00200000 333#define X86_MWAIT 0x00400000 334#define X86_SSE4A 0x00800000 335#define X86_CPUID 0x01000000 336#define X86_SSSE3 0x02000000 337#define X86_SSE4_1 0x04000000 338#define X86_SSE4_2 0x08000000 339#define X86_1GPG 0x10000000 340#define X86_CLFSH 0x20000000 341#define X86_64 0x40000000 342 343/* 344 * flags to patch tsc_read routine. 345 */ 346#define X86_NO_TSC 0x0 347#define X86_HAVE_TSCP 0x1 348#define X86_TSC_MFENCE 0x2 349#define X86_TSC_LFENCE 0x4 350 351#define FMT_X86_FEATURE \ 352 "\20" \ 353 "\34sse4_2\33sse4_1\32ssse3\31cpuid" \ 354 "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\ 355 "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 356 "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 357 358/* 359 * x86_type is a legacy concept; this is supplanted 360 * for most purposes by x86_feature; modern CPUs 361 * should be X86_TYPE_OTHER 362 */ 363#define X86_TYPE_OTHER 0 364#define X86_TYPE_486 1 365#define X86_TYPE_P5 2 366#define X86_TYPE_P6 3 367#define X86_TYPE_CYRIX_486 4 368#define X86_TYPE_CYRIX_6x86L 5 369#define X86_TYPE_CYRIX_6x86 6 370#define X86_TYPE_CYRIX_GXm 7 371#define X86_TYPE_CYRIX_6x86MX 8 372#define X86_TYPE_CYRIX_MediaGX 9 373#define X86_TYPE_CYRIX_MII 10 374#define X86_TYPE_VIA_CYRIX_III 11 375#define X86_TYPE_P4 12 376 377/* 378 * x86_vendor allows us to select between 379 * implementation features and helps guide 380 * the interpretation of the cpuid instruction. 381 */ 382#define X86_VENDOR_Intel 0 383#define X86_VENDORSTR_Intel "GenuineIntel" 384 385#define X86_VENDOR_IntelClone 1 386 387#define X86_VENDOR_AMD 2 388#define X86_VENDORSTR_AMD "AuthenticAMD" 389 390#define X86_VENDOR_Cyrix 3 391#define X86_VENDORSTR_CYRIX "CyrixInstead" 392 393#define X86_VENDOR_UMC 4 394#define X86_VENDORSTR_UMC "UMC UMC UMC " 395 396#define X86_VENDOR_NexGen 5 397#define X86_VENDORSTR_NexGen "NexGenDriven" 398 399#define X86_VENDOR_Centaur 6 400#define X86_VENDORSTR_Centaur "CentaurHauls" 401 402#define X86_VENDOR_Rise 7 403#define X86_VENDORSTR_Rise "RiseRiseRise" 404 405#define X86_VENDOR_SiS 8 406#define X86_VENDORSTR_SiS "SiS SiS SiS " 407 408#define X86_VENDOR_TM 9 409#define X86_VENDORSTR_TM "GenuineTMx86" 410 411#define X86_VENDOR_NSC 10 412#define X86_VENDORSTR_NSC "Geode by NSC" 413 414/* 415 * Vendor string max len + \0 416 */ 417#define X86_VENDOR_STRLEN 13 418 419/* 420 * Some vendor/family/model/stepping ranges are commonly grouped under 421 * a single identifying banner by the vendor. The following encode 422 * that "revision" in a uint32_t with the 8 most significant bits 423 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 424 * family, and the remaining 16 typically forming a bitmask of revisions 425 * within that family with more significant bits indicating "later" revisions. 426 */ 427 428#define _X86_CHIPREV_VENDOR_MASK 0xff000000u 429#define _X86_CHIPREV_VENDOR_SHIFT 24 430#define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 431#define _X86_CHIPREV_FAMILY_SHIFT 16 432#define _X86_CHIPREV_REV_MASK 0x0000ffffu 433 434#define _X86_CHIPREV_VENDOR(x) \ 435 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 436#define _X86_CHIPREV_FAMILY(x) \ 437 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 438#define _X86_CHIPREV_REV(x) \ 439 ((x) & _X86_CHIPREV_REV_MASK) 440 441/* True if x matches in vendor and family and if x matches the given rev mask */ 442#define X86_CHIPREV_MATCH(x, mask) \ 443 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 444 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 445 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 446 447/* True if x matches in vendor and family and rev is at least minx */ 448#define X86_CHIPREV_ATLEAST(x, minx) \ 449 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 450 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 451 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 452 453#define _X86_CHIPREV_MKREV(vendor, family, rev) \ 454 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 455 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 456 457/* Revision default */ 458#define X86_CHIPREV_UNKNOWN 0x0 459 460/* 461 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 462 * sufficiently different that we will distinguish them; in all other 463 * case we will identify the major revision. 464 */ 465#define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 466#define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 467#define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 468#define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 469#define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 470#define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 471#define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 472 473/* 474 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 475 */ 476#define X86_CHIPREV_AMD_10_REV_A \ 477 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 478#define X86_CHIPREV_AMD_10_REV_B \ 479 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 480 481/* 482 * Various socket/package types, extended as the need to distinguish 483 * a new type arises. The top 8 byte identfies the vendor and the 484 * remaining 24 bits describe 24 socket types. 485 */ 486 487#define _X86_SOCKET_VENDOR_SHIFT 24 488#define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 489#define _X86_SOCKET_TYPE_MASK 0x00ffffff 490#define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 491 492#define _X86_SOCKET_MKVAL(vendor, bitval) \ 493 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 494 495#define X86_SOCKET_MATCH(s, mask) \ 496 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 497 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 498 499#define X86_SOCKET_UNKNOWN 0x0 500 /* 501 * AMD socket types 502 */ 503#define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 504#define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 505#define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 506#define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 507#define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 508#define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 509 510#if !defined(_ASM) 511 512#if defined(_KERNEL) || defined(_KMEMUSER) 513 514extern uint_t x86_feature; 515extern uint_t x86_type; 516extern uint_t x86_vendor; 517extern uint_t x86_clflush_size; 518 519extern uint_t pentiumpro_bug4046376; 520extern uint_t pentiumpro_bug4064495; 521 522extern uint_t enable486; 523 524extern const char CyrixInstead[]; 525 526#endif 527 528#if defined(_KERNEL) 529 530/* 531 * This structure is used to pass arguments and get return values back 532 * from the CPUID instruction in __cpuid_insn() routine. 533 */ 534struct cpuid_regs { 535 uint32_t cp_eax; 536 uint32_t cp_ebx; 537 uint32_t cp_ecx; 538 uint32_t cp_edx; 539}; 540 541extern uint64_t rdmsr(uint_t); 542extern void wrmsr(uint_t, const uint64_t); 543extern uint64_t xrdmsr(uint_t); 544extern void xwrmsr(uint_t, const uint64_t); 545extern int checked_rdmsr(uint_t, uint64_t *); 546extern int checked_wrmsr(uint_t, uint64_t); 547 548extern void invalidate_cache(void); 549extern ulong_t getcr4(void); 550extern void setcr4(ulong_t); 551 552extern void mtrr_sync(void); 553 554extern void cpu_fast_syscall_enable(void *); 555extern void cpu_fast_syscall_disable(void *); 556 557struct cpu; 558 559extern int cpuid_checkpass(struct cpu *, int); 560extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 561extern uint32_t __cpuid_insn(struct cpuid_regs *); 562extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 563extern int cpuid_getidstr(struct cpu *, char *, size_t); 564extern const char *cpuid_getvendorstr(struct cpu *); 565extern uint_t cpuid_getvendor(struct cpu *); 566extern uint_t cpuid_getfamily(struct cpu *); 567extern uint_t cpuid_getmodel(struct cpu *); 568extern uint_t cpuid_getstep(struct cpu *); 569extern uint_t cpuid_getsig(struct cpu *); 570extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 571extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 572extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 573extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 574extern int cpuid_get_chipid(struct cpu *); 575extern id_t cpuid_get_coreid(struct cpu *); 576extern int cpuid_get_pkgcoreid(struct cpu *); 577extern int cpuid_get_clogid(struct cpu *); 578extern int cpuid_is_cmt(struct cpu *); 579extern int cpuid_syscall32_insn(struct cpu *); 580extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 581 582extern uint32_t cpuid_getchiprev(struct cpu *); 583extern const char *cpuid_getchiprevstr(struct cpu *); 584extern uint32_t cpuid_getsockettype(struct cpu *); 585 586extern int cpuid_opteron_erratum(struct cpu *, uint_t); 587 588struct cpuid_info; 589 590extern void setx86isalist(void); 591extern void cpuid_alloc_space(struct cpu *); 592extern void cpuid_free_space(struct cpu *); 593extern uint_t cpuid_pass1(struct cpu *); 594extern void cpuid_pass2(struct cpu *); 595extern void cpuid_pass3(struct cpu *); 596extern uint_t cpuid_pass4(struct cpu *); 597extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 598 599extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 600extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 601 602#if !defined(__xpv) 603extern uint32_t *cpuid_mwait_alloc(struct cpu *); 604extern void cpuid_mwait_free(struct cpu *); 605#endif 606 607struct cpu_ucode_info; 608 609extern void ucode_alloc_space(struct cpu *); 610extern void ucode_free_space(struct cpu *); 611extern void ucode_check(struct cpu *); 612extern void ucode_cleanup(); 613 614#if !defined(__xpv) 615extern char _tsc_mfence_start; 616extern char _tsc_mfence_end; 617extern char _tscp_start; 618extern char _tscp_end; 619extern char _no_rdtsc_start; 620extern char _no_rdtsc_end; 621extern char _tsc_lfence_start; 622extern char _tsc_lfence_end; 623#endif 624 625extern uint_t workaround_errata(struct cpu *); 626 627#if defined(OPTERON_ERRATUM_93) 628extern int opteron_erratum_93; 629#endif 630 631#if defined(OPTERON_ERRATUM_91) 632extern int opteron_erratum_91; 633#endif 634 635#if defined(OPTERON_ERRATUM_100) 636extern int opteron_erratum_100; 637#endif 638 639#if defined(OPTERON_ERRATUM_121) 640extern int opteron_erratum_121; 641#endif 642 643#if defined(OPTERON_WORKAROUND_6323525) 644extern int opteron_workaround_6323525; 645extern void patch_workaround_6323525(void); 646#endif 647 648#endif /* _KERNEL */ 649 650#endif 651 652#ifdef __cplusplus 653} 654#endif 655 656#endif /* _SYS_X86_ARCHEXT_H */ 657