radeon_irq.c revision 6393:0b9cb6400a73 
1
2/*
3 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
4 * Use is subject to license terms.
5 */
6/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
7/*
8 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
9 *
10 * The Weather Channel (TM) funded Tungsten Graphics to develop the
11 * initial release of the Radeon 8500 driver under the XFree86 license.
12 * This notice must be preserved.
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
23 * Software.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
28 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31 * DEALINGS IN THE SOFTWARE.
32 *
33 * Authors:
34 *    Keith Whitwell <keith@tungstengraphics.com>
35 *    Michel D���zer <michel@daenzer.net>
36 */
37
38#pragma ident	"%Z%%M%	%I%	%E% SMI"
39
40#include "drmP.h"
41#include "radeon_drm.h"
42#include "radeon_drv.h"
43#include "radeon_io32.h"
44
45static inline u32
46radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
47{
48	uint32_t irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
49	if (irqs)
50		RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
51	return (irqs);
52}
53
54/*
55 * Interrupts - Used for device synchronization and flushing in the
56 * following circumstances:
57 *
58 * - Exclusive FB access with hw idle:
59 *    - Wait for GUI Idle (?) interrupt, then do normal flush.
60 *
61 * - Frame throttling, NV_fence:
62 *    - Drop marker irq's into command stream ahead of time.
63 *    - Wait on irq's with lock *not held*
64 *    - Check each for termination condition
65 *
66 * - Internally in cp_getbuffer, etc:
67 *    - as above, but wait with lock held???
68 *
69 * NOTE: These functions are misleadingly named -- the irq's aren't
70 * tied to dma at all, this is just a hangover from dri prehistory.
71 */
72
73irqreturn_t
74radeon_driver_irq_handler(DRM_IRQ_ARGS)
75{
76	drm_device_t *dev = (drm_device_t *)(uintptr_t)arg;
77	drm_radeon_private_t *dev_priv =
78	    (drm_radeon_private_t *)dev->dev_private;
79	u32 stat;
80
81	/*
82	 * Only consider the bits we're interested in - others could be used
83	 * outside the DRM
84	 */
85	stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
86	    RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT));
87	if (!stat)
88		return (IRQ_NONE);
89
90	stat &= dev_priv->irq_enable_reg;
91
92	/* SW interrupt */
93	if (stat & RADEON_SW_INT_TEST) {
94		DRM_WAKEUP(&dev_priv->swi_queue);
95	}
96
97	/* VBLANK interrupt */
98	if (stat & (RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT)) {
99		int vblank_crtc = dev_priv->vblank_crtc;
100
101		if ((vblank_crtc &
102		    (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
103		    (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
104			if (stat & RADEON_CRTC_VBLANK_STAT)
105				atomic_inc(&dev->vbl_received);
106			if (stat & RADEON_CRTC2_VBLANK_STAT)
107				atomic_inc(&dev->vbl_received2);
108		} else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
109		    (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
110		    ((stat & RADEON_CRTC2_VBLANK_STAT) &&
111		    (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
112			atomic_inc(&dev->vbl_received);
113
114		DRM_WAKEUP(&dev->vbl_queue);
115		drm_vbl_send_signals(dev);
116	}
117
118	return (IRQ_HANDLED);
119}
120
121static int radeon_emit_irq(drm_device_t *dev)
122{
123	drm_radeon_private_t *dev_priv = dev->dev_private;
124	unsigned int ret;
125	RING_LOCALS;
126
127	atomic_inc(&dev_priv->swi_emitted);
128	ret = atomic_read(&dev_priv->swi_emitted);
129
130	BEGIN_RING(4);
131	OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
132	OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
133	ADVANCE_RING();
134	COMMIT_RING();
135
136	return (ret);
137}
138
139static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
140{
141	drm_radeon_private_t *dev_priv =
142	    (drm_radeon_private_t *)dev->dev_private;
143	int ret = 0;
144
145	if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
146		return (0);
147
148	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
149
150	DRM_WAIT_ON(ret, &dev_priv->swi_queue, 3 * DRM_HZ,
151	    RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
152
153	return (ret);
154}
155
156static int radeon_driver_vblank_do_wait(struct drm_device *dev,
157					unsigned int *sequence, int crtc)
158{
159	drm_radeon_private_t *dev_priv =
160	    (drm_radeon_private_t *)dev->dev_private;
161	unsigned int cur_vblank;
162	int ret = 0;
163	atomic_t *counter;
164	if (!dev_priv) {
165		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
166		return (EINVAL);
167	}
168
169	/*
170	 * I don't know why reset Intr Status Register here,
171	 * it might miss intr. So, I remove the code which
172	 * exists in open source, and changes as follows:
173	 */
174
175	if (crtc == DRM_RADEON_VBLANK_CRTC1) {
176		counter = &dev->vbl_received;
177	} else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
178		counter = &dev->vbl_received2;
179	} else
180		return (EINVAL);
181
182	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
183
184	/*
185	 * Assume that the user has missed the current sequence number
186	 * by about a day rather than she wants to wait for years
187	 * using vertical blanks...
188	 */
189	DRM_WAIT_ON(ret, &dev->vbl_queue, 3 * DRM_HZ,
190	    (((cur_vblank = atomic_read(counter)) - *sequence) <= (1 << 23)));
191
192	*sequence = cur_vblank;
193
194	return (ret);
195}
196
197int
198radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
199{
200	return (radeon_driver_vblank_do_wait(dev, sequence,
201	    DRM_RADEON_VBLANK_CRTC1));
202}
203
204int
205radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
206{
207	return (radeon_driver_vblank_do_wait(dev, sequence,
208	    DRM_RADEON_VBLANK_CRTC2));
209}
210
211/*
212 * Needs the lock as it touches the ring.
213 */
214/*ARGSUSED*/
215int
216radeon_irq_emit(DRM_IOCTL_ARGS)
217{
218	DRM_DEVICE;
219	drm_radeon_private_t *dev_priv = dev->dev_private;
220	drm_radeon_irq_emit_t emit;
221	int result;
222
223	LOCK_TEST_WITH_RETURN(dev, fpriv);
224
225	if (!dev_priv) {
226		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
227		return (EINVAL);
228	}
229
230#ifdef _MULTI_DATAMODEL
231	if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
232		drm_radeon_irq_emit_32_t emit32;
233
234		DRM_COPYFROM_WITH_RETURN(&emit32, (void *) data,
235		    sizeof (emit32));
236		emit.irq_seq = (void *)(uintptr_t)(emit32.irq_seq);
237	} else {
238#endif
239
240		DRM_COPYFROM_WITH_RETURN(&emit, (void *) data, sizeof (emit));
241#ifdef _MULTI_DATAMODEL
242}
243#endif
244
245	result = radeon_emit_irq(dev);
246
247	if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof (int))) {
248		DRM_ERROR("copy_to_user\n");
249		return (EFAULT);
250	}
251
252	return (0);
253}
254
255/*
256 * Doesn't need the hardware lock.
257 */
258/*ARGSUSED*/
259int
260radeon_irq_wait(DRM_IOCTL_ARGS)
261{
262	DRM_DEVICE;
263	drm_radeon_private_t *dev_priv = dev->dev_private;
264	drm_radeon_irq_wait_t irqwait;
265
266	if (!dev_priv) {
267		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
268		return (EINVAL);
269	}
270
271	DRM_COPYFROM_WITH_RETURN(&irqwait, (void *) data, sizeof (irqwait));
272
273	return (radeon_wait_irq(dev, irqwait.irq_seq));
274}
275
276static void radeon_enable_interrupt(struct drm_device *dev)
277{
278	drm_radeon_private_t *dev_priv;
279
280	dev_priv = (drm_radeon_private_t *)dev->dev_private;
281	dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
282
283	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1) {
284		dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
285	}
286
287	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2) {
288		dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
289	}
290
291	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
292	dev_priv->irq_enabled = 1;
293}
294
295
296/*
297 * drm_dma.h hooks
298 */
299void
300radeon_driver_irq_preinstall(drm_device_t *dev)
301{
302	drm_radeon_private_t *dev_priv =
303	    (drm_radeon_private_t *)dev->dev_private;
304
305	/* Disable *all* interrupts */
306	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
307
308	/* Clear bits if they're already high */
309	(void) radeon_acknowledge_irqs(dev_priv,
310	    (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT |
311	    RADEON_CRTC2_VBLANK_STAT));
312}
313
314void
315radeon_driver_irq_postinstall(drm_device_t *dev)
316{
317	drm_radeon_private_t *dev_priv =
318	    (drm_radeon_private_t *)dev->dev_private;
319
320	atomic_set(&dev_priv->swi_emitted, 0);
321	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue, DRM_INTR_PRI(dev));
322
323	radeon_enable_interrupt(dev);
324}
325
326void
327radeon_driver_irq_uninstall(drm_device_t *dev)
328{
329	drm_radeon_private_t *dev_priv =
330	    (drm_radeon_private_t *)dev->dev_private;
331	if (!dev_priv)
332		return;
333
334	/* Disable *all* interrupts */
335	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
336	DRM_FINI_WAITQUEUE(&dev_priv->swi_queue);
337}
338
339int
340radeon_vblank_crtc_get(drm_device_t *dev)
341{
342	drm_radeon_private_t *dev_priv;
343	u32 flag;
344	u32 value;
345
346	dev_priv = (drm_radeon_private_t *)dev->dev_private;
347	flag = RADEON_READ(RADEON_GEN_INT_CNTL);
348	value = 0;
349
350	if (flag & RADEON_CRTC_VBLANK_MASK)
351		value |= DRM_RADEON_VBLANK_CRTC1;
352
353	if (flag & RADEON_CRTC2_VBLANK_MASK)
354		value |= DRM_RADEON_VBLANK_CRTC2;
355	return (value);
356}
357
358int
359radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
360{
361	drm_radeon_private_t *dev_priv;
362
363	dev_priv = (drm_radeon_private_t *)dev->dev_private;
364	if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
365		DRM_ERROR("called with invalid crtc 0x%x\n",
366		    (unsigned int)value);
367		return (EINVAL);
368	}
369	dev_priv->vblank_crtc = (unsigned int)value;
370	radeon_enable_interrupt(dev);
371	return (0);
372}
373