ata_common.h revision 8550:0cc93b5e7ddc
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _ATA_COMMON_H 28#define _ATA_COMMON_H 29 30#ifdef __cplusplus 31extern "C" { 32#endif 33 34#include <sys/varargs.h> 35 36#include <sys/scsi/scsi.h> 37#include <sys/dktp/dadkio.h> 38#include <sys/dktp/dadev.h> 39#include <sys/dkio.h> 40#include <sys/dktp/tgdk.h> 41 42#include <sys/ddi.h> 43#include <sys/sunddi.h> 44 45#include "ghd.h" 46 47#include "pciide.h" 48#include "ata_cmd.h" 49#include "ata_fsm.h" 50#include "ata_debug.h" 51 52 53/* 54 * device types 55 */ 56#define ATA_DEV_NONE 0 57#define ATA_DEV_DISK 1 58#define ATA_DEV_ATAPI 2 59 60/* 61 * Largest sector allowed in 28 bit mode 62 */ 63#define MAX_28BIT_CAPACITY 0xfffffff 64 65/* 66 * Largest sector count allowed for device firmware file in one command. 67 */ 68#define MAX_FWFILE_SIZE_ONECMD 0xffff 69 70/* 71 * ata-options property configuration bits 72 */ 73 74#define ATA_OPTIONS_DMA 0x01 75 76#define ATAPRT(fmt) ghd_err fmt 77 78/* ad_flags (per-drive) */ 79 80#define AD_ATAPI 0x01 /* is an ATAPI drive */ 81#define AD_DISK 0x02 82#define AD_MUTEX_INIT 0x04 83#define AD_NO_CDB_INTR 0x20 84#define AD_1SECTOR 0x40 85#define AD_INT13LBA 0x80 /* supports LBA at Int13 interface */ 86#define AD_NORVRT 0x100 /* block revert-to-defaults */ 87#define AD_EXT48 0x200 /* 48 bit (extended) LBA */ 88#define AD_BLLBA48 0x400 89#define ATAPIDRV(X) ((X)->ad_flags & AD_ATAPI) 90 91 92/* max targets and luns */ 93 94#define ATA_MAXTARG 2 95#define ATA_MAXLUN 16 96 97/* 98 * PCI-IDE Bus Mastering Scatter/Gather list size 99 */ 100#define ATA_DMA_NSEGS 17 /* enough for at least 64K */ 101 102/* 103 * Controller port address defaults 104 */ 105#define ATA_BASE0 0x1f0 106#define ATA_BASE1 0x170 107 108/* 109 * port offsets from base address ioaddr1 110 */ 111#define AT_DATA 0x00 /* data register */ 112#define AT_ERROR 0x01 /* error register (read) */ 113#define AT_FEATURE 0x01 /* features (write) */ 114#define AT_COUNT 0x02 /* sector count */ 115#define AT_SECT 0x03 /* sector number */ 116#define AT_LCYL 0x04 /* cylinder low byte */ 117#define AT_HCYL 0x05 /* cylinder high byte */ 118#define AT_DRVHD 0x06 /* drive/head register */ 119#define AT_STATUS 0x07 /* status/command register */ 120#define AT_CMD 0x07 /* status/command register */ 121 122/* 123 * port offsets from base address ioaddr2 124 */ 125#define AT_ALTSTATUS 0x00 /* alternate status (read) */ 126#define AT_DEVCTL 0x00 /* device control (write) */ 127 128/* Device control register */ 129#define ATDC_NIEN 0x02 /* disable interrupts */ 130#define ATDC_SRST 0x04 /* controller reset */ 131#define ATDC_D3 0x08 /* Mysterious bit, must be set */ 132/* 133 * ATA-6 spec 134 * In 48-bit addressing, reading the LBA location and count 135 * registers when the high-order bit is set reads the "previous 136 * content" (LBA bits 47:24, count bits 15:8) instead of the 137 * "most recent" values (LBA bits 23:0, count bits 7:0). 138 */ 139#define ATDC_HOB 0x80 /* High order bit */ 140 141/* 142 * Status bits from AT_STATUS register 143 */ 144#define ATS_BSY 0x80 /* controller busy */ 145#define ATS_DRDY 0x40 /* drive ready */ 146#define ATS_DF 0x20 /* device fault */ 147#define ATS_DSC 0x10 /* seek operation complete */ 148#define ATS_DRQ 0x08 /* data request */ 149#define ATS_CORR 0x04 /* ECC correction applied */ 150#define ATS_IDX 0x02 /* disk revolution index */ 151#define ATS_ERR 0x01 /* error flag */ 152 153/* 154 * Status bits from AT_ERROR register 155 */ 156#define ATE_BBK_ICRC 0x80 /* bad block detected in ATA-1 */ 157 /* ICRC error in ATA-4 and newer */ 158#define ATE_UNC 0x40 /* uncorrectable data error */ 159#define ATE_MC 0x20 /* Media change */ 160#define ATE_IDNF 0x10 /* ID not found */ 161#define ATE_MCR 0x08 /* media change request */ 162#define ATE_ABORT 0x04 /* aborted command */ 163#define ATE_TKONF 0x02 /* track 0 not found */ 164#define ATE_AMNF 0x01 /* address mark not found */ 165 166#define ATE_NM 0x02 /* no media */ 167 168/* 169 * Drive selectors for AT_DRVHD register 170 */ 171#define ATDH_LBA 0x40 /* addressing in LBA mode not chs */ 172#define ATDH_DRIVE0 0xa0 /* or into AT_DRVHD to select drive 0 */ 173#define ATDH_DRIVE1 0xb0 /* or into AT_DRVHD to select drive 1 */ 174 175/* 176 * Feature register bits 177 */ 178#define ATF_ATAPI_DMA 0x01 /* ATAPI DMA enable bit */ 179#define ATF_XFRMOD_MDMA 0x20 /* Multi-Word DMA mode */ 180#define ATF_XFRMOD_UDMA 0x40 /* Ultra DMA mode */ 181#define ATACM_UDMA_SEL(id) (((id)->ai_ultradma >> 8) & 0x7f) 182 183/* 184 * Set feature register definitions. 185 */ 186#define ATSF_SET_XFRMOD 0X03 /* Set transfer mode */ 187#define ATSF_DIS_REVPOD 0x66 /* Disable reverting to power on defaults */ 188#define ATSF_ENA_REVPOD 0xcc /* Enable reverting to power on defaults */ 189 190/* 191 * common bits and options for set features (ATC_SET_FEAT) 192 */ 193#define FC_WRITE_CACHE_ON 0x02 194#define FC_WRITE_CACHE_OFF 0x82 195 196/* Test which version of ATA is supported */ 197#define IS_ATA_VERSION_SUPPORTED(idp, n) \ 198 ((idp->ai_majorversion != 0xffff) && \ 199 (idp->ai_majorversion & (1<<n))) 200 201/* Test if supported version >= ATA-n */ 202#define IS_ATA_VERSION_GE(idp, n) \ 203 ((idp->ai_majorversion != 0xffff) && \ 204 (idp->ai_majorversion != 0) && \ 205 (idp->ai_majorversion >= (1<<n))) 206 207/* Test whether a device is a CD drive */ 208#define IS_CDROM(dp) \ 209 ((dp->ad_flags & AD_ATAPI) && \ 210 ((dp->ad_id.ai_config >> 8) & DTYPE_MASK) == \ 211 DTYPE_RODIRECT) 212 213/* macros from old common hba code */ 214 215#define ATA_INTPROP(devi, pname, pval, plen) \ 216 (ddi_prop_op(DDI_DEV_T_ANY, (devi), PROP_LEN_AND_VAL_BUF, \ 217 DDI_PROP_DONTPASS, (pname), (caddr_t)(pval), (plen))) 218 219#define ATA_LONGPROP(devi, pname, pval, plen) \ 220 (ddi_getlongprop(DDI_DEV_T_ANY, (devi), DDI_PROP_DONTPASS, \ 221 (pname), (caddr_t)(pval), (plen))) 222 223/* 224 * 225 * per-controller soft-state data structure 226 * 227 */ 228 229#define CTL2DRV(cp, t, l) (cp->ac_drvp[t][l]) 230 231typedef struct ata_ctl { 232 233 dev_info_t *ac_dip; 234 uint_t ac_flags; 235 uint_t ac_timing_flags; 236 struct ata_drv *ac_drvp[ATA_MAXTARG][ATA_MAXLUN]; 237 int ac_max_transfer; /* max transfer in sectors */ 238 uint_t ac_standby_time; /* timer value seconds */ 239 240 ccc_t ac_ccc; /* for GHD module */ 241 struct ata_drv *ac_active_drvp; /* active drive, if any */ 242 struct ata_pkt *ac_active_pktp; /* active packet, if any */ 243 uchar_t ac_state; 244 245 scsi_hba_tran_t *ac_atapi_tran; /* for atapi module */ 246 247 /* 248 * port addresses associated with ioaddr1 249 */ 250 ddi_acc_handle_t ac_iohandle1; /* DDI I/O handle */ 251 caddr_t ac_ioaddr1; 252 ushort_t *ac_data; /* data register */ 253 uchar_t *ac_error; /* error register (read) */ 254 uchar_t *ac_feature; /* features (write) */ 255 uchar_t *ac_count; /* sector count */ 256 uchar_t *ac_sect; /* sector number */ 257 uchar_t *ac_lcyl; /* cylinder low byte */ 258 uchar_t *ac_hcyl; /* cylinder high byte */ 259 uchar_t *ac_drvhd; /* drive/head register */ 260 uchar_t *ac_status; /* status/command register */ 261 uchar_t *ac_cmd; /* status/command register */ 262 263 /* 264 * port addresses associated with ioaddr2 265 */ 266 ddi_acc_handle_t ac_iohandle2; /* DDI I/O handle */ 267 caddr_t ac_ioaddr2; 268 uchar_t *ac_altstatus; /* alternate status (read) */ 269 uchar_t *ac_devctl; /* device control (write) */ 270 271 /* 272 * handle and port addresss for PCI-IDE Bus Master controller 273 */ 274 ddi_acc_handle_t ac_bmhandle; /* DDI I/O handle */ 275 caddr_t ac_bmaddr; /* base addr of Bus Master Regs */ 276 uchar_t ac_pciide; /* PCI-IDE device */ 277 uchar_t ac_pciide_bm; /* Bus Mastering PCI-IDE device */ 278 279 /* 280 * Scatter/Gather list for PCI-IDE Bus Mastering controllers 281 */ 282 caddr_t ac_sg_list; /* virtual addr of S/G list */ 283 paddr_t ac_sg_paddr; /* phys addr of S/G list */ 284 ddi_acc_handle_t ac_sg_acc_handle; 285 ddi_dma_handle_t ac_sg_handle; 286 287 /* 288 * data for managing ARQ on ATAPI devices 289 */ 290 struct ata_pkt *ac_arq_pktp; /* pkt for performing ATAPI ARQ */ 291 struct ata_pkt *ac_fault_pktp; /* pkt that caused ARQ */ 292 uchar_t ac_arq_cdb[6]; 293 294 /* 295 * Power Management 296 */ 297 int ac_pm_support; 298 int ac_pm_level; 299} ata_ctl_t; 300 301/* ac_flags (per-controller) */ 302 303#define AC_GHD_INIT 0x02 304#define AC_ATAPI_INIT 0x04 305#define AC_DISK_INIT 0x08 306#define AC_ATTACHED 0x10 307#define AC_SCSI_HBA_TRAN_ALLOC 0x1000 308#define AC_SCSI_HBA_ATTACH 0x2000 309 310#define AC_BMSTATREG_PIO_BROKEN 0x80000000 311 312/* 313 * Bug 1256489: 314 * 315 * If AC_BSY_WAIT needs to be set for laptops that do 316 * suspend/resume but do not correctly wait for the busy bit to 317 * drop after a resume. 318 */ 319 320/* ac_timing_flags (per-controller) */ 321#define AC_BSY_WAIT 0x1 /* tweak timing in ata_start & atapi_start */ 322 323 324 325/* Identify drive data */ 326struct ata_id { 327/* WORD */ 328/* OFFSET COMMENT */ 329 ushort_t ai_config; /* 0 general configuration bits */ 330 ushort_t ai_fixcyls; /* 1 # of fixed cylinders */ 331 ushort_t ai_resv0; /* 2 # reserved */ 332 ushort_t ai_heads; /* 3 # of heads */ 333 ushort_t ai_trksiz; /* 4 # of unformatted bytes/track */ 334 ushort_t ai_secsiz; /* 5 # of unformatted bytes/sector */ 335 ushort_t ai_sectors; /* 6 # of sectors/track */ 336 ushort_t ai_resv1[3]; /* 7 "Vendor Unique" */ 337 char ai_drvser[20]; /* 10 Serial number */ 338 ushort_t ai_buftype; /* 20 Buffer type */ 339 ushort_t ai_bufsz; /* 21 Buffer size in 512 byte incr */ 340 ushort_t ai_ecc; /* 22 # of ecc bytes avail on rd/wr */ 341 char ai_fw[8]; /* 23 Firmware revision */ 342 char ai_model[40]; /* 27 Model # */ 343 ushort_t ai_mult1; /* 47 Multiple command flags */ 344 ushort_t ai_dwcap; /* 48 Doubleword capabilities */ 345 ushort_t ai_cap; /* 49 Capabilities */ 346 ushort_t ai_resv2; /* 50 Reserved */ 347 ushort_t ai_piomode; /* 51 PIO timing mode */ 348 ushort_t ai_dmamode; /* 52 DMA timing mode */ 349 ushort_t ai_validinfo; /* 53 bit0: wds 54-58, bit1: 64-70 */ 350 ushort_t ai_curcyls; /* 54 # of current cylinders */ 351 ushort_t ai_curheads; /* 55 # of current heads */ 352 ushort_t ai_cursectrk; /* 56 # of current sectors/track */ 353 ushort_t ai_cursccp[2]; /* 57 current sectors capacity */ 354 ushort_t ai_mult2; /* 59 multiple sectors info */ 355 ushort_t ai_addrsec[2]; /* 60 LBA only: no of addr secs */ 356 ushort_t ai_sworddma; /* 62 single word dma modes */ 357 ushort_t ai_dworddma; /* 63 double word dma modes */ 358 ushort_t ai_advpiomode; /* 64 advanced PIO modes supported */ 359 ushort_t ai_minmwdma; /* 65 min multi-word dma cycle info */ 360 ushort_t ai_recmwdma; /* 66 rec multi-word dma cycle info */ 361 ushort_t ai_minpio; /* 67 min PIO cycle info */ 362 ushort_t ai_minpioflow; /* 68 min PIO cycle info w/flow ctl */ 363 ushort_t ai_resv3[2]; /* 69,70 reserved */ 364 ushort_t ai_resv4[4]; /* 71-74 reserved */ 365 ushort_t ai_qdepth; /* 75 queue depth */ 366 ushort_t ai_resv5[4]; /* 76-79 reserved */ 367 ushort_t ai_majorversion; /* 80 major versions supported */ 368 ushort_t ai_minorversion; /* 81 minor version number supported */ 369 ushort_t ai_cmdset82; /* 82 command set supported */ 370 ushort_t ai_cmdset83; /* 83 more command sets supported */ 371 ushort_t ai_cmdset84; /* 84 more command sets supported */ 372 ushort_t ai_features85; /* 85 enabled features */ 373 ushort_t ai_features86; /* 86 enabled features */ 374 ushort_t ai_features87; /* 87 enabled features */ 375 ushort_t ai_ultradma; /* 88 Ultra DMA mode */ 376 ushort_t ai_erasetime; /* 89 security erase time */ 377 ushort_t ai_erasetimex; /* 90 enhanced security erase time */ 378 ushort_t ai_padding1[9]; /* pad through 99 */ 379 ushort_t ai_addrsecxt[4]; /* 100 extended max LBA sector */ 380 ushort_t ai_padding2[22]; /* pad to 126 */ 381 ushort_t ai_lastlun; /* 126 last LUN, as per SFF-8070i */ 382 ushort_t ai_resv6; /* 127 reserved */ 383 ushort_t ai_securestatus; /* 128 security status */ 384 ushort_t ai_vendor[31]; /* 129-159 vendor specific */ 385 ushort_t ai_padding3[16]; /* 160 pad to 176 */ 386 ushort_t ai_curmedser[30]; /* 176-205 current media serial number */ 387 ushort_t ai_padding4[49]; /* 206 pad to 255 */ 388 ushort_t ai_integrity; /* 255 integrity word */ 389}; 390 391/* Identify Drive: general config bits - word 0 */ 392 393#define ATA_ID_REM_DRV 0x80 394#define ATA_ID_COMPACT_FLASH 0x848a 395#define ATA_ID_CF_TO_ATA 0x040a 396#define ATA_ID_INCMPT 0x0004 397 398/* Identify Drive: common capability bits - word 49 */ 399 400#define ATAC_DMA_SUPPORT 0x0100 401#define ATAC_LBA_SUPPORT 0x0200 402#define ATAC_IORDY_DISABLE 0x0400 403#define ATAC_IORDY_SUPPORT 0x0800 404#define ATAC_RESERVED_IDPKT 0x1000 /* rsrvd for identify pkt dev */ 405#define ATAC_STANDBYTIMER 0x2000 406#define ATAC_ATA_TYPE_MASK 0x8001 407#define ATAC_ATA_TYPE 0x0000 408#define ATAC_ATAPI_TYPE_MASK 0xc000 409#define ATAC_ATAPI_TYPE 0x8000 410 411/* Identify Driver ai_validinfo (word 53) */ 412 413#define ATAC_VALIDINFO_83 0x0004 /* word 83 supported fields valid */ 414#define ATAC_VALIDINFO_70_64 0x0002 /* word 70:64 sup. fields valid */ 415 416/* Identify Drive: ai_dworddma (word 63) */ 417 418#define ATAC_MDMA_SUP_MASK 0x0007 /* Multiword DMA supported */ 419#define ATAC_MDMA_SEL_MASK 0x0700 /* Multiword DMA selected */ 420#define ATAC_MDMA_2_SEL 0x0400 /* Multiword DMA mode 2 selected */ 421#define ATAC_MDMA_1_SEL 0x0200 /* Multiword DMA mode 1 selected */ 422#define ATAC_MDMA_0_SEL 0x0100 /* Multiword DMA mode 0 selected */ 423#define ATAC_MDMA_2_SUP 0x0004 /* Multiword DMA mode 2 supported */ 424#define ATAC_MDMA_1_SUP 0x0002 /* Multiword DMA mode 1 supported */ 425#define ATAC_MDMA_0_SUP 0x0001 /* Multiword DMA mode 0 supported */ 426 427/* Identify Drive: ai_advpiomode (word 64) */ 428 429#define ATAC_ADVPIO_4_SUP 0x0002 /* PIO mode 4 supported */ 430#define ATAC_ADVPIO_3_SUP 0x0001 /* PIO mode 3 supported */ 431#define ATAC_ADVPIO_SERIAL 0x0003 /* Serial interface */ 432 433/* Identify Drive: ai_majorversion (word 80) */ 434 435#define ATAC_MAJVER_8 0x0100 /* ATA/ATAPI-8 version supported */ 436#define ATAC_MAJVER_6 0x0040 /* ATA/ATAPI-6 version supported */ 437#define ATAC_MAJVER_4 0x0010 /* ATA/ATAPI-4 version supported */ 438 439/* Identify Drive: command set supported/enabled bits - words 83 and 86 */ 440 441#define ATACS_EXT48 0x0400 /* 48 bit address feature */ 442 443/* Identify Drive: ai_features85 (word 85) */ 444#define ATAC_FEATURES85_WCE 0x0020 /* write cache enabled */ 445 446/* Identify Drive: ai_ultradma (word 88) */ 447#define ATAC_UDMA_SUP_MASK 0x007f /* UDMA modes supported */ 448#define ATAC_UDMA_SEL_MASK 0x7f00 /* UDMA modes selected */ 449 450 451/* per-drive data struct */ 452 453typedef struct ata_drv { 454 ata_ctl_t *ad_ctlp; /* pointer back to ctlr */ 455 struct ata_id ad_id; /* IDENTIFY DRIVE data */ 456 457 uint_t ad_flags; 458 uchar_t ad_pciide_dma; /* PCIIDE DMA supported */ 459 uchar_t ad_targ; /* target */ 460 uchar_t ad_lun; /* lun */ 461 uchar_t ad_drive_bits; 462 463 /* Used by atapi side only */ 464 465 uchar_t ad_state; /* state of ATAPI FSM */ 466 uchar_t ad_cdb_len; /* Size of ATAPI CDBs */ 467 468 uchar_t ad_bogus_drq; 469 uchar_t ad_nec_bad_status; 470 471 /* Used by disk side only */ 472 473 struct scsi_device *ad_device; 474 struct scsi_inquiry ad_inquiry; 475 struct ctl_obj ad_ctl_obj; 476 uchar_t ad_rd_cmd; 477 uchar_t ad_wr_cmd; 478 ushort_t ad_acyl; 479 480 /* 481 * Geometry note: The following three values are the geometry 482 * that the driver will use. They may differ from the 483 * geometry reported by the controller and/or BIOS. See note 484 * on ata_fix_large_disk_geometry in ata_disk.c for more 485 * details. 486 */ 487 uint32_t ad_drvrcyl; /* number of cyls */ 488 uint32_t ad_drvrhd; /* number of heads */ 489 uint32_t ad_drvrsec; /* number of sectors */ 490 ushort_t ad_phhd; /* number of phys heads */ 491 ushort_t ad_phsec; /* number of phys sectors */ 492 short ad_block_factor; 493 short ad_bytes_per_block; 494 495 /* 496 * Support for 48-bit LBA (ATA-6) 497 */ 498 uint64_t ad_capacity; /* Total sectors on disk */ 499 500 /* 501 * save/restore the DMA mode for suspend/resume 502 */ 503 ushort_t ad_dma_cap; 504 ushort_t ad_dma_mode; 505} ata_drv_t; 506 507/* values for ad_dma_cap */ 508#define ATA_DMA_ULTRAMODE 0x1 509#define ATA_DMA_MWORDMODE 0x2 510 511typedef struct ata_tgt { 512 ata_drv_t *at_drvp; 513 int at_arq; 514 ulong_t at_total_sectors; 515 ddi_dma_attr_t at_dma_attr; 516} ata_tgt_t; 517 518/* values for ad_pciide_dma */ 519#define ATA_DMA_OFF 0x0 520#define ATA_DMA_ON 0x1 521#define ATA_DMA_UNINITIALIZED 0x2 522 523/* 524 * (ata_pkt_t *) to (gcmd_t *) 525 */ 526#define APKT2GCMD(apktp) (apktp->ap_gcmdp) 527 528/* 529 * (gcmd_t *) to (ata_pkt_t *) 530 */ 531#define GCMD2APKT(gcmdp) ((ata_pkt_t *)gcmdp->cmd_private) 532 533/* 534 * (gtgt_t *) to (ata_ctl_t *) 535 */ 536#define GTGTP2ATAP(gtgtp) ((ata_ctl_t *)GTGTP2HBA(gtgtp)) 537 538/* 539 * (gtgt_t *) to (ata_tgt_t *) 540 */ 541#define GTGTP2ATATGTP(gtgtp) ((ata_tgt_t *)GTGTP2TARGET(gtgtp)) 542 543/* 544 * (gtgt_t *) to (ata_drv_t *) 545 */ 546#define GTGTP2ATADRVP(gtgtp) (GTGTP2ATATGTP(gtgtp)->at_drvp) 547 548/* 549 * (gcmd_t *) to (ata_tgt_t *) 550 */ 551#define GCMD2TGT(gcmdp) GTGTP2ATATGTP(GCMDP2GTGTP(gcmdp)) 552 553/* 554 * (gcmd_t *) to (ata_drv_t *) 555 */ 556#define GCMD2DRV(gcmdp) GTGTP2ATADRVP(GCMDP2GTGTP(gcmdp)) 557 558/* 559 * (ata_pkt_t *) to (ata_drv_t *) 560 */ 561#define APKT2DRV(apktp) GCMD2DRV(APKT2GCMD(apktp)) 562 563 564/* 565 * (struct hba_tran *) to (ata_ctl_t *) 566 */ 567#define TRAN2ATAP(tranp) ((ata_ctl_t *)TRAN2HBA(tranp)) 568 569 570/* 571 * ata common packet structure 572 */ 573typedef struct ata_pkt { 574 575 gcmd_t *ap_gcmdp; /* GHD command struct */ 576 577 uint_t ap_flags; /* packet flags */ 578 579 caddr_t ap_baddr; /* I/O buffer base address */ 580 size_t ap_boffset; /* current offset into I/O buffer */ 581 size_t ap_bcount; /* # bytes in this request */ 582 583 caddr_t ap_v_addr; /* I/O buffer address */ 584 size_t ap_resid; /* # bytes left to read/write */ 585 586 uchar_t ap_pciide_dma; /* This pkt uses DMA transfer mode */ 587 prde_t ap_sg_list[ATA_DMA_NSEGS]; /* Scatter/Gather list */ 588 int ap_sg_cnt; /* number of entries in S/G list */ 589 590 /* command, starting sector number, sector count */ 591 592 daddr_t ap_startsec; /* starting sector number */ 593 ushort_t ap_count; /* sector count */ 594 uchar_t ap_sec; 595 uchar_t ap_lwcyl; 596 uchar_t ap_hicyl; 597 uchar_t ap_hd; 598 uchar_t ap_cmd; 599 600 /* saved status and error registers for error case */ 601 602 uchar_t ap_status; 603 uchar_t ap_error; 604 605 /* disk/atapi callback routines */ 606 607 int (*ap_start)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 608 struct ata_pkt *ata_pktp); 609 int (*ap_intr)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 610 struct ata_pkt *ata_pktp); 611 void (*ap_complete)(ata_drv_t *ata_drvp, 612 struct ata_pkt *ata_pktp, int do_callback); 613 614 /* Used by disk side */ 615 616 char ap_cdb; /* disk command */ 617 char ap_scb; /* status after disk cmd */ 618 uint_t ap_bytes_per_block; /* blk mode factor */ 619 uint_t ap_wrt_count; /* size of last write */ 620 caddr_t ap_v_addr_sav; /* Original I/O buffer address. */ 621 size_t ap_resid_sav; /* Original # of bytes */ 622 /* left to read/write. */ 623 624 /* Used by atapi side */ 625 626 uchar_t *ap_cdbp; /* ptr to SCSI CDB */ 627 uchar_t ap_cdb_len; /* length of SCSI CDB (in bytes) */ 628 uchar_t ap_cdb_pad; /* padding after SCSI CDB (in shorts) */ 629 630 struct scsi_arq_status *ap_scbp; /* ptr to SCSI status block */ 631 uchar_t ap_statuslen; /* length of SCSI status block */ 632} ata_pkt_t; 633 634 635/* 636 * defines for ap_flags 637 */ 638#define AP_ATAPI 0x0001 /* device is atapi */ 639#define AP_ERROR 0x0002 /* normal error */ 640#define AP_TRAN_ERROR 0x0004 /* transport error */ 641#define AP_READ 0x0008 /* read data */ 642#define AP_WRITE 0x0010 /* write data */ 643#define AP_ABORT 0x0020 /* packet aborted */ 644#define AP_TIMEOUT 0x0040 /* packet timed out */ 645#define AP_BUS_RESET 0x0080 /* bus reset */ 646#define AP_DEV_RESET 0x0100 /* device reset */ 647 648#define AP_SENT_CMD 0x0200 /* atapi: cdb sent */ 649#define AP_XFERRED_DATA 0x0400 /* atapi: data transferred */ 650#define AP_GOT_STATUS 0x0800 /* atapi: status received */ 651#define AP_ARQ_ON_ERROR 0x1000 /* atapi: do ARQ on error */ 652#define AP_ARQ_OKAY 0x2000 653#define AP_ARQ_ERROR 0x4000 654 655#define AP_FREE 0x80000000u /* packet is free! */ 656 657 658/* 659 * public function prototypes 660 */ 661 662int ata_check_drive_blacklist(struct ata_id *aidp, uint_t flags); 663int ata_command(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, int expect_drdy, 664 int silent, uint_t busy_wait, uchar_t cmd, uchar_t feature, 665 uchar_t count, uchar_t sector, uchar_t head, uchar_t cyl_low, 666 uchar_t cyl_hi); 667int ata_get_status_clear_intr(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp); 668int ata_id_common(uchar_t id_cmd, int drdy_expected, 669 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 670 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 671 struct ata_id *ata_idp); 672int ata_prop_create(dev_info_t *tgt_dip, ata_drv_t *ata_drvp, char *name); 673int ata_queue_cmd(int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 674 void *arg, ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 675 gtgt_t *gtgtp); 676int ata_set_feature(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 677 uchar_t feature, uchar_t value); 678int ata_wait(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits, 679 uchar_t offbits, uint_t timeout_usec); 680int ata_wait3(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits1, 681 uchar_t offbits1, uchar_t failure_onbits2, 682 uchar_t failure_offbits2, uchar_t failure_onbits3, 683 uchar_t failure_offbits3, uint_t timeout_usec); 684int ata_test_lba_support(struct ata_id *aidp); 685void ata_nsecwait(clock_t count); 686int ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 687void ata_reset_dma_mode(ata_drv_t *ata_drvp); 688void atapi_reset_dma_mode(ata_drv_t *ata_drvp); 689 690 691/* 692 * PCIIDE DMA (Bus Mastering) functions and data in ata_dma.c 693 */ 694extern ddi_dma_attr_t ata_pciide_dma_attr; 695extern int ata_dma_disabled; 696 697int ata_pciide_alloc(dev_info_t *dip, ata_ctl_t *ata_ctlp); 698void ata_pciide_free(ata_ctl_t *ata_ctlp); 699 700void ata_pciide_dma_sg_func(gcmd_t *gcmdp, ddi_dma_cookie_t *dmackp, 701 int single_segment, int seg_index); 702void ata_pciide_dma_setup(ata_ctl_t *ata_ctlp, prde_t *srcp, int sg_cnt); 703void ata_pciide_dma_start(ata_ctl_t *ata_ctlp, uchar_t direction); 704void ata_pciide_dma_stop(ata_ctl_t *ata_ctlp); 705int ata_pciide_status_clear(ata_ctl_t *ata_ctlp); 706int ata_pciide_status_dmacheck_clear(ata_ctl_t *ata_ctlp); 707int ata_pciide_status_pending(ata_ctl_t *ata_ctlp); 708 709#ifdef __cplusplus 710} 711#endif 712 713#endif /* _ATA_COMMON_H */ 714