ohcid.h revision 7492:2387323b838f
1127668Sbms/* 2127668Sbms * CDDL HEADER START 326180Sfenner * 4127668Sbms * The contents of this file are subject to the terms of the 5127668Sbms * Common Development and Distribution License (the "License"). 626180Sfenner * You may not use this file except in compliance with the License. 7127668Sbms * 8127668Sbms * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9127668Sbms * or http://www.opensolaris.org/os/licensing. 10127668Sbms * See the License for the specific language governing permissions 11127668Sbms * and limitations under the License. 12127668Sbms * 13127668Sbms * When distributing Covered Code, include this CDDL HEADER in each 14127668Sbms * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15127668Sbms * If applicable, add the following below this CDDL HEADER, with the 16127668Sbms * fields enclosed by brackets "[]" replaced with your own identifying 17127668Sbms * information: Portions Copyright [yyyy] [name of copyright owner] 18127668Sbms * 19127668Sbms * CDDL HEADER END 2026180Sfenner */ 21127668Sbms/* 22127668Sbms * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23127668Sbms * Use is subject to license terms. 24127668Sbms */ 25127668Sbms 26127668Sbms#ifndef _SYS_USB_OHCID_H 27127668Sbms#define _SYS_USB_OHCID_H 28127668Sbms 29127668Sbms 30127668Sbms#ifdef __cplusplus 31127668Sbmsextern "C" { 3226180Sfenner#endif 3326180Sfenner 34127668Sbms/* 35127668Sbms * Open Host Controller Driver (OHCI) 36127668Sbms * 37127668Sbms * The USB Open Host Controller driver is a software driver which interfaces 38127668Sbms * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 3926180Sfenner * The interface to USB Open Host Controller is defined by the OpenHCI Host 40127668Sbms * Controller Interface. 41127668Sbms * 4226180Sfenner * This header file describes the data structures required for the USB Open 4326180Sfenner * Host Controller Driver to maintain state of USB Open Host Controller, to 4456893Sfenner * perform different USB transfers and for the bandwidth allocations. 4556893Sfenner */ 4656893Sfenner 4756893Sfenner#include <sys/usb/hcd/openhci/ohci.h> 48127668Sbms#include <sys/usb/hcd/openhci/ohci_hub.h> 4926180Sfenner 5026180Sfenner/* 51127668Sbms * OpenHCI interrupt status information structure 5226180Sfenner * 5326180Sfenner * The Host Controller Driver (HCD) has to maintain two different sets of 5426180Sfenner * Host Controller (HC) state information that includes HC registers, the 55127668Sbms * interrupt tables etc.. for the normal and polled modes. In addition, 5626180Sfenner * suppose if we switched to polled mode while ohci interrupt handler is 57127668Sbms * executing in the normal mode then we need to save the interrupt status 5826180Sfenner * information that includes interrupts for which ohci interrupt handler 59127668Sbms * is called and HCCA done head list in the polled mode. This infromation 60127668Sbms * will be used later in normal mode to service those missed interrupts. 61127668Sbms * This will avoid race conditions like missing of normal mode's ohci SOF 62127668Sbms * and WriteDoneHead interrupts because of this polled switch. 63127668Sbms */ 64127668Sbmstypedef struct ohci_save_intr_sts { 65127668Sbms /* 66127668Sbms * The following field has set of flags & these flags will be set 6798524Sfenner * in the ohci interrupt handler to indicate that currently ohci 68127668Sbms * interrupt handler is in execution and also while critical code 69127668Sbms * execution within the ohci interrupt handler. These flags will 70127668Sbms * be verified in polled mode while saving the normal mode's ohci 7126180Sfenner * interrupt status information. 72127668Sbms */ 73127668Sbms uint_t ohci_intr_flag; /* Intr handler flags */ 74127668Sbms 7526180Sfenner /* 76127668Sbms * The following fields will be used to save the interrupt status 77127668Sbms * and the HCCA done head list that the ohci interrupt handler is 78127668Sbms * currently handling. 79127668Sbms */ 80127668Sbms uint_t ohci_curr_intr_sts; /* Current interrupts */ 8198524Sfenner ohci_td_t *ohci_curr_done_lst; /* Current done head */ 82127668Sbms 83127668Sbms /* 84127668Sbms * The following fields will be used to save the interrupt status 85127668Sbms * and the HCCA done list currently being handled by the critical 8698524Sfenner * section of the ohci interrupt handler.. 87127668Sbms */ 88127668Sbms uint_t ohci_critical_intr_sts; /* Critical interrupts */ 89127668Sbms ohci_td_t *ohci_critical_done_lst; /* Critical done head */ 90127668Sbms 91127668Sbms /* 9298524Sfenner * The following fields will be used to save the interrupt status 93127668Sbms * and HCCA done head list by the polled code if an interrupt is 94127668Sbms * pending when polled code is entered. These missed interrupts & 95127668Sbms * done list will be serviced either in current normal mode ohci 96127668Sbms * interrupt handler execution or during the next ohci interrupt 97127668Sbms * handler execution. 98127668Sbms */ 99127668Sbms uint_t ohci_missed_intr_sts; /* Missed interrupts */ 100127668Sbms ohci_td_t *ohci_missed_done_lst; /* Missed done head */ 101127668Sbms} ohci_save_intr_sts_t; 102127668Sbms 10326180Sfenner/* 104127668Sbms * These flags will be set in the the normal mode ohci interrupt handler 10526180Sfenner * to indicate that currently ohci interrupt handler is in execution and 106127668Sbms * also while critical code execution within the ohci interrupt handler. 107127668Sbms * These flags will be verified in the polled mode while saving the normal 10826180Sfenner * mode's ohci interrupt status infromation. 109127668Sbms */ 110127668Sbms#define OHCI_INTR_HANDLING 0x01 /* Handling ohci intrs */ 111127668Sbms#define OHCI_INTR_CRITICAL 0x02 /* Critical intr code */ 112127668Sbms 113127668Sbms 114127668Sbms/* 115127668Sbms * OpenHCI Host Controller state structure 116127668Sbms * 117127668Sbms * The Host Controller Driver (HCD) maintains the state of Host Controller 11826180Sfenner * (HC). There is an ohci_state structure per instance of the OpenHCI 119127668Sbms * host controller. 120127668Sbms */ 12126180Sfenner 122127668Sbmstypedef struct ohci_state { 123127668Sbms dev_info_t *ohci_dip; /* Dip of HC */ 124127668Sbms uint_t ohci_instance; 125127668Sbms usba_hcdi_ops_t *ohci_hcdi_ops; /* HCDI structure */ 126127668Sbms uint_t ohci_flags; /* Used for cleanup */ 127127668Sbms uint16_t ohci_vendor_id; /* chip vendor */ 128127668Sbms uint16_t ohci_device_id; /* chip device */ 129127668Sbms uint8_t ohci_rev_id; /* chip revison */ 130127668Sbms 131127668Sbms ohci_regs_t *ohci_regsp; /* Host ctlr regs */ 132127668Sbms ddi_acc_handle_t ohci_regs_handle; /* Reg handle */ 133127668Sbms 134127668Sbms ddi_acc_handle_t ohci_config_handle; /* Config space hndle */ 135127668Sbms uint_t ohci_frame_interval; /* Frme inter reg */ 136127668Sbms ddi_dma_attr_t ohci_dma_attr; /* DMA attributes */ 137127668Sbms 138127668Sbms ddi_intr_handle_t *ohci_htable; /* intr handle */ 139127668Sbms int ohci_intr_type; /* intr type used */ 140127668Sbms int ohci_intr_cnt; /* # of intrs inuse */ 14126180Sfenner uint_t ohci_intr_pri; /* intr priority */ 14226180Sfenner int ohci_intr_cap; /* intr capabilities */ 143127668Sbms kmutex_t ohci_int_mutex; /* Mutex for struct */ 144127668Sbms 145127668Sbms /* HCCA area */ 146127668Sbms ohci_hcca_t *ohci_hccap; /* Virtual HCCA ptr */ 147127668Sbms ddi_dma_cookie_t ohci_hcca_cookie; /* DMA cookie */ 148127668Sbms ddi_dma_handle_t ohci_hcca_dma_handle; /* DMA handle */ 149127668Sbms ddi_acc_handle_t ohci_hcca_mem_handle; /* Memory handle */ 15098524Sfenner 151127668Sbms /* 152127668Sbms * There are two pools of memory. One pool contains the memory for 153127668Sbms * the transfer descriptors and other pool contains the memory for 154127668Sbms * the endpoint descriptors. The advantage of the pools is that it's 155127668Sbms * easy to go back and forth between the iommu and the cpu addresses. 156127668Sbms * 157127668Sbms * The pools are protected by the ohci_int_mutex because the memory 15898524Sfenner * in the pools may be accessed by either the host controller or the 159127668Sbms * host controller driver. 160127668Sbms */ 161127668Sbms 162127668Sbms /* General transfer descriptor pool */ 163127668Sbms ohci_td_t *ohci_td_pool_addr; /* Start of the pool */ 16498524Sfenner ddi_dma_cookie_t ohci_td_pool_cookie; /* DMA cookie */ 165127668Sbms ddi_dma_handle_t ohci_td_pool_dma_handle; /* DMA hndle */ 166127668Sbms ddi_acc_handle_t ohci_td_pool_mem_handle; /* Mem hndle */ 167127668Sbms 168127668Sbms /* Endpoint descriptor pool */ 169127668Sbms ohci_ed_t *ohci_ed_pool_addr; /* Start of the pool */ 170127668Sbms ddi_dma_cookie_t ohci_ed_pool_cookie; /* DMA cookie */ 171127668Sbms ddi_dma_handle_t ohci_ed_pool_dma_handle; /* DMA handle */ 17298524Sfenner ddi_acc_handle_t ohci_ed_pool_mem_handle; /* Mem handle */ 173127668Sbms uint_t ohci_dma_addr_bind_flag; /* DMA flag */ 174127668Sbms 175127668Sbms /* Condition variables */ 176127668Sbms kcondvar_t ohci_SOF_cv; /* SOF variable */ 177127668Sbms 178127668Sbms /* Semaphore to serialize opens and closes */ 179127668Sbms ksema_t ohci_ocsem; 180127668Sbms 181127668Sbms /* 18298524Sfenner * Bandwidth fields 18398524Sfenner * 184127668Sbms * The ohci_bandwidth array keeps track of the allocated bandwidth 185127668Sbms * for this host controller. The total bandwidth allocated for least 186127668Sbms * allocated list out of the 32 periodic lists is represented by the 187127668Sbms * ohci_periodic_minimum_bandwidth field. 188127668Sbms */ 189127668Sbms uint_t ohci_periodic_minimum_bandwidth; 190127668Sbms uint_t ohci_periodic_bandwidth[NUM_INTR_ED_LISTS]; 191127668Sbms 192127668Sbms /* Different transfer open pipe counts */ 193127668Sbms uint_t ohci_open_pipe_count; 194127668Sbms uint_t ohci_open_ctrl_pipe_count; 195127668Sbms uint_t ohci_open_bulk_pipe_count; 196127668Sbms uint_t ohci_open_periodic_pipe_count; 197127668Sbms uint_t ohci_open_isoch_pipe_count; 198127668Sbms /* 199127668Sbms * Endpoint Reclamation List 200127668Sbms * 201127668Sbms * The interrupt or isochronous list processing cannot be stopped 202127668Sbms * when a periodic endpoint is removed from the list. The endpoints 203127668Sbms * are detached from the interrupt lattice tree and put on to the 204127668Sbms * reclaimation list. On next SOF interrupt all those endpoints, 205127668Sbms * which are on the reclaimation list will be deallocated. 206127668Sbms */ 207127668Sbms ohci_ed_t *ohci_reclaim_list; /* Reclaimation list */ 208127668Sbms 209127668Sbms ohci_root_hub_t ohci_root_hub; /* Root hub info */ 210127668Sbms 211127668Sbms /* 212127668Sbms * Global transfer timeout handling & this transfer timeout handling 213127668Sbms * will be per USB Host Controller. 214127668Sbms */ 215127668Sbms struct ohci_trans_wrapper *ohci_timeout_list; /* Timeout List */ 216127668Sbms timeout_id_t ohci_timer_id; /* Timer id */ 217127668Sbms 218127668Sbms /* Frame number overflow information */ 219127668Sbms usb_frame_number_t ohci_fno; 220127668Sbms 221127668Sbms /* For Schedule Overrun error counter */ 222127668Sbms uint_t ohci_so_error; 223127668Sbms 224127668Sbms /* For host controller error counter */ 225127668Sbms uint_t ohci_hc_error; 226127668Sbms 227127668Sbms /* For SOF interrupt event */ 228127668Sbms boolean_t ohci_sof_flag; 229127668Sbms 230127668Sbms /* Openhci Host Controller Software State information */ 231127668Sbms uint_t ohci_hc_soft_state; 232127668Sbms 233127668Sbms /* 234127668Sbms * ohci_save_intr_stats is used to save the normal mode interrupt 235127668Sbms * status information while executing interrupt handler & also by 236127668Sbms * the polled code if an interrupt is pending for the normal mode 237127668Sbms * when polled code is entered. 238127668Sbms */ 239127668Sbms ohci_save_intr_sts_t ohci_save_intr_sts; 240127668Sbms 241127668Sbms /* 242127668Sbms * Saved copy of the ohci registers of the normal mode & change 243127668Sbms * required ohci registers values for the polled mode operation. 24498524Sfenner * Before returning from the polled mode to normal mode replace 245127668Sbms * the required current registers with this saved ohci registers 246127668Sbms * copy. 247127668Sbms */ 248127668Sbms ohci_regs_t ohci_polled_save_regs; 249127668Sbms 250127668Sbms /* 251127668Sbms * Saved copy of the interrupt table used in normal ohci mode and 252127668Sbms * replace this table by another interrupt table that used in the 25398524Sfenner * POLLED mode. 254127668Sbms */ 25598524Sfenner ohci_ed_t *ohci_polled_save_IntTble[NUM_INTR_ED_LISTS]; 256127668Sbms 257127668Sbms /* ohci polled mode enter counter for the input devices */ 258127668Sbms uint_t ohci_polled_enter_count; 259127668Sbms 260127668Sbms /* 26198524Sfenner * Counter for polled mode and used in suspend mode to see if 262127668Sbms * there is a input device connected. 263127668Sbms */ 264127668Sbms uint_t ohci_polled_kbd_count; 265127668Sbms 266127668Sbms /* Done list for the Polled mode */ 267127668Sbms ohci_td_t *ohci_polled_done_list; 268127668Sbms 26998524Sfenner /* Log handle for debug, console, log messages */ 270127668Sbms usb_log_handle_t ohci_log_hdl; 271127668Sbms 272127668Sbms /* Kstat structures */ 27326180Sfenner kstat_t *ohci_intrs_stats; 274127668Sbms kstat_t *ohci_total_stats; 27526180Sfenner kstat_t *ohci_count_stats[USB_N_COUNT_KSTATS]; 276127668Sbms} ohci_state_t; 277127668Sbms 278127668Sbmstypedef struct ohci_intrs_stats { 279127668Sbms struct kstat_named ohci_hcr_intr_so; 280127668Sbms struct kstat_named ohci_hcr_intr_wdh; 281127668Sbms struct kstat_named ohci_hcr_intr_sof; 282127668Sbms struct kstat_named ohci_hcr_intr_rd; 283127668Sbms struct kstat_named ohci_hcr_intr_ue; 28426180Sfenner struct kstat_named ohci_hcr_intr_fno; 28526180Sfenner struct kstat_named ohci_hcr_intr_rhsc; 28626180Sfenner struct kstat_named ohci_hcr_intr_oc; 287127668Sbms struct kstat_named ohci_hcr_intr_not_claimed; 288127668Sbms struct kstat_named ohci_hcr_intr_total; 28926180Sfenner} ohci_intrs_stats_t; 290127668Sbms 291127668Sbms/* 292127668Sbms * ohci kstat defines 293127668Sbms */ 294127668Sbms#define OHCI_INTRS_STATS(ohci) ((ohci)->ohci_intrs_stats) 295127668Sbms#define OHCI_INTRS_STATS_DATA(ohci) \ 296127668Sbms ((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data) 297127668Sbms 298127668Sbms#define OHCI_TOTAL_STATS(ohci) ((ohci)->ohci_total_stats) 299127668Sbms#define OHCI_TOTAL_STATS_DATA(ohci) (KSTAT_IO_PTR((ohci)->ohci_total_stats)) 300127668Sbms#define OHCI_CTRL_STATS(ohci) \ 301127668Sbms (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL])) 302127668Sbms#define OHCI_BULK_STATS(ohci) \ 303127668Sbms (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK])) 304127668Sbms#define OHCI_INTR_STATS(ohci) \ 305127668Sbms (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_INTR])) 306127668Sbms#define OHCI_ISOC_STATS(ohci) \ 307127668Sbms (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_ISOCH])) 30826180Sfenner 309127668Sbms/* warlock directives, stable data */ 310127668Sbms_NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_state_t)) 311127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_intr_pri)) 312127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dip)) 313127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_regsp)) 314127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_instance)) 315127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_vendor_id)) 316127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_device_id)) 317127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_rev_id)) 318127668Sbms 319127668Sbms/* this may not be stable data in the future */ 320127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_addr)) 321127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_mem_handle)) 322127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_addr)) 323127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_mem_handle)) 324127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_cookie)) 325127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_cookie)) 326127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hcca_mem_handle)) 327127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hccap)) 328127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dma_addr_bind_flag)) 329127668Sbms_NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_log_hdl)) 330127668Sbms 331127668Sbms_NOTE(LOCK_ORDER(ohci_state::ohci_int_mutex \ 332127668Sbms usba_pipe_handle_data::p_mutex \ 333127668Sbms usba_device::usb_mutex \ 334127668Sbms usba_ph_impl::usba_ph_mutex)) 335127668Sbms 336127668Sbms/* 337127668Sbms * Host Contoller Software States 338127668Sbms * 339127668Sbms * OHCI_CTLR_INIT_STATE: 340127668Sbms * The host controller soft state will be set to this during the 341127668Sbms * ohci_attach. 342127668Sbms * 343127668Sbms * OHCI_CTLR_SUSPEND_STATE: 344127668Sbms * The host controller soft state will be set to this during the 345127668Sbms * ohci_cpr_suspend. 346127668Sbms * 347127668Sbms * OHCI_CTLR_OPERATIONAL_STATE: 348127668Sbms * The host controller soft state will be set to this after moving 349127668Sbms * host controller to operational state and host controller start 350127668Sbms * generating SOF successfully. 351127668Sbms * 352127668Sbms * OHCI_CTLR_ERROR_STATE: 353127668Sbms * The host controller soft state will be set to this during the 354127668Sbms * no SOF or UE error conditions. 355127668Sbms * 356127668Sbms * Under this state or condition, only pipe stop polling, pipe reset 357127668Sbms * and pipe close are allowed. But all other entry points like pipe 358127668Sbms * open, get/set pipe policy, cotrol send/receive, bulk send/receive 359127668Sbms * isoch send/receive, start polling etc. will fail. 360127668Sbms * 361127668Sbms * State Diagram for the host controller software state 362127668Sbms * 363127668Sbms * 364127668Sbms * ohci_attach->[INIT_STATE] 365127668Sbms * | 366127668Sbms * | -------->----[ERROR_STATE]--<-----------<--- 367127668Sbms * | | Failure (UE/no SOF condition) | 368127668Sbms * | ^ ^ 369127668Sbms * V | Success | 370127668Sbms * ohci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ohci_send/recv/polling 371127668Sbms * ^ | 372127668Sbms * | | 373127668Sbms * | V 374 * -<-ohci_cpr_resume--[SUSPEND_STATE]-<-ohci_cpr_suspend 375 */ 376#define OHCI_CTLR_INIT_STATE 0 /* Initilization state */ 377#define OHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 378#define OHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 379#define OHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 380 381/* 382 * Define all ohci's Vendor-id and Device-id Here 383 */ 384#define RIO_VENDOR 0x108e 385#define RIO_DEVICE 0x1103 386#define OHCI_IS_RIO(ohcip) (ohcip->ohci_vendor_id == RIO_VENDOR) 387 388/* 389 * Periodic and non-periodic macros 390 */ 391#define OHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 392 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 393 ((endpoint->bmAttributes &\ 394 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 395 396#define OHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 397 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 398 ((endpoint->bmAttributes &\ 399 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 400 401/* 402 * OHCI ED and TD Pool sizes. 403 */ 404#define OHCI_ED_POOL_SIZE 100 405#define OHCI_TD_POOL_SIZE 200 406 407/* 408 * ohci_dma_addr_bind_flag values 409 * 410 * This flag indicates if the various DMA addresses allocated by the OHCI 411 * have been bound to their respective handles. This is needed to recover 412 * without errors from ohci_cleanup when it calls ddi_dma_unbind_handle() 413 */ 414#define OHCI_TD_POOL_BOUND 0x01 /* For TD pools */ 415#define OHCI_ED_POOL_BOUND 0x02 /* For ED pools */ 416#define OHCI_HCCA_DMA_BOUND 0x04 /* For HCCA area */ 417 418/* 419 * Maximum SOF wait count 420 */ 421#define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 422 423 424/* 425 * Pipe private structure 426 * 427 * There is an instance of this structure per pipe. This structure holds 428 * HCD specific pipe information. A pointer to this structure is kept in 429 * the USBA pipe handle (usba_pipe_handle_data_t). 430 */ 431typedef struct ohci_pipe_private { 432 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 433 ohci_ed_t *pp_ept; /* Pipe's ept */ 434 435 /* State of the pipe */ 436 uint_t pp_state; /* See below */ 437 438 /* Local copy of the pipe policy */ 439 usb_pipe_policy_t pp_policy; 440 441 /* For Periodic Pipes Only */ 442 uint_t pp_node; /* Node in lattice */ 443 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 444 uint_t pp_max_periodic_req_cnt; /* Max req count */ 445 446 /* For isochronous pipe only */ 447 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 448 449 /* 450 * Each pipe may have multiple transfer wrappers. Each transfer 451 * wrapper represents a USB transfer on the bus. A transfer is 452 * made up of one or more transactions. 453 */ 454 struct ohci_trans_wrapper *pp_tw_head; /* Head of the list */ 455 struct ohci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 456 457 /* Done td count */ 458 uint_t pp_count_done_tds; /* Done td count */ 459 460 /* Errors */ 461 usb_cr_t pp_error; /* Pipe error */ 462 463 /* Flags */ 464 uint_t pp_flag; /* Flags */ 465 466 /* Condition variable for transfers completion event */ 467 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 468 469 /* 470 * HCD gets Interrupt/Isochronous IN polling request only once and 471 * it has to insert next polling requests after completion of first 472 * request until either stop polling/pipe close is called. So HCD 473 * has to take copy of the original Interrupt/Isochronous IN request. 474 */ 475 usb_opaque_t pp_client_periodic_in_reqp; 476} ohci_pipe_private_t; 477 478/* warlock directives, stable data */ 479_NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_pipe_private_t)) 480 481/* 482 * Pipe states 483 * 484 * ohci pipe states will be similar to usba. Refer usbai.h. 485 */ 486#define OHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 487#define OHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 488#define OHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 489 490/* Additional ohci pipe states for the ohci_pipe_cleanup */ 491#define OHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 492#define OHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 493#define OHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 494 495/* 496 * Pipe specific Flags 497 */ 498#define OHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 499 500/* 501 * The maximum allowable usb isochronous data transfer size or maximum 502 * number of isochronous data packets. 503 * 504 * Each usb isochronous request must not exceed multiples of isochronous 505 * endpoint packet size and OHCI_MAX_ISOC_PKTS_PER_XFER. 506 * 507 * Ex: usb isochronous endpoint maximum packet size is 64 bytes 508 * maximum usb isochronous request will be OHCI_MAX_ISOC_PKTS_PER_XFER 509 * * 64 bytes 510 */ 511#define OHCI_MAX_ISOC_PKTS_PER_XFER 256 /* Max pkts per req */ 512 513/* 514 * The ohci supports maximum of eight isochronous data packets per transfer 515 * descriptor. 516 */ 517#define OHCI_ISOC_PKTS_PER_TD 8 /* Packets per TD */ 518 519/* 520 * USB frame offset 521 * 522 * Add appropriate frame offset to the current usb frame number and use it 523 * as a starting frame number for a given usb isochronous request. 524 */ 525#define OHCI_FRAME_OFFSET 2 /* Frame offset */ 526 527/* 528 * Default usb isochronous receive packets per request before ohci will do 529 * callback. 530 */ 531#define OHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 532 533/* 534 * Different interrupt polling intervals supported 535 */ 536#define INTR_1MS_POLL 1 537#define INTR_2MS_POLL 2 538#define INTR_4MS_POLL 4 539#define INTR_8MS_POLL 8 540#define INTR_16MS_POLL 16 541#define INTR_32MS_POLL 32 542 543/* 544 * Number of interrupt/isochronous transfer requests that should 545 * be maintained on the interrupt/isochronous endpoint corresponding 546 * to different polling intervals supported. 547 */ 548#define INTR_1MS_REQS 4 /* 1ms polling interval */ 549#define INTR_2MS_REQS 2 /* 2ms polling interval */ 550#define INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 551 552/* Function prototype */ 553typedef void (*ohci_handler_function_t)( 554 ohci_state_t *ohcip, 555 ohci_pipe_private_t *pp, 556 struct ohci_trans_wrapper *tw, 557 ohci_td_t *td, 558 void *ohci_handle_callback_value); 559 560 561/* 562 * Transfer wrapper 563 * 564 * The transfer wrapper represents a USB transfer on the bus and there 565 * is one instance per USB transfer. A transfer is made up of one or 566 * more transactions. OHCI uses one TD for one transaction. So one 567 * transfer wrapper may have one or more TDs associated. 568 * 569 * Control and bulk pipes will have one transfer wrapper per transfer 570 * and where as Isochronous and Interrupt pipes will only have one 571 * transfer wrapper. The transfers wrapper are continually reused for 572 * the Interrupt and Isochronous pipes as those pipes are polled. 573 * 574 * Control, bulk and interrupt transfers will have one DMA buffer per 575 * transfer. The data to be transferred are contained in the DMA buffer 576 * which is virtually contiguous but physically discontiguous. When 577 * preparing the TDs for a USB transfer, the DMA cookies contained in 578 * the buffer need to be walked through to retrieve the DMA addresses. 579 * 580 * Isochronous transfers may have multiple DMA buffers per transfer 581 * with each isoc TD having a DMA buffer. And one isoc TD may hold up to 582 * eight isoc packets, but two cookies at most. 583 */ 584typedef struct ohci_trans_wrapper { 585 struct ohci_trans_wrapper *tw_next; /* Next wrapper */ 586 ohci_pipe_private_t *tw_pipe_private; /* Back ptr */ 587 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 588 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 589 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 590 uint32_t tw_id; /* 32bit ID */ 591 size_t tw_length; /* Txfer length */ 592 char *tw_buf; /* Buffer for Xfer */ 593 uint_t tw_ncookies; /* DMA cookie count */ 594 uint_t tw_cookie_idx; /* DMA cookie index */ 595 size_t tw_dma_offs; /* DMA buffer offset */ 596 usb_flags_t tw_flags; /* Flags */ 597 uint_t tw_num_tds; /* Number of TDs */ 598 ohci_td_t *tw_hctd_head; /* Head TD */ 599 ohci_td_t *tw_hctd_tail; /* Tail TD */ 600 uint_t tw_direction; /* Direction of TD */ 601 uint_t tw_pkt_idx; /* packet index */ 602 603 /* We preallocate all the td's for each tw and place them here */ 604 ohci_td_t *tw_hctd_free_list; 605 606 /* Current transfer request pointer */ 607 usb_opaque_t tw_curr_xfer_reqp; 608 609 /* Current isochronous packet descriptor pointer */ 610 usb_isoc_pkt_descr_t *tw_curr_isoc_pktp; 611 612 /* Isochronous DMA handlers and buffer pointers are stored here */ 613 ohci_isoc_buf_t *tw_isoc_bufs; 614 size_t tw_isoc_strtlen; 615 616 /* Transfer timeout information */ 617 uint_t tw_timeout; /* Timeout value */ 618 struct ohci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 619 620 /* 621 * This is the function to call when this td is done. This way 622 * we don't have to look in the td to figure out what kind it is. 623 */ 624 ohci_handler_function_t tw_handle_td; 625 626 /* 627 * This is the callback value used when processing a done td. 628 */ 629 usb_opaque_t tw_handle_callback_value; 630} ohci_trans_wrapper_t; 631 632_NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_trans_wrapper)) 633 634 635/* 636 * Time waits for the different OHCI specific operations. 637 * These timeout values are specified in terms of microseconds. 638 */ 639#define OHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 640#define OHCI_RESUME_TIMEWAIT 40000 /* HC resume waiting time */ 641#define OHCI_TIMEWAIT 10000 /* HC any other waiting time */ 642 643/* These timeout values are specified in seconds */ 644#define OHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 645#define OHCI_MAX_SOF_TIMEWAIT 3 /* Maximum SOF waiting time */ 646#define OHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 647 648/* OHCI flags for general use */ 649#define OHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 650#define OHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 651#define OHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 652 653/* 654 * Maximum allowable data transfer size per transaction as supported 655 * by OHCI is 8k. (See Open Host Controller Interface Spec rev 1.0a) 656 */ 657#define OHCI_MAX_TD_XFER_SIZE 0x2000 /* Maxmum data per transaction */ 658 659/* 660 * One OHCI TD allows two physically discontiguous pages. The page size 661 * is 4k. 662 */ 663#define OHCI_MAX_TD_BUF_SIZE 0x1000 664 665/* 666 * The maximum allowable bulk data transfer size. It can be different 667 * from OHCI_MAX_TD_XFER_SIZE and if it is more then ohci driver will 668 * take care of breaking a bulk data request into multiples of ohci 669 * OHCI_MAX_TD_XFER_SIZE until request is satisfied. Currently this 670 * value is set to 256k bytes. 671 */ 672#define OHCI_MAX_BULK_XFER_SIZE 0x40000 /* Maximum bulk transfer size */ 673 674/* 675 * Timeout flags 676 * 677 * These flags will be used to stop the timer before timeout handler 678 * gets executed. 679 */ 680#define OHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last TD */ 681#define OHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 682 683 684/* 685 * Bandwidth allocation 686 * 687 * The following definitions are used during bandwidth calculations 688 * for a given endpoint maximum packet size. 689 */ 690#define MAX_USB_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 691#define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 692#define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 693#define SOF 6 /* Length in bytes of SOF */ 694#define EOF 4 /* Length in bytes of EOF */ 695#define TREE_HEIGHT 5 /* Log base 2 of 32 */ 696 697/* 698 * Minimum polling interval for low speed endpoint 699 * 700 * According USB Specifications, a full-speed endpoint can specify 701 * a desired polling interval 1ms to 255ms and a low speed endpoints 702 * are limited to specifying only 10ms to 255ms. But some old keyboards 703 * and mice uses polling interval of 8ms. For compatibility purpose, 704 * we are using polling interval between 8ms and 255ms for low speed 705 * endpoints. But ohci driver will reject any low speed endpoints which 706 * request polling interval less than 8ms. 707 */ 708#define MIN_LOW_SPEED_POLL_INTERVAL 8 709 710/* 711 * For non-periodic transfers, reserve atleast for one low-speed device 712 * transaction. According to USB Bandwidth Analysis white paper and also 713 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 714 * transaction takes 0x628h full speed bits (197 bytes), which comes to 715 * around 13% of USB frame time. 716 * 717 * The periodic transfers will get around 87% of USB frame time. 718 */ 719#define MAX_NON_PERIODIC_BANDWIDTH 197 720#define MAX_PERIODIC_BANDWIDTH (MAX_USB_BUS_BANDWIDTH - SOF - \ 721 EOF - MAX_NON_PERIODIC_BANDWIDTH) 722 723/* 724 * The USB periodic transfers like interrupt and isochronous transfers 725 * after completion of SOF and USB non-periodic transfers. 726 */ 727#define PERIODIC_XFER_STARTS (MAX_USB_BUS_BANDWIDTH - \ 728 SOF - MAX_NON_PERIODIC_BANDWIDTH) 729 730/* Number of Bits Per Byte */ 731#define BITS_PER_BYTE 8 732 733/* 734 * The following are the protocol overheads in terms of Bytes for the 735 * different transfer types. All these protocol overhead values are 736 * derived from the 5.9.3 section of USB Specification and with the 737 * help of Bandwidth Analysis white paper which is posted on the USB 738 * developer forum. 739 */ 740#define FS_NON_ISOC_PROTO_OVERHEAD 14 741#define FS_ISOC_INPUT_PROTO_OVERHEAD 11 742#define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 743#define LOW_SPEED_PROTO_OVERHEAD 97 744#define HUB_LOW_SPEED_PROTO_OVERHEAD 01 745 746/* 747 * The Host Controller (HC) delays are the USB host controller specific 748 * delays. The value shown below is the host controller delay for the 749 * RIO USB host controller. This value was calculated and given by the 750 * Sun USB hardware people. 751 */ 752#define HOST_CONTROLLER_DELAY 18 753 754/* 755 * The low speed clock below represents that to transmit one low-speed 756 * bit takes eight times more than one full speed bit time. 757 */ 758#define LOW_SPEED_CLOCK 8 759 760 761/* 762 * Macros for setting/getting information 763 */ 764#define Get_ED(addr) ddi_get32(ohcip->ohci_ed_pool_mem_handle, \ 765 (uint32_t *)&addr) 766 767#define Set_ED(addr, val) ddi_put32(ohcip->ohci_ed_pool_mem_handle, \ 768 ((uint32_t *)&addr), \ 769 ((int32_t)(val))) 770 771#define Get_TD(addr) ddi_get32(ohcip->ohci_td_pool_mem_handle, \ 772 (uint32_t *)&addr) 773 774#define Set_TD(addr, val) ddi_put32(ohcip->ohci_td_pool_mem_handle, \ 775 ((uint32_t *)&addr), \ 776 ((uint32_t)(uintptr_t)(val))) 777 778#define Get_HCCA(addr) ddi_get32(ohcip->ohci_hcca_mem_handle, \ 779 (uint32_t *)&addr) 780 781#define Set_HCCA(addr, val) ddi_put32(ohcip->ohci_hcca_mem_handle, \ 782 ((uint32_t *)&addr), \ 783 ((int32_t)(val))) 784 785#define Get_OpReg(addr) ddi_get32(ohcip->ohci_regs_handle, \ 786 (uint32_t *)&ohcip->ohci_regsp->addr) 787 788#define Set_OpReg(addr, val) ddi_put32(ohcip->ohci_regs_handle, \ 789 ((uint32_t *)&ohcip->ohci_regsp->addr), \ 790 ((int32_t)(val))) 791 792#define Sync_HCCA(ohcip) (void) ddi_dma_sync( \ 793 ohcip->ohci_hcca_dma_handle, \ 794 0, sizeof (ohci_hcca_t), \ 795 DDI_DMA_SYNC_FORCPU); 796 797#define Sync_ED_TD_Pool(ohcip) (void) ddi_dma_sync( \ 798 ohcip->ohci_ed_pool_dma_handle, \ 799 0, OHCI_ED_POOL_SIZE * sizeof (ohci_ed_t), \ 800 DDI_DMA_SYNC_FORCPU); \ 801 (void) ddi_dma_sync( \ 802 ohcip->ohci_td_pool_dma_handle, \ 803 0, OHCI_TD_POOL_SIZE * sizeof (ohci_td_t), \ 804 DDI_DMA_SYNC_FORCPU); 805 806#define Sync_IO_Buffer(dma_handle, length) \ 807 (void) ddi_dma_sync(dma_handle, \ 808 0, length, DDI_DMA_SYNC_FORCPU); 809 810/* 811 * Macros to speed handling of 32bit IDs 812 */ 813#define OHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 814#define OHCI_LOOKUP_ID(x) id32_lookup((x)) 815#define OHCI_FREE_ID(x) id32_free((x)) 816 817 818/* 819 * Miscellaneous definitions. 820 */ 821 822/* Data toggle bits */ 823#define DATA0 0 824#define DATA1 1 825 826/* sKip bit actions */ 827#define CLEAR_sKip 0 828#define SET_sKip 1 829 830typedef uint_t skip_bit_t; 831 832/* 833 * Setup Packet 834 */ 835typedef struct setup_pkt { 836 uchar_t bmRequestType; 837 uchar_t bRequest; 838 ushort_t wValue; 839 ushort_t wIndex; 840 ushort_t wLength; 841}setup_pkt_t; 842 843#define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 844 845#define REQUEST_TYPE_OFFSET 0 846#define REQUEST_OFFSET 1 847#define VALUE_OFFSET 2 848#define INDEX_OFFSET 4 849#define LENGTH_OFFSET 6 850 851#define TYPE_DEV_TO_HOST 0x80000000 852#define DEVICE 0x00000001 853#define CONFIGURATION 0x00000002 854 855/* 856 * The following are used in attach to indicate 857 * what has been succesfully allocated, so detach 858 * can remove them. 859 */ 860#define OHCI_ATTACH 0x01 /* ohci driver initilization */ 861#define OHCI_ZALLOC 0x02 /* Memory for ohci state structure */ 862#define OHCI_INTR 0x04 /* Interrupt handler registered */ 863#define OHCI_USBAREG 0x08 /* USBA registered */ 864#define OHCI_RHREG 0x10 /* Root hub driver loaded */ 865 866#define OHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 867 868/* 869 * Debug printing 870 * Masks 871 */ 872#define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 873#define PRINT_MASK_LISTS 0x00000002 /* List management */ 874#define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 875#define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 876#define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 877#define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 878#define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 879#define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 880#define PRINT_MASK_DUMPING 0x00000100 /* Dump ohci info */ 881#define PRINT_MASK_ALL 0xFFFFFFFF 882 883 884/* Polling support */ 885int ohci_hcdi_polled_input_init( 886 usba_pipe_handle_data_t *ph, 887 uchar_t **polled_buf, 888 usb_console_info_impl_t *info); 889int ohci_hcdi_polled_input_enter( 890 usb_console_info_impl_t *info); 891int ohci_hcdi_polled_read( 892 usb_console_info_impl_t *info, 893 uint_t *num_characters); 894int ohci_hcdi_polled_input_exit( 895 usb_console_info_impl_t *info); 896int ohci_hcdi_polled_input_fini( 897 usb_console_info_impl_t *info); 898 899/* Root hub related functions */ 900int ohci_init_root_hub( 901 ohci_state_t *ohcip); 902int ohci_load_root_hub_driver( 903 ohci_state_t *ohcip); 904int ohci_unload_root_hub_driver( 905 ohci_state_t *ohcip); 906int ohci_handle_root_hub_pipe_open( 907 usba_pipe_handle_data_t *ph, 908 usb_flags_t flags); 909int ohci_handle_root_hub_pipe_close( 910 usba_pipe_handle_data_t *ph); 911int ohci_handle_root_hub_pipe_reset( 912 usba_pipe_handle_data_t *ph, 913 usb_flags_t flags); 914int ohci_handle_root_hub_request( 915 ohci_state_t *ohcip, 916 usba_pipe_handle_data_t *ph, 917 usb_ctrl_req_t *ctrl_reqp); 918int ohci_handle_root_hub_pipe_start_intr_polling( 919 usba_pipe_handle_data_t *ph, 920 usb_intr_req_t *intr_reqp, 921 usb_flags_t flags); 922void ohci_handle_root_hub_pipe_stop_intr_polling( 923 usba_pipe_handle_data_t *ph, 924 usb_flags_t flags); 925void ohci_handle_root_hub_status_change(void *arg); 926 927/* Endpoint Descriptor (ED) related functions */ 928ohci_ed_t *ohci_alloc_hc_ed( 929 ohci_state_t *ohcip, 930 usba_pipe_handle_data_t *ph); 931void ohci_deallocate_ed( 932 ohci_state_t *ohcip, 933 ohci_ed_t *old_ed); 934uint32_t ohci_ed_cpu_to_iommu( 935 ohci_state_t *ohcip, 936 ohci_ed_t *addr); 937 938/* Transfer Descriptor (TD) related functions */ 939int ohci_start_periodic_pipe_polling( 940 ohci_state_t *ohcip, 941 usba_pipe_handle_data_t *ph, 942 usb_opaque_t periodic_in_reqp, 943 usb_flags_t flags); 944void ohci_traverse_tds( 945 ohci_state_t *ohcip, 946 usba_pipe_handle_data_t *ph); 947void ohci_deallocate_td( 948 ohci_state_t *ohcip, 949 ohci_td_t *old_td); 950uint32_t ohci_td_cpu_to_iommu( 951 ohci_state_t *ohcip, 952 ohci_td_t *addr); 953ohci_td_t *ohci_td_iommu_to_cpu( 954 ohci_state_t *ohcip, 955 uintptr_t addr); 956size_t ohci_get_td_residue( 957 ohci_state_t *ohcip, 958 ohci_td_t *td); 959void ohci_init_td( 960 ohci_state_t *ohcip, 961 ohci_trans_wrapper_t *tw, 962 uint32_t hctd_dma_offs, 963 size_t hctd_length, 964 ohci_td_t *td); 965 966/* Transfer Wrapper (TW) functions */ 967void ohci_deallocate_tw_resources( 968 ohci_state_t *ohcip, 969 ohci_pipe_private_t *pp, 970 ohci_trans_wrapper_t *tw); 971 972/* Interrupt Handling functions */ 973void ohci_handle_frame_number_overflow( 974 ohci_state_t *ohcip); 975 976/* Miscillaneous functions */ 977ohci_state_t *ohci_obtain_state( 978 dev_info_t *dip); 979int ohci_state_is_operational( 980 ohci_state_t *ohcip); 981int ohci_do_soft_reset( 982 ohci_state_t *ohcip); 983usb_frame_number_t ohci_get_current_frame_number( 984 ohci_state_t *ohcip); 985void ohci_handle_outstanding_requests( 986 ohci_state_t *ohcip, 987 ohci_pipe_private_t *pp); 988 989#ifdef __cplusplus 990} 991#endif 992 993#endif /* _SYS_USB_OHCID_H */ 994