mpi2_cnfg.h revision 9907:98086c85a8f7
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (c) 2000 to 2009, LSI Corporation. 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms of all code within 27 * this file that is exclusively owned by LSI, with or without 28 * modification, is permitted provided that, in addition to the CDDL 1.0 29 * License requirements, the following conditions are met: 30 * 31 * Neither the name of the author nor the names of its contributors may be 32 * used to endorse or promote products derived from this software without 33 * specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 38 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 39 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 41 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 42 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 43 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 45 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 46 * DAMAGE. 47 */ 48 49/* 50 * Name: mpi2_cnfg.h 51 * Title: MPI Configuration messages and pages 52 * Creation Date: November 10, 2006 53 * 54 * mpi2_cnfg.h Version: 02.00.10 55 * 56 * Version History 57 * --------------- 58 * 59 * Date Version Description 60 * -------- -------- ------------------------------------------------------ 61 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 62 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 63 * Added Manufacturing Page 11. 64 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 65 * define. 66 * 06-26-07 02.00.02 Adding generic structure for product-specific 67 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 68 * Rework of BIOS Page 2 configuration page. 69 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 70 * forms. 71 * Added configuration pages IOC Page 8 and Driver 72 * Persistent Mapping Page 0. 73 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 74 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 75 * RAID Physical Disk Pages 0 and 1, RAID Configuration 76 * Page 0). 77 * Added new value for AccessStatus field of SAS Device 78 * Page 0 (_SATA_NEEDS_INITIALIZATION). 79 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 80 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 81 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 82 * NVDATA. 83 * Modified IOC Page 7 to use masks and added field for 84 * SASBroadcastPrimitiveMasks. 85 * Added MPI2_CONFIG_PAGE_BIOS_4. 86 * Added MPI2_CONFIG_PAGE_LOG_0. 87 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 88 * Added SAS Device IDs. 89 * Updated Integrated RAID configuration pages including 90 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 91 * Page 0. 92 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 93 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 94 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 95 * Added missing MaxNumRoutedSasAddresses field to 96 * MPI2_CONFIG_PAGE_EXPANDER_0. 97 * Added SAS Port Page 0. 98 * Modified structure layout for 99 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 100 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 101 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 102 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 103 * to 0x000000FF. 104 * Added two new values for the Physical Disk Coercion Size 105 * bits in the Flags field of Manufacturing Page 4. 106 * Added product-specific Manufacturing pages 16 to 31. 107 * Modified Flags bits for controlling write cache on SATA 108 * drives in IO Unit Page 1. 109 * Added new bit to AdditionalControlFlags of SAS IO Unit 110 * Page 1 to control Invalid Topology Correction. 111 * Added additional defines for RAID Volume Page 0 112 * VolumeStatusFlags field. 113 * Modified meaning of RAID Volume Page 0 VolumeSettings 114 * define for auto-configure of hot-swap drives. 115 * Added SupportedPhysDisks field to RAID Volume Page 1 and 116 * added related defines. 117 * Added PhysDiskAttributes field (and related defines) to 118 * RAID Physical Disk Page 0. 119 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 120 * Added three new DiscoveryStatus bits for SAS IO Unit 121 * Page 0 and SAS Expander Page 0. 122 * Removed multiplexing information from SAS IO Unit pages. 123 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 124 * Removed Zone Address Resolved bit from PhyInfo and from 125 * Expander Page 0 Flags field. 126 * Added two new AccessStatus values to SAS Device Page 0 127 * for indicating routing problems. Added 3 reserved words 128 * to this page. 129 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 130 * Inserted missing reserved field into structure for IOC 131 * Page 6. 132 * Added more pending task bits to RAID Volume Page 0 133 * VolumeStatusFlags defines. 134 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 135 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 136 * and SAS Expander Page 0 to flag a downstream initiator 137 * when in simplified routing mode. 138 * Removed SATA Init Failure defines for DiscoveryStatus 139 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 140 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 141 * Added PortGroups, DmaGroup, and ControlGroup fields to 142 * SAS Device Page 0. 143 * -------------------------------------------------------------------------- 144 */ 145 146#ifndef MPI2_CNFG_H 147#define MPI2_CNFG_H 148 149/***************************************************************************** 150* Configuration Page Header and defines 151*****************************************************************************/ 152 153/* Config Page Header */ 154typedef struct _MPI2_CONFIG_PAGE_HEADER 155{ 156 U8 PageVersion; /* 0x00 */ 157 U8 PageLength; /* 0x01 */ 158 U8 PageNumber; /* 0x02 */ 159 U8 PageType; /* 0x03 */ 160} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 161 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 162 163typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 164{ 165 MPI2_CONFIG_PAGE_HEADER Struct; 166 U8 Bytes[4]; 167 U16 Word16[2]; 168 U32 Word32; 169} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 170 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 171 172/* Extended Config Page Header */ 173typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 174{ 175 U8 PageVersion; /* 0x00 */ 176 U8 Reserved1; /* 0x01 */ 177 U8 PageNumber; /* 0x02 */ 178 U8 PageType; /* 0x03 */ 179 U16 ExtPageLength; /* 0x04 */ 180 U8 ExtPageType; /* 0x06 */ 181 U8 Reserved2; /* 0x07 */ 182} MPI2_CONFIG_EXTENDED_PAGE_HEADER, 183 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 184 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 185 186typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 187{ 188 MPI2_CONFIG_PAGE_HEADER Struct; 189 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 190 U8 Bytes[8]; 191 U16 Word16[4]; 192 U32 Word32[2]; 193} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 194 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 195 196 197/* PageType field values */ 198#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 199#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 200#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 201#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 202 203#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 204#define MPI2_CONFIG_PAGETYPE_IOC (0x01) 205#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 206#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 207#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 208#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 209#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 210#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 211 212#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 213 214 215/* ExtPageType field values */ 216#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 217#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 218#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 219#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 220#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 221#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 222#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 223#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 224#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 225 226 227/***************************************************************************** 228* PageAddress defines 229*****************************************************************************/ 230 231/* RAID Volume PageAddress format */ 232#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 233#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 234#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 235 236#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 237 238 239/* RAID Physical Disk PageAddress format */ 240#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 241#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 242#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 243#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 244 245#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 246#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 247 248 249/* SAS Expander PageAddress format */ 250#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 251#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 252#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 253#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 254 255#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 256#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 257#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 258 259 260/* SAS Device PageAddress format */ 261#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 262#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 263#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 264 265#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 266 267 268/* SAS PHY PageAddress format */ 269#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 270#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 271#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 272 273#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 274#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 275 276 277/* SAS Port PageAddress format */ 278#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 279#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 280#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 281 282#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 283 284 285/* SAS Enclosure PageAddress format */ 286#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 287#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 288#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 289 290#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 291 292 293/* RAID Configuration PageAddress format */ 294#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 295#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 296#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 297#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 298 299#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 300 301 302/* Driver Persistent Mapping PageAddress format */ 303#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 304#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 305 306#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 307#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 308#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 309 310 311/**************************************************************************** 312* Configuration messages 313****************************************************************************/ 314 315/* Configuration Request Message */ 316typedef struct _MPI2_CONFIG_REQUEST 317{ 318 U8 Action; /* 0x00 */ 319 U8 SGLFlags; /* 0x01 */ 320 U8 ChainOffset; /* 0x02 */ 321 U8 Function; /* 0x03 */ 322 U16 ExtPageLength; /* 0x04 */ 323 U8 ExtPageType; /* 0x06 */ 324 U8 MsgFlags; /* 0x07 */ 325 U8 VP_ID; /* 0x08 */ 326 U8 VF_ID; /* 0x09 */ 327 U16 Reserved1; /* 0x0A */ 328 U32 Reserved2; /* 0x0C */ 329 U32 Reserved3; /* 0x10 */ 330 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 331 U32 PageAddress; /* 0x18 */ 332 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 333} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 334 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 335 336/* values for the Action field */ 337#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 338#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 339#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 340#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 341#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 342#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 343#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 344#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 345 346/* values for SGLFlags field are in the SGL section of mpi2.h */ 347 348 349/* Config Reply Message */ 350typedef struct _MPI2_CONFIG_REPLY 351{ 352 U8 Action; /* 0x00 */ 353 U8 SGLFlags; /* 0x01 */ 354 U8 MsgLength; /* 0x02 */ 355 U8 Function; /* 0x03 */ 356 U16 ExtPageLength; /* 0x04 */ 357 U8 ExtPageType; /* 0x06 */ 358 U8 MsgFlags; /* 0x07 */ 359 U8 VP_ID; /* 0x08 */ 360 U8 VF_ID; /* 0x09 */ 361 U16 Reserved1; /* 0x0A */ 362 U16 Reserved2; /* 0x0C */ 363 U16 IOCStatus; /* 0x0E */ 364 U32 IOCLogInfo; /* 0x10 */ 365 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 366} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 367 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 368 369 370 371/***************************************************************************** 372* 373* C o n f i g u r a t i o n P a g e s 374* 375*****************************************************************************/ 376 377/**************************************************************************** 378* Manufacturing Config pages 379****************************************************************************/ 380 381#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 382 383/* SAS */ 384#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 385#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 386#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 387#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 388#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 389#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 390#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 391 392 393/* Manufacturing Page 0 */ 394 395typedef struct _MPI2_CONFIG_PAGE_MAN_0 396{ 397 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 398 U8 ChipName[16]; /* 0x04 */ 399 U8 ChipRevision[8]; /* 0x14 */ 400 U8 BoardName[16]; /* 0x1C */ 401 U8 BoardAssembly[16]; /* 0x2C */ 402 U8 BoardTracerNumber[16]; /* 0x3C */ 403} MPI2_CONFIG_PAGE_MAN_0, 404 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 405 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 406 407#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 408 409 410/* Manufacturing Page 1 */ 411 412typedef struct _MPI2_CONFIG_PAGE_MAN_1 413{ 414 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 415 U8 VPD[256]; /* 0x04 */ 416} MPI2_CONFIG_PAGE_MAN_1, 417 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 418 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 419 420#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 421 422 423typedef struct _MPI2_CHIP_REVISION_ID 424{ 425 U16 DeviceID; /* 0x00 */ 426 U8 PCIRevisionID; /* 0x02 */ 427 U8 Reserved; /* 0x03 */ 428} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 429 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 430 431 432/* Manufacturing Page 2 */ 433 434/* 435 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 436 * one and check Header.PageLength at runtime. 437 */ 438#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 439#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 440#endif 441 442typedef struct _MPI2_CONFIG_PAGE_MAN_2 443{ 444 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 445 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 446 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 447} MPI2_CONFIG_PAGE_MAN_2, 448 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 449 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 450 451#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 452 453 454/* Manufacturing Page 3 */ 455 456/* 457 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 458 * one and check Header.PageLength at runtime. 459 */ 460#ifndef MPI2_MAN_PAGE_3_INFO_WORDS 461#define MPI2_MAN_PAGE_3_INFO_WORDS (1) 462#endif 463 464typedef struct _MPI2_CONFIG_PAGE_MAN_3 465{ 466 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 467 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 468 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 469} MPI2_CONFIG_PAGE_MAN_3, 470 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 471 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 472 473#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 474 475 476/* Manufacturing Page 4 */ 477 478typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 479{ 480 U8 PowerSaveFlags; /* 0x00 */ 481 U8 InternalOperationsSleepTime; /* 0x01 */ 482 U8 InternalOperationsRunTime; /* 0x02 */ 483 U8 HostIdleTime; /* 0x03 */ 484} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 485 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 486 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 487 488/* defines for the PowerSaveFlags field */ 489#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 490#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 491#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 492#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 493 494typedef struct _MPI2_CONFIG_PAGE_MAN_4 495{ 496 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 497 U32 Reserved1; /* 0x04 */ 498 U32 Flags; /* 0x08 */ 499 U8 InquirySize; /* 0x0C */ 500 U8 Reserved2; /* 0x0D */ 501 U16 Reserved3; /* 0x0E */ 502 U8 InquiryData[56]; /* 0x10 */ 503 U32 RAID0VolumeSettings; /* 0x48 */ 504 U32 RAID1EVolumeSettings; /* 0x4C */ 505 U32 RAID1VolumeSettings; /* 0x50 */ 506 U32 RAID10VolumeSettings; /* 0x54 */ 507 U32 Reserved4; /* 0x58 */ 508 U32 Reserved5; /* 0x5C */ 509 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 510 U8 MaxOCEDisks; /* 0x64 */ 511 U8 ResyncRate; /* 0x65 */ 512 U16 DataScrubDuration; /* 0x66 */ 513 U8 MaxHotSpares; /* 0x68 */ 514 U8 MaxPhysDisksPerVol; /* 0x69 */ 515 U8 MaxPhysDisks; /* 0x6A */ 516 U8 MaxVolumes; /* 0x6B */ 517} MPI2_CONFIG_PAGE_MAN_4, 518 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 519 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 520 521#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 522 523/* Manufacturing Page 4 Flags field */ 524#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 525#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 526 527#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 528#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 529#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 530 531#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 532#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 533#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 534#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 535#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 536 537#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 538#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 539#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 540#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 541 542#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 543#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 544#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 545#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 546#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 547#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 548#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 549#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 550 551 552/* Manufacturing Page 5 */ 553 554/* 555 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 556 * one and check Header.PageLength or NumPhys at runtime. 557 */ 558#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 559#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 560#endif 561 562typedef struct _MPI2_MANUFACTURING5_ENTRY 563{ 564 U64 WWID; /* 0x00 */ 565 U64 DeviceName; /* 0x08 */ 566} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 567 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 568 569typedef struct _MPI2_CONFIG_PAGE_MAN_5 570{ 571 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 572 U8 NumPhys; /* 0x04 */ 573 U8 Reserved1; /* 0x05 */ 574 U16 Reserved2; /* 0x06 */ 575 U32 Reserved3; /* 0x08 */ 576 U32 Reserved4; /* 0x0C */ 577 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 578} MPI2_CONFIG_PAGE_MAN_5, 579 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 580 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 581 582#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 583 584 585/* Manufacturing Page 6 */ 586 587typedef struct _MPI2_CONFIG_PAGE_MAN_6 588{ 589 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 590 U32 ProductSpecificInfo;/* 0x04 */ 591} MPI2_CONFIG_PAGE_MAN_6, 592 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 593 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 594 595#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 596 597 598/* Manufacturing Page 7 */ 599 600typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 601{ 602 U32 Pinout; /* 0x00 */ 603 U8 Connector[16]; /* 0x04 */ 604 U8 Location; /* 0x14 */ 605 U8 Reserved1; /* 0x15 */ 606 U16 Slot; /* 0x16 */ 607 U32 Reserved2; /* 0x18 */ 608} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 609 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 610 611/* defines for the Pinout field */ 612#define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 613#define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 614#define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 615#define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 616#define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 617#define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 618#define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 619#define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 620#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 621#define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 622 623/* defines for the Location field */ 624#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 625#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 626#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 627#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 628#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 629#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 630#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 631 632/* 633 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 634 * one and check NumPhys at runtime. 635 */ 636#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 637#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 638#endif 639 640typedef struct _MPI2_CONFIG_PAGE_MAN_7 641{ 642 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 643 U32 Reserved1; /* 0x04 */ 644 U32 Reserved2; /* 0x08 */ 645 U32 Flags; /* 0x0C */ 646 U8 EnclosureName[16]; /* 0x10 */ 647 U8 NumPhys; /* 0x20 */ 648 U8 Reserved3; /* 0x21 */ 649 U16 Reserved4; /* 0x22 */ 650 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 651} MPI2_CONFIG_PAGE_MAN_7, 652 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 653 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 654 655#define MPI2_MANUFACTURING7_PAGEVERSION (0x00) 656 657/* defines for the Flags field */ 658#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 659 660 661/* 662 * Generic structure to use for product-specific manufacturing pages 663 * (currently Manufacturing Page 8 through Manufacturing Page 31). 664 */ 665 666typedef struct _MPI2_CONFIG_PAGE_MAN_PS 667{ 668 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 669 U32 ProductSpecificInfo;/* 0x04 */ 670} MPI2_CONFIG_PAGE_MAN_PS, 671 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 672 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 673 674#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 675#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 676#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 677#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 678#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 679#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 680#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 681#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 682#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 683#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 684#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 685#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 686#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 687#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 688#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 689#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 690#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 691#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 692#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 693#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 694#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 695#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 696#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 697#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 698 699 700/**************************************************************************** 701* IO Unit Config Pages 702****************************************************************************/ 703 704/* IO Unit Page 0 */ 705 706typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 707{ 708 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 709 U64 UniqueValue; /* 0x04 */ 710 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 711 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 712} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 713 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 714 715#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 716 717 718/* IO Unit Page 1 */ 719 720typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 721{ 722 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 723 U32 Flags; /* 0x04 */ 724} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 725 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 726 727#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 728 729/* IO Unit Page 1 Flags defines */ 730#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 731#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 732#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 733#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 734#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 735#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 736#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 737#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 738#define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002) 739#define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 740 741 742/* IO Unit Page 3 */ 743 744/* 745 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 746 * one and check Header.PageLength at runtime. 747 */ 748#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 749#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 750#endif 751 752typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 753{ 754 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 755 U8 GPIOCount; /* 0x04 */ 756 U8 Reserved1; /* 0x05 */ 757 U16 Reserved2; /* 0x06 */ 758 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 759} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 760 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 761 762#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 763 764/* defines for IO Unit Page 3 GPIOVal field */ 765#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 766#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 767#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 768#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 769 770 771/**************************************************************************** 772* IOC Config Pages 773****************************************************************************/ 774 775/* IOC Page 0 */ 776 777typedef struct _MPI2_CONFIG_PAGE_IOC_0 778{ 779 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 780 U32 Reserved1; /* 0x04 */ 781 U32 Reserved2; /* 0x08 */ 782 U16 VendorID; /* 0x0C */ 783 U16 DeviceID; /* 0x0E */ 784 U8 RevisionID; /* 0x10 */ 785 U8 Reserved3; /* 0x11 */ 786 U16 Reserved4; /* 0x12 */ 787 U32 ClassCode; /* 0x14 */ 788 U16 SubsystemVendorID; /* 0x18 */ 789 U16 SubsystemID; /* 0x1A */ 790} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 791 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 792 793#define MPI2_IOCPAGE0_PAGEVERSION (0x02) 794 795 796/* IOC Page 1 */ 797 798typedef struct _MPI2_CONFIG_PAGE_IOC_1 799{ 800 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 801 U32 Flags; /* 0x04 */ 802 U32 CoalescingTimeout; /* 0x08 */ 803 U8 CoalescingDepth; /* 0x0C */ 804 U8 PCISlotNum; /* 0x0D */ 805 U8 PCIBusNum; /* 0x0E */ 806 U8 PCIDomainSegment; /* 0x0F */ 807 U32 Reserved1; /* 0x10 */ 808 U32 Reserved2; /* 0x14 */ 809} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 810 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 811 812#define MPI2_IOCPAGE1_PAGEVERSION (0x05) 813 814/* defines for IOC Page 1 Flags field */ 815#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 816 817#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 818#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 819#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 820 821/* IOC Page 6 */ 822 823typedef struct _MPI2_CONFIG_PAGE_IOC_6 824{ 825 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 826 U32 CapabilitiesFlags; /* 0x04 */ 827 U8 MaxDrivesRAID0; /* 0x08 */ 828 U8 MaxDrivesRAID1; /* 0x09 */ 829 U8 MaxDrivesRAID1E; /* 0x0A */ 830 U8 MaxDrivesRAID10; /* 0x0B */ 831 U8 MinDrivesRAID0; /* 0x0C */ 832 U8 MinDrivesRAID1; /* 0x0D */ 833 U8 MinDrivesRAID1E; /* 0x0E */ 834 U8 MinDrivesRAID10; /* 0x0F */ 835 U32 Reserved1; /* 0x10 */ 836 U8 MaxGlobalHotSpares; /* 0x14 */ 837 U8 MaxPhysDisks; /* 0x15 */ 838 U8 MaxVolumes; /* 0x16 */ 839 U8 MaxConfigs; /* 0x17 */ 840 U8 MaxOCEDisks; /* 0x18 */ 841 U8 Reserved2; /* 0x19 */ 842 U16 Reserved3; /* 0x1A */ 843 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 844 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 845 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 846 U32 Reserved4; /* 0x28 */ 847 U32 Reserved5; /* 0x2C */ 848 U16 DefaultMetadataSize; /* 0x30 */ 849 U16 Reserved6; /* 0x32 */ 850 U16 MaxBadBlockTableEntries; /* 0x34 */ 851 U16 Reserved7; /* 0x36 */ 852 U32 IRNvsramVersion; /* 0x38 */ 853} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 854 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 855 856#define MPI2_IOCPAGE6_PAGEVERSION (0x04) 857 858/* defines for IOC Page 6 CapabilitiesFlags */ 859#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 860#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 861#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 862#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 863#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 864 865 866/* IOC Page 7 */ 867 868#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 869 870typedef struct _MPI2_CONFIG_PAGE_IOC_7 871{ 872 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 873 U32 Reserved1; /* 0x04 */ 874 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 875 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 876 U16 Reserved2; /* 0x1A */ 877 U32 Reserved3; /* 0x1C */ 878} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 879 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 880 881#define MPI2_IOCPAGE7_PAGEVERSION (0x01) 882 883 884/* IOC Page 8 */ 885 886typedef struct _MPI2_CONFIG_PAGE_IOC_8 887{ 888 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 889 U8 NumDevsPerEnclosure; /* 0x04 */ 890 U8 Reserved1; /* 0x05 */ 891 U16 Reserved2; /* 0x06 */ 892 U16 MaxPersistentEntries; /* 0x08 */ 893 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 894 U16 Flags; /* 0x0C */ 895 U16 Reserved3; /* 0x0E */ 896 U16 IRVolumeMappingFlags; /* 0x10 */ 897 U16 Reserved4; /* 0x12 */ 898 U32 Reserved5; /* 0x14 */ 899} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 900 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 901 902#define MPI2_IOCPAGE8_PAGEVERSION (0x00) 903 904/* defines for IOC Page 8 Flags field */ 905#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 906#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 907 908#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 909#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 910#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 911 912#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 913#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 914 915/* defines for IOC Page 8 IRVolumeMappingFlags */ 916#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 917#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 918#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 919 920 921/**************************************************************************** 922* BIOS Config Pages 923****************************************************************************/ 924 925/* BIOS Page 1 */ 926 927typedef struct _MPI2_CONFIG_PAGE_BIOS_1 928{ 929 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 930 U32 BiosOptions; /* 0x04 */ 931 U32 IOCSettings; /* 0x08 */ 932 U32 Reserved1; /* 0x0C */ 933 U32 DeviceSettings; /* 0x10 */ 934 U16 NumberOfDevices; /* 0x14 */ 935 U16 Reserved2; /* 0x16 */ 936 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 937 U16 IOTimeoutSequential; /* 0x1A */ 938 U16 IOTimeoutOther; /* 0x1C */ 939 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 940} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 941 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 942 943#define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 944 945/* values for BIOS Page 1 BiosOptions field */ 946#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 947 948/* values for BIOS Page 1 IOCSettings field */ 949#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 950#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 951#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 952 953#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 954#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 955#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 956#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 957 958#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 959#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 960#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 961#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 962#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 963 964#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 965 966/* values for BIOS Page 1 DeviceSettings field */ 967#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 968#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 969#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 970#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 971#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 972 973 974/* BIOS Page 2 */ 975 976typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 977{ 978 U32 Reserved1; /* 0x00 */ 979 U32 Reserved2; /* 0x04 */ 980 U32 Reserved3; /* 0x08 */ 981 U32 Reserved4; /* 0x0C */ 982 U32 Reserved5; /* 0x10 */ 983 U32 Reserved6; /* 0x14 */ 984} MPI2_BOOT_DEVICE_ADAPTER_ORDER, 985 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 986 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 987 988typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 989{ 990 U64 SASAddress; /* 0x00 */ 991 U8 LUN[8]; /* 0x08 */ 992 U32 Reserved1; /* 0x10 */ 993 U32 Reserved2; /* 0x14 */ 994} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 995 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 996 997typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 998{ 999 U64 EnclosureLogicalID; /* 0x00 */ 1000 U32 Reserved1; /* 0x08 */ 1001 U32 Reserved2; /* 0x0C */ 1002 U16 SlotNumber; /* 0x10 */ 1003 U16 Reserved3; /* 0x12 */ 1004 U32 Reserved4; /* 0x14 */ 1005} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1006 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1007 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1008 1009typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1010{ 1011 U64 DeviceName; /* 0x00 */ 1012 U8 LUN[8]; /* 0x08 */ 1013 U32 Reserved1; /* 0x10 */ 1014 U32 Reserved2; /* 0x14 */ 1015} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1016 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1017 1018typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1019{ 1020 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1021 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1022 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1023 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1024} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1025 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1026 1027typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1028{ 1029 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1030 U32 Reserved1; /* 0x04 */ 1031 U32 Reserved2; /* 0x08 */ 1032 U32 Reserved3; /* 0x0C */ 1033 U32 Reserved4; /* 0x10 */ 1034 U32 Reserved5; /* 0x14 */ 1035 U32 Reserved6; /* 0x18 */ 1036 U8 ReqBootDeviceForm; /* 0x1C */ 1037 U8 Reserved7; /* 0x1D */ 1038 U16 Reserved8; /* 0x1E */ 1039 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1040 U8 ReqAltBootDeviceForm; /* 0x38 */ 1041 U8 Reserved9; /* 0x39 */ 1042 U16 Reserved10; /* 0x3A */ 1043 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1044 U8 CurrentBootDeviceForm; /* 0x58 */ 1045 U8 Reserved11; /* 0x59 */ 1046 U16 Reserved12; /* 0x5A */ 1047 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1048} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1049 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1050 1051#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1052 1053/* values for BIOS Page 2 BootDeviceForm fields */ 1054#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1055#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1056#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1057#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1058#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1059 1060 1061/* BIOS Page 3 */ 1062 1063typedef struct _MPI2_ADAPTER_INFO 1064{ 1065 U8 PciBusNumber; /* 0x00 */ 1066 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1067 U16 AdapterFlags; /* 0x02 */ 1068} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1069 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1070 1071#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1072#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1073 1074typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1075{ 1076 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1077 U32 GlobalFlags; /* 0x04 */ 1078 U32 BiosVersion; /* 0x08 */ 1079 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1080 U32 Reserved1; /* 0x1C */ 1081} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1082 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1083 1084#define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1085 1086/* values for BIOS Page 3 GlobalFlags */ 1087#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1088#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1089#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1090 1091#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1092#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1093#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1094#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1095 1096 1097/* BIOS Page 4 */ 1098 1099/* 1100 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1101 * one and check Header.PageLength or NumPhys at runtime. 1102 */ 1103#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1104#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1105#endif 1106 1107typedef struct _MPI2_BIOS4_ENTRY 1108{ 1109 U64 ReassignmentWWID; /* 0x00 */ 1110 U64 ReassignmentDeviceName; /* 0x08 */ 1111} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1112 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1113 1114typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1115{ 1116 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1117 U8 NumPhys; /* 0x04 */ 1118 U8 Reserved1; /* 0x05 */ 1119 U16 Reserved2; /* 0x06 */ 1120 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1121} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1122 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1123 1124#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1125 1126 1127/**************************************************************************** 1128* RAID Volume Config Pages 1129****************************************************************************/ 1130 1131/* RAID Volume Page 0 */ 1132 1133typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1134{ 1135 U8 RAIDSetNum; /* 0x00 */ 1136 U8 PhysDiskMap; /* 0x01 */ 1137 U8 PhysDiskNum; /* 0x02 */ 1138 U8 Reserved; /* 0x03 */ 1139} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1140 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1141 1142/* defines for the PhysDiskMap field */ 1143#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1144#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1145 1146typedef struct _MPI2_RAIDVOL0_SETTINGS 1147{ 1148 U16 Settings; /* 0x00 */ 1149 U8 HotSparePool; /* 0x01 */ 1150 U8 Reserved; /* 0x02 */ 1151} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1152 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1153 1154/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1155#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1156#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1157#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1158#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1159#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1160#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1161#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1162#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1163 1164/* RAID Volume Page 0 VolumeSettings defines */ 1165#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1166#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1167 1168#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1169#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1170#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1171#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1172 1173/* 1174 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1175 * one and check Header.PageLength at runtime. 1176 */ 1177#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1178#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1179#endif 1180 1181typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1182{ 1183 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1184 U16 DevHandle; /* 0x04 */ 1185 U8 VolumeState; /* 0x06 */ 1186 U8 VolumeType; /* 0x07 */ 1187 U32 VolumeStatusFlags; /* 0x08 */ 1188 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1189 U64 MaxLBA; /* 0x10 */ 1190 U32 StripeSize; /* 0x18 */ 1191 U16 BlockSize; /* 0x1C */ 1192 U16 Reserved1; /* 0x1E */ 1193 U8 SupportedPhysDisks; /* 0x20 */ 1194 U8 ResyncRate; /* 0x21 */ 1195 U16 DataScrubDuration; /* 0x22 */ 1196 U8 NumPhysDisks; /* 0x24 */ 1197 U8 Reserved2; /* 0x25 */ 1198 U8 Reserved3; /* 0x26 */ 1199 U8 InactiveStatus; /* 0x27 */ 1200 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1201} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1202 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1203 1204#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1205 1206/* values for RAID VolumeState */ 1207#define MPI2_RAID_VOL_STATE_MISSING (0x00) 1208#define MPI2_RAID_VOL_STATE_FAILED (0x01) 1209#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1210#define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1211#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1212#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1213 1214/* values for RAID VolumeType */ 1215#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1216#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1217#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1218#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1219#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1220 1221/* values for RAID Volume Page 0 VolumeStatusFlags field */ 1222#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1223#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1224#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1225#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1226#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1227#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1228#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1229#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1230#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1231#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1232#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1233#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1234#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1235#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1236#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1237#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1238#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1239#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1240 1241/* values for RAID Volume Page 0 SupportedPhysDisks field */ 1242#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1243#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1244#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1245#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1246 1247/* values for RAID Volume Page 0 InactiveStatus field */ 1248#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1249#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1250#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1251#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1252#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1253#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1254#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1255 1256 1257/* RAID Volume Page 1 */ 1258 1259typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1260{ 1261 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1262 U16 DevHandle; /* 0x04 */ 1263 U16 Reserved0; /* 0x06 */ 1264 U8 GUID[24]; /* 0x08 */ 1265 U8 Name[16]; /* 0x20 */ 1266 U64 WWID; /* 0x30 */ 1267 U32 Reserved1; /* 0x38 */ 1268 U32 Reserved2; /* 0x3C */ 1269} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1270 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1271 1272#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1273 1274 1275/**************************************************************************** 1276* RAID Physical Disk Config Pages 1277****************************************************************************/ 1278 1279/* RAID Physical Disk Page 0 */ 1280 1281typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1282{ 1283 U16 Reserved1; /* 0x00 */ 1284 U8 HotSparePool; /* 0x02 */ 1285 U8 Reserved2; /* 0x03 */ 1286} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1287 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1288 1289/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1290 1291typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1292{ 1293 U8 VendorID[8]; /* 0x00 */ 1294 U8 ProductID[16]; /* 0x08 */ 1295 U8 ProductRevLevel[4]; /* 0x18 */ 1296 U8 SerialNum[32]; /* 0x1C */ 1297} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1298 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1299 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1300 1301typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1302{ 1303 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1304 U16 DevHandle; /* 0x04 */ 1305 U8 Reserved1; /* 0x06 */ 1306 U8 PhysDiskNum; /* 0x07 */ 1307 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1308 U32 Reserved2; /* 0x0C */ 1309 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1310 U32 Reserved3; /* 0x4C */ 1311 U8 PhysDiskState; /* 0x50 */ 1312 U8 OfflineReason; /* 0x51 */ 1313 U8 IncompatibleReason; /* 0x52 */ 1314 U8 PhysDiskAttributes; /* 0x53 */ 1315 U32 PhysDiskStatusFlags; /* 0x54 */ 1316 U64 DeviceMaxLBA; /* 0x58 */ 1317 U64 HostMaxLBA; /* 0x60 */ 1318 U64 CoercedMaxLBA; /* 0x68 */ 1319 U16 BlockSize; /* 0x70 */ 1320 U16 Reserved5; /* 0x72 */ 1321 U32 Reserved6; /* 0x74 */ 1322} MPI2_CONFIG_PAGE_RD_PDISK_0, 1323 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1324 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1325 1326#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1327 1328/* PhysDiskState defines */ 1329#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1330#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1331#define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1332#define MPI2_RAID_PD_STATE_ONLINE (0x03) 1333#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1334#define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1335#define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1336#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1337 1338/* OfflineReason defines */ 1339#define MPI2_PHYSDISK0_ONLINE (0x00) 1340#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1341#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1342#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1343#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1344#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1345#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1346 1347/* IncompatibleReason defines */ 1348#define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1349#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1350#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1351#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1352#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1353#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1354#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1355 1356/* PhysDiskAttributes defines */ 1357#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1358#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1359#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1360#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1361 1362/* PhysDiskStatusFlags defines */ 1363#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1364#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1365#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1366#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1367#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1368#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1369#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1370#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1371 1372 1373/* RAID Physical Disk Page 1 */ 1374 1375/* 1376 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1377 * one and check Header.PageLength or NumPhysDiskPaths at runtime. 1378 */ 1379#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1380#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1381#endif 1382 1383typedef struct _MPI2_RAIDPHYSDISK1_PATH 1384{ 1385 U16 DevHandle; /* 0x00 */ 1386 U16 Reserved1; /* 0x02 */ 1387 U64 WWID; /* 0x04 */ 1388 U64 OwnerWWID; /* 0x0C */ 1389 U8 OwnerIdentifier; /* 0x14 */ 1390 U8 Reserved2; /* 0x15 */ 1391 U16 Flags; /* 0x16 */ 1392} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1393 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1394 1395/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1396#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1397#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1398#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1399 1400typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1401{ 1402 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1403 U8 NumPhysDiskPaths; /* 0x04 */ 1404 U8 PhysDiskNum; /* 0x05 */ 1405 U16 Reserved1; /* 0x06 */ 1406 U32 Reserved2; /* 0x08 */ 1407 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1408} MPI2_CONFIG_PAGE_RD_PDISK_1, 1409 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1410 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1411 1412#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1413 1414 1415/**************************************************************************** 1416* values for fields used by several types of SAS Config Pages 1417****************************************************************************/ 1418 1419/* values for NegotiatedLinkRates fields */ 1420#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1421#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1422#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1423/* link rates used for Negotiated Physical and Logical Link Rate */ 1424#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1425#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1426#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1427#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1428#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1429#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1430#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1431#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1432#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1433 1434 1435/* values for AttachedPhyInfo fields */ 1436#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1437#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1438#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1439 1440#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1441#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1442#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1443#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1444#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1445#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1446#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1447#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1448#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1449#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1450 1451 1452/* values for PhyInfo fields */ 1453#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1454#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1455#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1456#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1457#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1458#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1459#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1460 1461#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1462#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1463#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1464#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1465#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1466#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1467#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1468#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1469#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1470#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1471 1472#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1473#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1474#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1475#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1476 1477#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1478#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1479 1480#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1481#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1482#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1483#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1484 1485 1486/* values for SAS ProgrammedLinkRate fields */ 1487#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1488#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1489#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1490#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1491#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1492#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1493#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1494#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1495#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1496#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1497 1498 1499/* values for SAS HwLinkRate fields */ 1500#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1501#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1502#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1503#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1504#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1505#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1506#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1507#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1508 1509 1510 1511/**************************************************************************** 1512* SAS IO Unit Config Pages 1513****************************************************************************/ 1514 1515/* SAS IO Unit Page 0 */ 1516 1517typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1518{ 1519 U8 Port; /* 0x00 */ 1520 U8 PortFlags; /* 0x01 */ 1521 U8 PhyFlags; /* 0x02 */ 1522 U8 NegotiatedLinkRate; /* 0x03 */ 1523 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1524 U16 AttachedDevHandle; /* 0x08 */ 1525 U16 ControllerDevHandle; /* 0x0A */ 1526 U32 DiscoveryStatus; /* 0x0C */ 1527 U32 Reserved; /* 0x10 */ 1528} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1529 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1530 1531/* 1532 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1533 * one and check Header.ExtPageLength or NumPhys at runtime. 1534 */ 1535#ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1536#define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1537#endif 1538 1539typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1540{ 1541 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1542 U32 Reserved1; /* 0x08 */ 1543 U8 NumPhys; /* 0x0C */ 1544 U8 Reserved2; /* 0x0D */ 1545 U16 Reserved3; /* 0x0E */ 1546 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1547} MPI2_CONFIG_PAGE_SASIOUNIT_0, 1548 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1549 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1550 1551#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1552 1553/* values for SAS IO Unit Page 0 PortFlags */ 1554#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1555#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1556 1557/* values for SAS IO Unit Page 0 PhyFlags */ 1558#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1559#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1560 1561/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1562 1563/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1564 1565/* values for SAS IO Unit Page 0 DiscoveryStatus */ 1566#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1567#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1568#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1569#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1570#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1571#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1572#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1573#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1574#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1575#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1576#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1577#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1578#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1579#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1580#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1581#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1582#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1583#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1584#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1585#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1586 1587 1588/* SAS IO Unit Page 1 */ 1589 1590typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1591{ 1592 U8 Port; /* 0x00 */ 1593 U8 PortFlags; /* 0x01 */ 1594 U8 PhyFlags; /* 0x02 */ 1595 U8 MaxMinLinkRate; /* 0x03 */ 1596 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1597 U16 MaxTargetPortConnectTime; /* 0x08 */ 1598 U16 Reserved1; /* 0x0A */ 1599} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1600 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1601 1602/* 1603 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1604 * one and check Header.ExtPageLength or NumPhys at runtime. 1605 */ 1606#ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1607#define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1608#endif 1609 1610typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1611{ 1612 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1613 U16 ControlFlags; /* 0x08 */ 1614 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1615 U16 AdditionalControlFlags; /* 0x0C */ 1616 U16 SASWideMaxQueueDepth; /* 0x0E */ 1617 U8 NumPhys; /* 0x10 */ 1618 U8 SATAMaxQDepth; /* 0x11 */ 1619 U8 ReportDeviceMissingDelay; /* 0x12 */ 1620 U8 IODeviceMissingDelay; /* 0x13 */ 1621 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1622} MPI2_CONFIG_PAGE_SASIOUNIT_1, 1623 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1624 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1625 1626#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1627 1628/* values for SAS IO Unit Page 1 ControlFlags */ 1629#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1630#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1631#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1632#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1633 1634#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1635#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1636#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1637#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1638#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1639 1640#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1641#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1642#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1643#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1644#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1645#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1646#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1647#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1648 1649/* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1650#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1651#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1652#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1653#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1654#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1655#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1656#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1657#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1658 1659/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1660#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1661#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1662 1663/* values for SAS IO Unit Page 1 PortFlags */ 1664#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1665 1666/* values for SAS IO Unit Page 2 PhyFlags */ 1667#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1668#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1669 1670/* values for SAS IO Unit Page 0 MaxMinLinkRate */ 1671#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1672#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1673#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1674#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1675#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1676#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1677#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1678#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1679 1680/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1681 1682 1683/* SAS IO Unit Page 4 */ 1684 1685typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1686{ 1687 U8 MaxTargetSpinup; /* 0x00 */ 1688 U8 SpinupDelay; /* 0x01 */ 1689 U16 Reserved1; /* 0x02 */ 1690} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1691 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1692 1693/* 1694 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1695 * four and check Header.ExtPageLength or NumPhys at runtime. 1696 */ 1697#ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1698#define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1699#endif 1700 1701typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1702{ 1703 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1704 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1705 U32 Reserved1; /* 0x18 */ 1706 U32 Reserved2; /* 0x1C */ 1707 U32 Reserved3; /* 0x20 */ 1708 U8 BootDeviceWaitTime; /* 0x24 */ 1709 U8 Reserved4; /* 0x25 */ 1710 U16 Reserved5; /* 0x26 */ 1711 U8 NumPhys; /* 0x28 */ 1712 U8 PEInitialSpinupDelay; /* 0x29 */ 1713 U8 PEReplyDelay; /* 0x2A */ 1714 U8 Flags; /* 0x2B */ 1715 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1716} MPI2_CONFIG_PAGE_SASIOUNIT_4, 1717 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1718 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1719 1720#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1721 1722/* defines for Flags field */ 1723#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1724 1725/* defines for PHY field */ 1726#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1727 1728 1729/**************************************************************************** 1730* SAS Expander Config Pages 1731****************************************************************************/ 1732 1733/* SAS Expander Page 0 */ 1734 1735typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 1736{ 1737 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1738 U8 PhysicalPort; /* 0x08 */ 1739 U8 ReportGenLength; /* 0x09 */ 1740 U16 EnclosureHandle; /* 0x0A */ 1741 U64 SASAddress; /* 0x0C */ 1742 U32 DiscoveryStatus; /* 0x14 */ 1743 U16 DevHandle; /* 0x18 */ 1744 U16 ParentDevHandle; /* 0x1A */ 1745 U16 ExpanderChangeCount; /* 0x1C */ 1746 U16 ExpanderRouteIndexes; /* 0x1E */ 1747 U8 NumPhys; /* 0x20 */ 1748 U8 SASLevel; /* 0x21 */ 1749 U16 Flags; /* 0x22 */ 1750 U16 STPBusInactivityTimeLimit; /* 0x24 */ 1751 U16 STPMaxConnectTimeLimit; /* 0x26 */ 1752 U16 STP_SMP_NexusLossTime; /* 0x28 */ 1753 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 1754 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 1755 U16 ZoneLockInactivityLimit; /* 0x34 */ 1756 U16 Reserved1; /* 0x36 */ 1757} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 1758 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 1759 1760#define MPI2_SASEXPANDER0_PAGEVERSION (0x05) 1761 1762/* values for SAS Expander Page 0 DiscoveryStatus field */ 1763#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1764#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1765#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 1766#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1767#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1768#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1769#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1770#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 1771#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1772#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 1773#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 1774#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 1775#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 1776#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 1777#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 1778#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1779#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 1780#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 1781#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1782#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 1783 1784/* values for SAS Expander Page 0 Flags field */ 1785#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 1786#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 1787#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 1788#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 1789#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 1790#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 1791#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 1792#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 1793#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 1794#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 1795 1796 1797/* SAS Expander Page 1 */ 1798 1799typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 1800{ 1801 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1802 U8 PhysicalPort; /* 0x08 */ 1803 U8 Reserved1; /* 0x09 */ 1804 U16 Reserved2; /* 0x0A */ 1805 U8 NumPhys; /* 0x0C */ 1806 U8 Phy; /* 0x0D */ 1807 U16 NumTableEntriesProgrammed; /* 0x0E */ 1808 U8 ProgrammedLinkRate; /* 0x10 */ 1809 U8 HwLinkRate; /* 0x11 */ 1810 U16 AttachedDevHandle; /* 0x12 */ 1811 U32 PhyInfo; /* 0x14 */ 1812 U32 AttachedDeviceInfo; /* 0x18 */ 1813 U16 ExpanderDevHandle; /* 0x1C */ 1814 U8 ChangeCount; /* 0x1E */ 1815 U8 NegotiatedLinkRate; /* 0x1F */ 1816 U8 PhyIdentifier; /* 0x20 */ 1817 U8 AttachedPhyIdentifier; /* 0x21 */ 1818 U8 Reserved3; /* 0x22 */ 1819 U8 DiscoveryInfo; /* 0x23 */ 1820 U32 AttachedPhyInfo; /* 0x24 */ 1821 U8 ZoneGroup; /* 0x28 */ 1822 U8 SelfConfigStatus; /* 0x29 */ 1823 U16 Reserved4; /* 0x2A */ 1824} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 1825 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 1826 1827#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 1828 1829/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 1830 1831/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 1832 1833/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 1834 1835/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 1836 1837/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1838 1839/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 1840 1841/* values for SAS Expander Page 1 DiscoveryInfo field */ 1842#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 1843#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 1844#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 1845 1846 1847/**************************************************************************** 1848* SAS Device Config Pages 1849****************************************************************************/ 1850 1851/* SAS Device Page 0 */ 1852 1853typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 1854{ 1855 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1856 U16 Slot; /* 0x08 */ 1857 U16 EnclosureHandle; /* 0x0A */ 1858 U64 SASAddress; /* 0x0C */ 1859 U16 ParentDevHandle; /* 0x14 */ 1860 U8 PhyNum; /* 0x16 */ 1861 U8 AccessStatus; /* 0x17 */ 1862 U16 DevHandle; /* 0x18 */ 1863 U8 AttachedPhyIdentifier; /* 0x1A */ 1864 U8 ZoneGroup; /* 0x1B */ 1865 U32 DeviceInfo; /* 0x1C */ 1866 U16 Flags; /* 0x20 */ 1867 U8 PhysicalPort; /* 0x22 */ 1868 U8 MaxPortConnections; /* 0x23 */ 1869 U64 DeviceName; /* 0x24 */ 1870 U8 PortGroups; /* 0x2C */ 1871 U8 DmaGroup; /* 0x2D */ 1872 U8 ControlGroup; /* 0x2E */ 1873 U8 Reserved1; /* 0x2F */ 1874 U32 Reserved2; /* 0x30 */ 1875 U32 Reserved3; /* 0x34 */ 1876} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 1877 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 1878 1879#define MPI2_SASDEVICE0_PAGEVERSION (0x08) 1880 1881/* values for SAS Device Page 0 AccessStatus field */ 1882#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 1883#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 1884#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 1885#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 1886#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 1887#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 1888#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 1889#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 1890/* specific values for SATA Init failures */ 1891#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 1892#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 1893#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 1894#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 1895#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 1896#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 1897#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 1898#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 1899#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 1900#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 1901#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 1902 1903/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 1904 1905/* values for SAS Device Page 0 Flags field */ 1906#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 1907#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 1908#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 1909#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 1910#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 1911#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 1912#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 1913#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 1914#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 1915 1916 1917/* SAS Device Page 1 */ 1918 1919typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 1920{ 1921 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1922 U32 Reserved1; /* 0x08 */ 1923 U64 SASAddress; /* 0x0C */ 1924 U32 Reserved2; /* 0x14 */ 1925 U16 DevHandle; /* 0x18 */ 1926 U16 Reserved3; /* 0x1A */ 1927 U8 InitialRegDeviceFIS[20];/* 0x1C */ 1928} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 1929 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 1930 1931#define MPI2_SASDEVICE1_PAGEVERSION (0x01) 1932 1933 1934/**************************************************************************** 1935* SAS PHY Config Pages 1936****************************************************************************/ 1937 1938/* SAS PHY Page 0 */ 1939 1940typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 1941{ 1942 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1943 U16 OwnerDevHandle; /* 0x08 */ 1944 U16 Reserved1; /* 0x0A */ 1945 U16 AttachedDevHandle; /* 0x0C */ 1946 U8 AttachedPhyIdentifier; /* 0x0E */ 1947 U8 Reserved2; /* 0x0F */ 1948 U32 AttachedPhyInfo; /* 0x10 */ 1949 U8 ProgrammedLinkRate; /* 0x14 */ 1950 U8 HwLinkRate; /* 0x15 */ 1951 U8 ChangeCount; /* 0x16 */ 1952 U8 Flags; /* 0x17 */ 1953 U32 PhyInfo; /* 0x18 */ 1954 U8 NegotiatedLinkRate; /* 0x1C */ 1955 U8 Reserved3; /* 0x1D */ 1956 U16 Reserved4; /* 0x1E */ 1957} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 1958 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 1959 1960#define MPI2_SASPHY0_PAGEVERSION (0x03) 1961 1962/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 1963 1964/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 1965 1966/* values for SAS PHY Page 0 Flags field */ 1967#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 1968 1969/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 1970 1971/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1972 1973/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 1974 1975 1976/* SAS PHY Page 1 */ 1977 1978typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 1979{ 1980 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1981 U32 Reserved1; /* 0x08 */ 1982 U32 InvalidDwordCount; /* 0x0C */ 1983 U32 RunningDisparityErrorCount; /* 0x10 */ 1984 U32 LossDwordSynchCount; /* 0x14 */ 1985 U32 PhyResetProblemCount; /* 0x18 */ 1986} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 1987 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 1988 1989#define MPI2_SASPHY1_PAGEVERSION (0x01) 1990 1991 1992/**************************************************************************** 1993* SAS Port Config Pages 1994****************************************************************************/ 1995 1996/* SAS Port Page 0 */ 1997 1998typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 1999{ 2000 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2001 U8 PortNumber; /* 0x08 */ 2002 U8 PhysicalPort; /* 0x09 */ 2003 U8 PortWidth; /* 0x0A */ 2004 U8 PhysicalPortWidth; /* 0x0B */ 2005 U8 ZoneGroup; /* 0x0C */ 2006 U8 Reserved1; /* 0x0D */ 2007 U16 Reserved2; /* 0x0E */ 2008 U64 SASAddress; /* 0x10 */ 2009 U32 DeviceInfo; /* 0x18 */ 2010 U32 Reserved3; /* 0x1C */ 2011 U32 Reserved4; /* 0x20 */ 2012} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2013 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2014 2015#define MPI2_SASPORT0_PAGEVERSION (0x00) 2016 2017/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2018 2019 2020/**************************************************************************** 2021* SAS Enclosure Config Pages 2022****************************************************************************/ 2023 2024/* SAS Enclosure Page 0 */ 2025 2026typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2027{ 2028 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2029 U32 Reserved1; /* 0x08 */ 2030 U64 EnclosureLogicalID; /* 0x0C */ 2031 U16 Flags; /* 0x14 */ 2032 U16 EnclosureHandle; /* 0x16 */ 2033 U16 NumSlots; /* 0x18 */ 2034 U16 StartSlot; /* 0x1A */ 2035 U16 Reserved2; /* 0x1C */ 2036 U16 SEPDevHandle; /* 0x1E */ 2037 U32 Reserved3; /* 0x20 */ 2038 U32 Reserved4; /* 0x24 */ 2039} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2040 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2041 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2042 2043#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2044 2045/* values for SAS Enclosure Page 0 Flags field */ 2046#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2047#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2048#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2049#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2050#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2051#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2052#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2053 2054 2055/**************************************************************************** 2056* Log Config Page 2057****************************************************************************/ 2058 2059/* Log Page 0 */ 2060 2061/* 2062 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2063 * one and check Header.ExtPageLength or NumPhys at runtime. 2064 */ 2065#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2066#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2067#endif 2068 2069#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2070 2071typedef struct _MPI2_LOG_0_ENTRY 2072{ 2073 U64 TimeStamp; /* 0x00 */ 2074 U32 Reserved1; /* 0x08 */ 2075 U16 LogSequence; /* 0x0C */ 2076 U16 LogEntryQualifier; /* 0x0E */ 2077 U8 VP_ID; /* 0x10 */ 2078 U8 VF_ID; /* 0x11 */ 2079 U16 Reserved2; /* 0x12 */ 2080 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2081} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2082 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2083 2084/* values for Log Page 0 LogEntry LogEntryQualifier field */ 2085#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2086#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2087#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2088#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2089#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2090 2091typedef struct _MPI2_CONFIG_PAGE_LOG_0 2092{ 2093 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2094 U32 Reserved1; /* 0x08 */ 2095 U32 Reserved2; /* 0x0C */ 2096 U16 NumLogEntries; /* 0x10 */ 2097 U16 Reserved3; /* 0x12 */ 2098 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2099} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2100 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2101 2102#define MPI2_LOG_0_PAGEVERSION (0x02) 2103 2104 2105/**************************************************************************** 2106* RAID Config Page 2107****************************************************************************/ 2108 2109/* RAID Page 0 */ 2110 2111/* 2112 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2113 * one and check Header.ExtPageLength or NumPhys at runtime. 2114 */ 2115#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2116#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2117#endif 2118 2119typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2120{ 2121 U16 ElementFlags; /* 0x00 */ 2122 U16 VolDevHandle; /* 0x02 */ 2123 U8 HotSparePool; /* 0x04 */ 2124 U8 PhysDiskNum; /* 0x05 */ 2125 U16 PhysDiskDevHandle; /* 0x06 */ 2126} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2127 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2128 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2129 2130/* values for the ElementFlags field */ 2131#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2132#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2133#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2134#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2135#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2136 2137 2138typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2139{ 2140 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2141 U8 NumHotSpares; /* 0x08 */ 2142 U8 NumPhysDisks; /* 0x09 */ 2143 U8 NumVolumes; /* 0x0A */ 2144 U8 ConfigNum; /* 0x0B */ 2145 U32 Flags; /* 0x0C */ 2146 U8 ConfigGUID[24]; /* 0x10 */ 2147 U32 Reserved1; /* 0x28 */ 2148 U8 NumElements; /* 0x2C */ 2149 U8 Reserved2; /* 0x2D */ 2150 U16 Reserved3; /* 0x2E */ 2151 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2152} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2153 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2154 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2155 2156#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2157 2158/* values for RAID Configuration Page 0 Flags field */ 2159#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2160 2161 2162/**************************************************************************** 2163* Driver Persistent Mapping Config Pages 2164****************************************************************************/ 2165 2166/* Driver Persistent Mapping Page 0 */ 2167 2168typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2169{ 2170 U64 PhysicalIdentifier; /* 0x00 */ 2171 U16 MappingInformation; /* 0x08 */ 2172 U16 DeviceIndex; /* 0x0A */ 2173 U32 PhysicalBitsMapping; /* 0x0C */ 2174 U32 Reserved1; /* 0x10 */ 2175} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2176 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2177 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2178 2179typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2180{ 2181 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2182 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2183} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2184 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2185 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2186 2187#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2188 2189/* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2190#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2191#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2192#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2193 2194 2195#endif 2196 2197