sata_defs.h revision 9058:a7b4d0b3fd3d
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _SATA_DEFS_H 28#define _SATA_DEFS_H 29 30#ifdef __cplusplus 31extern "C" { 32#endif 33 34#include <sys/scsi/generic/mode.h> 35 36/* 37 * Common ATA commands (subset) 38 */ 39#define SATAC_DIAG 0x90 /* diagnose command */ 40#define SATAC_RECAL 0x10 /* restore cmd, 4 bits step rate */ 41#define SATAC_FORMAT 0x50 /* format track command */ 42#define SATAC_SET_FEATURES 0xef /* set features */ 43#define SATAC_IDLE_IM 0xe1 /* idle immediate */ 44#define SATAC_STANDBY_IM 0xe0 /* standby immediate */ 45#define SATAC_DOOR_LOCK 0xde /* door lock */ 46#define SATAC_DOOR_UNLOCK 0xdf /* door unlock */ 47#define SATAC_IDLE 0xe3 /* idle */ 48 49/* 50 * ATA/ATAPI disk commands (subset) 51 */ 52#define SATAC_DEVICE_RESET 0x08 /* ATAPI device reset */ 53#define SATAC_DOWNLOAD_MICROCODE 0x92 /* Download microcode */ 54#define SATAC_EJECT 0xed /* media eject */ 55#define SATAC_FLUSH_CACHE 0xe7 /* flush write-cache */ 56#define SATAC_ID_DEVICE 0xec /* IDENTIFY DEVICE */ 57#define SATAC_ID_PACKET_DEVICE 0xa1 /* ATAPI identify packet device */ 58#define SATAC_INIT_DEVPARMS 0x91 /* initialize device parameters */ 59#define SATAC_PACKET 0xa0 /* ATAPI packet */ 60#define SATAC_RDMULT 0xc4 /* read multiple w/DMA */ 61#define SATAC_RDSEC 0x20 /* read sector */ 62#define SATAC_RDVER 0x40 /* read verify */ 63#define SATAC_READ_DMA 0xc8 /* read DMA */ 64#define SATAC_SEEK 0x70 /* seek */ 65#define SATAC_SERVICE 0xa2 /* queued/overlap service */ 66#define SATAC_SETMULT 0xc6 /* set multiple mode */ 67#define SATAC_WRITE_DMA 0xca /* write (multiple) w/DMA */ 68#define SATAC_WRMULT 0xc5 /* write multiple */ 69#define SATAC_WRSEC 0x30 /* write sector */ 70#define SATAC_RDSEC_EXT 0x24 /* read sector extended (LBA48) */ 71#define SATAC_READ_DMA_EXT 0x25 /* read DMA extended (LBA48) */ 72#define SATAC_RDMULT_EXT 0x29 /* read multiple extended (LBA48) */ 73#define SATAC_WRSEC_EXT 0x34 /* read sector extended (LBA48) */ 74#define SATAC_WRITE_DMA_EXT 0x35 /* read DMA extended (LBA48) */ 75#define SATAC_WRMULT_EXT 0x39 /* read multiple extended (LBA48) */ 76 77#define SATAC_READ_DMA_QUEUED 0xc7 /* read DMA / may be queued */ 78#define SATAC_READ_DMA_QUEUED_EXT 0x26 /* read DMA ext / may be queued */ 79#define SATAC_WRITE_DMA_QUEUED 0xcc /* read DMA / may be queued */ 80#define SATAC_WRITE_DMA_QUEUED_EXT 0x36 /* read DMA ext / may be queued */ 81#define SATAC_READ_PM_REG 0xe4 /* read port mult reg */ 82#define SATAC_WRITE_PM_REG 0xe8 /* write port mult reg */ 83 84#define SATAC_READ_FPDMA_QUEUED 0x60 /* First-Party-DMA read queued */ 85#define SATAC_WRITE_FPDMA_QUEUED 0x61 /* First-Party-DMA write queued */ 86 87#define SATAC_READ_LOG_EXT 0x2f /* read log */ 88 89#define SATAC_SMART 0xb0 /* SMART */ 90 91#define SATA_LOG_PAGE_10 0x10 /* log page 0x10 - SATA error */ 92/* 93 * Power Managment Commands (subset) 94 */ 95#define SATAC_CHECK_POWER_MODE 0xe5 /* check power mode */ 96 97#define SATA_PWRMODE_STANDBY 0 /* standby mode */ 98#define SATA_PWRMODE_IDLE 0x80 /* idle mode */ 99#define SATA_PWRMODE_ACTIVE 0xFF /* active or idle mode, rev7 spec */ 100 101 102/* 103 * SMART FEATURES Subcommands 104 */ 105#define SATA_SMART_READ_DATA 0xd0 106#define SATA_SMART_ATTR_AUTOSAVE 0xd2 107#define SATA_SMART_EXECUTE_OFFLINE_IMM 0xd4 108#define SATA_SMART_READ_LOG 0xd5 109#define SATA_SMART_WRITE_LOG 0xd6 110#define SATA_SMART_ENABLE_OPS 0xd8 111#define SATA_SMART_DISABLE_OPS 0xd9 112#define SATA_SMART_RETURN_STATUS 0xda 113 114/* 115 * SET FEATURES Subcommands 116 */ 117#define SATAC_SF_ENABLE_WRITE_CACHE 0x02 118#define SATAC_SF_TRANSFER_MODE 0x03 119#define SATAC_SF_DISABLE_RMSN 0x31 120#define SATAC_SF_ENABLE_ACOUSTIC 0x42 121#define SATAC_SF_DISABLE_READ_AHEAD 0x55 122#define SATAC_SF_DISABLE_WRITE_CACHE 0x82 123#define SATAC_SF_ENABLE_READ_AHEAD 0xaa 124#define SATAC_SF_DISABLE_ACOUSTIC 0xc2 125#define SATAC_SF_ENABLE_RMSN 0x95 126 127/* 128 * SET FEATURES transfer mode values 129 */ 130#define SATAC_TRANSFER_MODE_PIO_DEFAULT 0x00 131#define SATAC_TRANSFER_MODE_PIO_DISABLE_IODRY 0x01 132#define SATAC_TRANSFER_MODE_PIO_FLOW_CONTROL 0x08 133#define SATAC_TRANSFER_MODE_MULTI_WORD_DMA 0x20 134#define SATAC_TRANSFER_MODE_ULTRA_DMA 0x40 135 136/* 137 * Download microcode subcommands 138 */ 139#define SATA_DOWNLOAD_MCODE_TEMP 1 /* Revert on/ reset/pwr cycle */ 140#define SATA_DOWNLOAD_MCODE_SAVE 7 /* No offset, keep mcode */ 141 142 143/* Generic ATA definitions */ 144 145#define SATA_TAG_QUEUING_SHIFT 3 146#define SATA_TAG_QUEUING_MASK 0x1f 147/* 148 * Identify Device data 149 * Although both ATA and ATAPI devices' Identify Data have the same length, 150 * some words have different meaning/content and/or are irrelevant for 151 * other type of device. 152 * Following is the ATA Device Identify data layout 153 */ 154typedef struct sata_id { 155/* WORD */ 156/* OFFSET COMMENT */ 157 ushort_t ai_config; /* 0 general configuration bits */ 158 ushort_t ai_fixcyls; /* 1 # of cylinders (obsolete) */ 159 ushort_t ai_resv0; /* 2 # reserved */ 160 ushort_t ai_heads; /* 3 # of heads (obsolete) */ 161 ushort_t ai_trksiz; /* 4 # of bytes/track (retired) */ 162 ushort_t ai_secsiz; /* 5 # of bytes/sector (retired) */ 163 ushort_t ai_sectors; /* 6 # of sectors/track (obsolete) */ 164 ushort_t ai_resv1[3]; /* 7 "Vendor Unique" */ 165 char ai_drvser[20]; /* 10 Serial number */ 166 ushort_t ai_buftype; /* 20 Buffer type */ 167 ushort_t ai_bufsz; /* 21 Buffer size in 512 byte incr */ 168 ushort_t ai_ecc; /* 22 # of ecc bytes avail on rd/wr */ 169 char ai_fw[8]; /* 23 Firmware revision */ 170 char ai_model[40]; /* 27 Model # */ 171 ushort_t ai_mult1; /* 47 Multiple command flags */ 172 ushort_t ai_dwcap; /* 48 Doubleword capabilities */ 173 ushort_t ai_cap; /* 49 Capabilities */ 174 ushort_t ai_resv2; /* 50 Reserved */ 175 ushort_t ai_piomode; /* 51 PIO timing mode */ 176 ushort_t ai_dmamode; /* 52 DMA timing mode */ 177 ushort_t ai_validinfo; /* 53 bit0: wds 54-58, bit1: 64-70 */ 178 ushort_t ai_curcyls; /* 54 # of current cylinders */ 179 ushort_t ai_curheads; /* 55 # of current heads */ 180 ushort_t ai_cursectrk; /* 56 # of current sectors/track */ 181 ushort_t ai_cursccp[2]; /* 57 current sectors capacity */ 182 ushort_t ai_mult2; /* 59 multiple sectors info */ 183 ushort_t ai_addrsec[2]; /* 60 LBA only: no of addr secs */ 184 ushort_t ai_dirdma; /* 62 valid in ATA/ATAPI7, DMADIR */ 185 ushort_t ai_dworddma; /* 63 multi word dma modes */ 186 ushort_t ai_advpiomode; /* 64 advanced PIO modes supported */ 187 ushort_t ai_minmwdma; /* 65 min multi-word dma cycle info */ 188 ushort_t ai_recmwdma; /* 66 rec multi-word dma cycle info */ 189 ushort_t ai_minpio; /* 67 min PIO cycle info */ 190 ushort_t ai_minpioflow; /* 68 min PIO cycle info w/flow ctl */ 191 ushort_t ai_resv3[2]; /* 69,70 reserved */ 192 ushort_t ai_typtime[2]; /* 71-72 timing */ 193 ushort_t ai_resv4[2]; /* 73-74 reserved */ 194 ushort_t ai_qdepth; /* 75 queue depth */ 195 ushort_t ai_satacap; /* 76 SATA capabilities */ 196 ushort_t ai_resv5; /* 77 reserved */ 197 ushort_t ai_satafsup; /* 78 SATA features supported */ 198 ushort_t ai_satafenbl; /* 79 SATA features enabled */ 199 ushort_t ai_majorversion; /* 80 major versions supported */ 200 ushort_t ai_minorversion; /* 81 minor version number supported */ 201 ushort_t ai_cmdset82; /* 82 command set supported */ 202 ushort_t ai_cmdset83; /* 83 more command sets supported */ 203 ushort_t ai_cmdset84; /* 84 more command sets supported */ 204 ushort_t ai_features85; /* 85 enabled features */ 205 ushort_t ai_features86; /* 86 enabled features */ 206 ushort_t ai_features87; /* 87 enabled features */ 207 ushort_t ai_ultradma; /* 88 Ultra DMA mode */ 208 ushort_t ai_erasetime; /* 89 security erase time */ 209 ushort_t ai_erasetimex; /* 90 enhanced security erase time */ 210 ushort_t ai_adv_pwr_mgmt; /* 91 advanced power management time */ 211 ushort_t ai_master_pwd; /* 92 master password revision code */ 212 ushort_t ai_hrdwre_reset; /* 93 hardware reset result */ 213 ushort_t ai_acoustic; /* 94 accoustic management values */ 214 ushort_t ai_stream_min_sz; /* 95 stream minimum request size */ 215 ushort_t ai_stream_xfer_d; /* 96 streaming transfer time (DMA) */ 216 ushort_t ai_stream_lat; /* 97 streaming access latency */ 217 ushort_t ai_streamperf[2]; /* 98-99 streaming performance gran. */ 218 ushort_t ai_addrsecxt[4]; /* 100 extended max LBA sector */ 219 ushort_t ai_stream_xfer_p; /* 104 streaming transfer time (PIO) */ 220 ushort_t ai_padding1; /* 105 pad */ 221 ushort_t ai_phys_sect_sz; /* 106 physical sector size */ 222 ushort_t ai_seek_delay; /* 107 inter-seek delay time (usecs) */ 223 ushort_t ai_naa_ieee_oui; /* 108 NAA/IEEE OUI */ 224 ushort_t ai_ieee_oui_uid; /* 109 IEEE OUT/unique id */ 225 ushort_t ai_uid_mid; /* 110 unique id (mid) */ 226 ushort_t ai_uid_low; /* 111 unique id (low) */ 227 ushort_t ai_resv_wwn[4]; /* 112-115 reserved for WWN ext. */ 228 ushort_t ai_incits; /* 116 reserved for INCITS TR-37-2004 */ 229 ushort_t ai_words_lsec[2]; /* 117-118 words per logical sector */ 230 ushort_t ai_cmdset119; /* 119 more command sets supported */ 231 ushort_t ai_features120; /* 120 enabled features */ 232 ushort_t ai_padding2[6]; /* pad to 126 */ 233 ushort_t ai_rmsn; /* 127 removable media notification */ 234 ushort_t ai_securestatus; /* 128 security status */ 235 ushort_t ai_vendor[31]; /* 129-159 vendor specific */ 236 ushort_t ai_padding3[16]; /* 160 pad to 176 */ 237 ushort_t ai_curmedser[30]; /* 176-205 current media serial # */ 238 ushort_t ai_sctsupport; /* 206 SCT command transport */ 239 ushort_t ai_padding4[48]; /* 207 pad to 255 */ 240 ushort_t ai_integrity; /* 255 integrity word */ 241} sata_id_t; 242 243 244/* Identify Device: general config bits - word 0 */ 245 246#define SATA_ATA_TYPE_MASK 0x8001 /* ATA Device type mask */ 247#define SATA_ATA_TYPE 0x0000 /* ATA device */ 248#define SATA_REM_MEDIA 0x0080 /* Removable media */ 249#define SATA_INCOMPLETE_DATA 0x0004 /* Incomplete Identify Device data */ 250 251#define SATA_ID_SERIAL_OFFSET 10 252#define SATA_ID_SERIAL_LEN 20 253#define SATA_ID_MODEL_OFFSET 27 254#define SATA_ID_MODEL_LEN 40 255#define SATA_ID_FW_LEN 8 256 257/* Identify Device: common capability bits - word 49 */ 258 259#define SATA_DMA_SUPPORT 0x0100 260#define SATA_LBA_SUPPORT 0x0200 261#define SATA_IORDY_DISABLE 0x0400 262#define SATA_IORDY_SUPPORT 0x0800 263#define SATA_STANDBYTIMER 0x2000 264 265/* Identify Device: ai_validinfo (word 53) */ 266 267#define SATA_VALIDINFO_88 0x0004 /* word 88 supported fields valid */ 268#define SATA_VALIDINFO_70_64 0x0004 /* words 70-64 fields valid */ 269 270/* Identify Device: ai_majorversion (word 80) */ 271 272#define SATA_MAJVER_7 0x0080 /* ATA/ATAPI-7 version supported */ 273#define SATA_MAJVER_654 0x0070 /* ATA/ATAPI-6,5 or 4 ver supported */ 274#define SATA_MAJVER_6 0x0040 /* ATA/ATAPI-6 version supported */ 275#define SATA_MAJVER_5 0x0020 /* ATA/ATAPI-7 version supported */ 276#define SATA_MAJVER_4 0x0010 /* ATA/ATAPI-4 version supported */ 277 278/* Identify Device: command set supported/enabled bits - words 83 and 86 */ 279 280#define SATA_EXT48 0x0400 /* 48 bit address feature */ 281#define SATA_PWRUP_IN_STANDBY 0x0020 /* Power-up in standby mode supp/en */ 282#define SATA_RM_STATUS_NOTIFIC 0x0010 /* Removable Media Stat Notification */ 283#define SATA_RW_DMA_QUEUED_CMD 0x0002 /* R/W DMA Queued supported */ 284#define SATA_DWNLOAD_MCODE_CMD 0x0001 /* Download Microcode CMD supp/enbld */ 285#define SATA_ACOUSTIC_MGMT 0x0200 /* Acoustic Management features */ 286 287/* Identify Device: command set supported/enabled bits - words 82 and 85 */ 288 289#define SATA_SMART_SUPPORTED 0x0001 /* SMART feature set is supported */ 290#define SATA_WRITE_CACHE 0x0020 /* Write Cache supported/enabled */ 291#define SATA_LOOK_AHEAD 0x0040 /* Look Ahead supported/enabled */ 292#define SATA_DEVICE_RESET_CMD 0x0200 /* Device Reset CMD supported/enbld */ 293#define SATA_READ_BUFFER_CMD 0x2000 /* Read Buffer CMD supported/enbld */ 294#define SATA_WRITE_BUFFER_CMD 0x1000 /* Write Buffer CMD supported/enbld */ 295#define SATA_SMART_ENABLED 0x0001 /* SMART feature set is enabled */ 296 297/* Identify Device: command set supported/enabled bits - words 84 & 87 */ 298#define SATA_SMART_SELF_TEST_SUPPORTED 0x0002 /* SMART self-test supported */ 299 300/* Identify (Packet) Device word 63, ATA/ATAPI-6 & 7 */ 301#define SATA_MDMA_SEL_MASK 0x0700 /* Multiword DMA selected */ 302#define SATA_MDMA_2_SEL 0x0400 /* Multiword DMA mode 2 selected */ 303#define SATA_MDMA_1_SEL 0x0200 /* Multiword DMA mode 1 selected */ 304#define SATA_MDMA_0_SEL 0x0100 /* Multiword DMA mode 0 selected */ 305#define SATA_MDMA_2_SUP 0x0004 /* Multiword DMA mode 2 supported */ 306#define SATA_MDMA_1_SUP 0x0002 /* Multiword DMA mode 1 supported */ 307#define SATA_MDMA_0_SUP 0x0001 /* Multiword DMA mode 0 supported */ 308#define SATA_MDMA_SUP_MASK 0x0007 /* Multiword DMA supported */ 309 310/* Identify (Packet) Device Word 88 */ 311#define SATA_UDMA_SUP_MASK 0x007f /* UDMA modes supported */ 312#define SATA_UDMA_SEL_MASK 0x7f00 /* UDMA modes selected */ 313 314/* Identify Device: command set supported/enabled bits - word 206 */ 315 316/* All are SCT Command Transport support */ 317#define SATA_SCT_CMD_TRANS_SUP 0x0001 /* anything */ 318#define SATA_SCT_CMD_TRANS_LNG_SECT_SUP 0x0002 /* Long Sector Access */ 319#define SATA_SCT_CMD_TRANS_WR_SAME_SUP 0x0004 /* Write Same */ 320#define SATA_SCT_CMD_TRANS_ERR_RCOV_SUP 0x0008 /* Error Recovery Control */ 321#define SATA_SCT_CMD_TRANS_FEAT_CTL_SUP 0x0010 /* Features Control */ 322#define SATA_SCT_CMD_TRANS_DATA_TBL_SUP 0x0020 /* Data Tables supported */ 323 324#define SATA_DISK_SECTOR_SIZE 512 /* HD physical sector size */ 325 326/* Identify Packet Device data definitions (ATAPI devices) */ 327 328/* Identify Packet Device: general config bits - word 0 */ 329 330#define SATA_ATAPI_TYPE_MASK 0xc000 331#define SATA_ATAPI_TYPE 0x8000 /* ATAPI device */ 332#define SATA_ATAPI_ID_PKT_SZ 0x0003 /* Packet size mask */ 333#define SATA_ATAPI_ID_PKT_12B 0x0000 /* Packet size 12 bytes */ 334#define SATA_ATAPI_ID_PKT_16B 0x0001 /* Packet size 16 bytes */ 335#define SATA_ATAPI_ID_DRQ_TYPE 0x0060 /* DRQ asserted in 3ms after pkt */ 336#define SATA_ATAPI_ID_DRQ_INTR 0x0020 /* Obsolete in ATA/ATAPI 7 */ 337 338#define SATA_ATAPI_ID_DEV_TYPE 0x0f00 /* device type/command set mask */ 339#define SATA_ATAPI_ID_DEV_SHFT 8 340#define SATA_ATAPI_DIRACC_DEV 0x0000 /* Direct Access device */ 341#define SATA_ATAPI_SQACC_DEV 0x0100 /* Sequential access dev (tape ?) */ 342#define SATA_ATAPI_CDROM_DEV 0x0500 /* CD_ROM device */ 343 344/* 345 * Status bits from ATAPI Interrupt reason register (AT_COUNT) register 346 */ 347#define SATA_ATAPI_I_COD 0x01 /* Command or Data */ 348#define SATA_ATAPI_I_IO 0x02 /* IO direction */ 349#define SATA_ATAPI_I_RELEASE 0x04 /* Release for ATAPI overlap */ 350 351/* ATAPI feature reg definitions */ 352 353#define SATA_ATAPI_F_DATA_DIR_READ 0x04 /* DMA transfer to the host */ 354#define SATA_ATAPI_F_OVERLAP 0x02 /* Not used by Sun drivers */ 355#define SATA_ATAPI_F_DMA 0x01 /* Packet DMA command */ 356 357 358/* ATAPI IDENTIFY_DRIVE capabilities word (49) */ 359 360#define SATA_ATAPI_ID_CAP_DMA 0x0100 /* if zero, check word 62 */ 361#define SATA_ATAPI_ID_CAP_OVERLAP 0x2000 362 363/* 364 * ATAPI Identify Packet Device word 62 365 * Word 62 is not valid for ATA/ATAPI-6 366 * Defs below are for ATA/ATAPI-7 367 */ 368#define SATA_ATAPI_ID_DMADIR_REQ 0x8000 /* DMA direction required */ 369#define SATA_ATAPI_ID_DMA_SUP 0x0400 /* DMA is supported */ 370 371/* 372 * ATAPI signature bits 373 */ 374#define SATA_ATAPI_SIG_HI 0xeb /* in high cylinder register */ 375#define SATA_ATAPI_SIG_LO 0x14 /* in low cylinder register */ 376 377/* These values are pre-set for CD_ROM/DVD ? */ 378 379#define SATA_ATAPI_SECTOR_SIZE 2048 380#define SATA_ATAPI_MAX_BYTES_PER_DRQ 0xf800 /* 16 bits - 2KB ie 62KB */ 381#define SATA_ATAPI_HEADS 64 382#define SATA_ATAPI_SECTORS_PER_TRK 32 383 384/* SATA Capabilites bits (word 76) */ 385 386#define SATA_NCQ 0x100 387#define SATA_2_SPEED 0x004 388#define SATA_1_SPEED 0x002 389 390/* SATA Features Supported (word 78) - not used */ 391 392/* SATA Features Enabled (word 79) - not used */ 393 394#define SATA_READ_AHEAD_SUPPORTED(x) ((x).ai_cmdset82 & SATA_LOOK_AHEAD) 395#define SATA_READ_AHEAD_ENABLED(x) ((x).ai_features85 & SATA_LOOK_AHEAD) 396#define SATA_WRITE_CACHE_SUPPORTED(x) ((x).ai_cmdset82 & SATA_WRITE_CACHE) 397#define SATA_WRITE_CACHE_ENABLED(x) ((x).ai_features85 & SATA_WRITE_CACHE) 398#define SATA_RM_NOTIFIC_SUPPORTED(x) \ 399 ((x).ai_cmdset83 & SATA_RM_STATUS_NOTIFIC) 400#define SATA_RM_NOTIFIC_ENABLED(x) \ 401 ((x).ai_features86 & SATA_RM_STATUS_NOTIFIC) 402 403/* 404 * Generic NCQ related defines 405 */ 406 407#define NQ 0x80 /* Not a queued cmd - tag not valid */ 408#define NCQ_TAG_MASK 0x1f /* NCQ command tag mask */ 409#define FIS_TYPE_REG_H2D 0x27 /* Reg FIS - Host to Device */ 410#define FIS_CMD_UPDATE 0x80 411/* 412 * Status bits from AT_STATUS register 413 */ 414#define SATA_STATUS_BSY 0x80 /* controller busy */ 415#define SATA_STATUS_DRDY 0x40 /* drive ready */ 416#define SATA_STATUS_DF 0x20 /* device fault */ 417#define SATA_STATUS_DSC 0x10 /* seek operation complete */ 418#define SATA_STATUS_DRQ 0x08 /* data request */ 419#define SATA_STATUS_CORR 0x04 /* obsolete */ 420#define SATA_STATUS_IDX 0x02 /* obsolete */ 421#define SATA_STATUS_ERR 0x01 /* error flag */ 422 423/* 424 * Status bits from AT_ERROR register 425 */ 426#define SATA_ERROR_ICRC 0x80 /* CRC data transfer error detected */ 427#define SATA_ERROR_UNC 0x40 /* uncorrectable data error */ 428#define SATA_ERROR_MC 0x20 /* Media change */ 429#define SATA_ERROR_IDNF 0x10 /* ID/Address not found */ 430#define SATA_ERROR_MCR 0x08 /* media change request */ 431#define SATA_ERROR_ABORT 0x04 /* aborted command */ 432#define SATA_ERROR_NM 0x02 /* no media */ 433#define SATA_ERROR_EOM 0x02 /* end of media (Packet cmds) */ 434#define SATA_ERROR_ILI 0x01 /* cmd sepcific */ 435 436 437/* 438 * Bits from the device control register 439 */ 440#define SATA_DEVCTL_NIEN 0x02 /* not interrupt enabled */ 441#define SATA_DEVCTL_SRST 0x04 /* software reset */ 442#define SATA_DEVCTL_HOB 0x80 /* high order bit */ 443 444/* device_reg */ 445#define SATA_ADH_LBA 0x40 /* addressing in LBA mode not chs */ 446 447/* ATAPI transport version-in Inquiry data */ 448#define SATA_ATAPI_TRANS_VERSION(inq) \ 449 (*((uint8_t *)(inq) + 3) >> 4) 450 451#define SCSI_LOG_PAGE_HDR_LEN 4 /* # bytes of a SCSI log page header */ 452#define SCSI_LOG_PARAM_HDR_LEN 4 /* # byttes of a SCSI log param hdr */ 453 454/* Number of log entries per extended selftest log block */ 455#define ENTRIES_PER_EXT_SELFTEST_LOG_BLK 19 456 457/* Number of entries per SCSI LOG SENSE SELFTEST RESULTS page */ 458#define SCSI_ENTRIES_IN_LOG_SENSE_SELFTEST_RESULTS 20 459 460/* Length of a SCSI LOG SENSE SELFTEST RESULTS parameter */ 461#define SCSI_LOG_SENSE_SELFTEST_PARAM_LEN 0x10 462 463#define DIAGNOSTIC_FAILURE_ON_COMPONENT 0x40 464 465#define SCSI_COMPONENT_81 0x81 466#define SCSI_COMPONENT_82 0x82 467#define SCSI_COMPONENT_83 0x83 468#define SCSI_COMPONENT_84 0x84 469#define SCSI_COMPONENT_85 0x85 470#define SCSI_COMPONENT_86 0x86 471#define SCSI_COMPONENT_87 0x87 472#define SCSI_COMPONENT_88 0x88 473 474#define SCSI_ASC_ATA_DEV_FEAT_NOT_ENABLED 0x67 475#define SCSI_ASCQ_ATA_DEV_FEAT_NOT_ENABLED 0x0b 476 477#define SCSI_PREDICTED_FAILURE 0x5d 478#define SCSI_GENERAL_HD_FAILURE 0x10 479 480#define SCSI_INFO_EXCEPTIONS_PARAM_LEN 4 481 482#define READ_LOG_EXT_LOG_DIRECTORY 0 483#define READ_LOG_EXT_NCQ_ERROR_RECOVERY 0x10 484#define SMART_SELFTEST_LOG_PAGE 6 485#define EXT_SMART_SELFTEST_LOG_PAGE 7 486 487/* 488 * SATA NCQ error recovery page (0x10) 489 */ 490struct sata_ncq_error_recovery_page { 491 uint8_t ncq_tag; 492 uint8_t reserved1; 493 uint8_t ncq_status; 494 uint8_t ncq_error; 495 uint8_t ncq_sector_number; 496 uint8_t ncq_cyl_low; 497 uint8_t ncq_cyl_high; 498 uint8_t ncq_dev_head; 499 uint8_t ncq_sector_number_ext; 500 uint8_t ncq_cyl_low_ext; 501 uint8_t ncq_cyl_high_ext; 502 uint8_t reserved2; 503 uint8_t ncq_sector_count; 504 uint8_t ncq_sector_count_ext; 505 uint8_t reserved3[242]; 506 uint8_t ncq_vendor_unique[255]; 507 uint8_t ncq_checksum; 508}; 509 510/* 511 * SMART data structures 512 */ 513struct smart_data { 514 uint8_t smart_vendor_specific[362]; 515 uint8_t smart_offline_data_collection_status; 516 uint8_t smart_selftest_exec_status; 517 uint8_t smart_secs_to_complete_offline_data[2]; 518 uint8_t smart_vendor_specific2; 519 uint8_t smart_offline_data_collection_capability; 520 uint8_t smart_capability[2]; 521 uint8_t smart_error_logging_capability; 522 uint8_t smart_vendor_specific3; 523 uint8_t smart_short_selftest_polling_time; 524 uint8_t smart_extended_selftest_polling_time; 525 uint8_t smart_conveyance_selftest_polling_time; 526 uint8_t smart_reserved[11]; 527 uint8_t smart_vendor_specific4[125]; 528 uint8_t smart_checksum; 529}; 530 531struct smart_selftest_log_entry { 532 uint8_t smart_selftest_log_lba_low; 533 uint8_t smart_selftest_log_status; 534 uint8_t smart_selftest_log_timestamp[2]; 535 uint8_t smart_selftest_log_checkpoint; 536 uint8_t smart_selftest_log_failing_lba[4]; /* from LSB to MSB */ 537 uint8_t smart_selftest_log_vendor_specific[15]; 538}; 539 540#define NUM_SMART_SELFTEST_LOG_ENTRIES 21 541struct smart_selftest_log { 542 uint8_t smart_selftest_log_revision[2]; 543 struct smart_selftest_log_entry 544 smart_selftest_log_entries[NUM_SMART_SELFTEST_LOG_ENTRIES]; 545 uint8_t smart_selftest_log_vendor_specific[2]; 546 uint8_t smart_selftest_log_index; 547 uint8_t smart_selftest_log_reserved[2]; 548 uint8_t smart_selftest_log_checksum; 549}; 550 551struct smart_ext_selftest_log_entry { 552 uint8_t smart_ext_selftest_log_lba_low; 553 uint8_t smart_ext_selftest_log_status; 554 uint8_t smart_ext_selftest_log_timestamp[2]; 555 uint8_t smart_ext_selftest_log_checkpoint; 556 uint8_t smart_ext_selftest_log_failing_lba[6]; 557 uint8_t smart_ext_selftest_log_vendor_specific[15]; 558}; 559 560struct smart_ext_selftest_log { 561 uint8_t smart_ext_selftest_log_rev; 562 uint8_t smart_ext_selftest_log_reserved; 563 uint8_t smart_ext_selftest_log_index[2]; 564 struct smart_ext_selftest_log_entry smart_ext_selftest_log_entries[19]; 565 uint8_t smart_ext_selftest_log_vendor_specific[2]; 566 uint8_t smart_ext_selftest_log_reserved2[11]; 567 uint8_t smart_ext_selftest_log_checksum; 568}; 569 570struct read_log_ext_directory { 571 uint8_t read_log_ext_vers[2]; /* general purpose log version */ 572 uint8_t read_log_ext_nblks[255][2]; /* # of blks @ log addr index+1 */ 573}; 574 575/* 576 * SMART specific data 577 * These eventually need to go to a generic scsi hearder file 578 * for now they will reside here 579 */ 580#define PC_CUMULATIVE_VALUES 0x01 581#define PAGE_CODE_GET_SUPPORTED_LOG_PAGES 0x00 582#define PAGE_CODE_SELF_TEST_RESULTS 0x10 583#define PAGE_CODE_INFORMATION_EXCEPTIONS 0x2f 584#define PAGE_CODE_SMART_READ_DATA 0x30 585 586 587struct log_parameter { 588 uint8_t param_code[2]; /* parameter dependant */ 589 uint8_t param_ctrl_flags; /* see defines below */ 590 uint8_t param_len; /* # of bytes following */ 591 uint8_t param_values[1]; /* # of bytes defined by param_len */ 592}; 593 594/* param_ctrl_flag fields */ 595#define LOG_CTRL_LP 0x01 /* list parameter */ 596#define LOG_CTRL_LBIN 0x02 /* list is binary */ 597#define LOG_CTRL_TMC 0x0c /* threshold met criteria */ 598#define LOG_CTRL_ETC 0x10 /* enable threshold comparison */ 599#define LOG_CTRL_TSD 0x20 /* target save disable */ 600#define LOG_CTRL_DS 0x40 /* disable save */ 601#define LOG_CTRL_DU 0x80 /* disable update */ 602 603#define SMART_MAGIC_VAL_1 0x4f 604#define SMART_MAGIC_VAL_2 0xc2 605#define SMART_MAGIC_VAL_3 0xf4 606#define SMART_MAGIC_VAL_4 0x2c 607 608#define SCT_STATUS_LOG_PAGE 0xe0 609 610/* 611 * Acoustic management 612 */ 613 614struct mode_acoustic_management { 615 struct mode_page mode_page; /* common mode page header */ 616 uchar_t acoustic_manag_enable; /* Set to 1 enable, Set 0 disable */ 617 uchar_t acoustic_manag_level; /* Acoustic management level */ 618 uchar_t vendor_recommended_value; /* Vendor recommended value */ 619}; 620 621#define PAGELENGTH_DAD_MODE_ACOUSTIC_MANAGEMENT 3 /* Acoustic manag pg len */ 622#define P_CNTRL_CURRENT 0 623#define P_CNTRL_CHANGEABLE 1 624#define P_CNTRL_DEFAULT 2 625#define P_CNTRL_SAVED 3 626 627#define ACOUSTIC_DISABLED 0 628#define ACOUSTIC_ENABLED 1 629 630#define MODEPAGE_ACOUSTIC_MANAG 0x30 631 632/* 633 * sstatus field definitions 634 */ 635#define SSTATUS_DET_SHIFT 0 636#define SSTATUS_SPD_SHIFT 4 637#define SSTATUS_IPM_SHIFT 8 638 639#define SSTATUS_DET (0xf << SSTATUS_DET_SHIFT) 640#define SSTATUS_SPD (0xf << SSTATUS_SPD_SHIFT) 641#define SSTATUS_IPM (0xf << SSTATUS_IPM_SHIFT) 642 643/* 644 * sstatus DET values 645 */ 646#define SSTATUS_DET_NODEV 0 /* No dev detected */ 647#define SSTATUS_DET_DEVPRE_NOPHYCOM 1 /* dev detected */ 648#define SSTATUS_DET_DEVPRE_PHYCOM 3 /* dev detected */ 649#define SSTATUS_DET_PHYOFFLINE 4 /* PHY is in offline */ 650 651#define SSTATUS_GET_DET(x) \ 652 (x & SSTATUS_DET) 653 654#define SSTATUS_SET_DET(x, new_val) \ 655 (x = (x & ~SSTATUS_DET) | (new_val & SSTATUS_DET)) 656 657#define SSTATUS_SPD_NOLIMIT 0 /* No speed limit */ 658#define SSTATUS_SPD_GEN1 1 /* Limit Gen 1 rate */ 659#define SSTATUS_SPD_GEN2 2 /* Limit Gen 2 rate */ 660 661/* 662 * sstatus IPM values 663 */ 664#define SSTATUS_IPM_NODEV_NOPHYCOM 0x0 /* No dev, no PHY */ 665#define SSTATUS_IPM_ACTIVE 0x1 /* Interface active */ 666#define SSTATUS_IPM_POWERPARTIAL 0x2 /* partial power mgmnt */ 667#define SSTATUS_IPM_POWERSLUMBER 0x6 /* slumber power mgmt */ 668 669#define SSTATUS_GET_IPM(x) \ 670 ((x & SSTATUS_IPM) >> SSTATUS_IPM_SHIFT) 671 672#define SSTATUS_SET_IPM(x, new_val) \ 673 (x = (x & ~SSTATUS_IPM) | \ 674 ((new_val << SSTATUS_IPM_SHIFT) & SSTATUS_IPM)) 675 676 677/* 678 * serror register fields 679 */ 680#define SERROR_DATA_ERR_FIXED (1 << 0) /* D integrity err */ 681#define SERROR_COMM_ERR_FIXED (1 << 1) /* comm err recov */ 682#define SERROR_DATA_ERR (1 << 8) /* D integrity err */ 683#define SERROR_PERSISTENT_ERR (1 << 9) /* norecov com err */ 684#define SERROR_PROTOCOL_ERR (1 << 10) /* protocol err */ 685#define SERROR_INT_ERR (1 << 11) /* internal err */ 686#define SERROR_PHY_RDY_CHG (1 << 16) /* PHY state change */ 687#define SERROR_PHY_INT_ERR (1 << 17) /* PHY internal err */ 688#define SERROR_COMM_WAKE (1 << 18) /* COM wake */ 689#define SERROR_10B_TO_8B_ERR (1 << 19) /* 10B-to-8B decode */ 690#define SERROR_DISPARITY_ERR (1 << 20) /* disparity err */ 691#define SERROR_CRC_ERR (1 << 21) /* CRC err */ 692#define SERROR_HANDSHAKE_ERR (1 << 22) /* Handshake err */ 693#define SERROR_LINK_SEQ_ERR (1 << 23) /* Link seq err */ 694#define SERROR_TRANS_ERR (1 << 24) /* Tran state err */ 695#define SERROR_FIS_TYPE (1 << 25) /* FIS type err */ 696#define SERROR_EXCHANGED_ERR (1 << 26) /* Device exchanged */ 697 698/* 699 * S-Control Bridge port x register fields 700 */ 701#define SCONTROL_DET_SHIFT 0 702#define SCONTROL_SPD_SHIFT 4 703#define SCONTROL_IPM_SHIFT 8 704#define SCONTROL_SPM_SHIFT 12 705 706#define SCONTROL_DET (0xf << SSTATUS_DET_SHIFT) 707#define SCONTROL_SPD (0xf << SSTATUS_SPD_SHIFT) 708#define SCONTROL_IPM (0xf << SSTATUS_IPM_SHIFT) 709#define SCONTROL_SPM (0xf << SSTATUS_SPM_SHIFT) 710 711#define SCONTROL_GET_DET(x) \ 712 (x & SCONTROL_DET) 713 714#define SCONTROL_SET_DET(x, new_val) \ 715 (x = (x & ~SCONTROL_DET) | (new_val & SCONTROL_DET)) 716 717#define SCONTROL_DET_NOACTION 0 /* Do nothing to port */ 718#define SCONTROL_DET_COMRESET 1 /* Re-initialize port */ 719#define SCONTROL_DET_DISABLE 4 /* Disable port */ 720 721#define SCONTROL_SPD_NOLIMIT 0 /* No speed limit */ 722#define SCONTROL_SPD_GEN1 1 /* Limit Gen 1 rate */ 723#define SCONTROL_SPD_GEN2 2 /* Limit Gen 2 rate */ 724 725#define SCONTROL_GET_IPM(x) \ 726 ((x & SCONTROL_IPM) >> SCONTROL_IPM_SHIFT) 727 728#define SCONTROL_SET_IPM(x, new_val) \ 729 (x = (x & ~SCONTROL_IPM) | \ 730 ((new_val << SCONTROL_IPM_SHIFT) & SCONTROL_IPM)) 731 732#define SCONTROL_IPM_NORESTRICT 0 /* No PM limit */ 733#define SCONTROL_IPM_DISABLE_PARTIAL 1 /* Disable partial */ 734#define SCONTROL_IPM_DISABLE_SLUMBER 2 /* Disable slumber */ 735#define SCONTROL_IPM_DISABLE_BOTH 3 /* Disable both */ 736 737#define SCONTROL_SPM_NORESTRICT 0 /* No PM limits */ 738#define SCONTROL_SPM_DO_PARTIAL 1 /* Go to partial */ 739#define SCONTROL_SPM_DO_SLUMBER 2 /* Go to slumber */ 740#define SCONTROL_SPM_DO_ACTIVE 4 /* Go to active */ 741 742#ifdef __cplusplus 743} 744#endif 745 746#endif /* _SATA_DEFS_H */ 747