nv_sata.h revision 7523:07ae6b88a218
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _NV_SATA_H 28#define _NV_SATA_H 29 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35 36/* 37 * SGPIO Support 38 * Enable SGPIO support only on x86/x64, because it is implemented using 39 * functions that are only available on x86/x64. 40 */ 41 42#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 43 44typedef struct nv_port nv_port_t; 45 46#ifdef SGPIO_SUPPORT 47typedef struct nv_sgp_cmn nv_sgp_cmn_t; 48#endif 49 50typedef struct nv_ctl { 51 /* 52 * Each of these are specific to the chipset in use. 53 */ 54 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 55 void (*nvc_reg_init)(struct nv_ctl *nvc, 56 ddi_acc_handle_t pci_conf_handle); 57 58 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 59 60 struct nv_port *nvc_port; /* array of pointers to port struct */ 61 62 /* 63 * handle and base address to register space. 64 * 65 * 0: port 0 task file 66 * 1: port 0 status 67 * 2: port 1 task file 68 * 3: port 1 status 69 * 4: bus master for both ports 70 * 5: extended registers for SATA features 71 */ 72 ddi_acc_handle_t nvc_bar_hdl[6]; 73 uchar_t *nvc_bar_addr[6]; 74 75 /* 76 * sata registers in bar 5 which are shared on all devices 77 * on the channel. 78 */ 79 uint32_t *nvc_mcp55_ctl; 80 uint32_t *nvc_mcp55_ncq; /* NCQ status control bits */ 81 82 kmutex_t nvc_mutex; /* ctrl level lock */ 83 84 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 85 int nvc_intr_type; /* What type of interrupt */ 86 int nvc_intr_cnt; /* # of intrs count returned */ 87 size_t nvc_intr_size; /* Size of intr array to */ 88 uint_t nvc_intr_pri; /* Interrupt priority */ 89 int nvc_intr_cap; /* Interrupt capabilities */ 90 uint8_t *nvc_mcp04_int_status; /* interrupt status mcp04 */ 91 92 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 93 94 /* 95 * enable/disable interrupts, controller specific 96 */ 97 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 98 int nvc_state; /* state flags of ctrl see below */ 99 uint8_t nvc_revid; /* PCI revid of device */ 100 101#ifdef SGPIO_SUPPORT 102 uint8_t nvc_ctlr_num; /* controller number within the part */ 103 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 104 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Command Block */ 105 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 106#endif 107} nv_ctl_t; 108 109 110struct nv_port { 111 112 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 113 114 uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 115 116 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 117 uint32_t nvp_signature; /* sig acquired from task file regs */ 118 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 119 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 120 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 121 122 ddi_acc_handle_t nvp_cmd_hdl; 123 uchar_t *nvp_data; /* data register */ 124 uchar_t *nvp_error; /* error register (read) */ 125 uchar_t *nvp_feature; /* features (write) */ 126 uchar_t *nvp_count; /* sector count */ 127 uchar_t *nvp_sect; /* sector number */ 128 uchar_t *nvp_lcyl; /* cylinder low byte */ 129 uchar_t *nvp_hcyl; /* cylinder high byte */ 130 uchar_t *nvp_drvhd; /* drive/head register */ 131 uchar_t *nvp_status; /* status/command register */ 132 uchar_t *nvp_cmd; /* status/command register */ 133 134 ddi_acc_handle_t nvp_ctl_hdl; 135 uchar_t *nvp_altstatus; /* alternate status (read) */ 136 uchar_t *nvp_devctl; /* device control (write) */ 137 138 ddi_acc_handle_t nvp_bm_hdl; 139 uchar_t *nvp_bmisx; 140 uint32_t *nvp_bmidtpx; 141 uchar_t *nvp_bmicx; 142 143 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 144 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 145 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 146 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 147 148 uint32_t *nvp_sstatus; 149 uint32_t *nvp_serror; 150 uint32_t *nvp_sctrl; 151 uint32_t *nvp_sactive; 152 153 kmutex_t nvp_mutex; /* main per port mutex */ 154 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 155 156 /* 157 * nvp_slot is a pointer to an array of nv_slot 158 */ 159 struct nv_slot *nvp_slot; 160 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 161 uint8_t nvp_queue_depth; 162 163 /* 164 * NCQ flow control. During NCQ operation, no other commands 165 * allowed. The following are used to enforce this. 166 */ 167 int nvp_ncq_run; 168 int nvp_non_ncq_run; 169 170 timeout_id_t nvp_timeout_id; 171 172 clock_t nvp_reset_time; /* time of last reset */ 173 clock_t nvp_probe_time; /* time when probe began */ 174 clock_t nvp_link_lost_time; /* time link lost was noticed */ 175 176 int nvp_state; /* state of port. flags defined below */ 177 178 uint16_t *nvp_mcp55_int_status; 179 uint16_t *nvp_mcp55_int_ctl; 180 181#ifdef SGPIO_SUPPORT 182 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 183#endif 184}; 185 186 187typedef struct nv_device_table { 188 ushort_t vendor_id; /* vendor id */ 189 ushort_t device_id; /* device id */ 190 ushort_t type; /* chipset type, mcp04 or mcp55 */ 191} nv_device_table_t; 192 193 194typedef struct nv_slot { 195 caddr_t nvslot_v_addr; /* I/O buffer address */ 196 size_t nvslot_byte_count; /* # bytes left to read/write */ 197 sata_pkt_t *nvslot_spkt; 198 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 199 clock_t nvslot_stime; 200 int (*nvslot_start)(nv_port_t *nvp, int queue); 201 void (*nvslot_intr)(nv_port_t *nvp, 202 struct nv_slot *nv_slotp); 203 uint32_t nvslot_flags; 204} nv_slot_t; 205 206 207#ifdef SGPIO_SUPPORT 208struct nv_sgp_cmn { 209 uint16_t nvs_magic; /* verification of valid structure */ 210 uint8_t nvs_in_use; /* bit-field of active ctlrs */ 211 uint8_t nvs_connected; /* port connected bit-field flag */ 212 uint8_t nvs_activity; /* port usage bit-field flag */ 213 int nvs_taskq_delay; /* rest time for activity LED taskq */ 214 kmutex_t nvs_slock; /* lock for shared data */ 215 kmutex_t nvs_tlock; /* lock for taskq */ 216 kcondvar_t nvs_cv; /* condition variable for taskq wait */ 217 ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 218}; 219#endif 220 221 222/* 223 * nvslot_flags 224 */ 225#define NVSLOT_COMPLETE 0x01 226#define NVSLOT_NCQ 0x02 /* NCQ is active */ 227#define NVSLOT_RQSENSE 0x04 /* processing request sense */ 228 229/* 230 * state values for nv_attach 231 */ 232#define ATTACH_PROGRESS_NONE (1 << 0) 233#define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 234#define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 235#define ATTACH_PROGRESS_BARS (1 << 3) 236#define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 237#define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 238#define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 239#define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 240#define ATTACH_PROGRESS_COUNT (1 << 8) 241#define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 242#define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 243 244#ifdef DEBUG 245 246#define NV_DEBUG 1 247 248#endif /* DEBUG */ 249 250 251/* 252 * nv_debug_flags 253 */ 254#define NVDBG_ALWAYS 0x0001 255#define NVDBG_INIT 0x0002 256#define NVDBG_ENTRY 0x0004 257#define NVDBG_DELIVER 0x0008 258#define NVDBG_EVENT 0x0010 259#define NVDBG_SYNC 0x0020 260#define NVDBG_PKTCOMP 0x0040 261#define NVDBG_TIMEOUT 0x0080 262#define NVDBG_INFO 0x0100 263#define NVDBG_VERBOSE 0x0200 264#define NVDBG_INTR 0x0400 265#define NVDBG_ERRS 0x0800 266#define NVDBG_COOKIES 0x1000 267#define NVDBG_HOT 0x2000 268#define NVDBG_PROBE 0x4000 269#define NVDBG_ATAPI 0x8000 270 271#ifdef DEBUG 272#define NVLOG(a) nv_log a 273#else 274#define NVLOG(a) 275#endif 276 277#define NV_SUCCESS 0 278#define NV_FAILURE -1 279 280/* 281 * indicates whether nv_wait functions can sleep or not. 282 */ 283#define NV_SLEEP 1 284#define NV_NOSLEEP 2 285 286/* 287 * port offsets from base address ioaddr1 288 */ 289#define NV_DATA 0x00 /* data register */ 290#define NV_ERROR 0x01 /* error register (read) */ 291#define NV_FEATURE 0x01 /* features (write) */ 292#define NV_COUNT 0x02 /* sector count */ 293#define NV_SECT 0x03 /* sector number */ 294#define NV_LCYL 0x04 /* cylinder low byte */ 295#define NV_HCYL 0x05 /* cylinder high byte */ 296#define NV_DRVHD 0x06 /* drive/head register */ 297#define NV_STATUS 0x07 /* status/command register */ 298#define NV_CMD 0x07 /* status/command register */ 299 300/* 301 * port offsets from base address ioaddr2 302 */ 303#define NV_ALTSTATUS 0x02 /* alternate status (read) */ 304#define NV_DEVCTL 0x02 /* device control (write) */ 305 306/* 307 * device control register 308 */ 309#define ATDC_NIEN 0x02 /* disable interrupts */ 310#define ATDC_SRST 0x04 /* controller reset */ 311#define ATDC_D3 0x08 /* mysterious bit */ 312#define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 313 314 315#define MCP55_CTL 0x400 /* queuing control */ 316#define MCP55_INT_STATUS 0x440 /* status bits for interrupt */ 317#define MCP55_INT_CTL 0x444 /* enable bits for interrupt */ 318#define MCP55_NCQ 0x448 /* NCQ status and ctrl bits */ 319 320/* 321 * if either of these bits are set, when using NCQ, if no other commands are 322 * active while a new command is started, DMA engine can be programmed ahead 323 * of time to save extra interrupt. Presumably pre-programming is discarded 324 * if a subsequent command ends up finishing first. 325 */ 326#define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 327#define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 328 329/* 330 * bit definitions to indicate which NCQ command requires 331 * DMA setup. 332 */ 333#define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 334#define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 335#define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 336 337 338/* 339 * Bits for NV_MCP55_INT_CTL and NV_MCP55_INT_STATUS 340 */ 341#define MCP55_INT_SNOTIFY 0x200 /* snotification set */ 342#define MCP55_INT_SERROR 0x100 /* serror set */ 343#define MCP55_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 344#define MCP55_INT_DH_REGFIS 0x40 /* REGFIS received */ 345#define MCP55_INT_SDB_FIS 0x20 /* SDB FIS */ 346#define MCP55_INT_TX_BACKOUT 0x10 /* TX backout */ 347#define MCP55_INT_REM 0x08 /* device removed */ 348#define MCP55_INT_ADD 0x04 /* device added */ 349#define MCP55_INT_PM 0x02 /* power changed */ 350#define MCP55_INT_COMPLETE 0x01 /* device interrupt */ 351 352/* 353 * Bits above that are not used for now. 354 */ 355#define MCP55_INT_IGNORE (MCP55_INT_DMA_SETUP|MCP55_INT_DH_REGFIS|\ 356 MCP55_INT_SDB_FIS|MCP55_INT_TX_BACKOUT|MCP55_INT_PM|\ 357 MCP55_INT_SNOTIFY|MCP55_INT_SERROR) 358 359/* 360 * Bits for MCP_SATA_AE_CTL 361 */ 362#define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 363#define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 364 365#define NV_DELAY_NSEC(wait_ns) \ 366{ \ 367 hrtime_t start, end; \ 368 start = end = gethrtime(); \ 369 while ((end - start) < wait_ns) \ 370 end = gethrtime(); \ 371} 372 373/* 374 * signatures in task file registers after device reset 375 */ 376#define NV_SIG_DISK 0x00000101 377#define NV_SIG_ATAPI 0xeb140101 378#define NV_SIG_PM 0x96690101 379#define NV_SIG_NOTREADY 0x00000000 380 381/* 382 * These bar5 offsets are common to mcp55/mcp04 and thus 383 * prefixed with NV. 384 */ 385#define NV_SSTATUS 0x00 386#define NV_SERROR 0x04 387#define NV_SCTRL 0x08 388#define NV_SACTIVE 0x0c 389#define NV_SNOTIFICATION 0x10 390 391#define CH0_SREG_OFFSET 0x0 392#define CH1_SREG_OFFSET 0x40 393 394 395/* 396 * The following config space offsets are needed to enable 397 * bar 5 register access in mcp04/mcp55 398 */ 399#define NV_SATA_CFG_20 0x50 400#define NV_BAR5_SPACE_EN 0x04 401#define NV_40BIT_PRD 0x20 402 403/* 404 * mcp04 interrupt status register 405 */ 406 407/* 408 * offsets to bar 5 registers 409 */ 410#define MCP04_SATA_INT_STATUS 0x440 411#define MCP04_SATA_INT_EN 0x441 412 413 414/* 415 * bit fields for int status and int enable 416 * registers 417 */ 418#define MCP04_INT_PDEV_INT 0x01 /* completion interrupt */ 419#define MCP04_INT_PDEV_PM 0x02 /* power change */ 420#define MCP04_INT_PDEV_ADD 0x04 /* hot plug */ 421#define MCP04_INT_PDEV_REM 0x08 /* hot remove */ 422#define MCP04_INT_PDEV_HOT MCP04_INT_PDEV_ADD|MCP04_INT_PDEV_REM 423 424#define MCP04_INT_SDEV_INT 0x10 /* completion interrupt */ 425#define MCP04_INT_SDEV_PM 0x20 /* power change */ 426#define MCP04_INT_SDEV_ADD 0x40 /* hot plug */ 427#define MCP04_INT_SDEV_REM 0x80 /* hot remove */ 428#define MCP04_INT_SDEV_HOT MCP04_INT_SDEV_ADD|MCP04_INT_SDEV_REM 429 430#define MCP04_INT_PDEV_ALL MCP04_INT_PDEV_INT|MCP04_INT_PDEV_HOT|\ 431 MCP04_INT_PDEV_PM 432#define MCP04_INT_SDEV_ALL MCP04_INT_SDEV_INT|MCP04_INT_SDEV_HOT|\ 433 MCP04_INT_SDEV_PM 434 435/* 436 * config space offset 42 437 */ 438#define NV_SATA_CFG_42 0xac 439 440/* 441 * bit in CFG_42 which delays hotplug interrupt until 442 * PHY ready 443 */ 444#define MCP04_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 445 446 447/* 448 * bar 5 offsets for SATA registers in ck804 449 */ 450#define MCP04_CH1_SSTATUS 0x00 451#define MCP04_CH1_SERROR 0x04 452#define MCP04_CH1_SCTRL 0x08 453#define MCP04_CH1_SACTIVE 0x0c 454#define MCP04_CH1_SNOTIFICATION 0x10 455 456#define MCP04_CH2_SSTATUS 0x40 457#define MCP04_CH2_SERROR 0x44 458#define MCP04_CH2_SCTRL 0x48 459#define MCP04_CH2_SACTIVE 0x4c 460#define MCP04_CH2_SNOTIFICATION 0x50 461 462 463/* 464 * bar 5 offsets for ADMACTL settings for both mcp04/mcp55 465 */ 466#define NV_ADMACTL_X 0x4C0 467#define NV_ADMACTL_Y 0x5C0 468 469/* 470 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 471 */ 472#define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 473#define NV_CH_RST 0x04 /* reset channel */ 474 475 476/* 477 * bar 5 offset for ADMASTAT regs for mcp04 478 */ 479#define MCP04_ADMASTAT_X 0x4C4 480#define MCP04_ADMASTAT_Y 0x5C4 481 482/* 483 * Bits for MCP04_ADMASTAT_X and MCP04_ADMASTAT_Y 484 */ 485#define MCP04_HPIRQ 0x4 486#define MCP05_HUIRQ 0x2 487 488 489/* 490 * bar 4 offset to bus master command registers 491 */ 492#define BMICX_REG 0 493 494/* 495 * bit definitions for BMICX_REG 496 */ 497#define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 498 /* 1=Start (Enable) */ 499 /* 0=Start (Disable) */ 500 501/* 502 * NOTE: "read" and "write" are the actions of the DMA engine 503 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 504 * command, program the DMA engine to "write to memory" mode 505 * (and vice versa). 506 */ 507#define BMICX_RWCON 0x08 /* Read/Write Control */ 508#define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 509#define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 510 511/* 512 * BMICX bits to preserve during updates 513 */ 514#define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 515 516/* 517 * bar 4 offset to bus master status register 518 */ 519#define BMISX_REG 2 520 521/* 522 * bit fields for bus master status register 523 */ 524#define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 525#define BMISX_IDERR 0x02 /* IDE DMA Error */ 526#define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 527 528/* 529 * bus master status register bits to preserve 530 */ 531#define BMISX_MASK 0xf8 532 533/* 534 * bar4 offset to bus master PRD descriptor table 535 */ 536#define BMIDTPX_REG 4 537 538 539/* 540 * structure for a single entry in the PRD table 541 * (physical region descriptor table) 542 */ 543typedef struct prde { 544 uint32_t p_address; /* physical address */ 545 uint32_t p_count; /* byte count, EOT in high order bit */ 546} prde_t; 547 548 549#define PRDE_EOT ((uint_t)0x80000000) 550 551#define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 552 553/* 554 * ck804 and mcp55 both have 2 ports per controller 555 */ 556#define NV_NUM_CPORTS 2 557 558/* 559 * Number of slots to allocate in data nv_sata structures to handle 560 * multiple commands at once. This does not reflect the capability of 561 * the drive or the hardware, and in many cases will not match. 562 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 563 * enabled but the drive doesn't support it, or supports fewer than 564 * 32 slots, here may be an over allocation of memory. 565 */ 566#ifdef NCQ 567#define NV_QUEUE_SLOTS 32 568#else 569#define NV_QUEUE_SLOTS 1 570#endif 571 572/* 573 * wait 30 seconds for signature 574 */ 575#define NV_SIG_TIMEOUT 45 576 577#define NV_BM_64K_BOUNDARY 0x10000ull 578 579/* 580 * every 1 second 581 */ 582#define NV_ONE_SEC 1000000 583 584 585/* 586 * the amount of time link can be down during 587 * reset without taking action. 588 */ 589#define NV_LINK_LOST_OK 2 590 591/* 592 * nv_reset() flags 593 */ 594#define NV_RESET_SEND_EVENT 0x1 /* send reset event to sata module */ 595#define NV_RESET_WAIT 0x2 /* OK to block waiting for reset */ 596 597 598 599#define NV_RESET_ATTEMPTS 3 600 601/* 602 * nvp_state flags 603 */ 604#define NV_PORT_INACTIVE 0x001 605#define NV_PORT_ABORTING 0x002 606#define NV_PORT_HOTREMOVED 0x004 607#define NV_PORT_INIT 0x008 608#define NV_PORT_FAILED 0x010 609#define NV_PORT_RESET 0x020 610#define NV_PORT_RESET_PROBE 0x040 611#define NV_PORT_RESTORE 0x080 612 613/* 614 * nvc_state flags 615 */ 616#define NV_CTRL_SUSPEND 0x1 617 618 619/* 620 * flags for mcp04_set_intr/mcp55_set_intr 621 */ 622#define NV_INTR_DISABLE 0x1 623#define NV_INTR_ENABLE 0x2 624#define NV_INTR_CLEAR_ALL 0x4 625 626/* 627 * sizes of strings to allocate 628 */ 629#define NV_STRING_10 10 630#define NV_STRING_512 512 631 632#define NV_BYTES_PER_SEC 512 633 634#define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 635#define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 636#define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 637#define MCP55_INT_CLEAR 0xffff /* clear all interrupts */ 638 639/* 640 * definition labels for the BAR registers 641 */ 642#define NV_BAR_0 0 /* chan 0 task file regs */ 643#define NV_BAR_1 1 /* chan 0 status reg */ 644#define NV_BAR_2 2 /* chan 1 task file regs */ 645#define NV_BAR_3 3 /* chan 1 status reg */ 646#define NV_BAR_4 4 /* bus master regs */ 647#define NV_BAR_5 5 /* extra regs mostly SATA related */ 648 649/* 650 * transform seconds to microseconds 651 */ 652#define NV_SEC2USEC(x) x * MICROSEC 653 654 655/* 656 * ck804 maps in task file regs into bar 5. These are 657 * only used to identify ck804, therefore only this reg is 658 * listed here. 659 */ 660#define NV_BAR5_TRAN_LEN_CH_X 0x518 661 662/* 663 * if after this many iterations through the interrupt 664 * processing loop, declare the interrupt wedged and 665 * disable. 666 */ 667#define NV_MAX_INTR_LOOP 10 668 669/* 670 * flag values for nv_copy_regs_out 671 */ 672#define NV_COPY_COMPLETE 0x01 /* normal command completion */ 673#define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 674#define NV_COPY_SSREGS 0x04 /* SS port registers */ 675 676#ifdef SGPIO_SUPPORT 677#define SGPIO_MAGIC 0x39da /* verifies good sgpio struct */ 678#define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 679#define SGPIO_TQ_NAME_LEN 32 680 681/* 682 * The drive number format is ccp (binary). 683 * cc is the controller number (0-based number) 684 * p is the port number (0 or 1) 685 */ 686#define SGP_DRV_TO_PORT(d) ((d) & 1) 687#define SGP_DRV_TO_CTLR(d) ((d) >> 1) 688#define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 689#endif 690 691#ifdef __cplusplus 692} 693#endif 694 695#endif /* _NV_SATA_H */ 696