nv_sata.h revision 10391:12b08c516444
175584Sru/* 275584Sru * CDDL HEADER START 375584Sru * 475584Sru * The contents of this file are subject to the terms of the 575584Sru * Common Development and Distribution License (the "License"). 675584Sru * You may not use this file except in compliance with the License. 775584Sru * 875584Sru * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 975584Sru * or http://www.opensolaris.org/os/licensing. 1075584Sru * See the License for the specific language governing permissions 1175584Sru * and limitations under the License. 1275584Sru * 1375584Sru * When distributing Covered Code, include this CDDL HEADER in each 1475584Sru * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1575584Sru * If applicable, add the following below this CDDL HEADER, with the 1675584Sru * fields enclosed by brackets "[]" replaced with your own identifying 1775584Sru * information: Portions Copyright [yyyy] [name of copyright owner] 1875584Sru * 1975584Sru * CDDL HEADER END 2075584Sru */ 2175584Sru 2275584Sru/* 2375584Sru * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2475584Sru * Use is subject to license terms. 2575584Sru */ 2675584Sru 2775584Sru#ifndef _NV_SATA_H 2875584Sru#define _NV_SATA_H 2975584Sru 3075584Sru 3175584Sru#ifdef __cplusplus 3275584Sruextern "C" { 3375584Sru#endif 3475584Sru 3575584Sru 3675584Sru/* 3775584Sru * SGPIO Support 3875584Sru * Enable SGPIO support only on x86/x64, because it is implemented using 3975584Sru * functions that are only available on x86/x64. 4075584Sru */ 4175584Sru 4275584Sru#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 4375584Sru 4475584Srutypedef struct nv_port nv_port_t; 4575584Sru 4675584Sru#ifdef SGPIO_SUPPORT 4775584Srutypedef struct nv_sgp_cmn nv_sgp_cmn_t; 4875584Sru#endif 4975584Sru 5075584Srutypedef struct nv_ctl { 5175584Sru /* 5275584Sru * Each of these are specific to the chipset in use. 5375584Sru */ 5475584Sru uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 5575584Sru void (*nvc_reg_init)(struct nv_ctl *nvc, 5675584Sru ddi_acc_handle_t pci_conf_handle); 5775584Sru 5875584Sru dev_info_t *nvc_dip; /* devinfo pointer of controller */ 5975584Sru 6075584Sru struct nv_port *nvc_port; /* array of pointers to port struct */ 6175584Sru 6275584Sru /* 6375584Sru * handle and base address to register space. 6475584Sru * 6575584Sru * 0: port 0 task file 6675584Sru * 1: port 0 status 6775584Sru * 2: port 1 task file 6875584Sru * 3: port 1 status 6975584Sru * 4: bus master for both ports 7075584Sru * 5: extended registers for SATA features 7175584Sru */ 7275584Sru ddi_acc_handle_t nvc_bar_hdl[6]; 7375584Sru uchar_t *nvc_bar_addr[6]; 7475584Sru 7575584Sru /* 7675584Sru * sata registers in bar 5 which are shared on all devices 7775584Sru * on the channel. 7875584Sru */ 7975584Sru uint32_t *nvc_mcp5x_ctl; 8075584Sru uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */ 8175584Sru 8275584Sru kmutex_t nvc_mutex; /* ctrl level lock */ 8375584Sru 8475584Sru ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 8575584Sru int nvc_intr_type; /* What type of interrupt */ 8675584Sru int nvc_intr_cnt; /* # of intrs count returned */ 8775584Sru size_t nvc_intr_size; /* Size of intr array to */ 8875584Sru uint_t nvc_intr_pri; /* Interrupt priority */ 8975584Sru int nvc_intr_cap; /* Interrupt capabilities */ 9075584Sru uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */ 9175584Sru 9275584Sru sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 9375584Sru 9475584Sru /* 9575584Sru * enable/disable interrupts, controller specific 9675584Sru */ 9775584Sru void (*nvc_set_intr)(nv_port_t *nvp, int flag); 9875584Sru int nvc_state; /* state flags of ctrl see below */ 9975584Sru uint8_t nvc_revid; /* PCI revid of device */ 10075584Sru boolean_t dma_40bit; /* 40bit DMA support */ 10175584Sru 10275584Sru#ifdef SGPIO_SUPPORT 10375584Sru int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */ 10475584Sru uint8_t nvc_ctlr_num; /* controller number within the part */ 10575584Sru uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 10675584Sru volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */ 10775584Sru nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 10875584Sru#endif 10975584Sru} nv_ctl_t; 11075584Sru 11175584Sru 11275584Srustruct nv_port { 11375584Sru 11475584Sru struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 11575584Sru 11675584Sru uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 11775584Sru 11875584Sru uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 11975584Sru uint32_t nvp_signature; /* sig acquired from task file regs */ 12075584Sru uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 12175584Sru uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 12275584Sru uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 12375584Sru 12475584Sru ddi_acc_handle_t nvp_cmd_hdl; 12575584Sru uchar_t *nvp_data; /* data register */ 12675584Sru uchar_t *nvp_error; /* error register (read) */ 12775584Sru uchar_t *nvp_feature; /* features (write) */ 12875584Sru uchar_t *nvp_count; /* sector count */ 12975584Sru uchar_t *nvp_sect; /* sector number */ 13075584Sru uchar_t *nvp_lcyl; /* cylinder low byte */ 13175584Sru uchar_t *nvp_hcyl; /* cylinder high byte */ 13275584Sru uchar_t *nvp_drvhd; /* drive/head register */ 13375584Sru uchar_t *nvp_status; /* status/command register */ 13475584Sru uchar_t *nvp_cmd; /* status/command register */ 13575584Sru 13675584Sru ddi_acc_handle_t nvp_ctl_hdl; 13775584Sru uchar_t *nvp_altstatus; /* alternate status (read) */ 13875584Sru uchar_t *nvp_devctl; /* device control (write) */ 13975584Sru 14075584Sru ddi_acc_handle_t nvp_bm_hdl; 14175584Sru uchar_t *nvp_bmisx; 14275584Sru uint32_t *nvp_bmidtpx; 14375584Sru uchar_t *nvp_bmicx; 14475584Sru 14575584Sru ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 14675584Sru caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 14775584Sru uint32_t *nvp_sg_paddr; /* physical address of prd table */ 14875584Sru ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 14975584Sru 15075584Sru uint32_t *nvp_sstatus; 15175584Sru uint32_t *nvp_serror; 15275584Sru uint32_t *nvp_sctrl; 15375584Sru uint32_t *nvp_sactive; 15475584Sru 15575584Sru kmutex_t nvp_mutex; /* main per port mutex */ 15675584Sru kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 15775584Sru 15875584Sru /* 15975584Sru * nvp_slot is a pointer to an array of nv_slot 16075584Sru */ 16175584Sru struct nv_slot *nvp_slot; 16275584Sru uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 16375584Sru uint8_t nvp_queue_depth; 16475584Sru 16575584Sru /* 16675584Sru * NCQ flow control. During NCQ operation, no other commands 16775584Sru * allowed. The following are used to enforce this. 16875584Sru */ 16975584Sru int nvp_ncq_run; 17075584Sru int nvp_non_ncq_run; 17175584Sru 17275584Sru timeout_id_t nvp_timeout_id; 17375584Sru 17475584Sru clock_t nvp_reset_time; /* time of last reset */ 17575584Sru 17675584Sru int nvp_state; /* state of port. flags defined below */ 17775584Sru 17875584Sru uint16_t *nvp_mcp5x_int_status; 17975584Sru uint16_t *nvp_mcp5x_int_ctl; 18075584Sru 18175584Sru#ifdef SGPIO_SUPPORT 18275584Sru uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 18375584Sru#endif 18475584Sru int nvp_timeout_duration; 18575584Sru 18675584Sru uint8_t nvp_last_cmd; 18775584Sru uint8_t nvp_previous_cmd; 18875584Sru int nvp_reset_count; 18975584Sru clock_t intr_duration; /* max length of port intr (ticks) */ 19075584Sru clock_t intr_start_time; 19175584Sru int intr_loop_cnt; 19275584Sru}; 19375584Sru 19475584Sru 19575584Srutypedef struct nv_device_table { 19675584Sru ushort_t vendor_id; /* vendor id */ 19775584Sru ushort_t device_id; /* device id */ 19875584Sru ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */ 19975584Sru} nv_device_table_t; 20075584Sru 20175584Sru 20275584Srutypedef struct nv_slot { 20375584Sru caddr_t nvslot_v_addr; /* I/O buffer address */ 20475584Sru size_t nvslot_byte_count; /* # bytes left to read/write */ 20575584Sru sata_pkt_t *nvslot_spkt; 20675584Sru uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 20775584Sru clock_t nvslot_stime; 20875584Sru int (*nvslot_start)(nv_port_t *nvp, int queue); 20975584Sru void (*nvslot_intr)(nv_port_t *nvp, 21075584Sru struct nv_slot *nv_slotp); 21175584Sru uint32_t nvslot_flags; 21275584Sru} nv_slot_t; 21375584Sru 21475584Sru 21575584Sru#ifdef SGPIO_SUPPORT 21675584Srustruct nv_sgp_cmn { 21775584Sru uint8_t nvs_in_use; /* bit-field of active ctlrs */ 21875584Sru uint8_t nvs_connected; /* port connected bit-field flag */ 21975584Sru uint8_t nvs_activity; /* port usage bit-field flag */ 22075584Sru int nvs_cbp; /* SGPIO Control Block Pointer */ 22175584Sru int nvs_taskq_delay; /* rest time for activity LED taskq */ 22275584Sru kmutex_t nvs_slock; /* lock for shared data */ 22375584Sru kmutex_t nvs_tlock; /* lock for taskq */ 22475584Sru kcondvar_t nvs_cv; /* condition variable for taskq wait */ 22575584Sru ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 22675584Sru}; 22775584Sru 22875584Srustruct nv_sgp_cbp2cmn { 22975584Sru uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */ 23075584Sru nv_sgp_cmn_t *c2cm_cmn; /* point to common space */ 23175584Sru}; 23275584Sru#endif 23375584Sru 23475584Sru 23575584Sru/* 23675584Sru * nvslot_flags 23775584Sru */ 23875584Sru#define NVSLOT_COMPLETE 0x01 23975584Sru#define NVSLOT_NCQ 0x02 /* NCQ is active */ 24075584Sru#define NVSLOT_RQSENSE 0x04 /* processing request sense */ 24175584Sru 24275584Sru/* 24375584Sru * state values for nv_attach 24475584Sru */ 24575584Sru#define ATTACH_PROGRESS_NONE (1 << 0) 24675584Sru#define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 24775584Sru#define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 24875584Sru#define ATTACH_PROGRESS_BARS (1 << 3) 24975584Sru#define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 25075584Sru#define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 25175584Sru#define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 25275584Sru#define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 25375584Sru#define ATTACH_PROGRESS_COUNT (1 << 8) 25475584Sru#define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 25575584Sru#define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 25675584Sru 25775584Sru#ifdef DEBUG 25875584Sru 25975584Sru#define NV_DEBUG 1 26075584Sru 26175584Sru#endif /* DEBUG */ 26275584Sru 26375584Sru 26475584Sru/* 26575584Sru * nv_debug_flags 26675584Sru */ 26775584Sru#define NVDBG_ALWAYS 0x0001 26875584Sru#define NVDBG_INIT 0x0002 26975584Sru#define NVDBG_ENTRY 0x0004 27075584Sru#define NVDBG_DELIVER 0x0008 27175584Sru#define NVDBG_EVENT 0x0010 27275584Sru#define NVDBG_SYNC 0x0020 27375584Sru#define NVDBG_PKTCOMP 0x0040 27475584Sru#define NVDBG_TIMEOUT 0x0080 27575584Sru#define NVDBG_INFO 0x0100 27675584Sru#define NVDBG_VERBOSE 0x0200 27775584Sru#define NVDBG_INTR 0x0400 27875584Sru#define NVDBG_ERRS 0x0800 27975584Sru#define NVDBG_COOKIES 0x1000 28075584Sru#define NVDBG_HOT 0x2000 28175584Sru#define NVDBG_RESET 0x4000 28275584Sru#define NVDBG_ATAPI 0x8000 28375584Sru 28475584Sru#ifdef DEBUG 28575584Sru#define NVLOG(a) nv_log a 28675584Sru#else 28775584Sru#define NVLOG(a) 28875584Sru#endif 28975584Sru 29075584Sru#define NV_SUCCESS 0 29175584Sru#define NV_FAILURE -1 29275584Sru 29375584Sru/* 29475584Sru * indicates whether nv_wait functions can sleep or not. 29575584Sru */ 29675584Sru#define NV_SLEEP 1 29775584Sru#define NV_NOSLEEP 2 29875584Sru 29975584Sru/* 30075584Sru * port offsets from base address ioaddr1 30175584Sru */ 30275584Sru#define NV_DATA 0x00 /* data register */ 30375584Sru#define NV_ERROR 0x01 /* error register (read) */ 30475584Sru#define NV_FEATURE 0x01 /* features (write) */ 30575584Sru#define NV_COUNT 0x02 /* sector count */ 30675584Sru#define NV_SECT 0x03 /* sector number */ 30775584Sru#define NV_LCYL 0x04 /* cylinder low byte */ 30875584Sru#define NV_HCYL 0x05 /* cylinder high byte */ 30975584Sru#define NV_DRVHD 0x06 /* drive/head register */ 31075584Sru#define NV_STATUS 0x07 /* status/command register */ 31175584Sru#define NV_CMD 0x07 /* status/command register */ 31275584Sru 31375584Sru/* 31475584Sru * port offsets from base address ioaddr2 31575584Sru */ 31675584Sru#define NV_ALTSTATUS 0x02 /* alternate status (read) */ 31775584Sru#define NV_DEVCTL 0x02 /* device control (write) */ 31875584Sru 31975584Sru/* 32075584Sru * device control register 32175584Sru */ 32275584Sru#define ATDC_NIEN 0x02 /* disable interrupts */ 32375584Sru#define ATDC_SRST 0x04 /* controller reset */ 32475584Sru#define ATDC_D3 0x08 /* mysterious bit */ 32575584Sru#define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 32675584Sru 32775584Sru/* 32875584Sru * MCP5x NCQ and INTR control registers 32975584Sru */ 33075584Sru#define MCP5X_CTL 0x400 /* queuing control */ 33175584Sru#define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */ 33275584Sru#define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */ 33375584Sru#define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */ 33475584Sru 33575584Sru/* 33675584Sru * if either of these bits are set, when using NCQ, if no other commands are 33775584Sru * active while a new command is started, DMA engine can be programmed ahead 33875584Sru * of time to save extra interrupt. Presumably pre-programming is discarded 33975584Sru * if a subsequent command ends up finishing first. 34075584Sru */ 34175584Sru#define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 34275584Sru#define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 34375584Sru 34475584Sru/* 34575584Sru * bit definitions to indicate which NCQ command requires 34675584Sru * DMA setup. 34775584Sru */ 34875584Sru#define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 34975584Sru#define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 35075584Sru#define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 35175584Sru 35275584Sru 35375584Sru/* 35475584Sru * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS 35575584Sru */ 35675584Sru#define MCP5X_INT_SNOTIFY 0x200 /* snotification set */ 35775584Sru#define MCP5X_INT_SERROR 0x100 /* serror set */ 35875584Sru#define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 35975584Sru#define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */ 36075584Sru#define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */ 36175584Sru#define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */ 36275584Sru#define MCP5X_INT_REM 0x08 /* device removed */ 36375584Sru#define MCP5X_INT_ADD 0x04 /* device added */ 36475584Sru#define MCP5X_INT_PM 0x02 /* power changed */ 36575584Sru#define MCP5X_INT_COMPLETE 0x01 /* device interrupt */ 36675584Sru 36775584Sru/* 36875584Sru * Bits above that are not used for now. 36975584Sru */ 37075584Sru#define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\ 37175584Sru MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\ 37275584Sru MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR) 37375584Sru 37475584Sru/* 37575584Sru * Bits for MCP_SATA_AE_CTL 37675584Sru */ 37775584Sru#define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 37875584Sru#define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 37975584Sru 38075584Sru#define NV_DELAY_NSEC(wait_ns) \ 38175584Sru{ \ 38275584Sru hrtime_t start, end; \ 38375584Sru start = end = gethrtime(); \ 38475584Sru while ((end - start) < wait_ns) \ 38575584Sru end = gethrtime(); \ 38675584Sru} 38775584Sru 38875584Sru/* 38975584Sru * signatures in task file registers after device reset 39075584Sru */ 39175584Sru#define NV_SIG_DISK 0x00000101 39275584Sru#define NV_SIG_ATAPI 0xeb140101 39375584Sru#define NV_SIG_PM 0x96690101 39475584Sru#define NV_SIG_NOTREADY 0x00000000 39575584Sru 396104862Sru/* 397104862Sru * These bar5 offsets are common to mcp51/mcp55/ck804 and thus 398104862Sru * prefixed with NV. 399104862Sru */ 400#define NV_SSTATUS 0x00 401#define NV_SERROR 0x04 402#define NV_SCTRL 0x08 403#define NV_SACTIVE 0x0c 404#define NV_SNOTIFICATION 0x10 405 406#define CH0_SREG_OFFSET 0x0 407#define CH1_SREG_OFFSET 0x40 408 409 410/* 411 * The following config space offsets are needed to enable 412 * bar 5 register access in ck804/mcp51/mcp55 413 */ 414#define NV_SATA_CFG_20 0x50 415#define NV_BAR5_SPACE_EN 0x04 416#define NV_40BIT_PRD 0x20 417 418/* 419 * ck804 interrupt status register 420 */ 421 422/* 423 * offsets to bar 5 registers 424 */ 425#define CK804_SATA_INT_STATUS 0x440 426#define CK804_SATA_INT_EN 0x441 427 428 429/* 430 * bit fields for int status and int enable 431 * registers 432 */ 433#define CK804_INT_PDEV_INT 0x01 /* completion interrupt */ 434#define CK804_INT_PDEV_PM 0x02 /* power change */ 435#define CK804_INT_PDEV_ADD 0x04 /* hot plug */ 436#define CK804_INT_PDEV_REM 0x08 /* hot remove */ 437#define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM 438 439#define CK804_INT_SDEV_INT 0x10 /* completion interrupt */ 440#define CK804_INT_SDEV_PM 0x20 /* power change */ 441#define CK804_INT_SDEV_ADD 0x40 /* hot plug */ 442#define CK804_INT_SDEV_REM 0x80 /* hot remove */ 443#define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM 444 445#define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\ 446 CK804_INT_PDEV_PM 447#define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\ 448 CK804_INT_SDEV_PM 449 450/* 451 * config space offset 42 452 */ 453#define NV_SATA_CFG_42 0xac 454 455/* 456 * bit in CFG_42 which delays hotplug interrupt until 457 * PHY ready 458 */ 459#define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 460 461 462/* 463 * bar 5 offsets for SATA registers in ck804 464 */ 465#define CK804_CH1_SSTATUS 0x00 466#define CK804_CH1_SERROR 0x04 467#define CK804_CH1_SCTRL 0x08 468#define CK804_CH1_SACTIVE 0x0c 469#define CK804_CH1_SNOTIFICATION 0x10 470 471#define CK804_CH2_SSTATUS 0x40 472#define CK804_CH2_SERROR 0x44 473#define CK804_CH2_SCTRL 0x48 474#define CK804_CH2_SACTIVE 0x4c 475#define CK804_CH2_SNOTIFICATION 0x50 476 477 478/* 479 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55 480 */ 481#define NV_ADMACTL_X 0x4C0 482#define NV_ADMACTL_Y 0x5C0 483 484/* 485 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 486 */ 487#define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 488#define NV_CH_RST 0x04 /* reset channel */ 489 490 491/* 492 * bar 5 offset for ADMASTAT regs for ck804 493 */ 494#define CK804_ADMASTAT_X 0x4C4 495#define CK804_ADMASTAT_Y 0x5C4 496 497/* 498 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y 499 */ 500#define CK804_HPIRQ 0x4 501#define MCP05_HUIRQ 0x2 502 503 504/* 505 * bar 4 offset to bus master command registers 506 */ 507#define BMICX_REG 0 508 509/* 510 * bit definitions for BMICX_REG 511 */ 512#define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 513 /* 1=Start (Enable) */ 514 /* 0=Start (Disable) */ 515 516/* 517 * NOTE: "read" and "write" are the actions of the DMA engine 518 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 519 * command, program the DMA engine to "write to memory" mode 520 * (and vice versa). 521 */ 522#define BMICX_RWCON 0x08 /* Read/Write Control */ 523#define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 524#define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 525 526/* 527 * BMICX bits to preserve during updates 528 */ 529#define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 530 531/* 532 * bar 4 offset to bus master status register 533 */ 534#define BMISX_REG 2 535 536/* 537 * bit fields for bus master status register 538 */ 539#define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 540#define BMISX_IDERR 0x02 /* IDE DMA Error */ 541#define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 542 543/* 544 * bus master status register bits to preserve 545 */ 546#define BMISX_MASK 0xf8 547 548/* 549 * bar4 offset to bus master PRD descriptor table 550 */ 551#define BMIDTPX_REG 4 552 553 554/* 555 * structure for a single entry in the PRD table 556 * (physical region descriptor table) 557 */ 558typedef struct prde { 559 uint32_t p_address; /* physical address */ 560 uint32_t p_count; /* byte count, EOT in high order bit */ 561} prde_t; 562 563 564#define PRDE_EOT ((uint_t)0x80000000) 565 566#define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 567 568/* 569 * ck804 and mcp55 both have 2 ports per controller 570 */ 571#define NV_NUM_CPORTS 2 572 573/* 574 * Number of slots to allocate in data nv_sata structures to handle 575 * multiple commands at once. This does not reflect the capability of 576 * the drive or the hardware, and in many cases will not match. 577 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 578 * enabled but the drive doesn't support it, or supports fewer than 579 * 32 slots, here may be an over allocation of memory. 580 */ 581#ifdef NCQ 582#define NV_QUEUE_SLOTS 32 583#else 584#define NV_QUEUE_SLOTS 1 585#endif 586 587#define NV_BM_64K_BOUNDARY 0x10000ull 588 589#define NV_MAX_INTR_PER_DEV 20 /* Empirical value */ 590 591/* 592 * 1 second (in microseconds) 593 */ 594#define NV_ONE_SEC 1000000 595 596/* 597 * 1 millisecond (in microseconds) 598 */ 599#define NV_ONE_MSEC 1000 600 601/* 602 * Length of port reset (microseconds) - SControl bit 0 set to 1 603 */ 604#define NV_RESET_LENGTH 1000 605 606#define NV_RESET_ATTEMPTS 3 607 608/* 609 * The maximum amount of time (milliseconds) a link can be down during 610 * reset without assuming that there is no device attached. 611 */ 612#define NV_LINK_DOWN_TIMEOUT 10 613 614/* 615 * The maximum amount of time (milliseconds) the signature acquisition can 616 * drag on before it is terminated. 617 * Some disks have very long acquisition times after hotplug, related to 618 * to spinning-up and reading some data from a media. 619 * The value below is empirical (20s) 620 * 621 */ 622#define NV_SIG_ACQUISITION_TIME 20000 623 624/* 625 * Minimum amount of time (milliseconds) to delay reporting hotplug 626 * (device added) event. 627 * It is the time allowed for a drive to initialize and to send a D2H FIS with 628 * a device signature. 629 * It varies between drives from a few milliseconds up to 20s. 630 */ 631#define NV_HOTPLUG_DELAY 20000 632 633/* 634 * nvp_state flags 635 */ 636#define NV_PORT_INACTIVE 0x001 637#define NV_PORT_ABORTING 0x002 638#define NV_PORT_HOTREMOVED 0x004 639#define NV_PORT_INIT 0x008 640#define NV_PORT_FAILED 0x010 641#define NV_PORT_RESET 0x020 642#define NV_PORT_RESET_RETRY 0x040 643#define NV_PORT_RESTORE 0x080 644#define NV_PORT_PROBE 0x100 645#define NV_PORT_HOTPLUG_DELAY 0x200 646 647/* 648 * nvc_state flags 649 */ 650#define NV_CTRL_SUSPEND 0x1 651 652 653/* 654 * flags for ck804_set_intr/mcp5x_set_intr 655 */ 656#define NV_INTR_DISABLE 0x1 657#define NV_INTR_ENABLE 0x2 658#define NV_INTR_CLEAR_ALL 0x4 659#define NV_INTR_DISABLE_NON_BLOCKING 0x8 660 661/* 662 * sizes of strings to allocate 663 */ 664#define NV_STRING_10 10 665#define NV_STRING_512 512 666 667#define NV_BYTES_PER_SEC 512 668 669#define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 670#define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 671#define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 672#define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */ 673 674/* 675 * definition labels for the BAR registers 676 */ 677#define NV_BAR_0 0 /* chan 0 task file regs */ 678#define NV_BAR_1 1 /* chan 0 status reg */ 679#define NV_BAR_2 2 /* chan 1 task file regs */ 680#define NV_BAR_3 3 /* chan 1 status reg */ 681#define NV_BAR_4 4 /* bus master regs */ 682#define NV_BAR_5 5 /* extra regs mostly SATA related */ 683 684/* 685 * transform seconds to microseconds 686 */ 687#define NV_SEC2USEC(x) x * MICROSEC 688 689 690/* 691 * ck804 maps in task file regs into bar 5. These are 692 * only used to identify ck804, therefore only this reg is 693 * listed here. 694 */ 695#define NV_BAR5_TRAN_LEN_CH_X 0x518 696 697/* 698 * if after this many iterations through the interrupt 699 * processing loop, declare the interrupt wedged and 700 * disable. 701 */ 702#define NV_MAX_INTR_LOOP 10 703 704/* 705 * flag values for nv_copy_regs_out 706 */ 707#define NV_COPY_COMPLETE 0x01 /* normal command completion */ 708#define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 709#define NV_COPY_SSREGS 0x04 /* SS port registers */ 710 711#ifdef SGPIO_SUPPORT 712#define NV_MAX_CBPS 16 /* Maximum # of Control Block */ 713 /* Pointers. Corresponds to */ 714 /* each MCP55 and IO55 */ 715#define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 716#define SGPIO_TQ_NAME_LEN 32 717 718/* 719 * The drive number format is ccp (binary). 720 * cc is the controller number (0-based number) 721 * p is the port number (0 or 1) 722 */ 723#define SGP_DRV_TO_PORT(d) ((d) & 1) 724#define SGP_DRV_TO_CTLR(d) ((d) >> 1) 725#define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 726#endif 727 728#ifdef __cplusplus 729} 730#endif 731 732#endif /* _NV_SATA_H */ 733