ahcivar.h revision 7623:76bac10725f1
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28#ifndef _AHCIVAR_H 29#define _AHCIVAR_H 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35/* Type for argument of event handler */ 36typedef struct ahci_event_arg { 37 void *ahciea_ctlp; 38 void *ahciea_portp; 39 uint32_t ahciea_event; 40} ahci_event_arg_t; 41 42/* Warlock annotation */ 43_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_ctlp)) 44_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_portp)) 45_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_event)) 46 47/* 48 * flags for ahciport_flags 49 * 50 * AHCI_PORT_FLAG_SPINUP: this flag will be set when a HBA which supports 51 * staggered spin-up needs to do a spin-up. 52 * 53 * AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped, 54 * and all the outstanding commands need to be aborted and sent to upper 55 * layers. 56 * 57 * AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is 58 * disabled, and the command is executed in POLLING mode. 59 * 60 * AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which 61 * is used to retrieve sense data is being executed. 62 * 63 * AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started, 64 * that is PxCMD.ST is set with '1', and be cleared when the port is put into 65 * idle, that is PxCMD.ST is changed from '1' to '0'. 66 * 67 * AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which 68 * is used to retrieve NCQ failure context is being executed. 69 * 70 * AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone 71 * during ahci_restart_port_wait_till_ready process. 72 */ 73#define AHCI_PORT_FLAG_SPINUP 0x01 74#define AHCI_PORT_FLAG_MOPPING 0x02 75#define AHCI_PORT_FLAG_POLLING 0x04 76#define AHCI_PORT_FLAG_RQSENSE 0x08 77#define AHCI_PORT_FLAG_STARTED 0x10 78#define AHCI_PORT_FLAG_RDLOGEXT 0x20 79#define AHCI_PORT_FLAG_NODEV 0x40 80 81typedef struct ahci_port { 82 /* The physical port number */ 83 uint8_t ahciport_port_num; 84 85 /* Type of the device attached to the port */ 86 uint8_t ahciport_device_type; 87 /* State of the port */ 88 uint32_t ahciport_port_state; 89 90 /* 91 * AHCI_PORT_FLAG_SPINUP 92 * AHCI_PORT_FLAG_MOPPING 93 * AHCI_PORT_FLAG_POLLING 94 * AHCI_PORT_FLAG_RQSENSE 95 * AHCI_PORT_FLAG_STARTED 96 * AHCI_PORT_FLAG_RDLOGEXT 97 * AHCI_PORT_FLAG_NODEV 98 */ 99 int ahciport_flags; 100 101 /* Pointer to received FIS structure */ 102 ahci_rcvd_fis_t *ahciport_rcvd_fis; 103 ddi_dma_handle_t ahciport_rcvd_fis_dma_handle; 104 ddi_acc_handle_t ahciport_rcvd_fis_acc_handle; 105 ddi_dma_cookie_t ahciport_rcvd_fis_dma_cookie; 106 107 /* Pointer to command list structure */ 108 ahci_cmd_header_t *ahciport_cmd_list; 109 ddi_dma_handle_t ahciport_cmd_list_dma_handle; 110 ddi_acc_handle_t ahciport_cmd_list_acc_handle; 111 ddi_dma_cookie_t ahciport_cmd_list_dma_cookie; 112 113 /* Pointer to cmmand table structure */ 114 ahci_cmd_table_t \ 115 *ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS]; 116 ddi_dma_handle_t \ 117 ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS]; 118 ddi_acc_handle_t \ 119 ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS]; 120 121 /* Condition variable used for sync mode commands */ 122 kcondvar_t ahciport_cv; 123 124 /* The whole mutex for the port structure */ 125 kmutex_t ahciport_mutex; 126 127 /* The maximum number of tags for native queuing command transfers */ 128 int ahciport_max_ncq_tags; 129 130 /* Keep the tags of all pending non-ncq commands */ 131 uint32_t ahciport_pending_tags; 132 133 /* 134 * Keep the tags of all pending ncq commands 135 * (READ/WRITE FPDMA QUEUED) 136 */ 137 uint32_t ahciport_pending_ncq_tags; 138 139 /* Keep all the pending sata packets */ 140 sata_pkt_t *ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS]; 141 142 /* Keep the error retrieval sata packet */ 143 sata_pkt_t *ahciport_err_retri_pkt; 144 145 /* 146 * SATA HBA driver is supposed to remember and maintain device 147 * reset state. While the reset is in progress, it doesn't accept 148 * any more commands until receiving the command with 149 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE. 150 */ 151 int ahciport_reset_in_progress; 152 153 /* This is for error recovery handler */ 154 ahci_event_arg_t *ahciport_event_args; 155 156 /* This is to calculate how many mops are in progress */ 157 int ahciport_mop_in_progress; 158} ahci_port_t; 159 160/* Warlock annotation */ 161_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle)) 162_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle)) 163_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle)) 164_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 165 ahci_port_t::ahciport_device_type)) 166_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 167 ahci_port_t::ahciport_port_state)) 168_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 169 ahci_port_t::ahciport_flags)) 170_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 171 ahci_port_t::ahciport_pending_tags)) 172_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 173 ahci_port_t::ahciport_slot_pkts)) 174_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 175 ahci_port_t::ahciport_reset_in_progress)) 176_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 177 ahci_port_t::ahciport_mop_in_progress)) 178 179typedef struct ahci_ctl { 180 dev_info_t *ahcictl_dip; 181 /* To map port number to cport number */ 182 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS]; 183 /* To map cport number to port number */ 184 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS]; 185 186 /* Number of controller ports */ 187 int ahcictl_num_ports; 188 /* Number of command slots */ 189 int ahcictl_num_cmd_slots; 190 /* Number of implemented ports */ 191 int ahcictl_num_implemented_ports; 192 /* Bit map to indicate which port is implemented */ 193 uint32_t ahcictl_ports_implemented; 194 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS]; 195 196 int ahcictl_flags; 197 int ahcictl_power_level; 198 off_t ahcictl_pmcsr_offset; 199 200 /* 201 * AHCI_CAP_PIO_MDRQ 202 * AHCI_CAP_NO_MCMDLIST_NONQUEUE 203 * AHCI_CAP_NCQ 204 * AHCI_CAP_PM 205 * AHCI_CAP_32BIT_DMA 206 */ 207 int ahcictl_cap; 208 209 /* Pci configuration space handle */ 210 ddi_acc_handle_t ahcictl_pci_conf_handle; 211 212 /* Mapping into bar 5 - AHCI base address */ 213 ddi_acc_handle_t ahcictl_ahci_acc_handle; 214 uintptr_t ahcictl_ahci_addr; 215 216 /* Pointer used for sata hba framework registration */ 217 struct sata_hba_tran *ahcictl_sata_hba_tran; 218 219 /* DMA attributes for the data buffer */ 220 ddi_dma_attr_t ahcictl_buffer_dma_attr; 221 /* DMA attributes for the rcvd FIS */ 222 ddi_dma_attr_t ahcictl_rcvd_fis_dma_attr; 223 /* DMA attributes for the command list */ 224 ddi_dma_attr_t ahcictl_cmd_list_dma_attr; 225 /* DMA attributes for command tables */ 226 ddi_dma_attr_t ahcictl_cmd_table_dma_attr; 227 228 /* Used for watchdog handler */ 229 timeout_id_t ahcictl_timeout_id; 230 231 /* Per controller mutex */ 232 kmutex_t ahcictl_mutex; 233 234 /* Components for interrupt */ 235 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */ 236 int ahcictl_intr_type; /* What type of interrupt */ 237 int ahcictl_intr_cnt; /* # of intrs returned */ 238 size_t ahcictl_intr_size; /* Size of intr array */ 239 uint_t ahcictl_intr_pri; /* Intr priority */ 240 int ahcictl_intr_cap; /* Intr capabilities */ 241 242 /* Taskq for handling event */ 243 ddi_taskq_t *ahcictl_event_taskq; 244} ahci_ctl_t; 245 246/* Warlock annotation */ 247_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports)) 248_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port)) 249_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport)) 250 251_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 252 ahci_ctl_t::ahcictl_power_level)) 253_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 254 ahci_ctl_t::ahcictl_flags)) 255_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 256 ahci_ctl_t::ahcictl_timeout_id)) 257 258#define AHCI_SUCCESS (0) /* Successful return */ 259#define AHCI_TIMEOUT (1) /* Timed out */ 260#define AHCI_FAILURE (-1) /* Unsuccessful return */ 261 262/* Flags for ahcictl_flags */ 263#define AHCI_ATTACH 0x1 264#define AHCI_DETACH 0x2 265#define AHCI_SUSPEND 0x4 266 267/* Values for ahcictl_cap */ 268/* PIO Multiple DRQ Block */ 269#define AHCI_CAP_PIO_MDRQ 0x1 270/* 271 * Multiple command slots in the command list cannot be used for 272 * non-queued commands 273 */ 274#define AHCI_CAP_NO_MCMDLIST_NONQUEUE 0x2 275/* Native Command Queuing (NCQ) */ 276#define AHCI_CAP_NCQ 0x4 277/* Power Management (PM) */ 278#define AHCI_CAP_PM 0x8 279/* 32-bit DMA addressing */ 280#define AHCI_CAP_32BIT_DMA 0x10 281 282/* Flags controlling the restart port behavior */ 283#define AHCI_PORT_RESET 0x0001 /* Reset the port */ 284#define AHCI_PORT_INIT 0x0002 /* Initialize port */ 285#define AHCI_RESET_NO_EVENTS_UP 0x0004 /* Don't send reset events up */ 286 287#define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \ 288 (ahci_portp->ahciport_flags & \ 289 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT)) 290 291#define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \ 292 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 293 ahci_portp->ahciport_pending_tags != 0 && \ 294 ahci_portp->ahciport_pending_ncq_tags == 0) 295 296#define NCQ_CMD_IN_PROGRESS(ahci_portp) \ 297 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 298 ahci_portp->ahciport_pending_ncq_tags != 0) 299 300/* Command type for ahci_claim_free_slot routine */ 301#define AHCI_NON_NCQ_CMD 0x0 302#define AHCI_NCQ_CMD 0x1 303#define AHCI_ERR_RETRI_CMD 0x2 304 305/* State values for ahci_attach */ 306#define AHCI_ATTACH_STATE_NONE (0x1 << 0) 307#define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1) 308#define AHCI_ATTACH_STATE_REG_MAP (0x1 << 2) 309#define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 3) 310#define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 4) 311#define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 5) 312#define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 6) 313#define AHCI_ATTACH_STATE_ERR_RECV_TASKQ (0x1 << 7) 314#define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8) 315#define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9) 316 317/* Interval used for delay */ 318#define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 ms */ 319#define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 ms */ 320#define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 us */ 321#define AHCI_1MS_USECS (1000) /* usecs in 1 millisec */ 322 323/* 324 * The following values are the numbers of times to retry polled requests. 325 */ 326#define AHCI_POLLRATE_HBA_RESET 100 327#define AHCI_POLLRATE_PORT_SSTATUS 10 328#define AHCI_POLLRATE_PORT_TFD_ERROR 1100 329#define AHCI_POLLRATE_PORT_IDLE 50 330#define AHCI_POLLRATE_PORT_SOFTRESET 100 331#define AHCI_POLLRATE_GET_SPKT 100 332 333 334/* Clearing & setting the n'th bit in a given tag */ 335#define CLEAR_BIT(tag, bit) (tag &= ~(0x1<<bit)) 336#define SET_BIT(tag, bit) (tag |= (0x1<<bit)) 337 338 339#if DEBUG 340 341#define AHCI_DEBUG 1 342 343#define AHCIDBG_INIT 0x0001 344#define AHCIDBG_ENTRY 0x0002 345#define AHCIDBG_DUMP_PRB 0x0004 346#define AHCIDBG_EVENT 0x0008 347#define AHCIDBG_POLL_LOOP 0x0010 348#define AHCIDBG_PKTCOMP 0x0020 349#define AHCIDBG_TIMEOUT 0x0040 350#define AHCIDBG_INFO 0x0080 351#define AHCIDBG_VERBOSE 0x0100 352#define AHCIDBG_INTR 0x0200 353#define AHCIDBG_ERRS 0x0400 354#define AHCIDBG_COOKIES 0x0800 355#define AHCIDBG_POWER 0x1000 356#define AHCIDBG_COMMAND 0x2000 357#define AHCIDBG_SENSEDATA 0x4000 358#define AHCIDBG_NCQ 0x8000 359#define AHCIDBG_PM 0x10000 360 361extern int ahci_debug_flag; 362 363#define AHCIDBG0(flag, ahci_ctlp, format) \ 364 if (ahci_debug_flags & (flag)) { \ 365 ahci_log(ahci_ctlp, CE_WARN, format); \ 366 } 367 368#define AHCIDBG1(flag, ahci_ctlp, format, arg1) \ 369 if (ahci_debug_flags & (flag)) { \ 370 ahci_log(ahci_ctlp, CE_WARN, format, arg1); \ 371 } 372 373#define AHCIDBG2(flag, ahci_ctlp, format, arg1, arg2) \ 374 if (ahci_debug_flags & (flag)) { \ 375 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2); \ 376 } 377 378#define AHCIDBG3(flag, ahci_ctlp, format, arg1, arg2, arg3) \ 379 if (ahci_debug_flags & (flag)) { \ 380 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, arg3); \ 381 } 382 383#define AHCIDBG4(flag, ahci_ctlp, format, arg1, arg2, arg3, arg4) \ 384 if (ahci_debug_flags & (flag)) { \ 385 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, arg3, arg4); \ 386 } 387 388#define AHCIDBG5(flag, ahci_ctlp, format, arg1, arg2, arg3, arg4, arg5) \ 389 if (ahci_debug_flags & (flag)) { \ 390 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, \ 391 arg3, arg4, arg5); \ 392 } 393#else 394 395#define AHCIDBG0(flag, dip, frmt) 396#define AHCIDBG1(flag, dip, frmt, arg1) 397#define AHCIDBG2(flag, dip, frmt, arg1, arg2) 398#define AHCIDBG3(flag, dip, frmt, arg1, arg2, arg3) 399#define AHCIDBG4(flag, dip, frmt, arg1, arg2, arg3, arg4) 400#define AHCIDBG5(flag, dip, frmt, arg1, arg2, arg3, arg4, arg5) 401 402#endif /* DEBUG */ 403 404 405#ifdef __cplusplus 406} 407#endif 408 409#endif /* _AHCIVAR_H */ 410