ahcivar.h revision 3333:88329a0ff1be
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28#ifndef _AHCIVAR_H 29#define _AHCIVAR_H 30 31#pragma ident "%Z%%M% %I% %E% SMI" 32 33#ifdef __cplusplus 34extern "C" { 35#endif 36 37typedef struct ahci_port { 38 /* The physical port number - for debug message */ 39 uint8_t ahciport_port_num; 40 /* Type of the device attached to the port */ 41 uint8_t ahciport_device_type; 42 /* State of the port */ 43 uint32_t ahciport_port_state; 44 /* Only used for staggered spin-up */ 45 int ahciport_flags; 46 47 /* Pointer to received FIS structure */ 48 ahci_rcvd_fis_t *ahciport_rcvd_fis; 49 ddi_dma_handle_t ahciport_rcvd_fis_dma_handle; 50 ddi_acc_handle_t ahciport_rcvd_fis_acc_handle; 51 52 /* Pointer to command list structure */ 53 ahci_cmd_header_t *ahciport_cmd_list; 54 ddi_dma_handle_t ahciport_cmd_list_dma_handle; 55 ddi_acc_handle_t ahciport_cmd_list_acc_handle; 56 57 /* Pointer to cmmand table structure */ 58 ahci_cmd_table_t \ 59 *ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS]; 60 ddi_dma_handle_t \ 61 ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS]; 62 ddi_acc_handle_t \ 63 ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS]; 64 65 kmutex_t ahciport_mutex; 66 uint32_t ahciport_pending_tags; 67 sata_pkt_t *ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS]; 68 69 /* 70 * SATA HBA driver is supposed to remember and maintain device 71 * reset state. While the reset is in progress, it doesn't accept 72 * any more commands until receiving the command with 73 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE. 74 */ 75 int ahciport_reset_in_progress; 76 77} ahci_port_t; 78 79/* Warlock annotation */ 80_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle)) 81_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle)) 82_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle)) 83_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 84 ahci_port_t::ahciport_device_type)) 85_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 86 ahci_port_t::ahciport_port_state)) 87_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 88 ahci_port_t::ahciport_flags)) 89_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 90 ahci_port_t::ahciport_pending_tags)) 91_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 92 ahci_port_t::ahciport_slot_pkts)) 93_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 94 ahci_port_t::ahciport_reset_in_progress)) 95 96typedef struct ahci_ctl { 97 dev_info_t *ahcictl_dip; 98 /* To map port number to cport number */ 99 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS]; 100 /* To map cport number to port number */ 101 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS]; 102 103 /* Number of controller ports */ 104 int ahcictl_num_ports; 105 /* Number of command slots */ 106 int ahcictl_num_cmd_slots; 107 /* Number of implemented ports */ 108 int ahcictl_num_implemented_ports; 109 /* Bit map to indicate which port is implemented */ 110 uint32_t ahcictl_ports_implemented; 111 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS]; 112 113 int ahcictl_flags; 114 int ahcictl_power_level; 115 off_t ahcictl_pmcsr_offset; 116 117 /* Pci configuration space handle */ 118 ddi_acc_handle_t ahcictl_pci_conf_handle; 119 120 /* Mapping into bar 5 - AHCI base address */ 121 ddi_acc_handle_t ahcictl_ahci_acc_handle; 122 uintptr_t ahcictl_ahci_addr; 123 124 /* Pointer used for sata hba framework registration */ 125 struct sata_hba_tran *ahcictl_sata_hba_tran; 126 127 /* DMA attributes for the data buffer */ 128 ddi_dma_attr_t ahcictl_buffer_dma_attr; 129 /* DMA attributes for the rcvd FIS */ 130 ddi_dma_attr_t ahcictl_rcvd_fis_dma_attr; 131 /* DMA attributes for the command list */ 132 ddi_dma_attr_t ahcictl_cmd_list_dma_attr; 133 /* DMA attributes for command tables */ 134 ddi_dma_attr_t ahcictl_cmd_table_dma_attr; 135 136 /* Used for watchdog handler */ 137 timeout_id_t ahcictl_timeout_id; 138 139 /* Per controller mutex */ 140 kmutex_t ahcictl_mutex; 141 142 /* Components for interrupt */ 143 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */ 144 int ahcictl_intr_type; /* What type of interrupt */ 145 int ahcictl_intr_cnt; /* # of intrs returned */ 146 size_t ahcictl_intr_size; /* Size of intr array */ 147 uint_t ahcictl_intr_pri; /* Intr priority */ 148 int ahcictl_intr_cap; /* Intr capabilities */ 149} ahci_ctl_t; 150 151/* Warlock annotation */ 152_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports)) 153_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port)) 154_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport)) 155 156_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 157 ahci_ctl_t::ahcictl_power_level)) 158_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 159 ahci_ctl_t::ahcictl_flags)) 160_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 161 ahci_ctl_t::ahcictl_timeout_id)) 162 163#define AHCI_SUCCESS (0) /* Successful return */ 164#define AHCI_TIMEOUT (1) /* Timed out */ 165#define AHCI_FAILURE (-1) /* Unsuccessful return */ 166 167/* Port flags */ 168#define AHCI_PORT_STATE_SPINUP 0x1 169#define AHCI_PORT_STATE_MOPPING 0x2 170 171/* Flags for ahcictl_flags */ 172#define AHCI_PM 0x1 173#define AHCI_ATTACH 0x2 174#define AHCI_DETACH 0x4 175/* PIO Multiple DRQ Block */ 176#define AHCI_PMD 0x8 177 178 179/* Flags controlling the reset behavior */ 180#define AHCI_PORT_RESET 0x0001 /* Reset the port */ 181#define AHCI_PORT_INIT 0x0002 /* Initialize port */ 182#define AHCI_RESET_NO_EVENTS_UP 0x0004 /* Don't send reset events up */ 183 184 185/* State values for ahci_attach */ 186#define AHCI_ATTACH_STATE_NONE (0x1 << 0) 187#define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1) 188#define AHCI_ATTACH_STATE_REG_MAP (0x1 << 2) 189#define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 3) 190#define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 4) 191#define AHCI_ATTACH_STATE_HW_INIT (0x1 << 5) 192#define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 6) 193 194/* Interval used for delay */ 195#define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 millisec */ 196#define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 millisec */ 197#define AHCI_1MS_USECS (1000) /* usecs in 1 millisec */ 198 199/* 200 * The following values are the numbers of times to retry polled requests. 201 */ 202#define AHCI_POLLRATE_HBA_RESET 100 203#define AHCI_POLLRATE_PORT_COMRESET 10 204#define AHCI_POLLRATE_PORT_SSTATUS 10 205#define AHCI_POLLRATE_PORT_TFD_BSY 1100 206#define AHCI_POLLRATE_PORT_TFD_ERROR 10 207#define AHCI_POLLRATE_PORT_IDLE 50 208#define AHCI_POLLRATE_PORT_SOFTRESET 100 209 210 211/* Clearing & setting the n'th bit in a given tag */ 212#define CLEAR_BIT(tag, bit) (tag &= ~(0x1<<bit)) 213#define SET_BIT(tag, bit) (tag |= (0x1<<bit)) 214 215 216#if DEBUG 217 218#define AHCI_DEBUG 1 219 220#define AHCIDBG_INIT 0x0001 221#define AHCIDBG_ENTRY 0x0002 222#define AHCIDBG_DUMP_PRB 0x0004 223#define AHCIDBG_EVENT 0x0008 224#define AHCIDBG_POLL_LOOP 0x0010 225#define AHCIDBG_PKTCOMP 0x0020 226#define AHCIDBG_TIMEOUT 0x0040 227#define AHCIDBG_INFO 0x0080 228#define AHCIDBG_VERBOSE 0x0100 229#define AHCIDBG_INTR 0x0200 230#define AHCIDBG_ERRS 0x0400 231#define AHCIDBG_COOKIES 0x0800 232#define AHCIDBG_POWER 0x1000 233 234extern int ahci_debug_flag; 235 236#define AHCIDBG0(flag, ahci_ctlp, format) \ 237 if (ahci_debug_flags & (flag)) { \ 238 ahci_log(ahci_ctlp, CE_WARN, format); \ 239 } 240 241#define AHCIDBG1(flag, ahci_ctlp, format, arg1) \ 242 if (ahci_debug_flags & (flag)) { \ 243 ahci_log(ahci_ctlp, CE_WARN, format, arg1); \ 244 } 245 246#define AHCIDBG2(flag, ahci_ctlp, format, arg1, arg2) \ 247 if (ahci_debug_flags & (flag)) { \ 248 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2); \ 249 } 250 251#define AHCIDBG3(flag, ahci_ctlp, format, arg1, arg2, arg3) \ 252 if (ahci_debug_flags & (flag)) { \ 253 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, arg3); \ 254 } 255 256#define AHCIDBG4(flag, ahci_ctlp, format, arg1, arg2, arg3, arg4) \ 257 if (ahci_debug_flags & (flag)) { \ 258 ahci_log(ahci_ctlp, CE_WARN, format, arg1, arg2, arg3, arg4); \ 259 } 260 261#else 262 263#define AHCIDBG0(flag, dip, frmt) 264#define AHCIDBG1(flag, dip, frmt, arg1) 265#define AHCIDBG2(flag, dip, frmt, arg1, arg2) 266#define AHCIDBG3(flag, dip, frmt, arg1, arg2, arg3) 267#define AHCIDBG4(flag, dip, frmt, arg1, arg2, arg3, arg4) 268 269#endif /* DEBUG */ 270 271 272#ifdef __cplusplus 273} 274#endif 275 276#endif /* _AHCIVAR_H */ 277