ahcivar.h revision 12548:026ee4e02773
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 27#ifndef _AHCIVAR_H 28#define _AHCIVAR_H 29 30#ifdef __cplusplus 31extern "C" { 32#endif 33 34/* 35 * AHCI address qualifier flags (in qual field of ahci_addr struct). 36 */ 37#define AHCI_ADDR_NULL 0x00 38#define AHCI_ADDR_PORT 0x01 39#define AHCI_ADDR_PMPORT 0x02 40#define AHCI_ADDR_PMULT 0x04 41#define AHCI_ADDR_VALID (AHCI_ADDR_PORT | \ 42 AHCI_ADDR_PMULT | \ 43 AHCI_ADDR_PMPORT) 44 45/* 46 * AHCI address structure. 47 */ 48struct ahci_addr { 49 50 /* HBA port number */ 51 uint8_t aa_port; 52 53 /* Port multiplier port number */ 54 uint8_t aa_pmport; 55 56 /* 57 * AHCI_ADDR_NULL 58 * AHCI_ADDR_PORT 59 * AHCI_ADDR_PMPORT 60 * AHCI_ADDR_PMULT 61 */ 62 uint8_t aa_qual; 63}; 64typedef struct ahci_addr ahci_addr_t; 65 66_NOTE(SCHEME_PROTECTS_DATA("unshared data", ahci_addr)) 67 68#define AHCI_ADDR_IS_PORT(addrp) \ 69 ((addrp)->aa_qual & AHCI_ADDR_PORT) 70#define AHCI_ADDR_IS_PMPORT(addrp) \ 71 ((addrp)->aa_qual & AHCI_ADDR_PMPORT) 72#define AHCI_ADDR_IS_PMULT(addrp) \ 73 ((addrp)->aa_qual & AHCI_ADDR_PMULT) 74#define AHCI_ADDR_IS_VALID(addrp) \ 75 ((addrp)->aa_port < SATA_MAX_CPORTS) && \ 76 ((addrp)->aa_pmport < SATA_MAX_PMPORTS) && \ 77 ((addrp)->aa_qual & AHCI_ADDR_VALID) 78 79#define AHCI_ADDR_SET(addrp, port, pmport, qual) \ 80 { \ 81 (addrp)->aa_port = port; \ 82 (addrp)->aa_pmport = pmport; \ 83 (addrp)->aa_qual = qual; \ 84 } 85#define AHCI_ADDR_SET_PORT(addrp, port) \ 86 AHCI_ADDR_SET(addrp, port, 0, AHCI_ADDR_PORT) 87#define AHCI_ADDR_SET_PMPORT(addrp, port, pmport) \ 88 AHCI_ADDR_SET(addrp, port, pmport, AHCI_ADDR_PMPORT) 89#define AHCI_ADDR_SET_PMULT(addrp, port) \ 90 AHCI_ADDR_SET(addrp, port, SATA_PMULT_HOSTPORT, AHCI_ADDR_PMULT) 91 92/* Type for argument of event handler */ 93typedef struct ahci_event_arg { 94 void *ahciea_ctlp; 95 void *ahciea_portp; 96 void *ahciea_addrp; 97 uint32_t ahciea_event; 98} ahci_event_arg_t; 99 100/* Warlock annotation */ 101_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_ctlp)) 102_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_portp)) 103_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_addrp)) 104_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_event)) 105 106 107/* 108 * ahci_pmult_info stores the information of a port multiplier and its 109 * sub-devices in case a port multiplier is attached to an HBA port. 110 */ 111struct ahci_pmult_info { 112 113 /* Number of the device ports */ 114 int ahcipmi_num_dev_ports; 115 116 /* Device type of the sub-devices of the port multipler */ 117 uint8_t ahcipmi_device_type[SATA_MAX_PMPORTS]; 118 119 /* State of port multiplier port */ 120 uint32_t ahcipmi_port_state[SATA_MAX_PMPORTS]; 121 122 /* 123 * Port multiplier port on which there is outstanding NCQ 124 * commands. Only make sense in command based switching mode. 125 */ 126 uint8_t ahcipmi_ncq_pmport; 127 128 /* Pending asynchronous notification events tags */ 129 uint32_t ahcipmi_snotif_tags; 130}; 131typedef struct ahci_pmult_info ahci_pmult_info_t; 132 133/* 134 * flags for ahciport_flags 135 * 136 * AHCI_PORT_FLAG_SPINUP: this flag will be set when a HBA which supports 137 * staggered spin-up needs to do a spin-up. 138 * 139 * AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped, 140 * and all the outstanding commands need to be aborted and sent to upper 141 * layers. 142 * 143 * AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is 144 * disabled, and the command is executed in POLLING mode. 145 * 146 * AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which 147 * is used to retrieve sense data is being executed. 148 * 149 * AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started, 150 * that is PxCMD.ST is set with '1', and be cleared when the port is put into 151 * idle, that is PxCMD.ST is changed from '1' to '0'. 152 * 153 * AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which 154 * is used to retrieve NCQ failure context is being executed. 155 * 156 * AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone 157 * during ahci_restart_port_wait_till_ready process. 158 * 159 * AHCI_PORT_FLAG_RDWR_PMULT: this flags will be set when a READ/WRITE 160 * PORTMULT command is being executed. 161 * 162 * AHCI_PORT_FLAG_IGNORE_IPMS: this flags will be set when enumerating a port 163 * multiplier. According AHCI spec, IPMS error should be ignore during 164 * enumeration of port multiplier. 165 * 166 * AHCI_PORT_FLAG_PMULT_SNTF: this flags will be set when the a asynchronous 167 * notification event on the port multiplier is being handled. 168 * 169 * AHCI_PORT_FLAG_HOTPLUG: this flags will be set when a hot plug event is 170 * being handled. 171 */ 172#define AHCI_PORT_FLAG_SPINUP 0x01 173#define AHCI_PORT_FLAG_MOPPING 0x02 174#define AHCI_PORT_FLAG_POLLING 0x04 175#define AHCI_PORT_FLAG_RQSENSE 0x08 176#define AHCI_PORT_FLAG_STARTED 0x10 177#define AHCI_PORT_FLAG_RDLOGEXT 0x20 178#define AHCI_PORT_FLAG_NODEV 0x40 179#define AHCI_PORT_FLAG_RDWR_PMULT 0x80 180#define AHCI_PORT_FLAG_IGNORE_IPMS 0x100 181#define AHCI_PORT_FLAG_PMULT_SNTF 0x200 182#define AHCI_PORT_FLAG_HOTPLUG 0x400 183 184typedef struct ahci_port { 185 /* The physical port number */ 186 uint8_t ahciport_port_num; 187 188 /* Type of the device attached to the port */ 189 uint8_t ahciport_device_type; 190 /* State of the port */ 191 uint32_t ahciport_port_state; 192 193 /* Port multiplier struct */ 194 ahci_pmult_info_t *ahciport_pmult_info; 195 196 /* 197 * AHCI_PORT_FLAG_SPINUP 198 * AHCI_PORT_FLAG_MOPPING 199 * AHCI_PORT_FLAG_POLLING 200 * AHCI_PORT_FLAG_RQSENSE 201 * AHCI_PORT_FLAG_STARTED 202 * AHCI_PORT_FLAG_RDLOGEXT 203 * AHCI_PORT_FLAG_NODEV 204 * AHCI_PORT_FLAG_RDWR_PMULT 205 * AHCI_PORT_FLAG_IGNORE_IPMS 206 * AHCI_PORT_FLAG_PMULT_SNTF 207 * AHCI_PORT_FLAG_HOTPLUG 208 */ 209 int ahciport_flags; 210 211 /* Pointer to received FIS structure */ 212 ahci_rcvd_fis_t *ahciport_rcvd_fis; 213 ddi_dma_handle_t ahciport_rcvd_fis_dma_handle; 214 ddi_acc_handle_t ahciport_rcvd_fis_acc_handle; 215 ddi_dma_cookie_t ahciport_rcvd_fis_dma_cookie; 216 217 /* Pointer to command list structure */ 218 ahci_cmd_header_t *ahciport_cmd_list; 219 ddi_dma_handle_t ahciport_cmd_list_dma_handle; 220 ddi_acc_handle_t ahciport_cmd_list_acc_handle; 221 ddi_dma_cookie_t ahciport_cmd_list_dma_cookie; 222 223 /* Pointer to cmmand table structure */ 224 ahci_cmd_table_t \ 225 *ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS]; 226 ddi_dma_handle_t \ 227 ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS]; 228 ddi_acc_handle_t \ 229 ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS]; 230 231 /* Condition variable used for sync mode commands */ 232 kcondvar_t ahciport_cv; 233 234 /* The whole mutex for the port structure */ 235 kmutex_t ahciport_mutex; 236 237 /* The maximum number of tags for native queuing command transfers */ 238 int ahciport_max_ncq_tags; 239 240 /* Keep the tags of all pending non-ncq commands */ 241 uint32_t ahciport_pending_tags; 242 243 /* 244 * Keep the tags of all pending ncq commands 245 * (READ/WRITE FPDMA QUEUED) 246 */ 247 uint32_t ahciport_pending_ncq_tags; 248 249 /* Keep all the pending sata packets */ 250 sata_pkt_t *ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS]; 251 252 /* Keep the byte count of all PRD entries for every sata packet */ 253 uint32_t \ 254 ahciport_prd_bytecounts[AHCI_PORT_MAX_CMD_SLOTS]; 255 256 /* Keep the error retrieval sata packet */ 257 sata_pkt_t *ahciport_err_retri_pkt; 258 259 /* Keep the read/write port multiplier packet */ 260 sata_pkt_t *ahciport_rdwr_pmult_pkt; 261 262 /* 263 * SATA HBA driver is supposed to remember and maintain device 264 * reset state. While the reset is in progress, it doesn't accept 265 * any more commands until receiving the command with 266 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE. 267 */ 268 int ahciport_reset_in_progress; 269 270 /* Taskq for handling event */ 271 ddi_taskq_t *ahciport_event_taskq; 272 273 /* This is for error recovery handler */ 274 ahci_event_arg_t *ahciport_event_args; 275 276 /* This is to calculate how many mops are in progress */ 277 int ahciport_mop_in_progress; 278} ahci_port_t; 279 280/* Warlock annotation */ 281_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle)) 282_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle)) 283_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle)) 284_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 285 ahci_port_t::ahciport_device_type)) 286_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 287 ahci_port_t::ahciport_port_state)) 288_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 289 ahci_port_t::ahciport_flags)) 290_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 291 ahci_port_t::ahciport_pending_tags)) 292_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 293 ahci_port_t::ahciport_slot_pkts)) 294_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 295 ahci_port_t::ahciport_reset_in_progress)) 296_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 297 ahci_port_t::ahciport_mop_in_progress)) 298_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 299 ahci_port_t::ahciport_event_taskq)) 300 301#define AHCI_NUM_PORTS(ctlp) \ 302 (ctlp)->ahcictl_num_ports 303 304#define AHCIPORT_NUM_PMPORTS(portp) \ 305 (portp)->ahciport_pmult_info->ahcipmi_num_dev_ports 306 307#define AHCIPORT_NCQ_PMPORT(ahci_portp) \ 308 (ahci_portp->ahciport_pmult_info->ahcipmi_ncq_pmport) 309 310#define AHCIPORT_DEV_TYPE(portp, addrp) \ 311 (portp)->ahciport_device_type 312 313#define AHCIPORT_PMDEV_TYPE(portp, addrp) \ 314 (portp)->ahciport_pmult_info->ahcipmi_device_type \ 315 [(addrp)->aa_pmport] 316 317#define AHCIPORT_GET_DEV_TYPE(portp, addrp) \ 318 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \ 319 AHCIPORT_DEV_TYPE(portp, addrp) : \ 320 AHCIPORT_PMDEV_TYPE(portp, addrp)) 321 322#define AHCIPORT_SET_DEV_TYPE(portp, addrp, type) \ 323 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \ 324 AHCIPORT_DEV_TYPE(portp, addrp) = type; \ 325 else \ 326 AHCIPORT_PMDEV_TYPE(portp, addrp) = type; 327 328#define AHCIPORT_STATE(portp, addrp) \ 329 (portp)->ahciport_port_state 330 331#define AHCIPORT_PMSTATE(portp, addrp) \ 332 (portp)->ahciport_pmult_info->ahcipmi_port_state \ 333 [(addrp)->aa_pmport] 334 335#define AHCIPORT_GET_STATE(portp, addrp) \ 336 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \ 337 AHCIPORT_STATE(portp, addrp) : AHCIPORT_PMSTATE(portp, addrp)) 338 339#define AHCIPORT_SET_STATE(portp, addrp, state) \ 340 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \ 341 AHCIPORT_STATE(portp, addrp) = state; \ 342 else \ 343 AHCIPORT_PMSTATE(portp, addrp) = state; 344 345typedef struct ahci_ctl { 346 dev_info_t *ahcictl_dip; 347 348 ushort_t ahcictl_venid; 349 ushort_t ahcictl_devid; 350 351 /* To map port number to cport number */ 352 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS]; 353 /* To map cport number to port number */ 354 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS]; 355 356 /* Number of controller ports */ 357 int ahcictl_num_ports; 358 /* Number of command slots */ 359 int ahcictl_num_cmd_slots; 360 /* Number of implemented ports */ 361 int ahcictl_num_implemented_ports; 362 /* Bit map to indicate which port is implemented */ 363 uint32_t ahcictl_ports_implemented; 364 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS]; 365 366 int ahcictl_flags; 367 int ahcictl_power_level; 368 off_t ahcictl_pmcsr_offset; 369 370 /* 371 * AHCI_CAP_PIO_MDRQ 372 * AHCI_CAP_NO_MCMDLIST_NONQUEUE 373 * AHCI_CAP_NCQ 374 * AHCI_CAP_PM 375 * AHCI_CAP_BUF_32BIT_DMA 376 * AHCI_CAP_SCLO 377 * AHCI_CAP_COMMU_32BIT_DMA 378 * AHCI_CAP_INIT_PORT_RESET 379 * AHCI_CAP_SNTF 380 * AHCI_CAP_PMULT_CBSS 381 * AHCI_CAP_PMULT_FBSS 382 * AHCI_CAP_SRST_NO_HOSTPORT 383 */ 384 int ahcictl_cap; 385 386 /* Pci configuration space handle */ 387 ddi_acc_handle_t ahcictl_pci_conf_handle; 388 389 /* Mapping into bar 5 - AHCI base address */ 390 ddi_acc_handle_t ahcictl_ahci_acc_handle; 391 uintptr_t ahcictl_ahci_addr; 392 393 /* Pointer used for sata hba framework registration */ 394 struct sata_hba_tran *ahcictl_sata_hba_tran; 395 396 /* DMA attributes for the data buffer */ 397 ddi_dma_attr_t ahcictl_buffer_dma_attr; 398 /* DMA attributes for the rcvd FIS */ 399 ddi_dma_attr_t ahcictl_rcvd_fis_dma_attr; 400 /* DMA attributes for the command list */ 401 ddi_dma_attr_t ahcictl_cmd_list_dma_attr; 402 /* DMA attributes for command tables */ 403 ddi_dma_attr_t ahcictl_cmd_table_dma_attr; 404 405 /* Used for watchdog handler */ 406 timeout_id_t ahcictl_timeout_id; 407 408 /* Per controller mutex */ 409 kmutex_t ahcictl_mutex; 410 411 /* Components for interrupt */ 412 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */ 413 int ahcictl_intr_type; /* What type of interrupt */ 414 int ahcictl_intr_cnt; /* # of intrs returned */ 415 size_t ahcictl_intr_size; /* Size of intr array */ 416 uint_t ahcictl_intr_pri; /* Intr priority */ 417 int ahcictl_intr_cap; /* Intr capabilities */ 418 419 /* FMA capabilities */ 420 int ahcictl_fm_cap; 421} ahci_ctl_t; 422 423/* Warlock annotation */ 424_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports)) 425_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port)) 426_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport)) 427 428_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 429 ahci_ctl_t::ahcictl_power_level)) 430_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 431 ahci_ctl_t::ahcictl_flags)) 432_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 433 ahci_ctl_t::ahcictl_timeout_id)) 434 435#define AHCI_SUCCESS (0) /* Successful return */ 436#define AHCI_TIMEOUT (1) /* Timed out */ 437#define AHCI_FAILURE (-1) /* Unsuccessful return */ 438 439/* Flags for ahcictl_flags */ 440#define AHCI_ATTACH 0x1 441#define AHCI_DETACH 0x2 442#define AHCI_SUSPEND 0x4 443 444/* Values for ahcictl_cap */ 445/* PIO Multiple DRQ Block */ 446#define AHCI_CAP_PIO_MDRQ 0x1 447/* 448 * Multiple command slots in the command list cannot be used for 449 * non-queued commands 450 */ 451#define AHCI_CAP_NO_MCMDLIST_NONQUEUE 0x2 452/* Native Command Queuing (NCQ) */ 453#define AHCI_CAP_NCQ 0x4 454/* Power Management (PM) */ 455#define AHCI_CAP_PM 0x8 456/* 32-bit DMA addressing for buffer block */ 457#define AHCI_CAP_BUF_32BIT_DMA 0x10 458/* Supports Command List Override */ 459#define AHCI_CAP_SCLO 0x20 460/* 32-bit DMA addressing for communication memory descriptors */ 461#define AHCI_CAP_COMMU_32BIT_DMA 0x40 462/* Port reset is needed for initialization */ 463#define AHCI_CAP_INIT_PORT_RESET 0x80 464/* Port Asychronous Notification */ 465#define AHCI_CAP_SNTF 0x100 466/* Port Multiplier Command-Based Switching Support (PMULT_CBSS) */ 467#define AHCI_CAP_PMULT_CBSS 0x200 468/* Port Multiplier FIS-Based Switching Support (PMULT_FBSS) */ 469#define AHCI_CAP_PMULT_FBSS 0x400 470/* Software Reset FIS cannot set pmport with 0xf for direct access device */ 471#define AHCI_CAP_SRST_NO_HOSTPORT 0x800 472 473/* Flags controlling the restart port behavior */ 474#define AHCI_PORT_RESET 0x0001 /* Reset the port */ 475#define AHCI_RESET_NO_EVENTS_UP 0x0002 /* Don't send reset events up */ 476 477#define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \ 478 (ahci_portp->ahciport_flags & \ 479 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT)) 480 481#define RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) \ 482 (ahci_portp->ahciport_flags & \ 483 AHCI_PORT_FLAG_RDWR_PMULT) 484 485#define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \ 486 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 487 ahci_portp->ahciport_pending_tags != 0 && \ 488 ahci_portp->ahciport_pending_ncq_tags == 0) 489 490#define NCQ_CMD_IN_PROGRESS(ahci_portp) \ 491 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 492 ahci_portp->ahciport_pending_ncq_tags != 0) 493 494/* Command type for ahci_claim_free_slot routine */ 495#define AHCI_NON_NCQ_CMD 0x0 496#define AHCI_NCQ_CMD 0x1 497#define AHCI_ERR_RETRI_CMD 0x2 498#define AHCI_RDWR_PMULT_CMD 0x4 499 500/* State values for ahci_attach */ 501#define AHCI_ATTACH_STATE_NONE (0x1 << 0) 502#define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1) 503#define AHCI_ATTACH_STATE_FMA (0x1 << 2) 504#define AHCI_ATTACH_STATE_REG_MAP (0x1 << 3) 505#define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 4) 506#define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 5) 507#define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 6) 508#define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 7) 509#define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8) 510#define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9) 511 512/* Interval used for delay */ 513#define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 ms */ 514#define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 ms */ 515#define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 us */ 516#define AHCI_10MS_USECS (10000) /* microsecs in 10 millisec */ 517#define AHCI_1MS_USECS (1000) /* microsecs in 1 millisec */ 518#define AHCI_100US_USECS (100) 519 520/* 521 * The following values are the numbers of times to retry polled requests. 522 */ 523#define AHCI_POLLRATE_HBA_RESET 100 524#define AHCI_POLLRATE_PORT_SSTATUS 10 525#define AHCI_POLLRATE_PORT_TFD_ERROR 1100 526#define AHCI_POLLRATE_PORT_IDLE 50 527#define AHCI_POLLRATE_PORT_SOFTRESET 100 528#define AHCI_POLLRATE_GET_SPKT 100 529 530 531/* Clearing & setting the n'th bit in a given tag */ 532#define CLEAR_BIT(tag, bit) (tag &= ~(0x1<<bit)) 533#define SET_BIT(tag, bit) (tag |= (0x1<<bit)) 534 535 536#if DEBUG 537 538#define AHCI_DEBUG 1 539 540#endif 541 542#define AHCIDBG_INIT 0x0001 543#define AHCIDBG_ENTRY 0x0002 544#define AHCIDBG_PRDT 0x0004 545#define AHCIDBG_EVENT 0x0008 546#define AHCIDBG_POLL_LOOP 0x0010 547#define AHCIDBG_PKTCOMP 0x0020 548#define AHCIDBG_TIMEOUT 0x0040 549#define AHCIDBG_INFO 0x0080 550#define AHCIDBG_VERBOSE 0x0100 551#define AHCIDBG_INTR 0x0200 552#define AHCIDBG_ERRS 0x0400 553#define AHCIDBG_ATACMD 0x0800 554#define AHCIDBG_ATAPICMD 0x1000 555#define AHCIDBG_SENSEDATA 0x2000 556#define AHCIDBG_NCQ 0x4000 557#define AHCIDBG_PM 0x8000 558#define AHCIDBG_UNDERFLOW 0x10000 559#define AHCIDBG_MSI 0x20000 560#define AHCIDBG_PMULT 0x40000 561 562extern uint32_t ahci_debug_flags; 563 564#if DEBUG 565 566#define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \ 567 if (ahci_debug_flags & (flag)) { \ 568 ahci_log(ahci_ctlp, CE_WARN, fmt, ## args); \ 569 if (ahci_ctlp == NULL) \ 570 sata_trace_debug(NULL, fmt, ## args); \ 571 else \ 572 sata_trace_debug(ahci_ctlp->ahcictl_dip,\ 573 fmt, ## args); \ 574 } 575 576#else 577 578#define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \ 579 if (ahci_debug_flags & (flag)) { \ 580 if (ahci_ctlp == NULL) \ 581 sata_trace_debug(NULL, fmt, ## args); \ 582 else \ 583 sata_trace_debug(ahci_ctlp->ahcictl_dip,\ 584 fmt, ## args); \ 585 } 586 587#endif /* DEBUG */ 588 589 590#ifdef __cplusplus 591} 592#endif 593 594#endif /* _AHCIVAR_H */ 595