ahcireg.h revision 8010:95c42a8a213e
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28#ifndef _AHCIREG_H 29#define _AHCIREG_H 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#define AHCI_MAX_PORTS 32 36#define AHCI_PORT_MAX_CMD_SLOTS 32 37 38#define VIA_VENID 0x1106 39 40/* 41 * In AHCI spec, command table contains a list of 0 (no data transfer) 42 * to up to 65,535 scatter/gather entries for the data transfer. 43 */ 44#define AHCI_MAX_PRDT_NUMBER 65535 45#define AHCI_MIN_PRDT_NUMBER 1 46 47/* 48 * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1 49 * if misaligned, and it's tuable by setting ahci_dma_prdt_number in 50 * /etc/system file. 51 */ 52#define AHCI_PRDT_NUMBER 257 53 54/* PCI header offset for AHCI Base Address */ 55#define AHCI_PCI_RNUM 0x24 56 57/* various global HBA capability bits */ 58#define AHCI_HBA_CAP_NP (0x1f << 0) /* number of ports */ 59#define AHCI_HBA_CAP_SXS (0x1 << 5) /* external SATA */ 60#define AHCI_HBA_CAP_EMS (0x1 << 6) /* enclosure management */ 61#define AHCI_HBA_CAP_CCCS (0x1 << 7) /* command completed coalescing */ 62#define AHCI_HBA_CAP_NCS (0x1f << 8) /* number of command slots */ 63#define AHCI_HBA_CAP_PSC (0x1 << 13) /* partial state capable */ 64#define AHCI_HBA_CAP_SSC (0x1 << 14) /* slumber state capable */ 65#define AHCI_HBA_CAP_PMD (0x1 << 15) /* PIO multiple DRQ block */ 66#define AHCI_HBA_CAP_FBSS (0x1 << 16) /* FIS-based switching */ 67#define AHCI_HBA_CAP_SPM (0x1 << 17) /* port multiplier */ 68#define AHCI_HBA_CAP_SAM (0x1 << 18) /* AHCI mode only */ 69#define AHCI_HBA_CAP_SNZO (0x1 << 19) /* non-zero DMA offsets */ 70#define AHCI_HBA_CAP_ISS (0xf << 20) /* interface speed support */ 71#define AHCI_HBA_CAP_SCLO (0x1 << 24) /* command list override */ 72#define AHCI_HBA_CAP_SAL (0x1 << 25) /* activity LED */ 73#define AHCI_HBA_CAP_SALP (0x1 << 26) /* aggressive link power mgmt */ 74#define AHCI_HBA_CAP_SSS (0x1 << 27) /* staggered spin-up */ 75#define AHCI_HBA_CAP_SMPS (0x1 << 28) /* mechanical presence switch */ 76#define AHCI_HBA_CAP_SSNTF (0x1 << 29) /* Snotification register */ 77#define AHCI_HBA_CAP_SNCQ (0x1 << 30) /* Native Command Queuing */ 78#define AHCI_HBA_CAP_S64A ((uint32_t)0x1 << 31) /* 64-bit addressing */ 79#define AHCI_HBA_CAP_NCS_SHIFT 8 /* Number of command slots */ 80#define AHCI_HBA_CAP_ISS_SHIFT 20 /* Interface speed support */ 81 82/* various global HBA control bits */ 83#define AHCI_HBA_GHC_HR (0x1 << 0) /* HBA Reset */ 84#define AHCI_HBA_GHC_IE (0x1 << 1) /* Interrupt Enable */ 85#define AHCI_HBA_GHC_MRSM (0x1 << 2) /* MSI Revert to Single Message */ 86#define AHCI_HBA_GHC_AE ((uint32_t)0x1 << 31) /* AHCI Enable */ 87 88/* various global HBA Command Completion Coalescing (CCC) control bits */ 89#define AHCI_HBA_CCC_CTL_EN 0x00000001 /* Enable */ 90#define AHCI_HBA_CCC_CTL_INT_MASK (0x1f << 3) /* Interrupt */ 91#define AHCI_HBA_CCC_CTL_CC_MASK 0x0000ff00 /* Command Completions */ 92#define AHCI_HBA_CCC_CTL_TV_MASK 0xffff0000 /* Timeout Value */ 93#define AHCI_HBA_CCC_CTL_INT_SHIFT 3 94#define AHCI_HBA_CCC_CTL_CC_SHIFT 8 95#define AHCI_HBA_CCC_CTL_TV_SHIFT 16 96 97/* global HBA Enclosure Management Location (EM_LOC) */ 98#define AHCI_HBA_EM_LOC_SZ_MASK 0x0000ffff /* Buffer Size */ 99#define AHCI_HBA_EM_LOC_OFST_MASK 0xffff0000 /* Offset */ 100#define AHCI_HBA_EM_LOC_OFST_SHIFT 16 101 102/* global HBA Enclosure Management Control (EM_CTL) bits */ 103#define AHCI_HBA_EM_CTL_STS_MR (0x1 << 0) /* Message Received */ 104#define AHCI_HBA_EM_CTL_CTL_TM (0x1 << 8) /* Transmit Message */ 105#define AHCI_HBA_EM_CTL_CTL_RST (0x1 << 9) /* Reset */ 106#define AHCI_HBA_EM_CTL_SUPP_LED (0x1 << 16) /* LED Message Types */ 107#define AHCI_HBA_EM_CTL_SUPP_SAFTE (0x1 << 17) /* SAF-TE EM Messages */ 108#define AHCI_HBA_EM_CTL_SUPP_SES2 (0x1 << 18) /* SES-2 EM Messages */ 109#define AHCI_HBA_EM_CTL_SUPP_SGPIO (0x1 << 19) /* SGPIO EM Messages */ 110#define AHCI_HBA_EM_CTL_ATTR_SMB (0x1 << 24) /* Single Message Buffer */ 111#define AHCI_HBA_EM_CTL_ATTR_XMT (0x1 << 25) /* Transmit Only */ 112#define AHCI_HBA_EM_CTL_ATTR_ALHD (0x1 << 26) /* Activity LED HW Driven */ 113#define AHCI_HBA_EM_CTL_ATTR_PM (0x1 << 27) /* PM Support */ 114 115 116/* global HBA registers definitions */ 117#define AHCI_GLOBAL_OFFSET(ahci_ctlp) (ahci_ctlp->ahcictl_ahci_addr) 118 /* HBA Capabilities */ 119#define AHCI_GLOBAL_CAP(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00) 120 /* Global HBA Control */ 121#define AHCI_GLOBAL_GHC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04) 122 /* Interrupt Status Register */ 123#define AHCI_GLOBAL_IS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08) 124 /* Ports Implemented */ 125#define AHCI_GLOBAL_PI(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c) 126 /* AHCI Version */ 127#define AHCI_GLOBAL_VS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10) 128 /* Command Completion Coalescing Control */ 129#define AHCI_GLOBAL_CCC_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14) 130 /* Command Completion Coalescing Ports */ 131#define AHCI_GLOBAL_CCC_PORTS(ahci_ctlp) \ 132 (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x18) 133 /* Enclosure Management Location */ 134#define AHCI_GLOBAL_EM_LOC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c) 135 /* Enclosure Management Control */ 136#define AHCI_GLOBAL_EM_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20) 137 138#define AHCI_PORT_IMPLEMENTED(ahci_ctlp, port) \ 139 ((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented) 140 141/* various port interrupt bits */ 142 /* Device to Host Register FIS Interrupt */ 143#define AHCI_INTR_STATUS_DHRS (0x1 << 0) 144 /* PIO Setup FIS Interrupt */ 145#define AHCI_INTR_STATUS_PSS (0x1 << 1) 146 /* DMA Setup FIS Interrupt */ 147#define AHCI_INTR_STATUS_DSS (0x1 << 2) 148 /* Set Device Bits Interrupt */ 149#define AHCI_INTR_STATUS_SDBS (0x1 << 3) 150 /* Unknown FIS Interrupt */ 151#define AHCI_INTR_STATUS_UFS (0x1 << 4) 152 /* Descriptor Processed */ 153#define AHCI_INTR_STATUS_DPS (0x1 << 5) 154 /* Port Connect Change Status */ 155#define AHCI_INTR_STATUS_PCS (0x1 << 6) 156 /* Device Mechanical Presence Status */ 157#define AHCI_INTR_STATUS_DMPS (0x1 << 7) 158 /* PhyRdy Change Status */ 159#define AHCI_INTR_STATUS_PRCS (0x1 << 22) 160 /* Incorrect Port Multiplier Status */ 161#define AHCI_INTR_STATUS_IPMS (0x1 << 23) 162 /* Overflow Status */ 163#define AHCI_INTR_STATUS_OFS (0x1 << 24) 164 /* Interface Non-fatal Error Status */ 165#define AHCI_INTR_STATUS_INFS (0x1 << 26) 166 /* Interface Fatal Error Status */ 167#define AHCI_INTR_STATUS_IFS (0x1 << 27) 168 /* Host Bus Data Error Status */ 169#define AHCI_INTR_STATUS_HBDS (0x1 << 28) 170 /* Host Bus Fatal Error Status */ 171#define AHCI_INTR_STATUS_HBFS (0x1 << 29) 172 /* Task File Error Status */ 173#define AHCI_INTR_STATUS_TFES (0x1 << 30) 174 /* Cold Port Detect Status */ 175#define AHCI_INTR_STATUS_CPDS ((uint32_t)0x1 << 31) 176#define AHCI_PORT_INTR_MASK 0xfec000ff 177 178/* port command and status bits */ 179#define AHCI_CMD_STATUS_ST (0x1 << 0) /* Start */ 180#define AHCI_CMD_STATUS_SUD (0x1 << 1) /* Spin-up device */ 181#define AHCI_CMD_STATUS_POD (0x1 << 2) /* Power on device */ 182#define AHCI_CMD_STATUS_CLO (0x1 << 3) /* Command list override */ 183#define AHCI_CMD_STATUS_FRE (0x1 << 4) /* FIS receive enable */ 184#define AHCI_CMD_STATUS_CCS (0x1f << 8) /* Current command slot */ 185 /* Mechanical presence switch state */ 186#define AHCI_CMD_STATUS_MPSS (0x1 << 13) 187#define AHCI_CMD_STATUS_FR (0x1 << 14) /* FIS receiving running */ 188#define AHCI_CMD_STATUS_CR (0x1 << 15) /* Command list running */ 189#define AHCI_CMD_STATUS_CPS (0x1 << 16) /* Cold presence state */ 190#define AHCI_CMD_STATUS_PMA (0x1 << 17) /* Port multiplier attached */ 191#define AHCI_CMD_STATUS_HPCP (0x1 << 18) /* Hot plug capable port */ 192 /* Mechanical presence switch attached to port */ 193#define AHCI_CMD_STATUS_MPSP (0x1 << 19) 194#define AHCI_CMD_STATUS_CPD (0x1 << 20) /* Cold presence detection */ 195#define AHCI_CMD_STATUS_ESP (0x1 << 21) /* External SATA port */ 196#define AHCI_CMD_STATUS_ATAPI (0x1 << 24) /* Device is ATAPI */ 197#define AHCI_CMD_STATUS_DLAE (0x1 << 25) /* Drive LED on ATAPI enable */ 198 /* Aggressive link power magament enable */ 199#define AHCI_CMD_STATUS_ALPE (0x1 << 26) 200#define AHCI_CMD_STATUS_ASP (0x1 << 27) /* Aggressive slumber/partial */ 201 /* Interface communication control */ 202#define AHCI_CMD_STATUS_ICC (0xf << 28) 203#define AHCI_CMD_STATUS_CCS_SHIFT 8 204#define AHCI_CMD_STATUS_ICC_SHIFT 28 205 206/* port task file data bits */ 207#define AHCI_TFD_STS_MASK 0x000000ff 208#define AHCI_TFD_ERR_MASK 0x0000ff00 209#define AHCI_TFD_STS_BSY (0x1 << 7) 210#define AHCI_TFD_STS_DRQ (0x1 << 3) 211#define AHCI_TFD_STS_ERR (0x1 << 0) 212#define AHCI_TFD_ERR_SHIFT 8 213 214#define AHCI_SERROR_CLEAR_ALL 0xffffffff 215 216/* per port registers offset */ 217#define AHCI_PORT_OFFSET(ahci_ctlp, port) \ 218 (ahci_ctlp->ahcictl_ahci_addr + (0x100 + (port * 0x80))) 219 /* Command List Base Address */ 220#define AHCI_PORT_PxCLB(ahci_ctlp, port) \ 221 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x00) 222 /* Command List Base Address Upper 32-Bits */ 223#define AHCI_PORT_PxCLBU(ahci_ctlp, port) \ 224 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x04) 225 /* FIS Base Address */ 226#define AHCI_PORT_PxFB(ahci_ctlp, port) \ 227 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x08) 228 /* FIS Base Address Upper 32-Bits */ 229#define AHCI_PORT_PxFBU(ahci_ctlp, port) \ 230 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x0c) 231 /* Interrupt Status */ 232#define AHCI_PORT_PxIS(ahci_ctlp, port) \ 233 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x10) 234 /* Interrupt Enable */ 235#define AHCI_PORT_PxIE(ahci_ctlp, port) \ 236 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x14) 237 /* Command and Status */ 238#define AHCI_PORT_PxCMD(ahci_ctlp, port) \ 239 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x18) 240 /* Task File Data */ 241#define AHCI_PORT_PxTFD(ahci_ctlp, port) \ 242 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x20) 243 /* Signature */ 244#define AHCI_PORT_PxSIG(ahci_ctlp, port) \ 245 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x24) 246 /* Serial ATA Status (SCR0:SStatus) */ 247#define AHCI_PORT_PxSSTS(ahci_ctlp, port) \ 248 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x28) 249 /* Serial ATA Control (SCR2:SControl) */ 250#define AHCI_PORT_PxSCTL(ahci_ctlp, port) \ 251 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x2c) 252 /* Serial ATA Error (SCR1:SError) */ 253#define AHCI_PORT_PxSERR(ahci_ctlp, port) \ 254 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x30) 255 /* Serial ATA Active (SCR3:SActive) */ 256#define AHCI_PORT_PxSACT(ahci_ctlp, port) \ 257 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x34) 258 /* Command Issue */ 259#define AHCI_PORT_PxCI(ahci_ctlp, port) \ 260 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x38) 261 /* SNotification */ 262#define AHCI_PORT_PxSNTF(ahci_ctlp, port) \ 263 (AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x3c) 264 265#define AHCI_SLOT_MASK(ahci_ctlp) \ 266 ((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \ 267 0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1)) 268#define AHCI_NCQ_SLOT_MASK(ahci_portp) \ 269 ((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \ 270 0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1)) 271 272/* Device signatures */ 273#define AHCI_SIGNATURE_PORT_MULTIPLIER 0x96690101 274#define AHCI_SIGNATURE_ATAPI 0xeb140101 275#define AHCI_SIGNATURE_DISK 0x00000101 276 277/* 278 * The address of the control port for the port multiplier, which is 279 * used for control and status communication with the port multiplier 280 * itself. 281 */ 282#define AHCI_PORTMULT_CONTROL_PORT 0x0f 283 284#define AHCI_H2D_REGISTER_FIS_TYPE 0x27 285#define AHCI_H2D_REGISTER_FIS_LENGTH 5 286 287#define AHCI_CMDHEAD_ATAPI 0x1 /* set to 1 for ATAPI command */ 288#define AHCI_CMDHEAD_DATA_WRITE 0x1 /* From system memory to device */ 289#define AHCI_CMDHEAD_DATA_READ 0x0 /* From device to system memory */ 290#define AHCI_CMDHEAD_PREFETCHABLE 0x1 /* if set, HBA prefetch PRDs */ 291 292/* Register - Host to Device FIS (from SATA spec) */ 293typedef struct ahci_fis_h2d_register { 294 /* offset 0x00 */ 295 uint32_t ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features; 296 297#define SET_FIS_TYPE(fis, type) \ 298 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff)) 299 300#define SET_FIS_PMP(fis, pmp) \ 301 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 302 ((pmp & 0xf) << 8)) 303 304#define SET_FIS_CDMDEVCTL(fis, cmddevctl) \ 305 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 306 ((cmddevctl & 0x1) << 15)) 307 308#define GET_FIS_COMMAND(fis) \ 309 ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff) 310 311#define SET_FIS_COMMAND(fis, command) \ 312 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 313 ((command & 0xff) << 16)) 314 315#define GET_FIS_FEATURES(fis) \ 316 ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff) 317 318#define SET_FIS_FEATURES(fis, features) \ 319 (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= \ 320 ((features & 0xff) << 24)) 321 322 /* offset 0x04 */ 323 uint32_t ahcifhr_sector_cyllow_cylhi_devhead; 324 325#define GET_FIS_SECTOR(fis) \ 326 (fis->ahcifhr_sector_cyllow_cylhi_devhead & 0xff) 327 328#define SET_FIS_SECTOR(fis, sector) \ 329 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff))) 330 331#define GET_FIS_CYL_LOW(fis) \ 332 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 8) & 0xff) 333 334#define SET_FIS_CYL_LOW(fis, cyl_low) \ 335 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8)) 336 337#define GET_FIS_CYL_HI(fis) \ 338 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff) 339 340#define SET_FIS_CYL_HI(fis, cyl_hi) \ 341 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16)) 342 343#define GET_FIS_DEV_HEAD(fis) \ 344 ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff) 345 346#define SET_FIS_DEV_HEAD(fis, dev_head) \ 347 (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24)) 348 349 /* offset 0x08 */ 350 uint32_t ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp; 351 352#define GET_FIS_SECTOR_EXP(fis) \ 353 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp & 0xff) 354 355#define SET_FIS_SECTOR_EXP(fis, sectorexp) \ 356 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 357 ((sectorexp & 0xff))) 358 359#define GET_FIS_CYL_LOW_EXP(fis) \ 360 ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff) 361 362#define SET_FIS_CYL_LOW_EXP(fis, cyllowexp) \ 363 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 364 ((cyllowexp & 0xff) << 8)) 365 366#define GET_FIS_CYL_HI_EXP(fis) \ 367 ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff) 368 369#define SET_FIS_CYL_HI_EXP(fis, cylhiexp) \ 370 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 371 ((cylhiexp & 0xff) << 16)) 372 373#define SET_FIS_FEATURES_EXP(fis, features_exp) \ 374 (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \ 375 ((features_exp & 0xff) << 24)) 376 377 /* offset 0x0c */ 378 uint32_t ahcifhr_sectcount_sectcountexp_rsvd_devctl; 379 380#define GET_FIS_SECTOR_COUNT(fis) \ 381 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff) 382 383#define SET_FIS_SECTOR_COUNT(fis, sector_count) \ 384 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 385 ((sector_count & 0xff))) 386 387#define GET_FIS_SECTOR_COUNT_EXP(fis) \ 388 ((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff) 389 390#define SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp) \ 391 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 392 ((sector_count_exp & 0xff) << 8)) 393 394#define SET_FIS_DEVCTL(fis, devctl) \ 395 (fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= \ 396 ((devctl & 0xff) << 24)) 397 398 /* offset 0x10 */ 399 uint32_t ahcifhr_rsvd3[1]; /* should be zero */ 400} ahci_fis_h2d_register_t; 401 402/* Register - Device to Host FIS (from SATA spec) */ 403typedef struct ahci_fis_d2h_register { 404 /* offset 0x00 */ 405 uint32_t ahcifdr_type_intr_rsvd_status_error; 406 407#define GET_RFIS_STATUS(fis) \ 408 ((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff) 409 410#define GET_RFIS_ERROR(fis) \ 411 ((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff) 412 413 /* offset 0x04 */ 414 uint32_t ahcifdr_sector_cyllow_cylhi_devhead; 415 416#define GET_RFIS_CYL_LOW(fis) \ 417 (fis->ahcifdr_sector_cyllow_cylhi_devhead & 0xff) 418 419#define GET_RFIS_CYL_MID(fis) \ 420 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 8) & 0xff) 421 422#define GET_RFIS_CYL_HI(fis) \ 423 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff) 424 425#define GET_RFIS_DEV_HEAD(fis) \ 426 ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff) 427 428 /* offset 0x08 */ 429 uint32_t ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd; 430 431#define GET_RFIS_CYL_LOW_EXP(fis) \ 432 (fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd & 0xff) 433 434#define GET_RFIS_CYL_MID_EXP(fis) \ 435 ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff) 436 437#define GET_RFIS_CYL_HI_EXP(fis) \ 438 ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff) 439 440 /* offset 0x0c */ 441 uint32_t ahcifdr_sectcount_sectcountexp_rsvd; 442 443#define GET_RFIS_SECTOR_COUNT(fis) \ 444 (fis->ahcifdr_sectcount_sectcountexp_rsvd & 0xff) 445 446#define GET_RFIS_SECTOR_COUNT_EXP(fis) \ 447 ((fis->ahcifdr_sectcount_sectcountexp_rsvd >> 8) & 0xff) 448 449 /* offset 0x10 */ 450 uint32_t ahcifdr_rsvd; 451} ahci_fis_d2h_register_t; 452 453/* Set Device Bits - Device to Host FIS (from SATA spec) */ 454typedef struct ahci_fis_set_device_bits { 455 /* offset 0x00 */ 456 uint32_t ahcifsdb_type_rsvd_intr_status_error; 457 458#define GET_N_BIT_OF_SET_DEV_BITS(fis) \ 459 ((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1) 460 461 /* offset 0x04 */ 462 uint32_t ahcifsdb_rsvd; 463} ahci_fis_set_device_bits_t; 464 465/* DMA Setup - Device to Host or Host to Device (from SATA spec) */ 466typedef struct ahci_fis_dma_setup { 467 /* offset 0x00 */ 468 uint32_t ahcifds_type_rsvd_direction_intr_rsvd; 469 470 /* offset 0x04 */ 471 uint32_t ahcifds_dma_buffer_identifier_low; 472 473 /* offset 0x08 */ 474 uint32_t ahcifds_dma_buffer_identifier_high; 475 476 /* offset 0x0c */ 477 uint32_t ahcifds_rsvd1; 478 479 /* offset 0x10 */ 480 uint32_t ahcifds_dma_buffer_offset; 481 482 /* offset 0x14 */ 483 uint32_t ahcifds_dma_transfer_count; 484 485 /* offset 0x18 */ 486 uint32_t ahcifds_rsvd2; 487} ahci_fis_dma_setup_t; 488 489/* PIO Setup - Device to Host FIS (from SATA spec) */ 490typedef struct ahci_fis_pio_setup { 491 /* offset 0x00 */ 492 uint32_t ahcifps_type_rsvd_direction_intr_status_error; 493 494 /* offset 0x04 */ 495 uint32_t ahcifps_sector_cyllow_cylhi_devhead; 496 497 /* offset 0x08 */ 498 uint32_t ahcifps_sectexp_cyllowexp_cylhiexp_rsvd; 499 500 /* offset 0x0c */ 501 uint32_t ahcifps_sectcount_sectcountexp_rsvd_e_status; 502 503 /* offset 0x10 */ 504 uint32_t ahcifps_transfer_count_rsvd; 505} ahci_fis_pio_setup_t; 506 507/* BIST Active - Host to Device or Device to Host (from SATA spec) */ 508typedef struct ahci_fis_bist_active { 509 /* offset 0x00 */ 510 uint32_t ahcifba_type_rsvd_pattern_rsvd; 511 512 /* offset 0x04 */ 513 uint32_t ahcifba_data1; 514 515 /* offset 0x08 */ 516 uint32_t ahcifba_data2; 517} ahci_fis_bist_active_t; 518 519/* Up to 64 bytes */ 520typedef struct ahci_fis_unknown { 521 uint32_t ahcifu_first_dword; 522 uint32_t ahcifu_dword[15]; 523} ahci_fis_unknown_t; 524 525/* 526 * This is a software constructed FIS. For data transfer, 527 * this is the H2D Register FIS format as specified in 528 * the Serial ATA 1.0a specification. Valid Command FIS 529 * length are 2 to 16 Dwords. 530 */ 531typedef struct ahci_fis_command { 532 union { 533 ahci_fis_h2d_register_t ahcifc_h2d_register; 534 ahci_fis_bist_active_t ahcifc_bist_active; 535 } ahcifc_fis; 536 uint32_t ahcifc_rsvd3[11]; /* should be zero */ 537} ahci_fis_command_t; 538 539/* Received FISes structure - size 100h */ 540typedef struct ahci_rcvd_fis { 541 /* offset 0x00 - DMA Setup FIS */ 542 ahci_fis_dma_setup_t ahcirf_dma_setup_fis; 543 uint32_t ahcirf_fis_rsvd1; 544 545 /* offset 0x20 - PIO Setup FIS */ 546 ahci_fis_pio_setup_t ahcirf_pio_setup_fis; 547 uint32_t ahcirf_fis_rsvd2[3]; 548 549 /* offset 0x40 - D2H Register FIS */ 550 ahci_fis_d2h_register_t ahcirf_d2h_register_fis; 551 uint32_t ahcirf_fis_rsvd3; 552 553 /* offset 0x58 - Set Device Bits FIS */ 554 ahci_fis_set_device_bits_t ahcirf_set_device_bits_fis; 555 556 /* offset 0x60 - Unknown FIS */ 557 ahci_fis_unknown_t ahcirf_unknown_fis; 558 559 /* offset 0xa0h - Reserved */ 560 uint32_t ahcirf_fis_rsvd4[15]; 561} ahci_rcvd_fis_t; 562 563/* physical region description table (PRDT) item structure */ 564typedef struct ahci_prdt_item { 565 /* DW 0 - Data Base Address */ 566 uint32_t ahcipi_data_base_addr; 567 568 /* DW 1 - Data Base Address Upper */ 569 uint32_t ahcipi_data_base_addr_upper; 570 571 /* DW 2 - Reserved */ 572 uint32_t ahcipi_rsvd; 573 574 /* DW 3 - Description Information */ 575 uint32_t ahcipi_descr_info; 576 577#define GET_PRDT_ITEM_INTR_ON_COMPLETION(prdt_item) \ 578 ((prdt_item.ahcipi_descr_info >> 31) & 0x01) 579 580#define GET_PRDT_ITEM_DATA_BYTE_COUNT(prdt_item) \ 581 (prdt_item.ahcipi_descr_info & 0x3fffff) 582 583} ahci_prdt_item_t; 584 585/* command table structure */ 586typedef struct ahci_cmd_table { 587 /* offset 0x00 - Command FIS */ 588 ahci_fis_command_t ahcict_command_fis; 589 590 /* offset 0x40 - ATAPI Command */ 591 uint8_t ahcict_atapi_cmd[SATA_ATAPI_MAX_CDB_LEN]; 592 593 /* offset 0x50 - Reserved */ 594 uint32_t ahcict_rsvd[12]; 595 596 /* offset 0x80 - Physical Region Description Table */ 597 ahci_prdt_item_t ahcict_prdt[AHCI_PRDT_NUMBER]; 598} ahci_cmd_table_t; 599 600/* command head structure - size 20h */ 601typedef struct ahci_cmd_header { 602 /* DW 0 - Description Information */ 603 uint32_t ahcich_descr_info; 604 605#define BZERO_DESCR_INFO(cmd_header) \ 606 (cmd_header->ahcich_descr_info = 0) 607 608#define GET_PRD_TABLE_LENGTH(cmd_header) \ 609 ((cmd_header->ahcich_descr_info >> 16) & 0xffff) 610 611#define SET_PRD_TABLE_LENGTH(cmd_header, length) \ 612 (cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16)) 613 614#define GET_PORT_MULTI_PORT(cmd_header) \ 615 ((cmd_header->ahcich_descr_info >> 12) & 0x0f) 616 617#define SET_PORT_MULTI_PORT(cmd_header, flags) \ 618 (cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12)) 619 620#define GET_CLEAR_BUSY_UPON_R_OK(cmd_header) \ 621 ((cmd_header->ahcich_descr_info >> 10) & 0x01) 622 623#define SET_CLEAR_BUSY_UPON_R_OK(cmd_header, flags) \ 624 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10)) 625 626#define GET_BIST(cmd_header) \ 627 ((cmd_header->ahcich_descr_info >> 9) & 0x01) 628 629#define GET_RESET(cmd_header) \ 630 ((cmd_header->ahcich_descr_info >> 8) & 0x01) 631 632#define SET_RESET(cmd_header, features_exp) \ 633 (cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8)) 634 635#define GET_PREFETCHABLE(cmd_header) \ 636 ((cmd_header->ahcich_descr_info >> 7) & 0x01) 637 638#define SET_PREFETCHABLE(cmd_header, flags) \ 639 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 7)) 640 641#define GET_WRITE(cmd_header) \ 642 ((cmd_header->ahcich_descr_info >> 6) & 0x01) 643 644#define SET_WRITE(cmd_header, flags) \ 645 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 6)) 646 647#define GET_ATAPI(cmd_header) \ 648 ((cmd_header->ahcich_descr_info >> 5) & 0x01) 649 650#define SET_ATAPI(cmd_header, flags) \ 651 (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 5)) 652 653#define GET_COMMAND_FIS_LENGTH(cmd_header) \ 654 (cmd_header->ahcich_descr_info && 0x1f) 655 656#define SET_COMMAND_FIS_LENGTH(cmd_header, length) \ 657 (cmd_header->ahcich_descr_info |= (length & 0x1f)) 658 659 /* DW 1 - Physical Region Descriptor Byte Count */ 660 uint32_t ahcich_prd_byte_count; 661 662#define BZERO_PRD_BYTE_COUNT(cmd_header) \ 663 (cmd_header->ahcich_prd_byte_count = 0) 664 665 /* DW 2 - Command Table Base Address */ 666 uint32_t ahcich_cmd_tab_base_addr; 667 668#define SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address) \ 669 (cmd_header->ahcich_cmd_tab_base_addr = base_address) 670 671 /* DW 3 - Command Table Base Address Upper */ 672 uint32_t ahcich_cmd_tab_base_addr_upper; 673 674#define SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \ 675 (cmd_header->ahcich_cmd_tab_base_addr_upper = base_address) 676 677 /* DW 4-7 - Reserved */ 678 uint32_t ahcich_rsvd[4]; 679} ahci_cmd_header_t; 680 681 682#ifdef __cplusplus 683} 684#endif 685 686#endif /* _AHCIREG_H */ 687