mpi_cnfg.h revision 7413:b0d1dc604d2a
1/* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6#ifndef _SYS_MPI_CNFG_H 7#define _SYS_MPI_CNFG_H 8 9#ifdef __cplusplus 10extern "C" { 11#endif 12 13/* 14 * Config Message and Structures 15 */ 16typedef struct config_page_header { 17 uint8_t PageVersion; 18 uint8_t PageLength; 19 uint8_t PageNumber; 20 uint8_t PageType; 21} config_page_header_t; 22 23typedef union config_page_header_union { 24 config_page_header_t Struct; 25 uint8_t Bytes[4]; 26 uint16_t Word16[2]; 27 uint32_t Word32; 28} config_page_header_union_t; 29 30/* 31 * The extended header is used for 1064 and on 32 */ 33typedef struct config_extended_page_header { 34 uint8_t PageVersion; 35 uint8_t Reserved1; 36 uint8_t PageNumber; 37 uint8_t PageType; 38 uint16_t ExtPageLength; 39 uint8_t ExtPageType; 40 uint8_t Reserved2; 41} config_extended_page_header_t; 42 43/* 44 * PageType field values 45 */ 46#define MPI_CONFIG_PAGEATTR_READ_ONLY 0x00 47#define MPI_CONFIG_PAGEATTR_CHANGEABLE 0x10 48#define MPI_CONFIG_PAGEATTR_PERSISTENT 0x20 49#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT 0x30 50#define MPI_CONFIG_PAGEATTR_MASK 0xF0 51 52#define MPI_CONFIG_PAGETYPE_IO_UNIT 0x00 53#define MPI_CONFIG_PAGETYPE_IOC 0x01 54#define MPI_CONFIG_PAGETYPE_BIOS 0x02 55#define MPI_CONFIG_PAGETYPE_SCSI_PORT 0x03 56#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE 0x04 57#define MPI_CONFIG_PAGETYPE_FC_PORT 0x05 58#define MPI_CONFIG_PAGETYPE_FC_DEVICE 0x06 59#define MPI_CONFIG_PAGETYPE_LAN 0x07 60#define MPI_CONFIG_PAGETYPE_RAID_VOLUME 0x08 61#define MPI_CONFIG_PAGETYPE_MANUFACTURING 0x09 62#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK 0x0A 63#define MPI_CONFIG_PAGETYPE_INBAND 0x0B 64#define MPI_CONFIG_PAGETYPE_EXTENDED 0x0F 65#define MPI_CONFIG_PAGETYPE_MASK 0x0F 66 67#define MPI_CONFIG_TYPENUM_MASK 0x0FFF 68 69/* 70 * ExtPageType field values 71 */ 72#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT 0x10 73#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER 0x11 74#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE 0x12 75#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY 0x13 76 77/* 78 * Page Address field values 79 */ 80#define MPI_SCSI_PORT_PGAD_PORT_MASK 0x000000FF 81 82#define MPI_SCSI_DEVICE_TARGET_ID_MASK 0x000000FF 83#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT 0 84#define MPI_SCSI_DEVICE_BUS_MASK 0x0000FF00 85#define MPI_SCSI_DEVICE_BUS_SHIFT 8 86 87#define MPI_FC_PORT_PGAD_PORT_MASK 0xF0000000 88#define MPI_FC_PORT_PGAD_PORT_SHIFT 28 89#define MPI_FC_PORT_PGAD_FORM_MASK 0x0F000000 90#define MPI_FC_PORT_PGAD_FORM_INDEX 0x01000000 91#define MPI_FC_PORT_PGAD_INDEX_MASK 0x0000FFFF 92#define MPI_FC_PORT_PGAD_INDEX_SHIFT 0 93 94#define MPI_FC_DEVICE_PGAD_PORT_MASK 0xF0000000 95#define MPI_FC_DEVICE_PGAD_PORT_SHIFT 28 96#define MPI_FC_DEVICE_PGAD_FORM_MASK 0x0F000000 97#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID 0x00000000 98#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK 0xF0000000 99#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT 28 100#define MPI_FC_DEVICE_PGAD_ND_DID_MASK 0x00FFFFFF 101#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT 0 102#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID 0x01000000 103#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK 0x0000FF00 104#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT 8 105#define MPI_FC_DEVICE_PGAD_BT_TID_MASK 0x000000FF 106#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT 0 107 108#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK 0x000000FF 109#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT 0 110 111#define MPI_SAS_EXPAND_PGAD_FORM_MASK 0xF0000000 112#define MPI_SAS_EXPAND_PGAD_FORM_SHIFT 28 113#define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE 0x00000000 114#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM 0x00000001 115#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE 0x00000002 116#define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE 0x0000FFFF 117#define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE 0 118#define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY 0x00FF0000 119#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY 16 120#define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE 0x0000FFFF 121#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE 0 122#define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE 0x0000FFFF 123#define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE 0 124 125#define MPI_SAS_DEVICE_PGAD_FORM_MASK 0xF0000000 126#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT 28 127#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE 0x00000000 128#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID 0x00000001 129#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE 0x00000002 130#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK 0x0000FFFF 131#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT 0 132#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK 0x0000FF00 133#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT 8 134#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK 0x000000FF 135#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT 0 136#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK 0x0000FFFF 137#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT 0 138 139#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK 0x000000FF 140#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT 0 141 142/* 143 * Config Message 144 */ 145typedef struct msg_config { 146 uint8_t Action; 147 uint8_t Reserved; 148 uint8_t ChainOffset; 149 uint8_t Function; 150 uint16_t ExtPageLength; /* 1064 only */ 151 uint8_t ExtPageType; /* 1064 only */ 152 uint8_t MsgFlags; 153 uint32_t MsgContext; 154 uint8_t Reserved2[8]; 155 config_page_header_t Header; 156 uint32_t PageAddress; 157 sge_io_union_t PageBufferSGE; 158} msg_config_t; 159 160/* 161 * Action field values 162 */ 163#define MPI_CONFIG_ACTION_PAGE_HEADER 0x00 164#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT 0x01 165#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT 0x02 166#define MPI_CONFIG_ACTION_PAGE_DEFAULT 0x03 167#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM 0x04 168#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT 0x05 169#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM 0x06 170 171/* 172 * Config Reply Message 173 */ 174typedef struct msg_config_reply { 175 uint8_t Action; 176 uint8_t Reserved; 177 uint8_t MsgLength; 178 uint8_t Function; 179 uint16_t ExtPageLength; 180 uint8_t ExtPageType; 181 uint8_t MsgFlags; 182 uint32_t MsgContext; 183 uint8_t Reserved2[2]; 184 uint16_t IOCStatus; 185 uint32_t IOCLogInfo; 186 config_page_header_t Header; 187} msg_config_reply_t; 188 189/* 190 * Manufacturing Config pages 191 */ 192#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC 0x1000 193#define MPI_MANUFACTPAGE_DEVICEID_FC909 0x0621 194#define MPI_MANUFACTPAGE_DEVICEID_FC919 0x0624 195#define MPI_MANUFACTPAGE_DEVICEID_FC929 0x0622 196#define MPI_MANUFACTPAGE_DEVICEID_FC919X 0x0628 197#define MPI_MANUFACTPAGE_DEVICEID_FC929X 0x0626 198#define MPI_MANUFACTPAGE_DEVID_53C1030 0x0030 199#define MPI_MANUFACTPAGE_DEVID_53C1030ZC 0x0031 200#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 0x0032 201#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 0x0033 202#define MPI_MANUFACTPAGE_DEVID_53C1035 0x0040 203#define MPI_MANUFACTPAGE_DEVID_53C1035ZC 0x0041 204#define MPI_MANUFACTPAGE_DEVID_SAS1064 0x0050 205 206typedef struct config_page_manufacturing_0 { 207 config_page_header_t Header; 208 uint8_t ChipName[16]; 209 uint8_t ChipRevision[8]; 210 uint8_t BoardName[16]; 211 uint8_t BoardAssembly[16]; 212 uint8_t BoardTracerNumber[16]; 213} config_page_manufacturing_0_t; 214 215#define MPI_MANUFACTURING0_PAGEVERSION 0x00 216 217typedef struct config_page_manufacturing_1 { 218 config_page_header_t Header; 219 uint8_t VPD[256]; 220} config_page_manufacturing_1_t; 221 222#define MPI_MANUFACTURING1_PAGEVERSION 0x00 223 224typedef struct mpi_chip_revision_id { 225 uint16_t DeviceID; 226 uint8_t PCIRevisionID; 227 uint8_t Reserved; 228} mpi_chip_revision_id_t; 229 230/* 231 * Host code (drivers, BIOS, utilities, etc.) should leave this 232 * define set to one and check Header.PageLength at runtime. 233 */ 234#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 235#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 1 236#endif 237 238typedef struct config_page_manufacturing_2 { 239 config_page_header_t Header; 240 mpi_chip_revision_id_t ChipId; 241 uint32_t HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS]; 242} config_page_manufacturing_2_t; 243 244#define MPI_MANUFACTURING2_PAGEVERSION 0x00 245 246/* 247 * Host code (drivers, BIOS, utilities, etc.) should leave this 248 * define set to one and check Header.PageLength at runtime. 249 */ 250#ifndef MPI_MAN_PAGE_3_INFO_WORDS 251#define MPI_MAN_PAGE_3_INFO_WORDS 1 252#endif 253 254typedef struct config_page_manufacturing_3 { 255 config_page_header_t Header; 256 mpi_chip_revision_id_t ChipId; 257 uint32_t Info[MPI_MAN_PAGE_3_INFO_WORDS]; 258} config_page_manufacturing_3_t; 259 260#define MPI_MANUFACTURING3_PAGEVERSION 0x00 261 262typedef struct config_page_manufacturing_4 { 263 config_page_header_t Header; 264 uint32_t Reserved1; 265 uint8_t InfoOffset0; 266 uint8_t InfoSize0; 267 uint8_t InfoOffset1; 268 uint8_t InfoSize1; 269 uint8_t InquirySize; 270 uint8_t Flags; 271 uint16_t Reserved2; 272 uint8_t InquiryData[56]; 273 uint32_t ISVolumeSettings; 274 uint32_t IMEVolumeSettings; 275 uint32_t IMVolumeSettings; 276} config_page_manufacturing_4_t; 277 278#define MPI_MANUFACTURING4_PAGEVERSION 0x01 279#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA 0x01 280 281typedef struct config_page_manufacturing_5 { 282 config_page_header_t Header; 283 uint64_t BaseWWID; 284} config_page_manufacturing_5_t; 285 286#define MPI_MANUFACTURING5_PAGEVERSION 0x00 287 288typedef struct config_page_manufacturing_6 { 289 config_page_header_t Header; 290 uint32_t ProductSpecificInfo; 291} config_page_manufacturing_6_t; 292 293#define MPI_MANUFACTURING6_PAGEVERSION 0x00 294 295/* 296 * IO Unit Config Pages 297 */ 298typedef struct config_page_io_unit_0 { 299 config_page_header_t Header; 300 uint64_t UniqueValue; 301} config_page_io_unit_0_t; 302 303#define MPI_IOUNITPAGE0_PAGEVERSION 0x00 304 305typedef struct config_page_io_unit_1 { 306 config_page_header_t Header; 307 uint32_t Flags; 308} config_page_io_unit_1_t; 309 310#define MPI_IOUNITPAGE1_PAGEVERSION 0x01 311 312#define MPI_IOUNITPAGE1_MULTI_FUNCTION 0x00000000 313#define MPI_IOUNITPAGE1_SINGLE_FUNCTION 0x00000001 314#define MPI_IOUNITPAGE1_MULTI_PATHING 0x00000002 315#define MPI_IOUNITPAGE1_SINGLE_PATHING 0x00000000 316#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID 0x00000004 317#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING 0x00000020 318#define MPI_IOUNITPAGE1_DISABLE_IR 0x00000040 319#define MPI_IOUNITPAGE1_FORCE_32 0x00000080 320#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE 0x00000100 321 322typedef struct mpi_adapter_info { 323 uint8_t PciBusNumber; 324 uint8_t PciDeviceAndFunctionNumber; 325 uint16_t AdapterFlags; 326} mpi_adapter_info_t; 327 328#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED 0x0001 329#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS 0x0002 330 331typedef struct config_page_io_unit_2 { 332 config_page_header_t Header; 333 uint32_t Flags; 334 uint32_t BiosVersion; 335 mpi_adapter_info_t AdapterOrder[4]; 336} config_page_io_unit_2_t; 337 338#define MPI_IOUNITPAGE2_PAGEVERSION 0x00 339 340#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR 0x00000002 341#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE 0x00000004 342#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE 0x00000008 343#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 0x00000010 344 345#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK 0x000000E0 346#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY 0x00000000 347#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY 0x00000020 348#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY 0x00000040 349 350/* 351 * Host code (drivers, BIOS, utilities, etc.) should leave this 352 * define set to one and check Header.PageLength at runtime. 353 */ 354#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 355#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 1 356#endif 357 358typedef struct config_page_io_unit_3 { 359 config_page_header_t Header; 360 uint8_t GPIOCount; 361 uint8_t Reserved1; 362 uint16_t Reserved2; 363 uint16_t GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; 364} config_page_io_unit_3_t; 365 366#define MPI_IOUNITPAGE3_PAGEVERSION 0x01 367 368#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK 0xFC 369#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT 2 370#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF 0x00 371#define MPI_IOUNITPAGE3_GPIO_SETTING_ON 0x01 372 373/* 374 * IOC Config Pages 375 */ 376typedef struct config_page_ioc_0 { 377 config_page_header_t Header; 378 uint32_t TotalNVStore; 379 uint32_t FreeNVStore; 380 uint16_t VendorID; 381 uint16_t DeviceID; 382 uint8_t RevisionID; 383 uint8_t Reserved[3]; 384 uint32_t ClassCode; 385 uint16_t SubsystemVendorID; 386 uint16_t SubsystemID; 387} config_page_ioc_0_t; 388 389#define MPI_IOCPAGE0_PAGEVERSION 0x01 390 391typedef struct config_page_ioc_1 { 392 config_page_header_t Header; 393 uint32_t Flags; 394 uint32_t CoalescingTimeout; 395 uint8_t CoalescingDepth; 396 uint8_t PCISlotNum; 397 uint8_t Reserved[2]; 398} config_page_ioc_1_t; 399 400#define MPI_IOCPAGE1_PAGEVERSION 0x01 401#define MPI_IOCPAGE1_EEDP_HOST_SUPPORTS_DIF 0x08000000 402#define MPI_IOCPAGE1_EEDP_MODE_MASK 0x07000000 403#define MPI_IOCPAGE1_EEDP_MODE_OFF 0x00000000 404#define MPI_IOCPAGE1_EEDP_MODE_T10 0x01000000 405#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 0x02000000 406#define MPI_IOCPAGE1_EEDP_MODE_LSI_2 0x03000000 407#define MPI_IOCPAGE1_REPLY_COALESCING 0x00000001 408#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN 0xFF 409 410typedef struct config_page_ioc_2_raid_vol { 411 uint8_t VolumeID; 412 uint8_t VolumeBus; 413 uint8_t VolumeIOC; 414 uint8_t VolumePageNumber; 415 uint8_t VolumeType; 416 uint8_t Flags; 417 uint16_t Reserved3; 418} config_page_ioc_2_raid_vol_t; 419 420#define MPI_RAID_VOL_TYPE_IS 0x00 421#define MPI_RAID_VOL_TYPE_IME 0x01 422#define MPI_RAID_VOL_TYPE_IM 0x02 423#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE 0x08 424 425/* 426 * Host code (drivers, BIOS, utilities, etc.) should leave this 427 * define set to one and check Header.PageLength at runtime. 428 */ 429#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 430#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1 431#endif 432 433typedef struct config_page_ioc_2 { 434 config_page_header_t Header; 435 uint32_t CapabilitiesFlags; 436 uint8_t NumActiveVolumes; 437 uint8_t MaxVolumes; 438 uint8_t NumActivePhysDisks; 439 uint8_t MaxPhysDisks; 440 config_page_ioc_2_raid_vol_t RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX]; 441} config_page_ioc_2_t; 442 443#define MPI_IOCPAGE2_PAGEVERSION 0x02 444 445/* 446 * IOC Page 2 Capabilities flags 447 */ 448#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT 0x00000001 449#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT 0x00000002 450#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT 0x00000004 451#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT 0x20000000 452#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT 0x40000000 453#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT 0x80000000 454 455typedef struct ioc_3_phys_disk { 456 uint8_t PhysDiskID; 457 uint8_t PhysDiskBus; 458 uint8_t PhysDiskIOC; 459 uint8_t PhysDiskNum; 460} ioc_3_phys_disk_t; 461 462/* 463 * Host code (drivers, BIOS, utilities, etc.) should leave this 464 * define set to one and check Header.PageLength at runtime. 465 */ 466#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 467#define MPI_IOC_PAGE_3_PHYSDISK_MAX 1 468#endif 469 470typedef struct config_page_ioc_3 { 471 config_page_header_t Header; 472 uint8_t NumPhysDisks; 473 uint8_t Reserved1; 474 uint16_t Reserved2; 475 ioc_3_phys_disk_t PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; 476} config_page_ioc_3_t; 477 478#define MPI_IOCPAGE3_PAGEVERSION 0x00 479 480typedef struct ioc_4_sep { 481 uint8_t SEPTargetID; 482 uint8_t SEPBus; 483 uint16_t Reserved; 484} ioc_4_sep_t; 485 486/* 487 * Host code (drivers, BIOS, utilities, etc.) should leave this 488 * define set to one and check Header.PageLength at runtime. 489 */ 490#ifndef MPI_IOC_PAGE_4_SEP_MAX 491#define MPI_IOC_PAGE_4_SEP_MAX 1 492#endif 493 494typedef struct config_page_ioc_4 { 495 config_page_header_t Header; 496 uint8_t ActiveSEP; 497 uint8_t MaxSEP; 498 uint16_t Reserved1; 499 ioc_4_sep_t SEP[MPI_IOC_PAGE_4_SEP_MAX]; 500} config_page_ioc_4_t; 501 502#define MPI_IOCPAGE4_PAGEVERSION 0x00 503 504/* 505 * SCSI Port Config Pages 506 */ 507typedef struct config_page_scsi_port_0 { 508 config_page_header_t Header; 509 uint32_t Capabilities; 510 uint32_t PhysicalInterface; 511} config_page_scsi_port_0_t; 512 513#define MPI_SCSIPORTPAGE0_PAGEVERSION 0x01 514 515/* 516 * Capabilities 517 */ 518#define MPI_SCSIPORTPAGE0_CAP_IU 0x00000001 519#define MPI_SCSIPORTPAGE0_CAP_DT 0x00000002 520#define MPI_SCSIPORTPAGE0_CAP_QAS 0x00000004 521#define MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS 0x00000008 522#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK 0x0000FF00 523#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK 0x00FF0000 524#define MPI_SCSIPORTPAGE0_CAP_WIDE 0x20000000 525#define MPI_SCSIPORTPAGE0_CAP_AIP 0x80000000 526 527/* 528 * Physical Interface 529 */ 530#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK 0x00000003 531#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD 0x01 532#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE 0x02 533#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD 0x03 534 535typedef struct config_page_scsi_port_1 { 536 config_page_header_t Header; 537 uint32_t Configuration; 538 uint32_t OnBusTimerValue; 539} config_page_scsi_port_1_t; 540 541#define MPI_SCSIPORTPAGE1_PAGEVERSION 0x02 542 543#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK 0x000000FF 544#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK 0xFFFF0000 545 546typedef struct mpi_device_info { 547 uint8_t Timeout; 548 uint8_t SyncFactor; 549 uint16_t DeviceFlags; 550} mpi_device_info_t; 551 552typedef struct config_page_scsi_port_2 { 553 config_page_header_t Header; 554 uint32_t PortFlags; 555 uint32_t PortSettings; 556 mpi_device_info_t DeviceSettings[16]; 557} config_page_scsi_port_2_t; 558 559#define MPI_SCSIPORTPAGE2_PAGEVERSION 0x01 560 561#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW 0x00000001 562#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET 0x00000004 563#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS 0x00000008 564#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE 0x00000010 565 566#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK 0x0000000F 567#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA 0x00000030 568#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA 0x00000000 569#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA 0x00000010 570#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA 0x00000020 571#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA 0x00000030 572#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA 0x000000C0 573#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK 0x00000F00 574#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS 0x00003000 575#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS 0x00000000 576#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS 0x00001000 577#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS 0x00003000 578 579#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE 0x0001 580#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE 0x0002 581#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE 0x0004 582#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE 0x0008 583#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE 0x0010 584#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE 0x0020 585 586/* 587 * SCSI Target Device Config Pages 588 */ 589typedef struct config_page_scsi_device_0 { 590 config_page_header_t Header; 591 uint32_t NegotiatedParameters; 592 uint32_t Information; 593} config_page_scsi_device_0_t; 594 595#define MPI_SCSIDEVPAGE0_PAGEVERSION 0x02 596 597#define MPI_SCSIDEVPAGE0_NP_IU 0x00000001 598#define MPI_SCSIDEVPAGE0_NP_DT 0x00000002 599#define MPI_SCSIDEVPAGE0_NP_QAS 0x00000004 600#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK 0x0000FF00 601#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK 0x00FF0000 602#define MPI_SCSIDEVPAGE0_NP_WIDE 0x20000000 603#define MPI_SCSIDEVPAGE0_NP_AIP 0x80000000 604#define MPI_SCSIDEVPAGE0_NP_IDP 0x08000000 605 606#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED 0x00000001 607#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED 0x00000002 608#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED 0x00000004 609#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED 0x00000008 610 611typedef struct config_page_scsi_device_1 { 612 config_page_header_t Header; 613 uint32_t RequestedParameters; 614 uint32_t Reserved; 615 uint32_t Configuration; 616} config_page_scsi_device_1_t; 617 618#define MPI_SCSIDEVPAGE1_PAGEVERSION 0x03 619 620#define MPI_SCSIDEVPAGE1_RP_IU 0x00000001 621#define MPI_SCSIDEVPAGE1_RP_DT 0x00000002 622#define MPI_SCSIDEVPAGE1_RP_QAS 0x00000004 623#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK 0x0000FF00 624#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK 0x00FF0000 625#define MPI_SCSIDEVPAGE1_RP_WIDE 0x20000000 626#define MPI_SCSIDEVPAGE1_RP_AIP 0x80000000 627#define MPI_SCSIDEVPAGE1_RP_IDP 0x08000000 628 629#define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK 0x00000003 630#define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK 0x00000300 631 632#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 0x00000002 633#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED 0x00000004 634 635typedef struct config_page_scsi_device_2 { 636 config_page_header_t Header; 637 uint32_t DomainValidation; 638 uint32_t ParityPipeSelect; 639 uint32_t DataPipeSelect; 640} config_page_scsi_device_2_t; 641 642#define MPI_SCSIDEVPAGE2_PAGEVERSION 0x00 643 644#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE 0x00000010 645#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE 0x00000020 646#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL 0x00000380 647#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL 0x00001C00 648#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL 0x0000E000 649#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST 0x10000000 650#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST 0x20000000 651#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT 0x40000000 652#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT 0x80000000 653 654#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK 0x00000003 655 656#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK 0x00000003 657#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK 0x0000000C 658#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK 0x00000030 659#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK 0x000000C0 660#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK 0x00000300 661#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK 0x00000C00 662#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK 0x00003000 663#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK 0x0000C000 664#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK 0x00030000 665#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK 0x000C0000 666#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK 0x00300000 667#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK 0x00C00000 668#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK 0x03000000 669#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK 0x0C000000 670#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK 0x30000000 671#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK 0xC0000000 672 673/* 674 * FC Port Config Pages 675 */ 676typedef struct config_page_fc_port_0 { 677 config_page_header_t Header; 678 uint32_t Flags; 679 uint8_t MPIPortNumber; 680 uint8_t Reserved[3]; 681 uint32_t PortIdentifier; 682 uint64_t WWNN; 683 uint64_t WWPN; 684 uint32_t SupportedServiceClass; 685 uint32_t SupportedSpeeds; 686 uint32_t CurrentSpeed; 687 uint32_t MaxFrameSize; 688 uint64_t FabricWWNN; 689 uint64_t FabricWWPN; 690 uint32_t DiscoveredPortsCount; 691 uint32_t MaxInitiators; 692} config_page_fc_port_0_t; 693 694#define MPI_FCPORTPAGE0_PAGEVERSION 0x01 695 696#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK 0x0000000F 697#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT \ 698 MPI_PORTFACTS_PROTOCOL_INITIATOR 699#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG \ 700 MPI_PORTFACTS_PROTOCOL_TARGET 701#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN \ 702 MPI_PORTFACTS_PROTOCOL_LAN 703#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR \ 704 MPI_PORTFACTS_PROTOCOL_LOGBUSADDR 705 706#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED 0x00000010 707#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED 0x00000020 708#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID 0x00000030 709 710#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK 0x00000F00 711#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT 0x00000000 712#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT 0x00000100 713#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP 0x00000200 714#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT 0x00000400 715#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP 0x00000800 716 717#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK 0x00000F00 718#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT 0x00000000 719#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT 0x00000100 720#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP 0x00000200 721#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT 0x00000400 722#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP 0x00000800 723 724#define MPI_FCPORTPAGE0_LTYPE_RESERVED 0x00 725#define MPI_FCPORTPAGE0_LTYPE_OTHER 0x01 726#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN 0x02 727#define MPI_FCPORTPAGE0_LTYPE_COPPER 0x03 728#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 0x04 729#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 0x05 730#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI 0x06 731#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI 0x07 732#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI 0x08 733#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI 0x09 734#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE 0x0A 735#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE 0x0B 736#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE 0x0C 737#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE 0x0D 738#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE 0x0E 739#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE 0x0F 740 741#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN 0x01 742#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE 0x02 743#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE 0x03 744#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED 0x04 745#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST 0x05 746#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN 0x06 747#define MPI_FCPORTPAGE0_PORTSTATE_ERROR 0x07 748#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK 0x08 749 750#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 0x00000001 751#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 0x00000002 752#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 0x00000004 753 754#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 0x00000001 755#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 0x00000002 756#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 0x00000004 757 758#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT \ 759 MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 760#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT \ 761 MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 762#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT \ 763 MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 764 765typedef struct config_page_fc_port_1 { 766 config_page_header_t Header; 767 uint32_t Flags; 768 uint64_t NoSEEPROMWWNN; 769 uint64_t NoSEEPROMWWPN; 770 uint8_t HardALPA; 771 uint8_t LinkConfig; 772 uint8_t TopologyConfig; 773 uint8_t Reserved; 774} config_page_fc_port_1_t; 775 776#define MPI_FCPORTPAGE1_PAGEVERSION 0x02 777 778#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN 0x08000000 779#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY 0x04000000 780#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID 0x00000001 781#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN 0x00000000 782 783/* 784 * Flags used for programming protocol modes in NVStore 785 */ 786#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK 0xF0000000 787#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT 28 788#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT \ 789 ((uint32_t)MPI_PORTFACTS_PROTOCOL_INITIATOR << \ 790 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 791#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG \ 792 ((uint32_t)MPI_PORTFACTS_PROTOCOL_TARGET << \ 793 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 794#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN \ 795 ((uint32_t)MPI_PORTFACTS_PROTOCOL_LAN << \ 796 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 797#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR \ 798 ((uint32_t)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << \ 799 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 800 801#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED 0xFF 802 803#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK 0x0F 804#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG 0x00 805#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG 0x01 806#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG 0x02 807#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG 0x03 808#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO 0x0F 809 810#define MPI_FCPORTPAGE1_TOPOLOGY_MASK 0x0F 811#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT 0x01 812#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT 0x02 813#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO 0x0F 814 815typedef struct config_page_fc_port_2 { 816 config_page_header_t Header; 817 uint8_t NumberActive; 818 uint8_t ALPA[127]; 819} config_page_fc_port_2_t; 820 821#define MPI_FCPORTPAGE2_PAGEVERSION 0x01 822 823typedef struct wwn_format { 824 uint64_t WWNN; 825 uint64_t WWPN; 826} wwn_format_t; 827 828typedef union fc_port_persistent_physical_id { 829 wwn_format_t WWN; 830 uint32_t Did; 831} fc_port_persistent_physical_id_t; 832 833typedef struct fc_port_persistent { 834 fc_port_persistent_physical_id_t PhysicalIdentifier; 835 uint8_t TargetID; 836 uint8_t Bus; 837 uint16_t Flags; 838} fc_port_persistent_t; 839 840#define MPI_PERSISTENT_FLAGS_SHIFT 16 841#define MPI_PERSISTENT_FLAGS_ENTRY_VALID 0x0001 842#define MPI_PERSISTENT_FLAGS_SCAN_ID 0x0002 843#define MPI_PERSISTENT_FLAGS_SCAN_LUNS 0x0004 844#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE 0x0008 845#define MPI_PERSISTENT_FLAGS_BY_DID 0x0080 846 847/* 848 * Host code (drivers, BIOS, utilities, etc.) should leave this 849 * define set to one and check Header.PageLength at runtime. 850 */ 851#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 852#define MPI_FC_PORT_PAGE_3_ENTRY_MAX 1 853#endif 854 855typedef struct config_page_fc_port_3 { 856 config_page_header_t Header; 857 fc_port_persistent_t Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; 858} config_page_fc_port_3_t; 859 860#define MPI_FCPORTPAGE3_PAGEVERSION 0x01 861 862typedef struct config_page_fc_port_4 { 863 config_page_header_t Header; 864 uint32_t PortFlags; 865 uint32_t PortSettings; 866} config_page_fc_port_4_t; 867 868#define MPI_FCPORTPAGE4_PAGEVERSION 0x00 869 870#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS 0x00000008 871 872#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA 0x00000030 873#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA 0x00000000 874#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA 0x00000010 875#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA 0x00000020 876#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA 0x00000030 877#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA 0x000000C0 878#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK 0x00000F00 879 880typedef struct config_page_fc_port_5_alias_info { 881 uint8_t Flags; 882 uint8_t AliasAlpa; 883 uint16_t Reserved; 884 uint64_t AliasWWNN; 885 uint64_t AliasWWPN; 886} config_page_fc_port_5_alias_info_t; 887 888/* 889 * Host code (drivers, BIOS, utilities, etc.) should leave this 890 * define set to one and check Header.PageLength at runtime. 891 */ 892#ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 893#define MPI_FC_PORT_PAGE_5_ALIAS_MAX 1 894#endif 895 896typedef struct config_page_fc_port_5 { 897 config_page_header_t Header; 898 config_page_fc_port_5_alias_info_t 899 AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX]; 900} config_page_fc_port_5_t; 901 902#define MPI_FCPORTPAGE5_PAGEVERSION 0x00 903 904#define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID 0x01 905#define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID 0x02 906 907typedef struct config_page_fc_port_6 { 908 config_page_header_t Header; 909 uint32_t Reserved; 910 uint64_t TimeSinceReset; 911 uint64_t TxFrames; 912 uint64_t RxFrames; 913 uint64_t TxWords; 914 uint64_t RxWords; 915 uint64_t LipCount; 916 uint64_t NosCount; 917 uint64_t ErrorFrames; 918 uint64_t DumpedFrames; 919 uint64_t LinkFailureCount; 920 uint64_t LossOfSyncCount; 921 uint64_t LossOfSignalCount; 922 uint64_t PrimativeSeqErrCount; 923 uint64_t InvalidTxWordCount; 924 uint64_t InvalidCrcCount; 925 uint64_t FcpInitiatorIoCount; 926} config_page_fc_port_6_t; 927 928#define MPI_FCPORTPAGE6_PAGEVERSION 0x00 929 930typedef struct config_page_fc_port_7 { 931 config_page_header_t Header; 932 uint32_t Reserved; 933 uint8_t PortSymbolicName[256]; 934} config_page_fc_port_7_t; 935 936#define MPI_FCPORTPAGE7_PAGEVERSION 0x00 937 938typedef struct config_page_fc_port_8 { 939 config_page_header_t Header; 940 uint32_t BitVector[8]; 941} config_page_fc_port_8_t; 942 943#define MPI_FCPORTPAGE8_PAGEVERSION 0x00 944 945typedef struct config_page_fc_port_9 { 946 config_page_header_t Header; 947 uint32_t Reserved; 948 uint64_t GlobalWWPN; 949 uint64_t GlobalWWNN; 950 uint32_t UnitType; 951 uint32_t PhysicalPortNumber; 952 uint32_t NumAttachedNodes; 953 uint16_t IPVersion; 954 uint16_t UDPPortNumber; 955 uint8_t IPAddress[16]; 956 uint16_t Reserved1; 957 uint16_t TopologyDiscoveryFlags; 958} config_page_fc_port_9_t; 959 960#define MPI_FCPORTPAGE9_PAGEVERSION 0x00 961 962/* 963 * FC Device Config Pages 964 */ 965typedef struct config_page_fc_device_0 { 966 config_page_header_t Header; 967 uint64_t WWNN; 968 uint64_t WWPN; 969 uint32_t PortIdentifier; 970 uint8_t Protocol; 971 uint8_t Flags; 972 uint16_t BBCredit; 973 uint16_t MaxRxFrameSize; 974 uint8_t Reserved1; 975 uint8_t PortNumber; 976 uint8_t FcPhLowestVersion; 977 uint8_t FcPhHighestVersion; 978 uint8_t CurrentTargetID; 979 uint8_t CurrentBus; 980} config_page_fc_device_0_t; 981 982#define MPI_FC_DEVICE_PAGE_0_PAGEVERSION 0x02 983 984#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID 0x01 985 986#define MPI_FC_DEVICE_PAGE_0_PROT_IP 0x01 987#define MPI_FC_DEVICE_PAGE_0_PROT_FCP_TARGET 0x02 988#define MPI_FC_DEVICE_PAGE_0_PROT_FCP_INITIATOR 0x04 989 990#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK \ 991 (MPI_FC_DEVICE_PGAD_PORT_MASK) 992#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK \ 993 (MPI_FC_DEVICE_PGAD_FORM_MASK) 994#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID \ 995 (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 996#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID \ 997 (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 998#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK \ 999 (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1000#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK \ 1001 (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1002#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT \ 1003 (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1004#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK \ 1005 (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1006 1007/* 1008 * RAID Volume Config Pages 1009 */ 1010typedef struct raid_vol0_phys_disk { 1011 uint16_t Reserved; 1012 uint8_t PhysDiskMap; 1013 uint8_t PhysDiskNum; 1014} raid_vol0_phys_disk_t; 1015 1016#define MPI_RAIDVOL0_PHYSDISK_PRIMARY 0x01 1017#define MPI_RAIDVOL0_PHYSDISK_SECONDARY 0x02 1018 1019typedef struct raid_vol0_status { 1020 uint8_t Flags; 1021 uint8_t State; 1022 uint16_t Reserved; 1023} raid_vol0_status_t; 1024 1025/* 1026 * RAID Volume Page 0 VolumeStatus defines 1027 */ 1028#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED 0x01 1029#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED 0x02 1030#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 0x04 1031#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 0x08 1032 1033#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL 0x00 1034#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED 0x01 1035#define MPI_RAIDVOL0_STATUS_STATE_FAILED 0x02 1036#define MPI_RAIDVOL0_STATUS_STATE_MISSING 0x03 1037 1038typedef struct raid_vol0_settings { 1039 uint16_t Settings; 1040 uint8_t HotSparePool; 1041 uint8_t Reserved; 1042} raid_vol0_settings_t; 1043 1044/* 1045 * RAID Volume Page 0 VolumeSettings defines 1046 */ 1047#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE 0x0001 1048#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART 0x0002 1049#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE 0x0004 1050#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC 0x0008 1051#define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE 0x00C0 1052#define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE 0x0000 1053#define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE 0x0040 1054#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX 0x0010 1055#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS 0x8000 1056 1057/* 1058 * RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk 1059 */ 1060#define MPI_RAID_HOT_SPARE_POOL_0 0x01 1061#define MPI_RAID_HOT_SPARE_POOL_1 0x02 1062#define MPI_RAID_HOT_SPARE_POOL_2 0x04 1063#define MPI_RAID_HOT_SPARE_POOL_3 0x08 1064#define MPI_RAID_HOT_SPARE_POOL_4 0x10 1065#define MPI_RAID_HOT_SPARE_POOL_5 0x20 1066#define MPI_RAID_HOT_SPARE_POOL_6 0x40 1067#define MPI_RAID_HOT_SPARE_POOL_7 0x80 1068 1069/* 1070 * Host code (drivers, BIOS, utilities, etc.) should leave this 1071 * define set to one and check Header.PageLength at runtime. 1072 */ 1073#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1074#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1 1075#endif 1076 1077typedef struct config_page_raid_vol_0 { 1078 config_page_header_t Header; 1079 uint8_t VolumeID; 1080 uint8_t VolumeBus; 1081 uint8_t VolumeIOC; 1082 uint8_t VolumeType; 1083 raid_vol0_status_t VolumeStatus; 1084 raid_vol0_settings_t VolumeSettings; 1085 uint32_t MaxLBA; 1086 uint32_t Reserved1; 1087 uint32_t StripeSize; 1088 uint32_t Reserved2; 1089 uint32_t Reserved3; 1090 uint8_t NumPhysDisks; 1091 uint8_t Reserved4; 1092 uint8_t ResyncRate; 1093 uint8_t Reserved5; 1094 raid_vol0_phys_disk_t PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX]; 1095} config_page_raid_vol_0_t; 1096 1097#define MPI_RAIDVOLPAGE0_PAGEVERSION 0x00 1098 1099typedef struct config_page_raid_vol_1 1100{ 1101 config_page_header_t Header; /* 00h */ 1102 uint8_t VolumeID; /* 04h */ 1103 uint8_t VolumeBus; /* 05h */ 1104 uint8_t VolumeIOC; /* 06h */ 1105 uint8_t Reserved0; /* 07h */ 1106 uint8_t GUID[24]; /* 08h */ 1107 uint8_t Name[32]; /* 20h */ 1108 uint64_t WWID; /* 40h */ 1109 uint8_t Reserved1; /* 48h */ 1110 uint8_t Reserved2; /* 4Ch */ 1111} config_page_raid_vol_1_t; 1112 1113#define MPI_RAIDVOLPAGE1_PAGEVERSION 0x01 1114 1115/* 1116 * RAID Physical Disk Config Pages 1117 */ 1118typedef struct raid_phys_disk0_error_data { 1119 uint8_t ErrorCdbByte; 1120 uint8_t ErrorSenseKey; 1121 uint16_t Reserved; 1122 uint16_t ErrorCount; 1123 uint8_t ErrorASC; 1124 uint8_t ErrorASCQ; 1125 uint16_t SmartCount; 1126 uint8_t SmartASC; 1127 uint8_t SmartASCQ; 1128} raid_phys_disk0_error_data_t; 1129 1130typedef struct raid_phys_disk_inquiry_data { 1131 uint8_t VendorID[8]; 1132 uint8_t ProductID[16]; 1133 uint8_t ProductRevLevel[4]; 1134 uint8_t Info[32]; 1135} raid_phys_disk0_inquiry_data_t; 1136 1137typedef struct raid_phys_disk0_settings { 1138 uint8_t SepID; 1139 uint8_t SepBus; 1140 uint8_t HotSparePool; 1141 uint8_t PhysDiskSettings; 1142} raid_phys_disk0_settings_t; 1143 1144typedef struct raid_phys_disk0_status { 1145 uint8_t Flags; 1146 uint8_t State; 1147 uint16_t Reserved; 1148} raid_phys_disk0_status_t; 1149 1150/* 1151 * RAID Volume 2 IM Physical Disk DiskStatus flags 1152 */ 1153#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 0x01 1154#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED 0x02 1155 1156#define MPI_PHYSDISK0_STATUS_ONLINE 0x00 1157#define MPI_PHYSDISK0_STATUS_MISSING 0x01 1158#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE 0x02 1159#define MPI_PHYSDISK0_STATUS_FAILED 0x03 1160#define MPI_PHYSDISK0_STATUS_INITIALIZING 0x04 1161#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED 0x05 1162#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED 0x06 1163#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE 0xFF 1164 1165typedef struct config_page_raid_phys_disk_0 { 1166 config_page_header_t Header; 1167 uint8_t PhysDiskID; 1168 uint8_t PhysDiskBus; 1169 uint8_t PhysDiskIOC; 1170 uint8_t PhysDiskNum; 1171 raid_phys_disk0_settings_t PhysDiskSettings; 1172 uint32_t Reserved1; 1173 uint32_t Reserved2; 1174 uint32_t Reserved3; 1175 uint8_t DiskIdentifier[16]; 1176 raid_phys_disk0_inquiry_data_t InquiryData; 1177 raid_phys_disk0_status_t PhysDiskStatus; 1178 uint32_t MaxLBA; 1179 raid_phys_disk0_error_data_t ErrorData; 1180} config_page_raid_phys_disk_0_t; 1181 1182#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION 0x00 1183 1184typedef struct raid_phys_disk1_path { 1185 uint8_t PhysDiskID; 1186 uint8_t PhysDiskBus; 1187 uint16_t Reserved1; 1188 uint64_t WWID; 1189 uint64_t OwnerWWID; 1190 uint8_t OwnerIdentifier; 1191 uint8_t Reserved2; 1192 uint16_t Flags; 1193} raid_phys_disk1_path_t; 1194 1195/* RAID Physical Disk Page 1 Flags field defines */ 1196 1197#define MPI_RAID_PHYSDISK1_FLAG_BROKEN 0x0002 1198#define MPI_RAID_PHYSDISK1_FLAG_INVALID 0x0001 1199 1200#ifndef MPI_RAID_PHYS_DISK1_PATH_MAX 1201#define MPI_RAID_PHYS_DISK1_PATH_MAX 1 1202#endif 1203 1204typedef struct config_page_raid_phys_disk_1 { 1205 config_page_header_t Header; 1206 uint8_t NumPhysDiskPaths; 1207 uint8_t PhysDiskNum; 1208 uint16_t Reserved2; 1209 uint32_t Reserved1; 1210 raid_phys_disk1_path_t Path[MPI_RAID_PHYS_DISK1_PATH_MAX]; 1211} config_page_raid_phys_disk_1_t; 1212 1213#define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION 0x01 1214/* 1215 * LAN Config Pages 1216 */ 1217typedef struct config_page_lan_0 { 1218 config_page_header_t Header; 1219 uint16_t TxRxModes; 1220 uint16_t Reserved; 1221 uint32_t PacketPrePad; 1222} config_page_lan_0_t; 1223 1224#define MPI_LAN_PAGE0_PAGEVERSION 0x01 1225 1226#define MPI_LAN_PAGE0_RETURN_LOOPBACK 0x0000 1227#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK 0x0001 1228#define MPI_LAN_PAGE0_LOOPBACK_MASK 0x0001 1229 1230typedef struct config_page_lan_1 { 1231 config_page_header_t Header; 1232 uint16_t Reserved; 1233 uint8_t CurrentDeviceState; 1234 uint8_t Reserved1; 1235 uint32_t MinPacketSize; 1236 uint32_t MaxPacketSize; 1237 uint32_t HardwareAddressLow; 1238 uint32_t HardwareAddressHigh; 1239 uint32_t MaxWireSpeedLow; 1240 uint32_t MaxWireSpeedHigh; 1241 uint32_t BucketsRemaining; 1242 uint32_t MaxReplySize; 1243 uint32_t NegWireSpeedLow; 1244 uint32_t NegWireSpeedHigh; 1245} config_page_lan_1_t; 1246 1247#define MPI_LAN_PAGE1_PAGEVERSION 0x03 1248 1249#define MPI_LAN_PAGE1_DEV_STATE_RESET 0x00 1250#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL 0x01 1251 1252/* 1253 * Inband config pages 1254 */ 1255typedef struct config_page_inband_0 { 1256 config_page_header_t Header; 1257 mpi_version_format_t InbandVersion; 1258 uint16_t MaximumBuffers; 1259 uint16_t Reserved1; 1260} config_page_inband_0_t; 1261 1262/* 1263 * SAS IO Unit config pages 1264 */ 1265typedef struct mpi_sas_io_unit0_phy_data { 1266 uint8_t Port; 1267 uint8_t PortFlags; 1268 uint8_t PhyFlags; 1269 uint8_t NegotiatedLinkRate; 1270 uint32_t ControllerPhyDeviceInfo; 1271 uint16_t AttachedDeviceHandle; 1272 uint16_t ControllerDevHandle; 1273 uint32_t Reserved2; 1274} mpi_sas_io_unit0_phy_data_t; 1275 1276/* 1277 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1278 * one and check Header.PageLength at runtime. 1279 */ 1280#ifndef MPI_SAS_IOUNIT0_PHY_MAX 1281#define MPI_SAS_IOUNIT0_PHY_MAX 1 1282#endif 1283 1284typedef struct config_page_sas_io_unit_0 { 1285 config_extended_page_header_t Header; 1286 uint32_t Reserved1; 1287 uint8_t NumPhys; 1288 uint8_t Reserved2; 1289 uint16_t Reserved3; 1290 mpi_sas_io_unit0_phy_data_t PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; 1291} config_page_sas_io_unit_0_t; 1292 1293#define MPI_SASIOUNITPAGE0_PAGEVERSION 0x00 1294 1295#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS 0x08 1296#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM 0x00 1297#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM 0x04 1298#define MPI_SAS_IOUNIT0_PORT_FLAGS_WAIT_FOR_PORTENABLE 0x02 1299#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG 0x01 1300 1301#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED 0x04 1302#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT 0x02 1303#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT 0x01 1304 1305#define MPI_SAS_IOUNIT0_RATE_UNKNOWN 0x00 1306#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED 0x01 1307#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION 0x02 1308#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE 0x03 1309#define MPI_SAS_IOUNIT0_RATE_1_5 0x08 1310#define MPI_SAS_IOUNIT0_RATE_3_0 0x09 1311 1312typedef struct mpi_sas_io_unit1_phy_data { 1313 uint8_t Port; 1314 uint8_t PortFlags; 1315 uint8_t PhyFlags; 1316 uint8_t MaxMinLinkRate; 1317 uint32_t ControllerPhyDeviceInfo; 1318 uint32_t Reserved1; 1319} mpi_sas_io_unit1_phy_data_t; 1320 1321/* 1322 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1323 * one and check Header.PageLength at runtime. 1324 */ 1325#ifndef MPI_SAS_IOUNIT1_PHY_MAX 1326#define MPI_SAS_IOUNIT1_PHY_MAX 1 1327#endif 1328 1329typedef struct config_page_sas_io_unit_1 { 1330 config_extended_page_header_t Header; 1331 uint16_t ControlFlags; 1332 uint16_t MaxNumSATATargets; 1333 uint16_t AdditionalControlFlags; 1334 uint16_t Reserved1; 1335 uint8_t NumPhys; 1336 uint8_t SATAMaxQDepth; 1337 uint8_t ReportMissingDeviceDelay; 1338 uint8_t IODeviceMissingDelay; 1339 mpi_sas_io_unit1_phy_data_t PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; 1340} config_page_sas_io_unit_1_t; 1341 1342#define MPI_SASIOUNITPAGE1_PAGEVERSION 0x00 1343 1344#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM 0x00 1345#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM 0x04 1346#define MPI_SAS_IOUNIT1_PORT_FLAGS_WAIT_FOR_PORTENABLE 0x02 1347#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG 0x01 1348 1349#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE 0x04 1350#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT 0x02 1351#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT 0x01 1352 1353#define MPI_SAS_IOUNIT1_MAX_RATE_MASK 0xF0 1354#define MPI_SAS_IOUNIT1_MAX_RATE_1_5 0x80 1355#define MPI_SAS_IOUNIT1_MAX_RATE_3_0 0x90 1356#define MPI_SAS_IOUNIT1_MIN_RATE_MASK 0x0F 1357#define MPI_SAS_IOUNIT1_MIN_RATE_1_5 0x08 1358#define MPI_SAS_IOUNIT1_MIN_RATE_3_0 0x09 1359 1360typedef struct config_page_sas_io_unit_2 { 1361 config_extended_page_header_t Header; 1362 uint32_t Reserved1; 1363 uint16_t MaxPersistentIDs; 1364 uint16_t NumPersistentIDsUsed; 1365 uint8_t Status; 1366 uint8_t Flags; 1367 uint16_t Reserved2; 1368} config_page_sas_io_unit_2_t; 1369 1370#define MPI_SASIOUNITPAGE2_PAGEVERSION 0x00 1371 1372#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS 0x02 1373#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS 0x01 1374 1375#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS 0x01 1376 1377#define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE 0x0E 1378#define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE 1 1379#define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP 0x00 1380#define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP 0x01 1381#define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP 0x02 1382#define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 0x07 1383 1384typedef struct config_page_sas_io_unit_3 { 1385 config_extended_page_header_t Header; 1386 uint32_t Reserved1; 1387 uint32_t MaxInvalidDwordCount; 1388 uint32_t InvalidDwordCountTime; 1389 uint32_t MaxRunningDisparityErrorCount; 1390 uint32_t RunningDisparityErrorTime; 1391 uint32_t MaxLossDwordSynchCount; 1392 uint32_t LossDwordSynchCountTime; 1393 uint32_t MaxPhyResetProblemCount; 1394 uint32_t PhyResetProblemTime; 1395} config_page_sas_io_unit_3_t; 1396 1397#define MPI_SASIOUNITPAGE3_PAGEVERSION 0x00 1398 1399typedef struct config_page_sas_expander_0 { 1400 config_extended_page_header_t Header; 1401 uint8_t PhysicalPort; 1402 uint8_t Reserved1; 1403 uint16_t EnclosureHandle; 1404 uint64_t SASAddress; 1405 uint32_t Reserved2; 1406 uint16_t DevHandle; 1407 uint16_t ParentDevHandle; 1408 uint16_t ExpanderChangeCount; 1409 uint16_t ExpanderRouteIndexes; 1410 uint8_t NumPhys; 1411 uint8_t SASLevel; 1412 uint8_t Flags; 1413 uint8_t Reserved3; 1414} config_page_sas_expander_0_t; 1415 1416#define MPI_SASEXPANDER0_PAGEVERSION 0x00 1417 1418#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG 0x02 1419#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS 0x01 1420 1421 1422typedef struct config_page_sas_expander_1 { 1423 config_extended_page_header_t Header; 1424 uint32_t Reserved1; 1425 uint8_t NumPhys; 1426 uint8_t Phy; 1427 uint16_t Reserved2; 1428 uint8_t ProgrammedLinkRate; 1429 uint8_t HwLinkRate; 1430 uint16_t AttachedDevHandle; 1431 uint32_t PhyInfo; 1432 uint32_t AttachedDeviceInfo; 1433 uint16_t OwnerDevHandle; 1434 uint8_t ChangeCount; 1435 uint8_t Reserved3; 1436 uint8_t PhyIdentifier; 1437 uint8_t AttachedPhyIdentifier; 1438 uint8_t NumTableEntriesProg; 1439 uint8_t DiscoveryInfo; 1440 uint32_t Reserved4; 1441} config_page_sas_expander_1_t; 1442 1443#define MPI_SASEXPANDER1_PAGEVERSION 0x00 1444 1445/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 1446 1447/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 1448 1449/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 1450 1451/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 1452 1453/* values for SAS Expander Page 1 DiscoveryInfo field */ 1454#define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE 0x02 1455#define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES 0x01 1456 1457typedef struct config_page_sas_device_0 { 1458 config_extended_page_header_t Header; 1459 uint16_t Slot; 1460 uint16_t EnclosureHandle; 1461 uint64_t SASAddress; 1462 uint16_t ParentDevHandle; 1463 uint8_t PhyNum; 1464 uint8_t AccessStatus; 1465 uint16_t DevHandle; 1466 uint8_t TargetID; 1467 uint8_t Bus; 1468 uint32_t DeviceInfo; 1469 uint16_t Flags; 1470 uint8_t PhysicalPort; 1471 uint8_t Reserved2; 1472} config_page_sas_device_0_t; 1473 1474#define MPI_SASDEVICE0_PAGEVERSION 0x00 1475 1476#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT 0x04 1477#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED 0x02 1478#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT 0x01 1479 1480typedef struct config_page_sas_device_1 { 1481 config_extended_page_header_t Header; 1482 uint32_t Reserved1; 1483 uint64_t SASAddress; 1484 uint32_t Reserved2; 1485 uint16_t DevHandle; 1486 uint8_t TargetID; 1487 uint8_t Bus; 1488 uint8_t InitialRegDeviceFIS[20]; 1489} config_page_sas_device_1_t; 1490 1491#define MPI_SASDEVICE1_PAGEVERSION 0x00 1492 1493typedef struct config_page_sas_phy_0 { 1494 config_extended_page_header_t Header; 1495 uint32_t Reserved1; 1496 uint64_t SASAddress; 1497 uint16_t AttachedDevHandle; 1498 uint8_t AttachedPhyIdentifier; 1499 uint8_t Reserved2; 1500 uint32_t AttachedDeviceInfo; 1501 uint8_t ProgrammedLinkRate; 1502 uint8_t HwLinkRate; 1503 uint8_t ChangeCount; 1504 uint8_t Reserved3; 1505 uint32_t PhyInfo; 1506} config_page_sas_phy_0_t; 1507 1508#define MPI_SASPHY0_PAGEVERSION 0x00 1509 1510#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK 0xF0 1511#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE 0x00 1512#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 0x80 1513#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 0x90 1514#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK 0x0F 1515#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE 0x00 1516#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 0x08 1517#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 0x09 1518 1519#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK 0xF0 1520#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 0x80 1521#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 0x90 1522#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK 0x0F 1523#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 0x08 1524#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 0x09 1525 1526#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE 0x00004000 1527#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR 0x00002000 1528#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY 0x00001000 1529 1530#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME 0x00000F00 1531#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME 8 1532 1533#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE 0x000000F0 1534#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING 0x00000000 1535#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING 0x00000010 1536#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING 0x00000020 1537 1538#define MPI_SAS_PHY0_DEVINFO_SATA_DEVICE 0x00000080 1539 1540#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE 0x0000000F 1541#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE 0x00000000 1542#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED 0x00000001 1543#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED 0x00000002 1544#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE 0x00000003 1545#define MPI_SAS_PHY0_PHYINFO_RATE_1_5 0x00000008 1546#define MPI_SAS_PHY0_PHYINFO_RATE_3_0 0x00000009 1547 1548typedef struct config_page_sas_phy_1 { 1549 config_extended_page_header_t Header; 1550 uint32_t Reserved1; 1551 uint32_t InvalidDwordCount; 1552 uint32_t RunningDisparityErrorCount; 1553 uint32_t LossDwordSynchCount; 1554 uint32_t PhyResetProblemCount; 1555} config_page_sas_phy_1_t; 1556 1557#define MPI_SASPHY1_PAGEVERSION 0x00 1558 1559#ifdef __cplusplus 1560} 1561#endif 1562 1563#endif /* _SYS_MPI_CNFG_H */ 1564