mpi_cnfg.h revision 5754:669f42f80bce
1/* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6#ifndef _SYS_MPI_CNFG_H 7#define _SYS_MPI_CNFG_H 8 9#pragma ident "%Z%%M% %I% %E% SMI" 10 11#ifdef __cplusplus 12extern "C" { 13#endif 14 15/* 16 * Config Message and Structures 17 */ 18typedef struct config_page_header { 19 uint8_t PageVersion; 20 uint8_t PageLength; 21 uint8_t PageNumber; 22 uint8_t PageType; 23} config_page_header_t; 24 25typedef union config_page_header_union { 26 config_page_header_t Struct; 27 uint8_t Bytes[4]; 28 uint16_t Word16[2]; 29 uint32_t Word32; 30} config_page_header_union_t; 31 32/* 33 * The extended header is used for 1064 and on 34 */ 35typedef struct config_extended_page_header { 36 uint8_t PageVersion; 37 uint8_t Reserved1; 38 uint8_t PageNumber; 39 uint8_t PageType; 40 uint16_t ExtPageLength; 41 uint8_t ExtPageType; 42 uint8_t Reserved2; 43} config_extended_page_header_t; 44 45/* 46 * PageType field values 47 */ 48#define MPI_CONFIG_PAGEATTR_READ_ONLY 0x00 49#define MPI_CONFIG_PAGEATTR_CHANGEABLE 0x10 50#define MPI_CONFIG_PAGEATTR_PERSISTENT 0x20 51#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT 0x30 52#define MPI_CONFIG_PAGEATTR_MASK 0xF0 53 54#define MPI_CONFIG_PAGETYPE_IO_UNIT 0x00 55#define MPI_CONFIG_PAGETYPE_IOC 0x01 56#define MPI_CONFIG_PAGETYPE_BIOS 0x02 57#define MPI_CONFIG_PAGETYPE_SCSI_PORT 0x03 58#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE 0x04 59#define MPI_CONFIG_PAGETYPE_FC_PORT 0x05 60#define MPI_CONFIG_PAGETYPE_FC_DEVICE 0x06 61#define MPI_CONFIG_PAGETYPE_LAN 0x07 62#define MPI_CONFIG_PAGETYPE_RAID_VOLUME 0x08 63#define MPI_CONFIG_PAGETYPE_MANUFACTURING 0x09 64#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK 0x0A 65#define MPI_CONFIG_PAGETYPE_INBAND 0x0B 66#define MPI_CONFIG_PAGETYPE_EXTENDED 0x0F 67#define MPI_CONFIG_PAGETYPE_MASK 0x0F 68 69#define MPI_CONFIG_TYPENUM_MASK 0x0FFF 70 71/* 72 * ExtPageType field values 73 */ 74#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT 0x10 75#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER 0x11 76#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE 0x12 77#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY 0x13 78 79/* 80 * Page Address field values 81 */ 82#define MPI_SCSI_PORT_PGAD_PORT_MASK 0x000000FF 83 84#define MPI_SCSI_DEVICE_TARGET_ID_MASK 0x000000FF 85#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT 0 86#define MPI_SCSI_DEVICE_BUS_MASK 0x0000FF00 87#define MPI_SCSI_DEVICE_BUS_SHIFT 8 88 89#define MPI_FC_PORT_PGAD_PORT_MASK 0xF0000000 90#define MPI_FC_PORT_PGAD_PORT_SHIFT 28 91#define MPI_FC_PORT_PGAD_FORM_MASK 0x0F000000 92#define MPI_FC_PORT_PGAD_FORM_INDEX 0x01000000 93#define MPI_FC_PORT_PGAD_INDEX_MASK 0x0000FFFF 94#define MPI_FC_PORT_PGAD_INDEX_SHIFT 0 95 96#define MPI_FC_DEVICE_PGAD_PORT_MASK 0xF0000000 97#define MPI_FC_DEVICE_PGAD_PORT_SHIFT 28 98#define MPI_FC_DEVICE_PGAD_FORM_MASK 0x0F000000 99#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID 0x00000000 100#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK 0xF0000000 101#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT 28 102#define MPI_FC_DEVICE_PGAD_ND_DID_MASK 0x00FFFFFF 103#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT 0 104#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID 0x01000000 105#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK 0x0000FF00 106#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT 8 107#define MPI_FC_DEVICE_PGAD_BT_TID_MASK 0x000000FF 108#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT 0 109 110#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK 0x000000FF 111#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT 0 112 113#define MPI_SAS_EXPAND_PGAD_FORM_MASK 0xF0000000 114#define MPI_SAS_EXPAND_PGAD_FORM_SHIFT 28 115#define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE 0x00000000 116#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM 0x00000001 117#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE 0x00000002 118#define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE 0x0000FFFF 119#define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE 0 120#define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY 0x00FF0000 121#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY 16 122#define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE 0x0000FFFF 123#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE 0 124#define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE 0x0000FFFF 125#define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE 0 126 127#define MPI_SAS_DEVICE_PGAD_FORM_MASK 0xF0000000 128#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT 28 129#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE 0x00000000 130#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID 0x00000001 131#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE 0x00000002 132#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK 0x0000FFFF 133#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT 0 134#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK 0x0000FF00 135#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT 8 136#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK 0x000000FF 137#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT 0 138#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK 0x0000FFFF 139#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT 0 140 141#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK 0x000000FF 142#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT 0 143 144/* 145 * Config Message 146 */ 147typedef struct msg_config { 148 uint8_t Action; 149 uint8_t Reserved; 150 uint8_t ChainOffset; 151 uint8_t Function; 152 uint16_t ExtPageLength; /* 1064 only */ 153 uint8_t ExtPageType; /* 1064 only */ 154 uint8_t MsgFlags; 155 uint32_t MsgContext; 156 uint8_t Reserved2[8]; 157 config_page_header_t Header; 158 uint32_t PageAddress; 159 sge_io_union_t PageBufferSGE; 160} msg_config_t; 161 162/* 163 * Action field values 164 */ 165#define MPI_CONFIG_ACTION_PAGE_HEADER 0x00 166#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT 0x01 167#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT 0x02 168#define MPI_CONFIG_ACTION_PAGE_DEFAULT 0x03 169#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM 0x04 170#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT 0x05 171#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM 0x06 172 173/* 174 * Config Reply Message 175 */ 176typedef struct msg_config_reply { 177 uint8_t Action; 178 uint8_t Reserved; 179 uint8_t MsgLength; 180 uint8_t Function; 181 uint16_t ExtPageLength; 182 uint8_t ExtPageType; 183 uint8_t MsgFlags; 184 uint32_t MsgContext; 185 uint8_t Reserved2[2]; 186 uint16_t IOCStatus; 187 uint32_t IOCLogInfo; 188 config_page_header_t Header; 189} msg_config_reply_t; 190 191/* 192 * Manufacturing Config pages 193 */ 194#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC 0x1000 195#define MPI_MANUFACTPAGE_DEVICEID_FC909 0x0621 196#define MPI_MANUFACTPAGE_DEVICEID_FC919 0x0624 197#define MPI_MANUFACTPAGE_DEVICEID_FC929 0x0622 198#define MPI_MANUFACTPAGE_DEVICEID_FC919X 0x0628 199#define MPI_MANUFACTPAGE_DEVICEID_FC929X 0x0626 200#define MPI_MANUFACTPAGE_DEVID_53C1030 0x0030 201#define MPI_MANUFACTPAGE_DEVID_53C1030ZC 0x0031 202#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 0x0032 203#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 0x0033 204#define MPI_MANUFACTPAGE_DEVID_53C1035 0x0040 205#define MPI_MANUFACTPAGE_DEVID_53C1035ZC 0x0041 206#define MPI_MANUFACTPAGE_DEVID_SAS1064 0x0050 207 208typedef struct config_page_manufacturing_0 { 209 config_page_header_t Header; 210 uint8_t ChipName[16]; 211 uint8_t ChipRevision[8]; 212 uint8_t BoardName[16]; 213 uint8_t BoardAssembly[16]; 214 uint8_t BoardTracerNumber[16]; 215} config_page_manufacturing_0_t; 216 217#define MPI_MANUFACTURING0_PAGEVERSION 0x00 218 219typedef struct config_page_manufacturing_1 { 220 config_page_header_t Header; 221 uint8_t VPD[256]; 222} config_page_manufacturing_1_t; 223 224#define MPI_MANUFACTURING1_PAGEVERSION 0x00 225 226typedef struct mpi_chip_revision_id { 227 uint16_t DeviceID; 228 uint8_t PCIRevisionID; 229 uint8_t Reserved; 230} mpi_chip_revision_id_t; 231 232/* 233 * Host code (drivers, BIOS, utilities, etc.) should leave this 234 * define set to one and check Header.PageLength at runtime. 235 */ 236#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 237#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 1 238#endif 239 240typedef struct config_page_manufacturing_2 { 241 config_page_header_t Header; 242 mpi_chip_revision_id_t ChipId; 243 uint32_t HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS]; 244} config_page_manufacturing_2_t; 245 246#define MPI_MANUFACTURING2_PAGEVERSION 0x00 247 248/* 249 * Host code (drivers, BIOS, utilities, etc.) should leave this 250 * define set to one and check Header.PageLength at runtime. 251 */ 252#ifndef MPI_MAN_PAGE_3_INFO_WORDS 253#define MPI_MAN_PAGE_3_INFO_WORDS 1 254#endif 255 256typedef struct config_page_manufacturing_3 { 257 config_page_header_t Header; 258 mpi_chip_revision_id_t ChipId; 259 uint32_t Info[MPI_MAN_PAGE_3_INFO_WORDS]; 260} config_page_manufacturing_3_t; 261 262#define MPI_MANUFACTURING3_PAGEVERSION 0x00 263 264typedef struct config_page_manufacturing_4 { 265 config_page_header_t Header; 266 uint32_t Reserved1; 267 uint8_t InfoOffset0; 268 uint8_t InfoSize0; 269 uint8_t InfoOffset1; 270 uint8_t InfoSize1; 271 uint8_t InquirySize; 272 uint8_t Flags; 273 uint16_t Reserved2; 274 uint8_t InquiryData[56]; 275 uint32_t ISVolumeSettings; 276 uint32_t IMEVolumeSettings; 277 uint32_t IMVolumeSettings; 278} config_page_manufacturing_4_t; 279 280#define MPI_MANUFACTURING4_PAGEVERSION 0x01 281#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA 0x01 282 283typedef struct config_page_manufacturing_5 { 284 config_page_header_t Header; 285 uint64_t BaseWWID; 286} config_page_manufacturing_5_t; 287 288#define MPI_MANUFACTURING5_PAGEVERSION 0x00 289 290typedef struct config_page_manufacturing_6 { 291 config_page_header_t Header; 292 uint32_t ProductSpecificInfo; 293} config_page_manufacturing_6_t; 294 295#define MPI_MANUFACTURING6_PAGEVERSION 0x00 296 297/* 298 * IO Unit Config Pages 299 */ 300typedef struct config_page_io_unit_0 { 301 config_page_header_t Header; 302 uint64_t UniqueValue; 303} config_page_io_unit_0_t; 304 305#define MPI_IOUNITPAGE0_PAGEVERSION 0x00 306 307typedef struct config_page_io_unit_1 { 308 config_page_header_t Header; 309 uint32_t Flags; 310} config_page_io_unit_1_t; 311 312#define MPI_IOUNITPAGE1_PAGEVERSION 0x01 313 314#define MPI_IOUNITPAGE1_MULTI_FUNCTION 0x00000000 315#define MPI_IOUNITPAGE1_SINGLE_FUNCTION 0x00000001 316#define MPI_IOUNITPAGE1_MULTI_PATHING 0x00000002 317#define MPI_IOUNITPAGE1_SINGLE_PATHING 0x00000000 318#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID 0x00000004 319#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING 0x00000020 320#define MPI_IOUNITPAGE1_DISABLE_IR 0x00000040 321#define MPI_IOUNITPAGE1_FORCE_32 0x00000080 322#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE 0x00000100 323 324typedef struct mpi_adapter_info { 325 uint8_t PciBusNumber; 326 uint8_t PciDeviceAndFunctionNumber; 327 uint16_t AdapterFlags; 328} mpi_adapter_info_t; 329 330#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED 0x0001 331#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS 0x0002 332 333typedef struct config_page_io_unit_2 { 334 config_page_header_t Header; 335 uint32_t Flags; 336 uint32_t BiosVersion; 337 mpi_adapter_info_t AdapterOrder[4]; 338} config_page_io_unit_2_t; 339 340#define MPI_IOUNITPAGE2_PAGEVERSION 0x00 341 342#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR 0x00000002 343#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE 0x00000004 344#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE 0x00000008 345#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 0x00000010 346 347#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK 0x000000E0 348#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY 0x00000000 349#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY 0x00000020 350#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY 0x00000040 351 352/* 353 * Host code (drivers, BIOS, utilities, etc.) should leave this 354 * define set to one and check Header.PageLength at runtime. 355 */ 356#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 357#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 1 358#endif 359 360typedef struct config_page_io_unit_3 { 361 config_page_header_t Header; 362 uint8_t GPIOCount; 363 uint8_t Reserved1; 364 uint16_t Reserved2; 365 uint16_t GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; 366} config_page_io_unit_3_t; 367 368#define MPI_IOUNITPAGE3_PAGEVERSION 0x01 369 370#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK 0xFC 371#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT 2 372#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF 0x00 373#define MPI_IOUNITPAGE3_GPIO_SETTING_ON 0x01 374 375/* 376 * IOC Config Pages 377 */ 378typedef struct config_page_ioc_0 { 379 config_page_header_t Header; 380 uint32_t TotalNVStore; 381 uint32_t FreeNVStore; 382 uint16_t VendorID; 383 uint16_t DeviceID; 384 uint8_t RevisionID; 385 uint8_t Reserved[3]; 386 uint32_t ClassCode; 387 uint16_t SubsystemVendorID; 388 uint16_t SubsystemID; 389} config_page_ioc_0_t; 390 391#define MPI_IOCPAGE0_PAGEVERSION 0x01 392 393typedef struct config_page_ioc_1 { 394 config_page_header_t Header; 395 uint32_t Flags; 396 uint32_t CoalescingTimeout; 397 uint8_t CoalescingDepth; 398 uint8_t PCISlotNum; 399 uint8_t Reserved[2]; 400} config_page_ioc_1_t; 401 402#define MPI_IOCPAGE1_PAGEVERSION 0x01 403#define MPI_IOCPAGE1_EEDP_HOST_SUPPORTS_DIF 0x08000000 404#define MPI_IOCPAGE1_EEDP_MODE_MASK 0x07000000 405#define MPI_IOCPAGE1_EEDP_MODE_OFF 0x00000000 406#define MPI_IOCPAGE1_EEDP_MODE_T10 0x01000000 407#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 0x02000000 408#define MPI_IOCPAGE1_EEDP_MODE_LSI_2 0x03000000 409#define MPI_IOCPAGE1_REPLY_COALESCING 0x00000001 410#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN 0xFF 411 412typedef struct config_page_ioc_2_raid_vol { 413 uint8_t VolumeID; 414 uint8_t VolumeBus; 415 uint8_t VolumeIOC; 416 uint8_t VolumePageNumber; 417 uint8_t VolumeType; 418 uint8_t Flags; 419 uint16_t Reserved3; 420} config_page_ioc_2_raid_vol_t; 421 422#define MPI_RAID_VOL_TYPE_IS 0x00 423#define MPI_RAID_VOL_TYPE_IME 0x01 424#define MPI_RAID_VOL_TYPE_IM 0x02 425#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE 0x08 426 427/* 428 * Host code (drivers, BIOS, utilities, etc.) should leave this 429 * define set to one and check Header.PageLength at runtime. 430 */ 431#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 432#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1 433#endif 434 435typedef struct config_page_ioc_2 { 436 config_page_header_t Header; 437 uint32_t CapabilitiesFlags; 438 uint8_t NumActiveVolumes; 439 uint8_t MaxVolumes; 440 uint8_t NumActivePhysDisks; 441 uint8_t MaxPhysDisks; 442 config_page_ioc_2_raid_vol_t RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX]; 443} config_page_ioc_2_t; 444 445#define MPI_IOCPAGE2_PAGEVERSION 0x02 446 447/* 448 * IOC Page 2 Capabilities flags 449 */ 450#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT 0x00000001 451#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT 0x00000002 452#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT 0x00000004 453#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT 0x20000000 454#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT 0x40000000 455#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT 0x80000000 456 457typedef struct ioc_3_phys_disk { 458 uint8_t PhysDiskID; 459 uint8_t PhysDiskBus; 460 uint8_t PhysDiskIOC; 461 uint8_t PhysDiskNum; 462} ioc_3_phys_disk_t; 463 464/* 465 * Host code (drivers, BIOS, utilities, etc.) should leave this 466 * define set to one and check Header.PageLength at runtime. 467 */ 468#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 469#define MPI_IOC_PAGE_3_PHYSDISK_MAX 1 470#endif 471 472typedef struct config_page_ioc_3 { 473 config_page_header_t Header; 474 uint8_t NumPhysDisks; 475 uint8_t Reserved1; 476 uint16_t Reserved2; 477 ioc_3_phys_disk_t PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; 478} config_page_ioc_3_t; 479 480#define MPI_IOCPAGE3_PAGEVERSION 0x00 481 482typedef struct ioc_4_sep { 483 uint8_t SEPTargetID; 484 uint8_t SEPBus; 485 uint16_t Reserved; 486} ioc_4_sep_t; 487 488/* 489 * Host code (drivers, BIOS, utilities, etc.) should leave this 490 * define set to one and check Header.PageLength at runtime. 491 */ 492#ifndef MPI_IOC_PAGE_4_SEP_MAX 493#define MPI_IOC_PAGE_4_SEP_MAX 1 494#endif 495 496typedef struct config_page_ioc_4 { 497 config_page_header_t Header; 498 uint8_t ActiveSEP; 499 uint8_t MaxSEP; 500 uint16_t Reserved1; 501 ioc_4_sep_t SEP[MPI_IOC_PAGE_4_SEP_MAX]; 502} config_page_ioc_4_t; 503 504#define MPI_IOCPAGE4_PAGEVERSION 0x00 505 506/* 507 * SCSI Port Config Pages 508 */ 509typedef struct config_page_scsi_port_0 { 510 config_page_header_t Header; 511 uint32_t Capabilities; 512 uint32_t PhysicalInterface; 513} config_page_scsi_port_0_t; 514 515#define MPI_SCSIPORTPAGE0_PAGEVERSION 0x01 516 517/* 518 * Capabilities 519 */ 520#define MPI_SCSIPORTPAGE0_CAP_IU 0x00000001 521#define MPI_SCSIPORTPAGE0_CAP_DT 0x00000002 522#define MPI_SCSIPORTPAGE0_CAP_QAS 0x00000004 523#define MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS 0x00000008 524#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK 0x0000FF00 525#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK 0x00FF0000 526#define MPI_SCSIPORTPAGE0_CAP_WIDE 0x20000000 527#define MPI_SCSIPORTPAGE0_CAP_AIP 0x80000000 528 529/* 530 * Physical Interface 531 */ 532#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK 0x00000003 533#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD 0x01 534#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE 0x02 535#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD 0x03 536 537typedef struct config_page_scsi_port_1 { 538 config_page_header_t Header; 539 uint32_t Configuration; 540 uint32_t OnBusTimerValue; 541} config_page_scsi_port_1_t; 542 543#define MPI_SCSIPORTPAGE1_PAGEVERSION 0x02 544 545#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK 0x000000FF 546#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK 0xFFFF0000 547 548typedef struct mpi_device_info { 549 uint8_t Timeout; 550 uint8_t SyncFactor; 551 uint16_t DeviceFlags; 552} mpi_device_info_t; 553 554typedef struct config_page_scsi_port_2 { 555 config_page_header_t Header; 556 uint32_t PortFlags; 557 uint32_t PortSettings; 558 mpi_device_info_t DeviceSettings[16]; 559} config_page_scsi_port_2_t; 560 561#define MPI_SCSIPORTPAGE2_PAGEVERSION 0x01 562 563#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW 0x00000001 564#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET 0x00000004 565#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS 0x00000008 566#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE 0x00000010 567 568#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK 0x0000000F 569#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA 0x00000030 570#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA 0x00000000 571#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA 0x00000010 572#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA 0x00000020 573#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA 0x00000030 574#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA 0x000000C0 575#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK 0x00000F00 576#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS 0x00003000 577#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS 0x00000000 578#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS 0x00001000 579#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS 0x00003000 580 581#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE 0x0001 582#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE 0x0002 583#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE 0x0004 584#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE 0x0008 585#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE 0x0010 586#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE 0x0020 587 588/* 589 * SCSI Target Device Config Pages 590 */ 591typedef struct config_page_scsi_device_0 { 592 config_page_header_t Header; 593 uint32_t NegotiatedParameters; 594 uint32_t Information; 595} config_page_scsi_device_0_t; 596 597#define MPI_SCSIDEVPAGE0_PAGEVERSION 0x02 598 599#define MPI_SCSIDEVPAGE0_NP_IU 0x00000001 600#define MPI_SCSIDEVPAGE0_NP_DT 0x00000002 601#define MPI_SCSIDEVPAGE0_NP_QAS 0x00000004 602#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK 0x0000FF00 603#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK 0x00FF0000 604#define MPI_SCSIDEVPAGE0_NP_WIDE 0x20000000 605#define MPI_SCSIDEVPAGE0_NP_AIP 0x80000000 606#define MPI_SCSIDEVPAGE0_NP_IDP 0x08000000 607 608#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED 0x00000001 609#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED 0x00000002 610#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED 0x00000004 611#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED 0x00000008 612 613typedef struct config_page_scsi_device_1 { 614 config_page_header_t Header; 615 uint32_t RequestedParameters; 616 uint32_t Reserved; 617 uint32_t Configuration; 618} config_page_scsi_device_1_t; 619 620#define MPI_SCSIDEVPAGE1_PAGEVERSION 0x03 621 622#define MPI_SCSIDEVPAGE1_RP_IU 0x00000001 623#define MPI_SCSIDEVPAGE1_RP_DT 0x00000002 624#define MPI_SCSIDEVPAGE1_RP_QAS 0x00000004 625#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK 0x0000FF00 626#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK 0x00FF0000 627#define MPI_SCSIDEVPAGE1_RP_WIDE 0x20000000 628#define MPI_SCSIDEVPAGE1_RP_AIP 0x80000000 629#define MPI_SCSIDEVPAGE1_RP_IDP 0x08000000 630 631#define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK 0x00000003 632#define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK 0x00000300 633 634#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 0x00000002 635#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED 0x00000004 636 637typedef struct config_page_scsi_device_2 { 638 config_page_header_t Header; 639 uint32_t DomainValidation; 640 uint32_t ParityPipeSelect; 641 uint32_t DataPipeSelect; 642} config_page_scsi_device_2_t; 643 644#define MPI_SCSIDEVPAGE2_PAGEVERSION 0x00 645 646#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE 0x00000010 647#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE 0x00000020 648#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL 0x00000380 649#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL 0x00001C00 650#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL 0x0000E000 651#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST 0x10000000 652#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST 0x20000000 653#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT 0x40000000 654#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT 0x80000000 655 656#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK 0x00000003 657 658#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK 0x00000003 659#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK 0x0000000C 660#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK 0x00000030 661#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK 0x000000C0 662#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK 0x00000300 663#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK 0x00000C00 664#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK 0x00003000 665#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK 0x0000C000 666#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK 0x00030000 667#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK 0x000C0000 668#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK 0x00300000 669#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK 0x00C00000 670#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK 0x03000000 671#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK 0x0C000000 672#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK 0x30000000 673#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK 0xC0000000 674 675/* 676 * FC Port Config Pages 677 */ 678typedef struct config_page_fc_port_0 { 679 config_page_header_t Header; 680 uint32_t Flags; 681 uint8_t MPIPortNumber; 682 uint8_t Reserved[3]; 683 uint32_t PortIdentifier; 684 uint64_t WWNN; 685 uint64_t WWPN; 686 uint32_t SupportedServiceClass; 687 uint32_t SupportedSpeeds; 688 uint32_t CurrentSpeed; 689 uint32_t MaxFrameSize; 690 uint64_t FabricWWNN; 691 uint64_t FabricWWPN; 692 uint32_t DiscoveredPortsCount; 693 uint32_t MaxInitiators; 694} config_page_fc_port_0_t; 695 696#define MPI_FCPORTPAGE0_PAGEVERSION 0x01 697 698#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK 0x0000000F 699#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT \ 700 MPI_PORTFACTS_PROTOCOL_INITIATOR 701#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG \ 702 MPI_PORTFACTS_PROTOCOL_TARGET 703#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN \ 704 MPI_PORTFACTS_PROTOCOL_LAN 705#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR \ 706 MPI_PORTFACTS_PROTOCOL_LOGBUSADDR 707 708#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED 0x00000010 709#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED 0x00000020 710#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID 0x00000030 711 712#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK 0x00000F00 713#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT 0x00000000 714#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT 0x00000100 715#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP 0x00000200 716#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT 0x00000400 717#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP 0x00000800 718 719#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK 0x00000F00 720#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT 0x00000000 721#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT 0x00000100 722#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP 0x00000200 723#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT 0x00000400 724#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP 0x00000800 725 726#define MPI_FCPORTPAGE0_LTYPE_RESERVED 0x00 727#define MPI_FCPORTPAGE0_LTYPE_OTHER 0x01 728#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN 0x02 729#define MPI_FCPORTPAGE0_LTYPE_COPPER 0x03 730#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 0x04 731#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 0x05 732#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI 0x06 733#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI 0x07 734#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI 0x08 735#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI 0x09 736#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE 0x0A 737#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE 0x0B 738#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE 0x0C 739#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE 0x0D 740#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE 0x0E 741#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE 0x0F 742 743#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN 0x01 744#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE 0x02 745#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE 0x03 746#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED 0x04 747#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST 0x05 748#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN 0x06 749#define MPI_FCPORTPAGE0_PORTSTATE_ERROR 0x07 750#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK 0x08 751 752#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 0x00000001 753#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 0x00000002 754#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 0x00000004 755 756#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 0x00000001 757#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 0x00000002 758#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 0x00000004 759 760#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT \ 761 MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 762#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT \ 763 MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 764#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT \ 765 MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 766 767typedef struct config_page_fc_port_1 { 768 config_page_header_t Header; 769 uint32_t Flags; 770 uint64_t NoSEEPROMWWNN; 771 uint64_t NoSEEPROMWWPN; 772 uint8_t HardALPA; 773 uint8_t LinkConfig; 774 uint8_t TopologyConfig; 775 uint8_t Reserved; 776} config_page_fc_port_1_t; 777 778#define MPI_FCPORTPAGE1_PAGEVERSION 0x02 779 780#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN 0x08000000 781#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY 0x04000000 782#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID 0x00000001 783#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN 0x00000000 784 785/* 786 * Flags used for programming protocol modes in NVStore 787 */ 788#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK 0xF0000000 789#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT 28 790#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT \ 791 ((uint32_t)MPI_PORTFACTS_PROTOCOL_INITIATOR << \ 792 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 793#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG \ 794 ((uint32_t)MPI_PORTFACTS_PROTOCOL_TARGET << \ 795 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 796#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN \ 797 ((uint32_t)MPI_PORTFACTS_PROTOCOL_LAN << \ 798 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 799#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR \ 800 ((uint32_t)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << \ 801 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 802 803#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED 0xFF 804 805#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK 0x0F 806#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG 0x00 807#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG 0x01 808#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG 0x02 809#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG 0x03 810#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO 0x0F 811 812#define MPI_FCPORTPAGE1_TOPOLOGY_MASK 0x0F 813#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT 0x01 814#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT 0x02 815#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO 0x0F 816 817typedef struct config_page_fc_port_2 { 818 config_page_header_t Header; 819 uint8_t NumberActive; 820 uint8_t ALPA[127]; 821} config_page_fc_port_2_t; 822 823#define MPI_FCPORTPAGE2_PAGEVERSION 0x01 824 825typedef struct wwn_format { 826 uint64_t WWNN; 827 uint64_t WWPN; 828} wwn_format_t; 829 830typedef union fc_port_persistent_physical_id { 831 wwn_format_t WWN; 832 uint32_t Did; 833} fc_port_persistent_physical_id_t; 834 835typedef struct fc_port_persistent { 836 fc_port_persistent_physical_id_t PhysicalIdentifier; 837 uint8_t TargetID; 838 uint8_t Bus; 839 uint16_t Flags; 840} fc_port_persistent_t; 841 842#define MPI_PERSISTENT_FLAGS_SHIFT 16 843#define MPI_PERSISTENT_FLAGS_ENTRY_VALID 0x0001 844#define MPI_PERSISTENT_FLAGS_SCAN_ID 0x0002 845#define MPI_PERSISTENT_FLAGS_SCAN_LUNS 0x0004 846#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE 0x0008 847#define MPI_PERSISTENT_FLAGS_BY_DID 0x0080 848 849/* 850 * Host code (drivers, BIOS, utilities, etc.) should leave this 851 * define set to one and check Header.PageLength at runtime. 852 */ 853#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 854#define MPI_FC_PORT_PAGE_3_ENTRY_MAX 1 855#endif 856 857typedef struct config_page_fc_port_3 { 858 config_page_header_t Header; 859 fc_port_persistent_t Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; 860} config_page_fc_port_3_t; 861 862#define MPI_FCPORTPAGE3_PAGEVERSION 0x01 863 864typedef struct config_page_fc_port_4 { 865 config_page_header_t Header; 866 uint32_t PortFlags; 867 uint32_t PortSettings; 868} config_page_fc_port_4_t; 869 870#define MPI_FCPORTPAGE4_PAGEVERSION 0x00 871 872#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS 0x00000008 873 874#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA 0x00000030 875#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA 0x00000000 876#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA 0x00000010 877#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA 0x00000020 878#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA 0x00000030 879#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA 0x000000C0 880#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK 0x00000F00 881 882typedef struct config_page_fc_port_5_alias_info { 883 uint8_t Flags; 884 uint8_t AliasAlpa; 885 uint16_t Reserved; 886 uint64_t AliasWWNN; 887 uint64_t AliasWWPN; 888} config_page_fc_port_5_alias_info_t; 889 890/* 891 * Host code (drivers, BIOS, utilities, etc.) should leave this 892 * define set to one and check Header.PageLength at runtime. 893 */ 894#ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 895#define MPI_FC_PORT_PAGE_5_ALIAS_MAX 1 896#endif 897 898typedef struct config_page_fc_port_5 { 899 config_page_header_t Header; 900 config_page_fc_port_5_alias_info_t 901 AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX]; 902} config_page_fc_port_5_t; 903 904#define MPI_FCPORTPAGE5_PAGEVERSION 0x00 905 906#define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID 0x01 907#define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID 0x02 908 909typedef struct config_page_fc_port_6 { 910 config_page_header_t Header; 911 uint32_t Reserved; 912 uint64_t TimeSinceReset; 913 uint64_t TxFrames; 914 uint64_t RxFrames; 915 uint64_t TxWords; 916 uint64_t RxWords; 917 uint64_t LipCount; 918 uint64_t NosCount; 919 uint64_t ErrorFrames; 920 uint64_t DumpedFrames; 921 uint64_t LinkFailureCount; 922 uint64_t LossOfSyncCount; 923 uint64_t LossOfSignalCount; 924 uint64_t PrimativeSeqErrCount; 925 uint64_t InvalidTxWordCount; 926 uint64_t InvalidCrcCount; 927 uint64_t FcpInitiatorIoCount; 928} config_page_fc_port_6_t; 929 930#define MPI_FCPORTPAGE6_PAGEVERSION 0x00 931 932typedef struct config_page_fc_port_7 { 933 config_page_header_t Header; 934 uint32_t Reserved; 935 uint8_t PortSymbolicName[256]; 936} config_page_fc_port_7_t; 937 938#define MPI_FCPORTPAGE7_PAGEVERSION 0x00 939 940typedef struct config_page_fc_port_8 { 941 config_page_header_t Header; 942 uint32_t BitVector[8]; 943} config_page_fc_port_8_t; 944 945#define MPI_FCPORTPAGE8_PAGEVERSION 0x00 946 947typedef struct config_page_fc_port_9 { 948 config_page_header_t Header; 949 uint32_t Reserved; 950 uint64_t GlobalWWPN; 951 uint64_t GlobalWWNN; 952 uint32_t UnitType; 953 uint32_t PhysicalPortNumber; 954 uint32_t NumAttachedNodes; 955 uint16_t IPVersion; 956 uint16_t UDPPortNumber; 957 uint8_t IPAddress[16]; 958 uint16_t Reserved1; 959 uint16_t TopologyDiscoveryFlags; 960} config_page_fc_port_9_t; 961 962#define MPI_FCPORTPAGE9_PAGEVERSION 0x00 963 964/* 965 * FC Device Config Pages 966 */ 967typedef struct config_page_fc_device_0 { 968 config_page_header_t Header; 969 uint64_t WWNN; 970 uint64_t WWPN; 971 uint32_t PortIdentifier; 972 uint8_t Protocol; 973 uint8_t Flags; 974 uint16_t BBCredit; 975 uint16_t MaxRxFrameSize; 976 uint8_t Reserved1; 977 uint8_t PortNumber; 978 uint8_t FcPhLowestVersion; 979 uint8_t FcPhHighestVersion; 980 uint8_t CurrentTargetID; 981 uint8_t CurrentBus; 982} config_page_fc_device_0_t; 983 984#define MPI_FC_DEVICE_PAGE_0_PAGEVERSION 0x02 985 986#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID 0x01 987 988#define MPI_FC_DEVICE_PAGE_0_PROT_IP 0x01 989#define MPI_FC_DEVICE_PAGE_0_PROT_FCP_TARGET 0x02 990#define MPI_FC_DEVICE_PAGE_0_PROT_FCP_INITIATOR 0x04 991 992#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK \ 993 (MPI_FC_DEVICE_PGAD_PORT_MASK) 994#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK \ 995 (MPI_FC_DEVICE_PGAD_FORM_MASK) 996#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID \ 997 (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 998#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID \ 999 (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1000#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK \ 1001 (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1002#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK \ 1003 (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1004#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT \ 1005 (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1006#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK \ 1007 (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1008 1009/* 1010 * RAID Volume Config Pages 1011 */ 1012typedef struct raid_vol0_phys_disk { 1013 uint16_t Reserved; 1014 uint8_t PhysDiskMap; 1015 uint8_t PhysDiskNum; 1016} raid_vol0_phys_disk_t; 1017 1018#define MPI_RAIDVOL0_PHYSDISK_PRIMARY 0x01 1019#define MPI_RAIDVOL0_PHYSDISK_SECONDARY 0x02 1020 1021typedef struct raid_vol0_status { 1022 uint8_t Flags; 1023 uint8_t State; 1024 uint16_t Reserved; 1025} raid_vol0_status_t; 1026 1027/* 1028 * RAID Volume Page 0 VolumeStatus defines 1029 */ 1030#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED 0x01 1031#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED 0x02 1032#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 0x04 1033#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 0x08 1034 1035#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL 0x00 1036#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED 0x01 1037#define MPI_RAIDVOL0_STATUS_STATE_FAILED 0x02 1038 1039typedef struct raid_vol0_settings { 1040 uint16_t Settings; 1041 uint8_t HotSparePool; 1042 uint8_t Reserved; 1043} raid_vol0_settings_t; 1044 1045/* 1046 * RAID Volume Page 0 VolumeSettings defines 1047 */ 1048#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE 0x0001 1049#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART 0x0002 1050#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE 0x0004 1051#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC 0x0008 1052#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX 0x0010 1053#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS 0x8000 1054 1055/* 1056 * RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk 1057 */ 1058#define MPI_RAID_HOT_SPARE_POOL_0 0x01 1059#define MPI_RAID_HOT_SPARE_POOL_1 0x02 1060#define MPI_RAID_HOT_SPARE_POOL_2 0x04 1061#define MPI_RAID_HOT_SPARE_POOL_3 0x08 1062#define MPI_RAID_HOT_SPARE_POOL_4 0x10 1063#define MPI_RAID_HOT_SPARE_POOL_5 0x20 1064#define MPI_RAID_HOT_SPARE_POOL_6 0x40 1065#define MPI_RAID_HOT_SPARE_POOL_7 0x80 1066 1067/* 1068 * Host code (drivers, BIOS, utilities, etc.) should leave this 1069 * define set to one and check Header.PageLength at runtime. 1070 */ 1071#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1072#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1 1073#endif 1074 1075typedef struct config_page_raid_vol_0 { 1076 config_page_header_t Header; 1077 uint8_t VolumeID; 1078 uint8_t VolumeBus; 1079 uint8_t VolumeIOC; 1080 uint8_t VolumeType; 1081 raid_vol0_status_t VolumeStatus; 1082 raid_vol0_settings_t VolumeSettings; 1083 uint32_t MaxLBA; 1084 uint32_t Reserved1; 1085 uint32_t StripeSize; 1086 uint32_t Reserved2; 1087 uint32_t Reserved3; 1088 uint8_t NumPhysDisks; 1089 uint8_t Reserved4; 1090 uint8_t ResyncRate; 1091 uint8_t Reserved5; 1092 raid_vol0_phys_disk_t PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX]; 1093} config_page_raid_vol_0_t; 1094 1095#define MPI_RAIDVOLPAGE0_PAGEVERSION 0x00 1096 1097/* 1098 * RAID Physical Disk Config Pages 1099 */ 1100typedef struct raid_phys_disk0_error_data { 1101 uint8_t ErrorCdbByte; 1102 uint8_t ErrorSenseKey; 1103 uint16_t Reserved; 1104 uint16_t ErrorCount; 1105 uint8_t ErrorASC; 1106 uint8_t ErrorASCQ; 1107 uint16_t SmartCount; 1108 uint8_t SmartASC; 1109 uint8_t SmartASCQ; 1110} raid_phys_disk0_error_data_t; 1111 1112typedef struct raid_phys_disk_inquiry_data { 1113 uint8_t VendorID[8]; 1114 uint8_t ProductID[16]; 1115 uint8_t ProductRevLevel[4]; 1116 uint8_t Info[32]; 1117} raid_phys_disk0_inquiry_data_t; 1118 1119typedef struct raid_phys_disk0_settings { 1120 uint8_t SepID; 1121 uint8_t SepBus; 1122 uint8_t HotSparePool; 1123 uint8_t PhysDiskSettings; 1124} raid_phys_disk0_settings_t; 1125 1126typedef struct raid_phys_disk0_status { 1127 uint8_t Flags; 1128 uint8_t State; 1129 uint16_t Reserved; 1130} raid_phys_disk0_status_t; 1131 1132/* 1133 * RAID Volume 2 IM Physical Disk DiskStatus flags 1134 */ 1135#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 0x01 1136#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED 0x02 1137 1138#define MPI_PHYSDISK0_STATUS_ONLINE 0x00 1139#define MPI_PHYSDISK0_STATUS_MISSING 0x01 1140#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE 0x02 1141#define MPI_PHYSDISK0_STATUS_FAILED 0x03 1142#define MPI_PHYSDISK0_STATUS_INITIALIZING 0x04 1143#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED 0x05 1144#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED 0x06 1145#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE 0xFF 1146 1147typedef struct config_page_raid_phys_disk_0 { 1148 config_page_header_t Header; 1149 uint8_t PhysDiskID; 1150 uint8_t PhysDiskBus; 1151 uint8_t PhysDiskIOC; 1152 uint8_t PhysDiskNum; 1153 raid_phys_disk0_settings_t PhysDiskSettings; 1154 uint32_t Reserved1; 1155 uint32_t Reserved2; 1156 uint32_t Reserved3; 1157 uint8_t DiskIdentifier[16]; 1158 raid_phys_disk0_inquiry_data_t InquiryData; 1159 raid_phys_disk0_status_t PhysDiskStatus; 1160 uint32_t MaxLBA; 1161 raid_phys_disk0_error_data_t ErrorData; 1162} config_page_raid_phys_disk_0_t; 1163 1164#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION 0x00 1165 1166/* 1167 * LAN Config Pages 1168 */ 1169typedef struct config_page_lan_0 { 1170 config_page_header_t Header; 1171 uint16_t TxRxModes; 1172 uint16_t Reserved; 1173 uint32_t PacketPrePad; 1174} config_page_lan_0_t; 1175 1176#define MPI_LAN_PAGE0_PAGEVERSION 0x01 1177 1178#define MPI_LAN_PAGE0_RETURN_LOOPBACK 0x0000 1179#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK 0x0001 1180#define MPI_LAN_PAGE0_LOOPBACK_MASK 0x0001 1181 1182typedef struct config_page_lan_1 { 1183 config_page_header_t Header; 1184 uint16_t Reserved; 1185 uint8_t CurrentDeviceState; 1186 uint8_t Reserved1; 1187 uint32_t MinPacketSize; 1188 uint32_t MaxPacketSize; 1189 uint32_t HardwareAddressLow; 1190 uint32_t HardwareAddressHigh; 1191 uint32_t MaxWireSpeedLow; 1192 uint32_t MaxWireSpeedHigh; 1193 uint32_t BucketsRemaining; 1194 uint32_t MaxReplySize; 1195 uint32_t NegWireSpeedLow; 1196 uint32_t NegWireSpeedHigh; 1197} config_page_lan_1_t; 1198 1199#define MPI_LAN_PAGE1_PAGEVERSION 0x03 1200 1201#define MPI_LAN_PAGE1_DEV_STATE_RESET 0x00 1202#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL 0x01 1203 1204/* 1205 * Inband config pages 1206 */ 1207typedef struct config_page_inband_0 { 1208 config_page_header_t Header; 1209 mpi_version_format_t InbandVersion; 1210 uint16_t MaximumBuffers; 1211 uint16_t Reserved1; 1212} config_page_inband_0_t; 1213 1214/* 1215 * SAS IO Unit config pages 1216 */ 1217typedef struct mpi_sas_io_unit0_phy_data { 1218 uint8_t Port; 1219 uint8_t PortFlags; 1220 uint8_t PhyFlags; 1221 uint8_t NegotiatedLinkRate; 1222 uint32_t ControllerPhyDeviceInfo; 1223 uint16_t AttachedDeviceHandle; 1224 uint16_t ControllerDevHandle; 1225 uint32_t Reserved2; 1226} mpi_sas_io_unit0_phy_data_t; 1227 1228/* 1229 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1230 * one and check Header.PageLength at runtime. 1231 */ 1232#ifndef MPI_SAS_IOUNIT0_PHY_MAX 1233#define MPI_SAS_IOUNIT0_PHY_MAX 1 1234#endif 1235 1236typedef struct config_page_sas_io_unit_0 { 1237 config_extended_page_header_t Header; 1238 uint32_t Reserved1; 1239 uint8_t NumPhys; 1240 uint8_t Reserved2; 1241 uint16_t Reserved3; 1242 mpi_sas_io_unit0_phy_data_t PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; 1243} config_page_sas_io_unit_0_t; 1244 1245#define MPI_SASIOUNITPAGE0_PAGEVERSION 0x00 1246 1247#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS 0x08 1248#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM 0x00 1249#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM 0x04 1250#define MPI_SAS_IOUNIT0_PORT_FLAGS_WAIT_FOR_PORTENABLE 0x02 1251#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG 0x01 1252 1253#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED 0x04 1254#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT 0x02 1255#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT 0x01 1256 1257#define MPI_SAS_IOUNIT0_RATE_UNKNOWN 0x00 1258#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED 0x01 1259#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION 0x02 1260#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE 0x03 1261#define MPI_SAS_IOUNIT0_RATE_1_5 0x08 1262#define MPI_SAS_IOUNIT0_RATE_3_0 0x09 1263 1264typedef struct mpi_sas_io_unit1_phy_data { 1265 uint8_t Port; 1266 uint8_t PortFlags; 1267 uint8_t PhyFlags; 1268 uint8_t MaxMinLinkRate; 1269 uint32_t ControllerPhyDeviceInfo; 1270 uint32_t Reserved1; 1271} mpi_sas_io_unit1_phy_data_t; 1272 1273/* 1274 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1275 * one and check Header.PageLength at runtime. 1276 */ 1277#ifndef MPI_SAS_IOUNIT1_PHY_MAX 1278#define MPI_SAS_IOUNIT1_PHY_MAX 1 1279#endif 1280 1281typedef struct config_page_sas_io_unit_1 { 1282 config_extended_page_header_t Header; 1283 uint32_t Reserved1; 1284 uint8_t NumPhys; 1285 uint8_t Reserved2; 1286 uint16_t Reserved3; 1287 mpi_sas_io_unit1_phy_data_t PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; 1288} config_page_sas_io_unit_1_t; 1289 1290#define MPI_SASIOUNITPAGE1_PAGEVERSION 0x00 1291 1292#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM 0x00 1293#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM 0x04 1294#define MPI_SAS_IOUNIT1_PORT_FLAGS_WAIT_FOR_PORTENABLE 0x02 1295#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG 0x01 1296 1297#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE 0x04 1298#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT 0x02 1299#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT 0x01 1300 1301#define MPI_SAS_IOUNIT1_MAX_RATE_MASK 0xF0 1302#define MPI_SAS_IOUNIT1_MAX_RATE_1_5 0x80 1303#define MPI_SAS_IOUNIT1_MAX_RATE_3_0 0x90 1304#define MPI_SAS_IOUNIT1_MIN_RATE_MASK 0x0F 1305#define MPI_SAS_IOUNIT1_MIN_RATE_1_5 0x08 1306#define MPI_SAS_IOUNIT1_MIN_RATE_3_0 0x09 1307 1308typedef struct config_page_sas_io_unit_2 { 1309 config_extended_page_header_t Header; 1310 uint32_t Reserved1; 1311 uint16_t MaxPersistentIDs; 1312 uint16_t NumPersistentIDsUsed; 1313 uint8_t Status; 1314 uint8_t Flags; 1315 uint16_t Reserved2; 1316} config_page_sas_io_unit_2_t; 1317 1318#define MPI_SASIOUNITPAGE2_PAGEVERSION 0x00 1319 1320#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS 0x02 1321#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS 0x01 1322 1323#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS 0x01 1324 1325 1326typedef struct config_page_sas_io_unit_3 { 1327 config_extended_page_header_t Header; 1328 uint32_t Reserved1; 1329 uint32_t MaxInvalidDwordCount; 1330 uint32_t InvalidDwordCountTime; 1331 uint32_t MaxRunningDisparityErrorCount; 1332 uint32_t RunningDisparityErrorTime; 1333 uint32_t MaxLossDwordSynchCount; 1334 uint32_t LossDwordSynchCountTime; 1335 uint32_t MaxPhyResetProblemCount; 1336 uint32_t PhyResetProblemTime; 1337} config_page_sas_io_unit_3_t; 1338 1339#define MPI_SASIOUNITPAGE3_PAGEVERSION 0x00 1340 1341typedef struct config_page_sas_expander_0 { 1342 config_extended_page_header_t Header; 1343 uint8_t PhysicalPort; 1344 uint8_t Reserved1; 1345 uint16_t EnclosureHandle; 1346 uint64_t SASAddress; 1347 uint32_t Reserved2; 1348 uint16_t DevHandle; 1349 uint16_t ParentDevHandle; 1350 uint16_t ExpanderChangeCount; 1351 uint16_t ExpanderRouteIndexes; 1352 uint8_t NumPhys; 1353 uint8_t SASLevel; 1354 uint8_t Flags; 1355 uint8_t Reserved3; 1356} config_page_sas_expander_0_t; 1357 1358#define MPI_SASEXPANDER0_PAGEVERSION 0x00 1359 1360#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG 0x02 1361#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS 0x01 1362 1363 1364typedef struct config_page_sas_expander_1 { 1365 config_extended_page_header_t Header; 1366 uint32_t Reserved1; 1367 uint8_t NumPhys; 1368 uint8_t Phy; 1369 uint16_t Reserved2; 1370 uint8_t ProgrammedLinkRate; 1371 uint8_t HwLinkRate; 1372 uint16_t AttachedDevHandle; 1373 uint32_t PhyInfo; 1374 uint32_t AttachedDeviceInfo; 1375 uint16_t OwnerDevHandle; 1376 uint8_t ChangeCount; 1377 uint8_t Reserved3; 1378 uint8_t PhyIdentifier; 1379 uint8_t AttachedPhyIdentifier; 1380 uint8_t NumTableEntriesProg; 1381 uint8_t DiscoveryInfo; 1382 uint32_t Reserved4; 1383} config_page_sas_expander_1_t; 1384 1385#define MPI_SASEXPANDER1_PAGEVERSION 0x00 1386 1387/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 1388 1389/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 1390 1391/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 1392 1393/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 1394 1395/* values for SAS Expander Page 1 DiscoveryInfo field */ 1396#define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE 0x02 1397#define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES 0x01 1398 1399typedef struct config_page_sas_device_0 { 1400 config_extended_page_header_t Header; 1401 uint16_t Slot; 1402 uint16_t EnclosureHandle; 1403 uint64_t SASAddress; 1404 uint16_t ParentDevHandle; 1405 uint8_t PhyNum; 1406 uint8_t AccessStatus; 1407 uint16_t DevHandle; 1408 uint8_t TargetID; 1409 uint8_t Bus; 1410 uint32_t DeviceInfo; 1411 uint16_t Flags; 1412 uint8_t PhysicalPort; 1413 uint8_t Reserved2; 1414} config_page_sas_device_0_t; 1415 1416#define MPI_SASDEVICE0_PAGEVERSION 0x00 1417 1418#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT 0x04 1419#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED 0x02 1420#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT 0x01 1421 1422typedef struct config_page_sas_device_1 { 1423 config_extended_page_header_t Header; 1424 uint32_t Reserved1; 1425 uint64_t SASAddress; 1426 uint32_t Reserved2; 1427 uint16_t DevHandle; 1428 uint8_t TargetID; 1429 uint8_t Bus; 1430 uint8_t InitialRegDeviceFIS[20]; 1431} config_page_sas_device_1_t; 1432 1433#define MPI_SASDEVICE1_PAGEVERSION 0x00 1434 1435typedef struct config_page_sas_phy_0 { 1436 config_extended_page_header_t Header; 1437 uint32_t Reserved1; 1438 uint64_t SASAddress; 1439 uint16_t AttachedDevHandle; 1440 uint8_t AttachedPhyIdentifier; 1441 uint8_t Reserved2; 1442 uint32_t AttachedDeviceInfo; 1443 uint8_t ProgrammedLinkRate; 1444 uint8_t HwLinkRate; 1445 uint8_t ChangeCount; 1446 uint8_t Reserved3; 1447 uint32_t PhyInfo; 1448} config_page_sas_phy_0_t; 1449 1450#define MPI_SASPHY0_PAGEVERSION 0x00 1451 1452#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK 0xF0 1453#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE 0x00 1454#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 0x80 1455#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 0x90 1456#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK 0x0F 1457#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE 0x00 1458#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 0x08 1459#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 0x09 1460 1461#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK 0xF0 1462#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 0x80 1463#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 0x90 1464#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK 0x0F 1465#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 0x08 1466#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 0x09 1467 1468#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE 0x00004000 1469#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR 0x00002000 1470#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY 0x00001000 1471 1472#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME 0x00000F00 1473#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME 8 1474 1475#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE 0x000000F0 1476#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING 0x00000000 1477#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING 0x00000010 1478#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING 0x00000020 1479 1480#define MPI_SAS_PHY0_DEVINFO_SATA_DEVICE 0x00000080 1481 1482#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE 0x0000000F 1483#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE 0x00000000 1484#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED 0x00000001 1485#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED 0x00000002 1486#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE 0x00000003 1487#define MPI_SAS_PHY0_PHYINFO_RATE_1_5 0x00000008 1488#define MPI_SAS_PHY0_PHYINFO_RATE_3_0 0x00000009 1489 1490typedef struct config_page_sas_phy_1 { 1491 config_extended_page_header_t Header; 1492 uint32_t Reserved1; 1493 uint32_t InvalidDwordCount; 1494 uint32_t RunningDisparityErrorCount; 1495 uint32_t LossDwordSynchCount; 1496 uint32_t PhyResetProblemCount; 1497} config_page_sas_phy_1_t; 1498 1499#define MPI_SASPHY1_PAGEVERSION 0x00 1500 1501#ifdef __cplusplus 1502} 1503#endif 1504 1505#endif /* _SYS_MPI_CNFG_H */ 1506