ural.c revision 7656:2621e50fdf4a
1/* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6/* 7 * Copyright (c) 2005, 2006 8 * Damien Bergamini <damien.bergamini@free.fr> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23/* 24 * Ralink Technology RT2500USB chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/types.h> 29#include <sys/byteorder.h> 30#include <sys/conf.h> 31#include <sys/cmn_err.h> 32#include <sys/stat.h> 33#include <sys/ddi.h> 34#include <sys/sunddi.h> 35#include <sys/strsubr.h> 36#include <sys/ethernet.h> 37#include <inet/common.h> 38#include <inet/nd.h> 39#include <inet/mi.h> 40#include <sys/note.h> 41#include <sys/stream.h> 42#include <sys/strsun.h> 43#include <sys/modctl.h> 44#include <sys/devops.h> 45#include <sys/dlpi.h> 46#include <sys/mac.h> 47#include <sys/mac_wifi.h> 48#include <sys/net80211.h> 49#include <sys/net80211_proto.h> 50#include <sys/varargs.h> 51#include <sys/policy.h> 52#include <sys/pci.h> 53#include <sys/crypto/common.h> 54#include <sys/crypto/api.h> 55#include <inet/wifi_ioctl.h> 56 57#define USBDRV_MAJOR_VER 2 58#define USBDRV_MINOR_VER 0 59#include <sys/usb/usba.h> 60 61#include "ural_reg.h" 62#include "ural_var.h" 63 64static void *ural_soft_state_p = NULL; 65 66#define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN) 67#define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN) 68 69/* quickly determine if a given rate is CCK or OFDM */ 70#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 71#define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 72#define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 73#define RAL_SIFS 10 /* us */ 74#define RAL_RXTX_TURNAROUND 5 /* us */ 75 76#define URAL_N(a) (sizeof (a) / sizeof ((a)[0])) 77 78/* 79 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 80 */ 81static const struct ieee80211_rateset ural_rateset_11a = 82 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 83 84static const struct ieee80211_rateset ural_rateset_11b = 85 { 4, { 2, 4, 11, 22 } }; 86 87static const struct ieee80211_rateset ural_rateset_11g = 88 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 89 90/* 91 * Default values for MAC registers; values taken from the reference driver. 92 */ 93static const struct { 94 uint16_t reg; 95 uint16_t val; 96} ural_def_mac[] = { 97 { RAL_TXRX_CSR5, 0x8c8d }, 98 { RAL_TXRX_CSR6, 0x8b8a }, 99 { RAL_TXRX_CSR7, 0x8687 }, 100 { RAL_TXRX_CSR8, 0x0085 }, 101 { RAL_MAC_CSR13, 0x1111 }, 102 { RAL_MAC_CSR14, 0x1e11 }, 103 { RAL_TXRX_CSR21, 0xe78f }, 104 { RAL_MAC_CSR9, 0xff1d }, 105 { RAL_MAC_CSR11, 0x0002 }, 106 { RAL_MAC_CSR22, 0x0053 }, 107 { RAL_MAC_CSR15, 0x0000 }, 108 { RAL_MAC_CSR8, 0x0780 }, 109 { RAL_TXRX_CSR19, 0x0000 }, 110 { RAL_TXRX_CSR18, 0x005a }, 111 { RAL_PHY_CSR2, 0x0000 }, 112 { RAL_TXRX_CSR0, 0x1ec0 }, 113 { RAL_PHY_CSR4, 0x000f } 114}; 115 116/* 117 * Default values for BBP registers; values taken from the reference driver. 118 */ 119static const struct { 120 uint8_t reg; 121 uint8_t val; 122} ural_def_bbp[] = { 123 { 3, 0x02 }, 124 { 4, 0x19 }, 125 { 14, 0x1c }, 126 { 15, 0x30 }, 127 { 16, 0xac }, 128 { 17, 0x48 }, 129 { 18, 0x18 }, 130 { 19, 0xff }, 131 { 20, 0x1e }, 132 { 21, 0x08 }, 133 { 22, 0x08 }, 134 { 23, 0x08 }, 135 { 24, 0x80 }, 136 { 25, 0x50 }, 137 { 26, 0x08 }, 138 { 27, 0x23 }, 139 { 30, 0x10 }, 140 { 31, 0x2b }, 141 { 32, 0xb9 }, 142 { 34, 0x12 }, 143 { 35, 0x50 }, 144 { 39, 0xc4 }, 145 { 40, 0x02 }, 146 { 41, 0x60 }, 147 { 53, 0x10 }, 148 { 54, 0x18 }, 149 { 56, 0x08 }, 150 { 57, 0x10 }, 151 { 58, 0x08 }, 152 { 61, 0x60 }, 153 { 62, 0x10 }, 154 { 75, 0xff } 155}; 156 157/* 158 * Default values for RF register R2 indexed by channel numbers. 159 */ 160static const uint32_t ural_rf2522_r2[] = { 161 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 162 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 163}; 164 165static const uint32_t ural_rf2523_r2[] = { 166 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 167 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 168}; 169 170static const uint32_t ural_rf2524_r2[] = { 171 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 172 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 173}; 174 175static const uint32_t ural_rf2525_r2[] = { 176 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 177 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 178}; 179 180static const uint32_t ural_rf2525_hi_r2[] = { 181 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 182 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 183}; 184 185static const uint32_t ural_rf2525e_r2[] = { 186 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 187 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 188}; 189 190static const uint32_t ural_rf2526_hi_r2[] = { 191 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 192 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 193}; 194 195static const uint32_t ural_rf2526_r2[] = { 196 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 197 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 198}; 199 200/* 201 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 202 * values taken from the reference driver. 203 */ 204static const struct { 205 uint8_t chan; 206 uint32_t r1; 207 uint32_t r2; 208 uint32_t r4; 209} ural_rf5222[] = { 210 { 1, 0x08808, 0x0044d, 0x00282 }, 211 { 2, 0x08808, 0x0044e, 0x00282 }, 212 { 3, 0x08808, 0x0044f, 0x00282 }, 213 { 4, 0x08808, 0x00460, 0x00282 }, 214 { 5, 0x08808, 0x00461, 0x00282 }, 215 { 6, 0x08808, 0x00462, 0x00282 }, 216 { 7, 0x08808, 0x00463, 0x00282 }, 217 { 8, 0x08808, 0x00464, 0x00282 }, 218 { 9, 0x08808, 0x00465, 0x00282 }, 219 { 10, 0x08808, 0x00466, 0x00282 }, 220 { 11, 0x08808, 0x00467, 0x00282 }, 221 { 12, 0x08808, 0x00468, 0x00282 }, 222 { 13, 0x08808, 0x00469, 0x00282 }, 223 { 14, 0x08808, 0x0046b, 0x00286 }, 224 225 { 36, 0x08804, 0x06225, 0x00287 }, 226 { 40, 0x08804, 0x06226, 0x00287 }, 227 { 44, 0x08804, 0x06227, 0x00287 }, 228 { 48, 0x08804, 0x06228, 0x00287 }, 229 { 52, 0x08804, 0x06229, 0x00287 }, 230 { 56, 0x08804, 0x0622a, 0x00287 }, 231 { 60, 0x08804, 0x0622b, 0x00287 }, 232 { 64, 0x08804, 0x0622c, 0x00287 }, 233 234 { 100, 0x08804, 0x02200, 0x00283 }, 235 { 104, 0x08804, 0x02201, 0x00283 }, 236 { 108, 0x08804, 0x02202, 0x00283 }, 237 { 112, 0x08804, 0x02203, 0x00283 }, 238 { 116, 0x08804, 0x02204, 0x00283 }, 239 { 120, 0x08804, 0x02205, 0x00283 }, 240 { 124, 0x08804, 0x02206, 0x00283 }, 241 { 128, 0x08804, 0x02207, 0x00283 }, 242 { 132, 0x08804, 0x02208, 0x00283 }, 243 { 136, 0x08804, 0x02209, 0x00283 }, 244 { 140, 0x08804, 0x0220a, 0x00283 }, 245 246 { 149, 0x08808, 0x02429, 0x00281 }, 247 { 153, 0x08808, 0x0242b, 0x00281 }, 248 { 157, 0x08808, 0x0242d, 0x00281 }, 249 { 161, 0x08808, 0x0242f, 0x00281 } 250}; 251 252/* 253 * device operations 254 */ 255static int ural_attach(dev_info_t *, ddi_attach_cmd_t); 256static int ural_detach(dev_info_t *, ddi_detach_cmd_t); 257 258/* 259 * Module Loading Data & Entry Points 260 */ 261DDI_DEFINE_STREAM_OPS(ural_dev_ops, nulldev, nulldev, ural_attach, 262 ural_detach, nodev, NULL, D_MP, NULL, ddi_quiesce_not_supported); 263 264static struct modldrv ural_modldrv = { 265 &mod_driverops, /* Type of module. This one is a driver */ 266 "ural driver", /* short description */ 267 &ural_dev_ops /* driver specific ops */ 268}; 269 270static struct modlinkage modlinkage = { 271 MODREV_1, 272 (void *)&ural_modldrv, 273 NULL 274}; 275 276static int ural_m_stat(void *, uint_t, uint64_t *); 277static int ural_m_start(void *); 278static void ural_m_stop(void *); 279static int ural_m_promisc(void *, boolean_t); 280static int ural_m_multicst(void *, boolean_t, const uint8_t *); 281static int ural_m_unicst(void *, const uint8_t *); 282static mblk_t *ural_m_tx(void *, mblk_t *); 283static void ural_m_ioctl(void *, queue_t *, mblk_t *); 284 285static mac_callbacks_t ural_m_callbacks = { 286 MC_IOCTL, 287 ural_m_stat, 288 ural_m_start, 289 ural_m_stop, 290 ural_m_promisc, 291 ural_m_multicst, 292 ural_m_unicst, 293 ural_m_tx, 294 NULL, /* mc_resources; */ 295 ural_m_ioctl, 296 NULL /* mc_getcapab */ 297}; 298 299extern const char *usb_str_cr(int); 300static void ural_amrr_start(struct ural_softc *, struct ieee80211_node *); 301static int ural_tx_trigger(struct ural_softc *, mblk_t *); 302static int ural_rx_trigger(struct ural_softc *); 303 304uint32_t ural_dbg_flags = 0; 305 306#ifdef DEBUG 307void 308ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...) 309{ 310 va_list args; 311 312 if (dbg_flags & ural_dbg_flags) { 313 va_start(args, fmt); 314 vcmn_err(CE_CONT, fmt, args); 315 va_end(args); 316 } 317} 318#endif 319 320static uint16_t 321ural_read(struct ural_softc *sc, uint16_t reg) 322{ 323 usb_ctrl_setup_t req; 324 usb_cr_t cr; 325 usb_cb_flags_t cf; 326 mblk_t *mp; 327 int err; 328 uint16_t val; 329 330 bzero(&req, sizeof (req)); 331 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST; 332 req.bRequest = RAL_READ_MAC; 333 req.wValue = 0; 334 req.wIndex = reg; 335 req.wLength = sizeof (uint16_t); 336 337 mp = NULL; 338 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp, 339 &cr, &cf, 0); 340 341 if (err != USB_SUCCESS) { 342 RAL_DEBUG(RAL_DBG_ERR, 343 "ural_read(): could not read MAC register:" 344 " cr:%s(%d), cf:(%x)\n", 345 usb_str_cr(cr), cr, cf); 346 return (0); 347 } 348 349 bcopy(mp->b_rptr, &val, sizeof (uint16_t)); 350 351 if (mp) 352 freemsg(mp); 353 354 return (LE_16(val)); 355} 356 357static void 358ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 359{ 360 usb_ctrl_setup_t req; 361 usb_cr_t cr; 362 usb_cb_flags_t cf; 363 mblk_t *mp; 364 int err; 365 366 bzero(&req, sizeof (req)); 367 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST; 368 req.bRequest = RAL_READ_MULTI_MAC; 369 req.wValue = 0; 370 req.wIndex = reg; 371 req.wLength = (uint16_t)len; 372 req.attrs = USB_ATTRS_AUTOCLEARING; 373 374 mp = NULL; 375 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp, 376 &cr, &cf, 0); 377 378 if (err != USB_SUCCESS) { 379 RAL_DEBUG(RAL_DBG_ERR, 380 "ural_read_multi(): could not read MAC register:" 381 "cr:%s(%d), cf:(%x)\n", 382 usb_str_cr(cr), cr, cf); 383 return; 384 } 385 386 bcopy(mp->b_rptr, buf, len); 387 388 if (mp) 389 freemsg(mp); 390} 391 392static void 393ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 394{ 395 usb_ctrl_setup_t req; 396 usb_cr_t cr; 397 usb_cb_flags_t cf; 398 int err; 399 400 bzero(&req, sizeof (req)); 401 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV; 402 req.bRequest = RAL_WRITE_MAC; 403 req.wValue = val; 404 req.wIndex = reg; 405 req.wLength = 0; 406 req.attrs = USB_ATTRS_NONE; 407 408 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL, 409 &cr, &cf, 0); 410 411 if (err != USB_SUCCESS) { 412 RAL_DEBUG(RAL_DBG_ERR, 413 "ural_write(): could not write MAC register:" 414 "cr:%s(%d), cf:(%x)\n", 415 usb_str_cr(cr), cr, cf); 416 } 417} 418 419/* ARGSUSED */ 420static void 421ural_txeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req) 422{ 423 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private; 424 struct ieee80211com *ic = &sc->sc_ic; 425 426 RAL_DEBUG(RAL_DBG_TX, 427 "ural_txeof(): cr:%s(%d), flags:0x%x, tx_queued:%d", 428 usb_str_cr(req->bulk_completion_reason), 429 req->bulk_completion_reason, 430 req->bulk_cb_flags, 431 sc->tx_queued); 432 433 if (req->bulk_completion_reason != USB_CR_OK) 434 sc->sc_tx_err++; 435 436 mutex_enter(&sc->tx_lock); 437 438 sc->tx_queued--; 439 sc->sc_tx_timer = 0; 440 441 if (sc->sc_need_sched) { 442 sc->sc_need_sched = 0; 443 mac_tx_update(ic->ic_mach); 444 } 445 446 mutex_exit(&sc->tx_lock); 447 usb_free_bulk_req(req); 448} 449 450/* ARGSUSED */ 451static void 452ural_rxeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req) 453{ 454 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private; 455 struct ieee80211com *ic = &sc->sc_ic; 456 457 struct ural_rx_desc *desc; 458 struct ieee80211_frame *wh; 459 struct ieee80211_node *ni; 460 461 mblk_t *m, *mp; 462 int len, pktlen; 463 char *rxbuf; 464 465 mp = req->bulk_data; 466 req->bulk_data = NULL; 467 468 RAL_DEBUG(RAL_DBG_RX, 469 "ural_rxeof(): cr:%s(%d), flags:0x%x, rx_queued:%d", 470 usb_str_cr(req->bulk_completion_reason), 471 req->bulk_completion_reason, 472 req->bulk_cb_flags, 473 sc->rx_queued); 474 475 if (req->bulk_completion_reason != USB_CR_OK) { 476 sc->sc_rx_err++; 477 goto fail; 478 } 479 480 len = (uintptr_t)mp->b_wptr - (uintptr_t)mp->b_rptr; 481 rxbuf = (char *)mp->b_rptr; 482 483 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 484 RAL_DEBUG(RAL_DBG_ERR, 485 "ural_rxeof(): xfer too short %d\n", len); 486 sc->sc_rx_err++; 487 goto fail; 488 } 489 490 /* rx descriptor is located at the end */ 491 desc = (struct ural_rx_desc *)(rxbuf + len - RAL_RX_DESC_SIZE); 492 493 if ((LE_32(desc->flags) & RAL_RX_PHY_ERROR) || 494 (LE_32(desc->flags) & RAL_RX_CRC_ERROR)) { 495 /* 496 * This should not happen since we did not request to receive 497 * those frames when we filled RAL_TXRX_CSR2. 498 */ 499 RAL_DEBUG(RAL_DBG_ERR, "PHY or CRC error\n"); 500 sc->sc_rx_err++; 501 goto fail; 502 } 503 504 pktlen = (LE_32(desc->flags) >> 16) & 0xfff; 505 506 if (pktlen > (len - RAL_RX_DESC_SIZE)) { 507 RAL_DEBUG(RAL_DBG_ERR, 508 "ural_rxeof(): pktlen mismatch <%d, %d>.\n", pktlen, len); 509 goto fail; 510 } 511 512 /* Strip trailing 802.11 MAC FCS. */ 513 pktlen -= IEEE80211_CRC_LEN; 514 515 if ((m = allocb(pktlen, BPRI_MED)) == NULL) { 516 RAL_DEBUG(RAL_DBG_ERR, 517 "ural_rxeof(): allocate mblk failed.\n"); 518 sc->sc_rx_nobuf++; 519 goto fail; 520 } 521 522 bcopy(rxbuf, m->b_rptr, pktlen); 523 m->b_wptr += pktlen; 524 525 wh = (struct ieee80211_frame *)m->b_rptr; 526 ni = ieee80211_find_rxnode(ic, wh); 527 528 /* send the frame to the 802.11 layer */ 529 (void) ieee80211_input(ic, m, ni, desc->rssi, 0); 530 531 /* node is no longer needed */ 532 ieee80211_free_node(ni); 533fail: 534 mutex_enter(&sc->rx_lock); 535 sc->rx_queued--; 536 mutex_exit(&sc->rx_lock); 537 538 freemsg(mp); 539 usb_free_bulk_req(req); 540 541 if (RAL_IS_RUNNING(sc)) 542 (void) ural_rx_trigger(sc); 543} 544 545/* 546 * Return the expected ack rate for a frame transmitted at rate `rate'. 547 * this should depend on the destination node basic rate set. 548 */ 549static int 550ural_ack_rate(struct ieee80211com *ic, int rate) 551{ 552 switch (rate) { 553 /* CCK rates */ 554 case 2: 555 return (2); 556 case 4: 557 case 11: 558 case 22: 559 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate); 560 561 /* OFDM rates */ 562 case 12: 563 case 18: 564 return (12); 565 case 24: 566 case 36: 567 return (24); 568 case 48: 569 case 72: 570 case 96: 571 case 108: 572 return (48); 573 } 574 575 /* default to 1Mbps */ 576 return (2); 577} 578 579/* 580 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 581 * The function automatically determines the operating mode depending on the 582 * given rate. `flags' indicates whether short preamble is in use or not. 583 */ 584static uint16_t 585ural_txtime(int len, int rate, uint32_t flags) 586{ 587 uint16_t txtime; 588 589 if (RAL_RATE_IS_OFDM(rate)) { 590 /* IEEE Std 802.11a-1999, pp. 37 */ 591 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 592 txtime = 16 + 4 + 4 * txtime + 6; 593 } else { 594 /* IEEE Std 802.11b-1999, pp. 28 */ 595 txtime = (16 * len + rate - 1) / rate; 596 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 597 txtime += 72 + 24; 598 else 599 txtime += 144 + 48; 600 } 601 return (txtime); 602} 603 604static uint8_t 605ural_plcp_signal(int rate) 606{ 607 switch (rate) { 608 /* CCK rates (returned values are device-dependent) */ 609 case 2: return (0x0); 610 case 4: return (0x1); 611 case 11: return (0x2); 612 case 22: return (0x3); 613 614 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 615 case 12: return (0xb); 616 case 18: return (0xf); 617 case 24: return (0xa); 618 case 36: return (0xe); 619 case 48: return (0x9); 620 case 72: return (0xd); 621 case 96: return (0x8); 622 case 108: return (0xc); 623 624 /* unsupported rates (should not get there) */ 625 default: return (0xff); 626 } 627} 628 629static void 630ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 631 uint32_t flags, int len, int rate) 632{ 633 struct ieee80211com *ic = &sc->sc_ic; 634 uint16_t plcp_length; 635 int remainder; 636 637 desc->flags = LE_32(flags); 638 desc->flags |= LE_32(RAL_TX_NEWSEQ); 639 desc->flags |= LE_32(len << 16); 640 641 desc->wme = LE_16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 642 desc->wme |= LE_16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 643 644 /* setup PLCP fields */ 645 desc->plcp_signal = ural_plcp_signal(rate); 646 desc->plcp_service = 4; 647 648 len += IEEE80211_CRC_LEN; 649 if (RAL_RATE_IS_OFDM(rate)) { 650 desc->flags |= LE_32(RAL_TX_OFDM); 651 652 plcp_length = len & 0xfff; 653 desc->plcp_length_hi = plcp_length >> 6; 654 desc->plcp_length_lo = plcp_length & 0x3f; 655 } else { 656 plcp_length = (16 * len + rate - 1) / rate; 657 if (rate == 22) { 658 remainder = (16 * len) % 22; 659 if (remainder != 0 && remainder < 7) 660 desc->plcp_service |= RAL_PLCP_LENGEXT; 661 } 662 desc->plcp_length_hi = plcp_length >> 8; 663 desc->plcp_length_lo = plcp_length & 0xff; 664 665 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 666 desc->plcp_signal |= 0x08; 667 } 668 669 desc->iv = 0; 670 desc->eiv = 0; 671} 672 673#define RAL_TX_TIMEOUT 5 674 675static int 676ural_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 677{ 678 struct ural_softc *sc = (struct ural_softc *)ic; 679 struct ural_tx_desc *desc; 680 681 struct ieee80211_frame *wh; 682 struct ieee80211_key *k; 683 684 uint16_t dur; 685 uint32_t flags = 0; 686 int rate, err = DDI_SUCCESS; 687 688 struct ieee80211_node *ni = NULL; 689 mblk_t *m, *m0; 690 int off, mblen, pktlen, xferlen; 691 692 mutex_enter(&sc->tx_lock); 693 694 if (sc->tx_queued > RAL_TX_LIST_COUNT) { 695 RAL_DEBUG(RAL_DBG_TX, "ural_send(): " 696 "no TX buffer available!\n"); 697 if ((type & IEEE80211_FC0_TYPE_MASK) == 698 IEEE80211_FC0_TYPE_DATA) { 699 sc->sc_need_sched = 1; 700 } 701 sc->sc_tx_nobuf++; 702 err = ENOMEM; 703 goto fail; 704 } 705 706 m = allocb(RAL_TXBUF_SIZE + RAL_TX_DESC_SIZE, BPRI_MED); 707 if (m == NULL) { 708 RAL_DEBUG(RAL_DBG_ERR, "ural_send(): can't alloc mblk.\n"); 709 err = DDI_FAILURE; 710 goto fail; 711 } 712 713 m->b_rptr += RAL_TX_DESC_SIZE; /* skip TX descriptor */ 714 m->b_wptr += RAL_TX_DESC_SIZE; 715 716 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 717 mblen = (uintptr_t)m0->b_wptr - (uintptr_t)m0->b_rptr; 718 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 719 off += mblen; 720 } 721 m->b_wptr += off; 722 723 wh = (struct ieee80211_frame *)m->b_rptr; 724 725 ni = ieee80211_find_txnode(ic, wh->i_addr1); 726 if (ni == NULL) { 727 err = DDI_FAILURE; 728 sc->sc_tx_err++; 729 freemsg(m); 730 goto fail; 731 } 732 733 if ((type & IEEE80211_FC0_TYPE_MASK) == 734 IEEE80211_FC0_TYPE_DATA) { 735 (void) ieee80211_encap(ic, m, ni); 736 } 737 738 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 739 k = ieee80211_crypto_encap(ic, m); 740 if (k == NULL) { 741 sc->sc_tx_err++; 742 freemsg(m); 743 err = DDI_FAILURE; 744 goto fail; 745 } 746 /* packet header may have moved, reset our local pointer */ 747 wh = (struct ieee80211_frame *)m->b_rptr; 748 } 749 750 m->b_rptr -= RAL_TX_DESC_SIZE; /* restore */ 751 desc = (struct ural_tx_desc *)m->b_rptr; 752 753 if ((type & IEEE80211_FC0_TYPE_MASK) == 754 IEEE80211_FC0_TYPE_DATA) { /* DATA */ 755 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) 756 rate = ic->ic_bss->in_rates.ir_rates[ic->ic_fixed_rate]; 757 else 758 rate = ni->in_rates.ir_rates[ni->in_txrate]; 759 760 rate &= IEEE80211_RATE_VAL; 761 if (rate <= 0) { 762 rate = 2; /* basic rate */ 763 } 764 765 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 766 flags |= RAL_TX_ACK; 767 flags |= RAL_TX_RETRY(7); 768 769 dur = ural_txtime(RAL_ACK_SIZE, ural_ack_rate(ic, rate), 770 ic->ic_flags) + RAL_SIFS; 771 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur); 772 } 773 } else { /* MGMT */ 774 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 775 776 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 777 flags |= RAL_TX_ACK; 778 779 dur = ural_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) 780 + RAL_SIFS; 781 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur); 782 783 /* tell hardware to add timestamp for probe responses */ 784 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 785 IEEE80211_FC0_TYPE_MGT && 786 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 787 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 788 flags |= RAL_TX_TIMESTAMP; 789 } 790 } 791 792 pktlen = (uintptr_t)m->b_wptr - (uintptr_t)m->b_rptr - RAL_TX_DESC_SIZE; 793 ural_setup_tx_desc(sc, desc, flags, pktlen, rate); 794 795 /* align end on a 2-bytes boundary */ 796 xferlen = (RAL_TX_DESC_SIZE + pktlen + 1) & ~1; 797 798 /* 799 * No space left in the last URB to store the extra 2 bytes, force 800 * sending of another URB. 801 */ 802 if ((xferlen % 64) == 0) 803 xferlen += 2; 804 805 m->b_wptr = m->b_rptr + xferlen; 806 807 RAL_DEBUG(RAL_DBG_TX, "sending data frame len=%u rate=%u xfer len=%u\n", 808 pktlen, rate, xferlen); 809 810 (void) ural_tx_trigger(sc, m); 811 812 ic->ic_stats.is_tx_frags++; 813 ic->ic_stats.is_tx_bytes += pktlen; 814 815fail: 816 if (ni != NULL) 817 ieee80211_free_node(ni); 818 819 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA || 820 err == 0) { 821 freemsg(mp); 822 } 823 824 mutex_exit(&sc->tx_lock); 825 826 return (err); 827} 828 829static mblk_t * 830ural_m_tx(void *arg, mblk_t *mp) 831{ 832 struct ural_softc *sc = (struct ural_softc *)arg; 833 struct ieee80211com *ic = &sc->sc_ic; 834 mblk_t *next; 835 836 /* 837 * No data frames go out unless we're associated; this 838 * should not happen as the 802.11 layer does not enable 839 * the xmit queue until we enter the RUN state. 840 */ 841 if (ic->ic_state != IEEE80211_S_RUN) { 842 RAL_DEBUG(RAL_DBG_ERR, "ural_m_tx(): " 843 "discard, state %u\n", ic->ic_state); 844 freemsgchain(mp); 845 return (NULL); 846 } 847 848 while (mp != NULL) { 849 next = mp->b_next; 850 mp->b_next = NULL; 851 if (ural_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != DDI_SUCCESS) { 852 mp->b_next = next; 853 freemsgchain(mp); 854 return (NULL); 855 } 856 mp = next; 857 } 858 return (mp); 859} 860 861static void 862ural_set_testmode(struct ural_softc *sc) 863{ 864 usb_ctrl_setup_t req; 865 usb_cr_t cr; 866 usb_cb_flags_t cf; 867 int err; 868 869 bzero(&req, sizeof (req)); 870 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV; 871 req.bRequest = RAL_VENDOR_REQUEST; 872 req.wValue = 4; 873 req.wIndex = 1; 874 req.wLength = 0; 875 req.attrs = USB_ATTRS_NONE; 876 877 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL, 878 &cr, &cf, 0); 879 880 if (err != USB_SUCCESS) { 881 RAL_DEBUG(RAL_DBG_USB, 882 "ural_set_testmode(): could not set test mode:" 883 "cr:%s(%d), cf:%(x)\n", 884 usb_str_cr(cr), cr, cf); 885 } 886} 887 888static void 889ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 890{ 891 usb_ctrl_setup_t req; 892 usb_cr_t cr; 893 usb_cb_flags_t cf; 894 mblk_t *mp; 895 int err; 896 897 bzero(&req, sizeof (req)); 898 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST; 899 req.bRequest = RAL_READ_EEPROM; 900 req.wValue = 0; 901 req.wIndex = addr; 902 req.wLength = (uint16_t)len; 903 904 mp = NULL; 905 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp, 906 &cr, &cf, 0); 907 908 if (err != USB_SUCCESS) { 909 RAL_DEBUG(RAL_DBG_USB, 910 "ural_eeprom_read(): could not read EEPROM:" 911 "cr:%s(%d), cf:(%x)\n", 912 usb_str_cr(cr), cr, cf); 913 return; 914 } 915 916 bcopy(mp->b_rptr, buf, len); 917 918 if (mp) 919 freemsg(mp); 920} 921 922static void 923ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 924{ 925 uint16_t tmp; 926 int ntries; 927 928 for (ntries = 0; ntries < 5; ntries++) { 929 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 930 break; 931 } 932 if (ntries == 5) { 933 RAL_DEBUG(RAL_DBG_ERR, 934 "ural_bbp_write(): could not write to BBP\n"); 935 return; 936 } 937 938 tmp = reg << 8 | val; 939 ural_write(sc, RAL_PHY_CSR7, tmp); 940} 941 942static uint8_t 943ural_bbp_read(struct ural_softc *sc, uint8_t reg) 944{ 945 uint16_t val; 946 int ntries; 947 948 val = RAL_BBP_WRITE | reg << 8; 949 ural_write(sc, RAL_PHY_CSR7, val); 950 951 for (ntries = 0; ntries < 5; ntries++) { 952 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 953 break; 954 } 955 if (ntries == 5) { 956 RAL_DEBUG(RAL_DBG_ERR, "ural_bbp_read(): could not read BBP\n"); 957 return (0); 958 } 959 960 return (ural_read(sc, RAL_PHY_CSR7) & 0xff); 961} 962 963static void 964ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 965{ 966 uint32_t tmp; 967 int ntries; 968 969 for (ntries = 0; ntries < 5; ntries++) { 970 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 971 break; 972 } 973 if (ntries == 5) { 974 RAL_DEBUG(RAL_DBG_ERR, 975 "ural_rf_write(): could not write to RF\n"); 976 return; 977 } 978 979 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xffff) << 2 | (reg & 0x3); 980 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 981 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 982 983 /* remember last written value in sc */ 984 sc->rf_regs[reg] = val; 985 986 RAL_DEBUG(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 987} 988 989/* 990 * Disable RF auto-tuning. 991 */ 992static void 993ural_disable_rf_tune(struct ural_softc *sc) 994{ 995 uint32_t tmp; 996 997 if (sc->rf_rev != RAL_RF_2523) { 998 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 999 ural_rf_write(sc, RAL_RF1, tmp); 1000 } 1001 1002 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1003 ural_rf_write(sc, RAL_RF3, tmp); 1004 1005 RAL_DEBUG(RAL_DBG_HW, "disabling RF autotune\n"); 1006} 1007 1008 1009static void 1010ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1011{ 1012 struct ieee80211com *ic = &sc->sc_ic; 1013 uint8_t power, tmp; 1014 uint_t i, chan; 1015 1016 chan = ieee80211_chan2ieee(ic, c); 1017 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1018 return; 1019 1020 if (IEEE80211_IS_CHAN_2GHZ(c)) 1021 power = min(sc->txpow[chan - 1], 31); 1022 else 1023 power = 31; 1024 1025 /* adjust txpower using ifconfig settings */ 1026 power -= (100 - ic->ic_txpowlimit) / 8; 1027 1028 RAL_DEBUG(RAL_DBG_HW, "setting channel to %u, txpower to %u\n", 1029 chan, power); 1030 1031 switch (sc->rf_rev) { 1032 case RAL_RF_2522: 1033 ural_rf_write(sc, RAL_RF1, 0x00814); 1034 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1035 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1036 break; 1037 1038 case RAL_RF_2523: 1039 ural_rf_write(sc, RAL_RF1, 0x08804); 1040 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1041 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1042 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1043 break; 1044 1045 case RAL_RF_2524: 1046 ural_rf_write(sc, RAL_RF1, 0x0c808); 1047 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1048 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1049 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1050 break; 1051 1052 case RAL_RF_2525: 1053 ural_rf_write(sc, RAL_RF1, 0x08808); 1054 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1055 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1056 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1057 1058 ural_rf_write(sc, RAL_RF1, 0x08808); 1059 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1060 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1061 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1062 break; 1063 1064 case RAL_RF_2525E: 1065 ural_rf_write(sc, RAL_RF1, 0x08808); 1066 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1067 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1068 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1069 break; 1070 1071 case RAL_RF_2526: 1072 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1073 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1074 ural_rf_write(sc, RAL_RF1, 0x08804); 1075 1076 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1077 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1078 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1079 break; 1080 1081 /* dual-band RF */ 1082 case RAL_RF_5222: 1083 for (i = 0; ural_rf5222[i].chan != chan; i++) { 1084 if (i > URAL_N(ural_rf5222)) break; 1085 } 1086 1087 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1088 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1089 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1090 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1091 break; 1092 } 1093 1094 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1095 ic->ic_state != IEEE80211_S_SCAN) { 1096 /* set Japan filter bit for channel 14 */ 1097 tmp = ural_bbp_read(sc, 70); 1098 1099 tmp &= ~RAL_JAPAN_FILTER; 1100 if (chan == 14) 1101 tmp |= RAL_JAPAN_FILTER; 1102 1103 ural_bbp_write(sc, 70, tmp); 1104 1105 /* clear CRC errs */ 1106 (void) ural_read(sc, RAL_STA_CSR0); 1107 1108 drv_usecwait(10000); 1109 ural_disable_rf_tune(sc); 1110 } 1111} 1112 1113/* 1114 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1115 * synchronization. 1116 */ 1117static void 1118ural_enable_tsf_sync(struct ural_softc *sc) 1119{ 1120 struct ieee80211com *ic = &sc->sc_ic; 1121 uint16_t logcwmin, preload, tmp; 1122 1123 /* first, disable TSF synchronization */ 1124 ural_write(sc, RAL_TXRX_CSR19, 0); 1125 1126 tmp = (16 * ic->ic_bss->in_intval) << 4; 1127 ural_write(sc, RAL_TXRX_CSR18, tmp); 1128 1129 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1130 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1131 tmp = logcwmin << 12 | preload; 1132 ural_write(sc, RAL_TXRX_CSR20, tmp); 1133 1134 /* finally, enable TSF synchronization */ 1135 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1136 if (ic->ic_opmode == IEEE80211_M_STA) 1137 tmp |= RAL_ENABLE_TSF_SYNC(1); 1138 else 1139 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1140 ural_write(sc, RAL_TXRX_CSR19, tmp); 1141 1142 RAL_DEBUG(RAL_DBG_HW, "enabling TSF synchronization\n"); 1143} 1144 1145/* 1146 * This function can be called by ieee80211_set_shortslottime(). Refer to 1147 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed. 1148 */ 1149/* ARGSUSED */ 1150static void 1151ural_update_slot(struct ieee80211com *ic, int onoff) 1152{ 1153 struct ural_softc *sc = (struct ural_softc *)ic; 1154 uint16_t slottime, sifs, eifs; 1155 1156 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1157 /* slottime = (onoff ? 9 : 20); */ 1158 1159 /* 1160 * These settings may sound a bit inconsistent but this is what the 1161 * reference driver does. 1162 */ 1163 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1164 sifs = 16 - RAL_RXTX_TURNAROUND; 1165 eifs = 364; 1166 } else { 1167 sifs = 10 - RAL_RXTX_TURNAROUND; 1168 eifs = 64; 1169 } 1170 1171 ural_write(sc, RAL_MAC_CSR10, slottime); 1172 ural_write(sc, RAL_MAC_CSR11, sifs); 1173 ural_write(sc, RAL_MAC_CSR12, eifs); 1174} 1175 1176static void 1177ural_set_txpreamble(struct ural_softc *sc) 1178{ 1179 uint16_t tmp; 1180 1181 tmp = ural_read(sc, RAL_TXRX_CSR10); 1182 1183 tmp &= ~RAL_SHORT_PREAMBLE; 1184 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1185 tmp |= RAL_SHORT_PREAMBLE; 1186 1187 ural_write(sc, RAL_TXRX_CSR10, tmp); 1188} 1189 1190static void 1191ural_set_basicrates(struct ural_softc *sc) 1192{ 1193 struct ieee80211com *ic = &sc->sc_ic; 1194 1195 /* update basic rate set */ 1196 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1197 /* 11b basic rates: 1, 2Mbps */ 1198 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1199 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->in_chan)) { 1200 /* 11a basic rates: 6, 12, 24Mbps */ 1201 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1202 } else { 1203 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1204 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1205 } 1206} 1207 1208static void 1209ural_set_bssid(struct ural_softc *sc, uint8_t *bssid) 1210{ 1211 uint16_t tmp; 1212 1213 tmp = bssid[0] | bssid[1] << 8; 1214 ural_write(sc, RAL_MAC_CSR5, tmp); 1215 1216 tmp = bssid[2] | bssid[3] << 8; 1217 ural_write(sc, RAL_MAC_CSR6, tmp); 1218 1219 tmp = bssid[4] | bssid[5] << 8; 1220 ural_write(sc, RAL_MAC_CSR7, tmp); 1221 1222 RAL_DEBUG(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid)); 1223} 1224 1225static void 1226ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1227{ 1228 uint16_t tmp; 1229 1230 tmp = addr[0] | addr[1] << 8; 1231 ural_write(sc, RAL_MAC_CSR2, tmp); 1232 1233 tmp = addr[2] | addr[3] << 8; 1234 ural_write(sc, RAL_MAC_CSR3, tmp); 1235 1236 tmp = addr[4] | addr[5] << 8; 1237 ural_write(sc, RAL_MAC_CSR4, tmp); 1238 1239 RAL_DEBUG(RAL_DBG_HW, 1240 "setting MAC address to " MACSTR "\n", MAC2STR(addr)); 1241} 1242 1243static void 1244ural_update_promisc(struct ural_softc *sc) 1245{ 1246 uint32_t tmp; 1247 1248 tmp = ural_read(sc, RAL_TXRX_CSR2); 1249 1250 tmp &= ~RAL_DROP_NOT_TO_ME; 1251 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1252 tmp |= RAL_DROP_NOT_TO_ME; 1253 1254 ural_write(sc, RAL_TXRX_CSR2, tmp); 1255 1256 RAL_DEBUG(RAL_DBG_HW, "%s promiscuous mode\n", 1257 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving"); 1258} 1259 1260static const char * 1261ural_get_rf(int rev) 1262{ 1263 switch (rev) { 1264 case RAL_RF_2522: return ("RT2522"); 1265 case RAL_RF_2523: return ("RT2523"); 1266 case RAL_RF_2524: return ("RT2524"); 1267 case RAL_RF_2525: return ("RT2525"); 1268 case RAL_RF_2525E: return ("RT2525e"); 1269 case RAL_RF_2526: return ("RT2526"); 1270 case RAL_RF_5222: return ("RT5222"); 1271 default: return ("unknown"); 1272 } 1273} 1274 1275static void 1276ural_read_eeprom(struct ural_softc *sc) 1277{ 1278 struct ieee80211com *ic = &sc->sc_ic; 1279 uint16_t val; 1280 1281 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1282 val = LE_16(val); 1283 sc->rf_rev = (val >> 11) & 0x7; 1284 sc->hw_radio = (val >> 10) & 0x1; 1285 sc->led_mode = (val >> 6) & 0x7; 1286 sc->rx_ant = (val >> 4) & 0x3; 1287 sc->tx_ant = (val >> 2) & 0x3; 1288 sc->nb_ant = val & 0x3; 1289 1290 /* read MAC address */ 1291 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1292 1293 /* read default values for BBP registers */ 1294 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1295 1296 /* read Tx power for all b/g channels */ 1297 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1298} 1299 1300static int 1301ural_bbp_init(struct ural_softc *sc) 1302{ 1303 int i, ntries; 1304 1305 /* wait for BBP to be ready */ 1306 for (ntries = 0; ntries < 100; ntries++) { 1307 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1308 break; 1309 drv_usecwait(1000); 1310 } 1311 if (ntries == 100) { 1312 RAL_DEBUG(RAL_DBG_ERR, "timeout waiting for BBP\n"); 1313 return (EIO); 1314 } 1315 1316 /* initialize BBP registers to default values */ 1317 for (i = 0; i < URAL_N(ural_def_bbp); i++) 1318 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1319 1320 return (0); 1321} 1322 1323static void 1324ural_set_txantenna(struct ural_softc *sc, int antenna) 1325{ 1326 uint16_t tmp; 1327 uint8_t tx; 1328 1329 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1330 if (antenna == 1) 1331 tx |= RAL_BBP_ANTA; 1332 else if (antenna == 2) 1333 tx |= RAL_BBP_ANTB; 1334 else 1335 tx |= RAL_BBP_DIVERSITY; 1336 1337 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1338 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1339 sc->rf_rev == RAL_RF_5222) 1340 tx |= RAL_BBP_FLIPIQ; 1341 1342 ural_bbp_write(sc, RAL_BBP_TX, tx); 1343 1344 /* update values in PHY_CSR5 and PHY_CSR6 */ 1345 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1346 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1347 1348 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 1349 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1350} 1351 1352static void 1353ural_set_rxantenna(struct ural_softc *sc, int antenna) 1354{ 1355 uint8_t rx; 1356 1357 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 1358 if (antenna == 1) 1359 rx |= RAL_BBP_ANTA; 1360 else if (antenna == 2) 1361 rx |= RAL_BBP_ANTB; 1362 else 1363 rx |= RAL_BBP_DIVERSITY; 1364 1365 /* need to force no I/Q flip for RF 2525e and 2526 */ 1366 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 1367 rx &= ~RAL_BBP_FLIPIQ; 1368 1369 ural_bbp_write(sc, RAL_BBP_RX, rx); 1370} 1371 1372/* 1373 * This function is called periodically (every 200ms) during scanning to 1374 * switch from one channel to another. 1375 */ 1376static void 1377ural_next_scan(void *arg) 1378{ 1379 struct ural_softc *sc = arg; 1380 struct ieee80211com *ic = &sc->sc_ic; 1381 1382 if (ic->ic_state == IEEE80211_S_SCAN) 1383 ieee80211_next_scan(ic); 1384} 1385 1386static int 1387ural_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1388{ 1389 struct ural_softc *sc = (struct ural_softc *)ic; 1390 enum ieee80211_state ostate; 1391 struct ieee80211_node *ni; 1392 int err; 1393 1394 RAL_LOCK(sc); 1395 1396 ostate = ic->ic_state; 1397 1398 if (sc->sc_scan_id != 0) { 1399 (void) untimeout(sc->sc_scan_id); 1400 sc->sc_scan_id = 0; 1401 } 1402 1403 if (sc->sc_amrr_id != 0) { 1404 (void) untimeout(sc->sc_amrr_id); 1405 sc->sc_amrr_id = 0; 1406 } 1407 1408 switch (nstate) { 1409 case IEEE80211_S_INIT: 1410 if (ostate == IEEE80211_S_RUN) { 1411 /* abort TSF synchronization */ 1412 ural_write(sc, RAL_TXRX_CSR19, 0); 1413 /* force tx led to stop blinking */ 1414 ural_write(sc, RAL_MAC_CSR20, 0); 1415 } 1416 break; 1417 1418 case IEEE80211_S_SCAN: 1419 ural_set_chan(sc, ic->ic_curchan); 1420 sc->sc_scan_id = timeout(ural_next_scan, (void *)sc, 1421 drv_usectohz(sc->dwelltime * 1000)); 1422 break; 1423 1424 case IEEE80211_S_AUTH: 1425 RAL_DEBUG(RAL_DBG_MSG, "-> IEEE80211_S_AUTH ...\n"); 1426 ural_set_chan(sc, ic->ic_curchan); 1427 break; 1428 1429 case IEEE80211_S_ASSOC: 1430 RAL_DEBUG(RAL_DBG_MSG, "-> IEEE80211_S_ASSOC ...\n"); 1431 ural_set_chan(sc, ic->ic_curchan); 1432 break; 1433 1434 case IEEE80211_S_RUN: 1435 RAL_DEBUG(RAL_DBG_MSG, "-> IEEE80211_S_RUN ...\n"); 1436 ural_set_chan(sc, ic->ic_curchan); 1437 1438 ni = ic->ic_bss; 1439 1440 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1441 ural_update_slot(ic, 1); 1442 ural_set_txpreamble(sc); 1443 ural_set_basicrates(sc); 1444 ural_set_bssid(sc, ni->in_bssid); 1445 } 1446 1447 1448 /* make tx led blink on tx (controlled by ASIC) */ 1449 ural_write(sc, RAL_MAC_CSR20, 1); 1450 1451 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1452 ural_enable_tsf_sync(sc); 1453 1454 /* enable automatic rate adaptation in STA mode */ 1455 if (ic->ic_opmode == IEEE80211_M_STA && 1456 ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) 1457 ural_amrr_start(sc, ni); 1458 1459 break; 1460 } 1461 1462 RAL_UNLOCK(sc); 1463 1464 err = sc->sc_newstate(ic, nstate, arg); 1465 /* 1466 * Finally, start any timers. 1467 */ 1468 if (nstate == IEEE80211_S_RUN) 1469 ieee80211_start_watchdog(ic, 1); 1470 1471 return (err); 1472} 1473 1474 1475 1476static void 1477ural_close_pipes(struct ural_softc *sc) 1478{ 1479 usb_flags_t flags = USB_FLAGS_SLEEP; 1480 1481 if (sc->sc_rx_pipeh != NULL) { 1482 usb_pipe_reset(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0); 1483 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0); 1484 sc->sc_rx_pipeh = NULL; 1485 } 1486 1487 if (sc->sc_tx_pipeh != NULL) { 1488 usb_pipe_reset(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0); 1489 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0); 1490 sc->sc_tx_pipeh = NULL; 1491 } 1492} 1493 1494static int 1495ural_open_pipes(struct ural_softc *sc) 1496{ 1497 usb_ep_data_t *ep_node; 1498 usb_pipe_policy_t policy; 1499 int err; 1500 1501 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0, 1502 USB_EP_ATTR_BULK, USB_EP_DIR_OUT); 1503 1504 bzero(&policy, sizeof (usb_pipe_policy_t)); 1505 policy.pp_max_async_reqs = RAL_TX_LIST_COUNT; 1506 1507 if ((err = usb_pipe_open(sc->sc_dev, 1508 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP, 1509 &sc->sc_tx_pipeh)) != USB_SUCCESS) { 1510 RAL_DEBUG(RAL_DBG_ERR, 1511 "ural_open_pipes(): %x failed to open tx pipe\n", err); 1512 goto fail; 1513 } 1514 1515 RAL_DEBUG(RAL_DBG_MSG, "tx pipe opened\n"); 1516 1517 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0, 1518 USB_EP_ATTR_BULK, USB_EP_DIR_IN); 1519 1520 bzero(&policy, sizeof (usb_pipe_policy_t)); 1521 policy.pp_max_async_reqs = RAL_RX_LIST_COUNT + 32; 1522 1523 if ((err = usb_pipe_open(sc->sc_dev, 1524 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP, 1525 &sc->sc_rx_pipeh)) != USB_SUCCESS) { 1526 RAL_DEBUG(RAL_DBG_ERR, 1527 "ural_open_pipes(): %x failed to open rx pipe\n", err); 1528 goto fail; 1529 } 1530 1531 RAL_DEBUG(RAL_DBG_MSG, "rx pipe opened\n"); 1532 1533 return (USB_SUCCESS); 1534 1535fail: 1536 if (sc->sc_rx_pipeh != NULL) { 1537 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, 1538 USB_FLAGS_SLEEP, NULL, 0); 1539 sc->sc_rx_pipeh = NULL; 1540 } 1541 1542 if (sc->sc_tx_pipeh != NULL) { 1543 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, 1544 USB_FLAGS_SLEEP, NULL, 0); 1545 sc->sc_tx_pipeh = NULL; 1546 } 1547 1548 return (USB_FAILURE); 1549} 1550 1551static int 1552ural_tx_trigger(struct ural_softc *sc, mblk_t *mp) 1553{ 1554 usb_bulk_req_t *req; 1555 int err; 1556 1557 sc->sc_tx_timer = RAL_TX_TIMEOUT; 1558 1559 req = usb_alloc_bulk_req(sc->sc_dev, 0, USB_FLAGS_SLEEP); 1560 if (req == NULL) { 1561 RAL_DEBUG(RAL_DBG_ERR, 1562 "ural_tx_trigger(): failed to allocate req"); 1563 freemsg(mp); 1564 return (-1); 1565 } 1566 1567 req->bulk_len = (uintptr_t)mp->b_wptr - (uintptr_t)mp->b_rptr; 1568 req->bulk_data = mp; 1569 req->bulk_client_private = (usb_opaque_t)sc; 1570 req->bulk_timeout = RAL_TX_TIMEOUT; 1571 req->bulk_attributes = USB_ATTRS_AUTOCLEARING; 1572 req->bulk_cb = ural_txeof; 1573 req->bulk_exc_cb = ural_txeof; 1574 req->bulk_completion_reason = 0; 1575 req->bulk_cb_flags = 0; 1576 1577 if ((err = usb_pipe_bulk_xfer(sc->sc_tx_pipeh, req, 0)) 1578 != USB_SUCCESS) { 1579 1580 RAL_DEBUG(RAL_DBG_ERR, "ural_tx_trigger(): " 1581 "failed to do tx xfer, %d", err); 1582 usb_free_bulk_req(req); 1583 return (-1); 1584 } 1585 1586 sc->tx_queued++; 1587 1588 return (0); 1589} 1590 1591static int 1592ural_rx_trigger(struct ural_softc *sc) 1593{ 1594 usb_bulk_req_t *req; 1595 int err; 1596 1597 req = usb_alloc_bulk_req(sc->sc_dev, RAL_RXBUF_SIZE, USB_FLAGS_SLEEP); 1598 if (req == NULL) { 1599 RAL_DEBUG(RAL_DBG_ERR, 1600 "ural_rx_trigger(): failed to allocate req"); 1601 return (-1); 1602 } 1603 1604 req->bulk_len = RAL_RXBUF_SIZE; 1605 req->bulk_client_private = (usb_opaque_t)sc; 1606 req->bulk_timeout = 0; 1607 req->bulk_attributes = USB_ATTRS_SHORT_XFER_OK 1608 | USB_ATTRS_AUTOCLEARING; 1609 req->bulk_cb = ural_rxeof; 1610 req->bulk_exc_cb = ural_rxeof; 1611 req->bulk_completion_reason = 0; 1612 req->bulk_cb_flags = 0; 1613 1614 err = usb_pipe_bulk_xfer(sc->sc_rx_pipeh, req, 0); 1615 1616 if (err != USB_SUCCESS) { 1617 RAL_DEBUG(RAL_DBG_ERR, "ural_rx_trigger(): " 1618 "failed to do rx xfer, %d", err); 1619 usb_free_bulk_req(req); 1620 1621 return (-1); 1622 } 1623 1624 mutex_enter(&sc->rx_lock); 1625 sc->rx_queued++; 1626 mutex_exit(&sc->rx_lock); 1627 1628 return (0); 1629} 1630 1631static void 1632ural_init_tx_queue(struct ural_softc *sc) 1633{ 1634 sc->tx_queued = 0; 1635} 1636 1637static int 1638ural_init_rx_queue(struct ural_softc *sc) 1639{ 1640 int i; 1641 1642 sc->rx_queued = 0; 1643 1644 for (i = 0; i < RAL_RX_LIST_COUNT; i++) { 1645 if (ural_rx_trigger(sc) != 0) { 1646 return (USB_FAILURE); 1647 } 1648 } 1649 1650 return (USB_SUCCESS); 1651} 1652 1653static void 1654ural_stop(struct ural_softc *sc) 1655{ 1656 struct ieee80211com *ic = &sc->sc_ic; 1657 1658 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1659 ieee80211_stop_watchdog(ic); /* stop the watchdog */ 1660 1661 RAL_LOCK(sc); 1662 1663 sc->sc_tx_timer = 0; 1664 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 1665 1666 /* disable Rx */ 1667 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 1668 1669 /* reset ASIC and BBP (but won't reset MAC registers!) */ 1670 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 1671 ural_write(sc, RAL_MAC_CSR1, 0); 1672 1673 ural_close_pipes(sc); 1674 1675 RAL_UNLOCK(sc); 1676} 1677 1678static int 1679ural_init(struct ural_softc *sc) 1680{ 1681 struct ieee80211com *ic = &sc->sc_ic; 1682 uint16_t tmp; 1683 int i, ntries; 1684 1685 ural_set_testmode(sc); 1686 ural_write(sc, 0x308, 0x00f0); /* magic */ 1687 1688 ural_stop(sc); 1689 1690 /* initialize MAC registers to default values */ 1691 for (i = 0; i < URAL_N(ural_def_mac); i++) 1692 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 1693 1694 /* wait for BBP and RF to wake up (this can take a long time!) */ 1695 for (ntries = 0; ntries < 100; ntries++) { 1696 tmp = ural_read(sc, RAL_MAC_CSR17); 1697 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 1698 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 1699 break; 1700 drv_usecwait(1000); 1701 } 1702 if (ntries == 100) { 1703 RAL_DEBUG(RAL_DBG_ERR, 1704 "ural_init(): timeout waiting for BBP/RF to wakeup\n"); 1705 goto fail; 1706 } 1707 1708 /* we're ready! */ 1709 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 1710 1711 /* set basic rate set (will be updated later) */ 1712 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1713 1714 if (ural_bbp_init(sc) != 0) 1715 goto fail; 1716 1717 /* set default BSS channel */ 1718 ural_set_chan(sc, ic->ic_curchan); 1719 1720 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 1721 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta)); 1722 1723 ural_set_txantenna(sc, sc->tx_ant); 1724 ural_set_rxantenna(sc, sc->rx_ant); 1725 1726 ural_set_macaddr(sc, ic->ic_macaddr); 1727 1728 if (ural_open_pipes(sc) != USB_SUCCESS) { 1729 RAL_DEBUG(RAL_DBG_ERR, "ural_init(): " 1730 "could not open pipes.\n"); 1731 goto fail; 1732 } 1733 1734 ural_init_tx_queue(sc); 1735 1736 if (ural_init_rx_queue(sc) != USB_SUCCESS) 1737 goto fail; 1738 1739 /* kick Rx */ 1740 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 1741 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1742 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 1743 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 1744 tmp |= RAL_DROP_TODS; 1745 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1746 tmp |= RAL_DROP_NOT_TO_ME; 1747 } 1748 ural_write(sc, RAL_TXRX_CSR2, tmp); 1749 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */ 1750 1751 return (DDI_SUCCESS); 1752fail: 1753 ural_stop(sc); 1754 return (EIO); 1755} 1756 1757static int 1758ural_offline(dev_info_t *devinfo) 1759{ 1760 struct ural_softc *sc; 1761 struct ieee80211com *ic; 1762 1763 RAL_DEBUG(RAL_DBG_MSG, "ural_offline()\n"); 1764 1765 /* 1766 * We can't call ural_stop() here, since the hardware is removed, 1767 * we can't access the register anymore. 1768 */ 1769 1770 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo)); 1771 ic = &sc->sc_ic; 1772 1773 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1774 ieee80211_stop_watchdog(ic); /* stop the watchdog */ 1775 1776 RAL_LOCK(sc); 1777 1778 sc->sc_tx_timer = 0; 1779 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 1780 1781 ural_close_pipes(sc); 1782 1783 RAL_UNLOCK(sc); 1784 1785 return (DDI_SUCCESS); 1786} 1787 1788static int 1789ural_online(dev_info_t *devinfo) 1790{ 1791 struct ural_softc *sc; 1792 int err; 1793 1794 RAL_DEBUG(RAL_DBG_MSG, "ural_online()\n"); 1795 1796 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo)); 1797 err = ural_init(sc); 1798 1799 return (err); 1800} 1801 1802#define URAL_AMRR_MIN_SUCCESS_THRESHOLD 1 1803#define URAL_AMRR_MAX_SUCCESS_THRESHOLD 10 1804 1805/* 1806 * Naive implementation of the Adaptive Multi Rate Retry algorithm: 1807 * "IEEE 802.11 Rate Adaptation: A Practical Approach" 1808 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti 1809 * INRIA Sophia - Projet Planete 1810 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html 1811 * 1812 * This algorithm is particularly well suited for ural since it does not 1813 * require per-frame retry statistics. Note however that since h/w does 1814 * not provide per-frame stats, we can't do per-node rate adaptation and 1815 * thus automatic rate adaptation is only enabled in STA operating mode. 1816 */ 1817#define is_success(amrr) \ 1818 ((amrr)->retrycnt < (amrr)->txcnt / 10) 1819#define is_failure(amrr) \ 1820 ((amrr)->retrycnt > (amrr)->txcnt / 3) 1821#define is_enough(amrr) \ 1822 ((amrr)->txcnt > 10) 1823#define is_min_rate(ni) \ 1824 ((ni)->in_txrate == 0) 1825#define is_max_rate(ni) \ 1826 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1) 1827#define increase_rate(ni) \ 1828 ((ni)->in_txrate++) 1829#define decrease_rate(ni) \ 1830 ((ni)->in_txrate--) 1831#define reset_cnt(amrr) do { \ 1832 (amrr)->txcnt = (amrr)->retrycnt = 0; \ 1833 _NOTE(CONSTCOND) \ 1834} while (/* CONSTCOND */0) 1835 1836static void 1837ural_ratectl(struct ural_amrr *amrr, struct ieee80211_node *ni) 1838{ 1839 int need_change = 0; 1840 1841 if (is_success(amrr) && is_enough(amrr)) { 1842 amrr->success++; 1843 if (amrr->success >= amrr->success_threshold && 1844 !is_max_rate(ni)) { 1845 amrr->recovery = 1; 1846 amrr->success = 0; 1847 increase_rate(ni); 1848 need_change = 1; 1849 } else { 1850 amrr->recovery = 0; 1851 } 1852 } else if (is_failure(amrr)) { 1853 amrr->success = 0; 1854 if (!is_min_rate(ni)) { 1855 if (amrr->recovery) { 1856 amrr->success_threshold *= 2; 1857 if (amrr->success_threshold > 1858 URAL_AMRR_MAX_SUCCESS_THRESHOLD) 1859 amrr->success_threshold = 1860 URAL_AMRR_MAX_SUCCESS_THRESHOLD; 1861 } else { 1862 amrr->success_threshold = 1863 URAL_AMRR_MIN_SUCCESS_THRESHOLD; 1864 } 1865 decrease_rate(ni); 1866 need_change = 1; 1867 } 1868 amrr->recovery = 0; /* original paper was incorrect */ 1869 } 1870 1871 if (is_enough(amrr) || need_change) 1872 reset_cnt(amrr); 1873} 1874 1875static void 1876ural_amrr_timeout(void *arg) 1877{ 1878 struct ural_softc *sc = (struct ural_softc *)arg; 1879 struct ural_amrr *amrr = &sc->amrr; 1880 1881 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta)); 1882 1883 /* count TX retry-fail as Tx errors */ 1884 sc->sc_tx_err += sc->sta[9]; 1885 sc->sc_tx_retries += (sc->sta[7] + sc->sta[8]); 1886 1887 amrr->retrycnt = 1888 sc->sta[7] + /* TX one-retry ok count */ 1889 sc->sta[8] + /* TX more-retry ok count */ 1890 sc->sta[9]; /* TX retry-fail count */ 1891 1892 amrr->txcnt = 1893 amrr->retrycnt + 1894 sc->sta[6]; /* TX no-retry ok count */ 1895 1896 ural_ratectl(amrr, sc->sc_ic.ic_bss); 1897 1898 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc, 1899 drv_usectohz(1000 * 1000)); /* 1 second */ 1900} 1901 1902 1903static void 1904ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni) 1905{ 1906 struct ural_amrr *amrr = &sc->amrr; 1907 int i; 1908 1909 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 1910 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta)); 1911 1912 amrr->success = 0; 1913 amrr->recovery = 0; 1914 amrr->txcnt = amrr->retrycnt = 0; 1915 amrr->success_threshold = URAL_AMRR_MIN_SUCCESS_THRESHOLD; 1916 1917 /* set rate to some reasonable initial value */ 1918 for (i = ni->in_rates.ir_nrates - 1; 1919 i > 0 && (ni->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72; 1920 i--) { 1921 } 1922 1923 ni->in_txrate = i; 1924 1925 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc, 1926 drv_usectohz(1000 * 1000)); /* 1 second */ 1927} 1928 1929void 1930ural_watchdog(void *arg) 1931{ 1932 struct ural_softc *sc = arg; 1933 struct ieee80211com *ic = &sc->sc_ic; 1934 int ntimer = 0; 1935 1936 RAL_LOCK(sc); 1937 ic->ic_watchdog_timer = 0; 1938 1939 if (!RAL_IS_RUNNING(sc)) { 1940 RAL_UNLOCK(sc); 1941 return; 1942 } 1943 1944 if (sc->sc_tx_timer > 0) { 1945 if (--sc->sc_tx_timer == 0) { 1946 RAL_DEBUG(RAL_DBG_ERR, "tx timer timeout\n"); 1947 RAL_UNLOCK(sc); 1948 (void) ural_init(sc); 1949 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1950 return; 1951 } 1952 } 1953 1954 if (ic->ic_state == IEEE80211_S_RUN) 1955 ntimer = 1; 1956 1957 RAL_UNLOCK(sc); 1958 1959 ieee80211_watchdog(ic); 1960 1961 if (ntimer) 1962 ieee80211_start_watchdog(ic, ntimer); 1963} 1964 1965static int 1966ural_m_start(void *arg) 1967{ 1968 struct ural_softc *sc = (struct ural_softc *)arg; 1969 crypto_mech_type_t type; 1970 int err; 1971 1972 1973 type = crypto_mech2id(SUN_CKM_RC4); /* load rc4 module into kernel */ 1974 RAL_DEBUG(RAL_DBG_MSG, "ural_m_start(%d)\n", type); 1975 1976 /* 1977 * initialize RT2500USB hardware 1978 */ 1979 err = ural_init(sc); 1980 if (err != DDI_SUCCESS) { 1981 RAL_DEBUG(RAL_DBG_ERR, "device configuration failed\n"); 1982 goto fail; 1983 } 1984 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */ 1985 return (err); 1986 1987fail: 1988 ural_stop(sc); 1989 return (err); 1990} 1991 1992static void 1993ural_m_stop(void *arg) 1994{ 1995 struct ural_softc *sc = (struct ural_softc *)arg; 1996 1997 RAL_DEBUG(RAL_DBG_MSG, "ural_m_stop()\n"); 1998 1999 (void) ural_stop(sc); 2000 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 2001} 2002 2003static int 2004ural_m_unicst(void *arg, const uint8_t *macaddr) 2005{ 2006 struct ural_softc *sc = (struct ural_softc *)arg; 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 2009 RAL_DEBUG(RAL_DBG_MSG, "ural_m_unicst(): " MACSTR "\n", 2010 MAC2STR(macaddr)); 2011 2012 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr); 2013 (void) ural_set_macaddr(sc, (uint8_t *)macaddr); 2014 (void) ural_init(sc); 2015 2016 return (0); 2017} 2018 2019/*ARGSUSED*/ 2020static int 2021ural_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 2022{ 2023 return (0); 2024} 2025 2026static int 2027ural_m_promisc(void *arg, boolean_t on) 2028{ 2029 struct ural_softc *sc = (struct ural_softc *)arg; 2030 2031 RAL_DEBUG(RAL_DBG_MSG, "ural_m_promisc()\n"); 2032 2033 if (on) { 2034 sc->sc_rcr |= RAL_RCR_PROMISC; 2035 sc->sc_rcr |= RAL_RCR_MULTI; 2036 } else { 2037 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2038 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2039 } 2040 2041 ural_update_promisc(sc); 2042 return (0); 2043} 2044 2045static void 2046ural_m_ioctl(void* arg, queue_t *wq, mblk_t *mp) 2047{ 2048 struct ural_softc *sc = (struct ural_softc *)arg; 2049 struct ieee80211com *ic = &sc->sc_ic; 2050 int err; 2051 2052 err = ieee80211_ioctl(ic, wq, mp); 2053 RAL_LOCK(sc); 2054 if (err == ENETRESET) { 2055 if (RAL_IS_RUNNING(sc)) { 2056 RAL_UNLOCK(sc); 2057 (void) ural_init(sc); 2058 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2059 RAL_LOCK(sc); 2060 } 2061 } 2062 RAL_UNLOCK(sc); 2063} 2064 2065static int 2066ural_m_stat(void *arg, uint_t stat, uint64_t *val) 2067{ 2068 struct ural_softc *sc = (struct ural_softc *)arg; 2069 ieee80211com_t *ic = &sc->sc_ic; 2070 ieee80211_node_t *ni = ic->ic_bss; 2071 struct ieee80211_rateset *rs = &ni->in_rates; 2072 2073 RAL_LOCK(sc); 2074 switch (stat) { 2075 case MAC_STAT_IFSPEED: 2076 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ? 2077 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL) 2078 : ic->ic_fixed_rate) / 2 * 1000000; 2079 break; 2080 case MAC_STAT_NOXMTBUF: 2081 *val = sc->sc_tx_nobuf; 2082 break; 2083 case MAC_STAT_NORCVBUF: 2084 *val = sc->sc_rx_nobuf; 2085 break; 2086 case MAC_STAT_IERRORS: 2087 *val = sc->sc_rx_err; 2088 break; 2089 case MAC_STAT_RBYTES: 2090 *val = ic->ic_stats.is_rx_bytes; 2091 break; 2092 case MAC_STAT_IPACKETS: 2093 *val = ic->ic_stats.is_rx_frags; 2094 break; 2095 case MAC_STAT_OBYTES: 2096 *val = ic->ic_stats.is_tx_bytes; 2097 break; 2098 case MAC_STAT_OPACKETS: 2099 *val = ic->ic_stats.is_tx_frags; 2100 break; 2101 case MAC_STAT_OERRORS: 2102 case WIFI_STAT_TX_FAILED: 2103 *val = sc->sc_tx_err; 2104 break; 2105 case WIFI_STAT_TX_RETRANS: 2106 *val = sc->sc_tx_retries; 2107 break; 2108 case WIFI_STAT_FCS_ERRORS: 2109 case WIFI_STAT_WEP_ERRORS: 2110 case WIFI_STAT_TX_FRAGS: 2111 case WIFI_STAT_MCAST_TX: 2112 case WIFI_STAT_RTS_SUCCESS: 2113 case WIFI_STAT_RTS_FAILURE: 2114 case WIFI_STAT_ACK_FAILURE: 2115 case WIFI_STAT_RX_FRAGS: 2116 case WIFI_STAT_MCAST_RX: 2117 case WIFI_STAT_RX_DUPS: 2118 RAL_UNLOCK(sc); 2119 return (ieee80211_stat(ic, stat, val)); 2120 default: 2121 RAL_UNLOCK(sc); 2122 return (ENOTSUP); 2123 } 2124 RAL_UNLOCK(sc); 2125 2126 return (0); 2127} 2128 2129 2130static int 2131ural_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2132{ 2133 struct ural_softc *sc; 2134 struct ieee80211com *ic; 2135 int err, i; 2136 int instance; 2137 2138 char strbuf[32]; 2139 2140 wifi_data_t wd = { 0 }; 2141 mac_register_t *macp; 2142 2143 RAL_DEBUG(RAL_DBG_MSG, "ural_attach()\n"); 2144 2145 if (cmd != DDI_ATTACH) 2146 return (DDI_FAILURE); 2147 2148 instance = ddi_get_instance(devinfo); 2149 2150 if (ddi_soft_state_zalloc(ural_soft_state_p, instance) != DDI_SUCCESS) { 2151 RAL_DEBUG(RAL_DBG_MSG, "ural_attach(): " 2152 "unable to alloc soft_state_p\n"); 2153 return (DDI_FAILURE); 2154 } 2155 2156 sc = ddi_get_soft_state(ural_soft_state_p, instance); 2157 ic = (ieee80211com_t *)&sc->sc_ic; 2158 sc->sc_dev = devinfo; 2159 2160 if (usb_client_attach(devinfo, USBDRV_VERSION, 0) != USB_SUCCESS) { 2161 RAL_DEBUG(RAL_DBG_ERR, 2162 "ural_attach(): usb_client_attach failed\n"); 2163 goto fail1; 2164 } 2165 2166 if (usb_get_dev_data(devinfo, &sc->sc_udev, 2167 USB_PARSE_LVL_ALL, 0) != USB_SUCCESS) { 2168 sc->sc_udev = NULL; 2169 goto fail2; 2170 } 2171 2172 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL); 2173 mutex_init(&sc->tx_lock, NULL, MUTEX_DRIVER, NULL); 2174 mutex_init(&sc->rx_lock, NULL, MUTEX_DRIVER, NULL); 2175 2176 /* retrieve RT2570 rev. no */ 2177 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 2178 2179 /* retrieve MAC address and various other things from EEPROM */ 2180 ural_read_eeprom(sc); 2181 2182 RAL_DEBUG(RAL_DBG_MSG, "ural: MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 2183 sc->asic_rev, ural_get_rf(sc->rf_rev)); 2184 2185 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 2186 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 2187 ic->ic_state = IEEE80211_S_INIT; 2188 2189 ic->ic_maxrssi = 63; 2190 ic->ic_set_shortslot = ural_update_slot; 2191 ic->ic_xmit = ural_send; 2192 2193 /* set device capabilities */ 2194 ic->ic_caps = 2195 IEEE80211_C_TXPMGT | /* tx power management */ 2196 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 2197 IEEE80211_C_SHSLOT; /* short slot time supported */ 2198 2199 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2200 2201#define IEEE80211_CHAN_A \ 2202 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) 2203 2204 if (sc->rf_rev == RAL_RF_5222) { 2205 /* set supported .11a rates */ 2206 ic->ic_sup_rates[IEEE80211_MODE_11A] = ural_rateset_11a; 2207 2208 /* set supported .11a channels */ 2209 for (i = 36; i <= 64; i += 4) { 2210 ic->ic_sup_channels[i].ich_freq = 2211 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2212 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2213 } 2214 for (i = 100; i <= 140; i += 4) { 2215 ic->ic_sup_channels[i].ich_freq = 2216 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2217 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2218 } 2219 for (i = 149; i <= 161; i += 4) { 2220 ic->ic_sup_channels[i].ich_freq = 2221 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2222 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2223 } 2224 } 2225 2226 /* set supported .11b and .11g rates */ 2227 ic->ic_sup_rates[IEEE80211_MODE_11B] = ural_rateset_11b; 2228 ic->ic_sup_rates[IEEE80211_MODE_11G] = ural_rateset_11g; 2229 2230 /* set supported .11b and .11g channels (1 through 14) */ 2231 for (i = 1; i <= 14; i++) { 2232 ic->ic_sup_channels[i].ich_freq = 2233 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 2234 ic->ic_sup_channels[i].ich_flags = 2235 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 2236 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 2237 } 2238 2239 ieee80211_attach(ic); 2240 2241 /* register WPA door */ 2242 ieee80211_register_door(ic, ddi_driver_name(devinfo), 2243 ddi_get_instance(devinfo)); 2244 2245 /* override state transition machine */ 2246 sc->sc_newstate = ic->ic_newstate; 2247 ic->ic_newstate = ural_newstate; 2248 ic->ic_watchdog = ural_watchdog; 2249 ieee80211_media_init(ic); 2250 ic->ic_def_txkey = 0; 2251 2252 sc->sc_rcr = 0; 2253 sc->dwelltime = 300; 2254 sc->sc_flags &= ~RAL_FLAG_RUNNING; 2255 2256 /* 2257 * Provide initial settings for the WiFi plugin; whenever this 2258 * information changes, we need to call mac_plugindata_update() 2259 */ 2260 wd.wd_opmode = ic->ic_opmode; 2261 wd.wd_secalloc = WIFI_SEC_NONE; 2262 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2263 2264 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2265 RAL_DEBUG(RAL_DBG_ERR, "ural_attach(): " 2266 "MAC version mismatch\n"); 2267 goto fail3; 2268 } 2269 2270 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2271 macp->m_driver = sc; 2272 macp->m_dip = devinfo; 2273 macp->m_src_addr = ic->ic_macaddr; 2274 macp->m_callbacks = &ural_m_callbacks; 2275 macp->m_min_sdu = 0; 2276 macp->m_max_sdu = IEEE80211_MTU; 2277 macp->m_pdata = &wd; 2278 macp->m_pdata_size = sizeof (wd); 2279 2280 err = mac_register(macp, &ic->ic_mach); 2281 mac_free(macp); 2282 if (err != 0) { 2283 RAL_DEBUG(RAL_DBG_ERR, "ural_attach(): " 2284 "mac_register() err %x\n", err); 2285 goto fail3; 2286 } 2287 2288 if (usb_register_hotplug_cbs(devinfo, ural_offline, 2289 ural_online) != USB_SUCCESS) { 2290 RAL_DEBUG(RAL_DBG_ERR, 2291 "ural: ural_attach() failed to register events"); 2292 goto fail4; 2293 } 2294 2295 /* 2296 * Create minor node of type DDI_NT_NET_WIFI 2297 */ 2298 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2299 "ural", instance); 2300 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2301 instance + 1, DDI_NT_NET_WIFI, 0); 2302 2303 if (err != DDI_SUCCESS) 2304 RAL_DEBUG(RAL_DBG_ERR, "ddi_create_minor_node() failed\n"); 2305 2306 /* 2307 * Notify link is down now 2308 */ 2309 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2310 2311 RAL_DEBUG(RAL_DBG_MSG, "ural_attach() done successfully.\n"); 2312 return (DDI_SUCCESS); 2313fail4: 2314 (void) mac_unregister(ic->ic_mach); 2315fail3: 2316 mutex_destroy(&sc->sc_genlock); 2317 mutex_destroy(&sc->tx_lock); 2318 mutex_destroy(&sc->rx_lock); 2319fail2: 2320 usb_client_detach(sc->sc_dev, sc->sc_udev); 2321fail1: 2322 ddi_soft_state_free(ural_soft_state_p, ddi_get_instance(devinfo)); 2323 2324 return (DDI_FAILURE); 2325} 2326 2327static int 2328ural_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2329{ 2330 struct ural_softc *sc; 2331 2332 RAL_DEBUG(RAL_DBG_MSG, "ural_detach()\n"); 2333 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo)); 2334 2335 if (cmd != DDI_DETACH) 2336 return (DDI_FAILURE); 2337 2338 if (mac_disable(sc->sc_ic.ic_mach) != 0) 2339 return (DDI_FAILURE); 2340 2341 ural_stop(sc); 2342 usb_unregister_hotplug_cbs(devinfo); 2343 2344 /* 2345 * Unregister from the MAC layer subsystem 2346 */ 2347 (void) mac_unregister(sc->sc_ic.ic_mach); 2348 2349 /* 2350 * detach ieee80211 layer 2351 */ 2352 ieee80211_detach(&sc->sc_ic); 2353 2354 mutex_destroy(&sc->sc_genlock); 2355 mutex_destroy(&sc->tx_lock); 2356 mutex_destroy(&sc->rx_lock); 2357 2358 /* pipes will be close in ural_stop() */ 2359 usb_client_detach(devinfo, sc->sc_udev); 2360 sc->sc_udev = NULL; 2361 2362 ddi_remove_minor_node(devinfo, NULL); 2363 ddi_soft_state_free(ural_soft_state_p, ddi_get_instance(devinfo)); 2364 2365 return (DDI_SUCCESS); 2366} 2367 2368int 2369_info(struct modinfo *modinfop) 2370{ 2371 return (mod_info(&modlinkage, modinfop)); 2372} 2373 2374int 2375_init(void) 2376{ 2377 int status; 2378 2379 status = ddi_soft_state_init(&ural_soft_state_p, 2380 sizeof (struct ural_softc), 1); 2381 if (status != 0) 2382 return (status); 2383 2384 mac_init_ops(&ural_dev_ops, "ural"); 2385 status = mod_install(&modlinkage); 2386 if (status != 0) { 2387 mac_fini_ops(&ural_dev_ops); 2388 ddi_soft_state_fini(&ural_soft_state_p); 2389 } 2390 return (status); 2391} 2392 2393int 2394_fini(void) 2395{ 2396 int status; 2397 2398 status = mod_remove(&modlinkage); 2399 if (status == 0) { 2400 mac_fini_ops(&ural_dev_ops); 2401 ddi_soft_state_fini(&ural_soft_state_p); 2402 } 2403 return (status); 2404} 2405