ahci.c revision 9204:561855cf06ec
1193323Sed/* 2193323Sed * CDDL HEADER START 3193323Sed * 4193323Sed * The contents of this file are subject to the terms of the 5193323Sed * Common Development and Distribution License (the "License"). 6193323Sed * You may not use this file except in compliance with the License. 7193323Sed * 8193323Sed * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9193323Sed * or http://www.opensolaris.org/os/licensing. 10193323Sed * See the License for the specific language governing permissions 11193323Sed * and limitations under the License. 12193323Sed * 13193323Sed * When distributing Covered Code, include this CDDL HEADER in each 14193323Sed * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15193323Sed * If applicable, add the following below this CDDL HEADER, with the 16193323Sed * fields enclosed by brackets "[]" replaced with your own identifying 17193323Sed * information: Portions Copyright [yyyy] [name of copyright owner] 18193323Sed * 19193323Sed * CDDL HEADER END 20193323Sed */ 21193323Sed 22193323Sed/* 23193323Sed * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24193323Sed * Use is subject to license terms. 25193323Sed */ 26198090Srdivacky 27193323Sed/* 28193323Sed * AHCI (Advanced Host Controller Interface) SATA HBA Driver 29193323Sed * 30193323Sed * Power Management Support 31193323Sed * ------------------------ 32193323Sed * 33198090Srdivacky * At the moment, the ahci driver only implements suspend/resume to 34198090Srdivacky * support Suspend to RAM on X86 feature. Device power management isn't 35198090Srdivacky * implemented, link power management is disabled, and hot plug isn't 36198090Srdivacky * allowed during the period from suspend to resume. 37198090Srdivacky * 38198090Srdivacky * For s/r support, the ahci driver only need to implement DDI_SUSPEND 39193323Sed * and DDI_RESUME entries, and don't need to take care of new requests 40193323Sed * sent down after suspend because the target driver (sd) has already 41193323Sed * handled these conditions, and blocked these requests. For the detailed 42193323Sed * information, please check with sdopen, sdclose and sdioctl routines. 43193323Sed * 44193323Sed */ 45193323Sed 46193323Sed#include <sys/note.h> 47198090Srdivacky#include <sys/scsi/scsi.h> 48193323Sed#include <sys/pci.h> 49193323Sed#include <sys/disp.h> 50193323Sed#include <sys/sata/sata_hba.h> 51193323Sed#include <sys/sata/adapters/ahci/ahcireg.h> 52193323Sed#include <sys/sata/adapters/ahci/ahcivar.h> 53193323Sed 54193323Sed/* 55193323Sed * This is the string displayed by modinfo, etc. 56193323Sed * Make sure you keep the version ID up to date! 57193323Sed */ 58193323Sedstatic char ahci_ident[] = "ahci driver"; 59193323Sed 60193323Sed/* 61193323Sed * Function prototypes for driver entry points 62193323Sed */ 63193323Sedstatic int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 64193323Sedstatic int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 65193323Sedstatic int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 66193323Sedstatic int ahci_quiesce(dev_info_t *); 67193323Sed 68193323Sed/* 69193323Sed * Function prototypes for SATA Framework interfaces 70193323Sed */ 71193323Sedstatic int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 72193323Sedstatic int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 73193323Sed 74193323Sedstatic int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 75193323Sedstatic int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 76193323Sedstatic int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 77193323Sedstatic int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 78193323Sedstatic int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 79193323Sedstatic int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 80193323Sed#if defined(__lock_lint) 81198090Srdivackystatic int ahci_selftest(dev_info_t *, sata_device_t *); 82198090Srdivacky#endif 83193323Sed 84193323Sed/* 85193323Sed * Local function prototypes 86193323Sed */ 87193323Sedstatic int ahci_alloc_ports_state(ahci_ctl_t *); 88193323Sedstatic void ahci_dealloc_ports_state(ahci_ctl_t *); 89193323Sedstatic int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 90193323Sedstatic void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 91193323Sedstatic int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 92193323Sedstatic void ahci_dealloc_rcvd_fis(ahci_port_t *); 93193323Sedstatic int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 94193323Sedstatic void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 95193323Sedstatic int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 96193323Sedstatic void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 97193323Sed 98193323Sedstatic int ahci_initialize_controller(ahci_ctl_t *); 99193323Sedstatic void ahci_uninitialize_controller(ahci_ctl_t *); 100193323Sedstatic int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 101193323Sedstatic int ahci_config_space_init(ahci_ctl_t *); 102193323Sed 103193323Sedstatic void ahci_drain_ports_taskq(ahci_ctl_t *); 104193323Sedstatic void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 105193323Sedstatic int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 106193323Sedstatic void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 107193323Sedstatic void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 108193323Sedstatic int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 109193323Sed uint8_t, sata_pkt_t *); 110193323Sedstatic int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 111193323Sed uint8_t, sata_pkt_t *); 112193323Sedstatic int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 113193323Sedstatic void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 114193323Sedstatic void ahci_copy_ncq_err_page(sata_cmd_t *, 115193323Sed struct sata_ncq_error_recovery_page *); 116193323Sedstatic void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 117193323Sed 118193323Sedstatic int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 119193323Sedstatic int ahci_hba_reset(ahci_ctl_t *); 120193323Sedstatic int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 121193323Sedstatic void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 122193323Sedstatic int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 123193323Sedstatic int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 124193323Sedstatic int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 125193323Sedstatic int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 126193323Sed uint8_t); 127193323Sedstatic int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 128194612Sed uint8_t, int, int *); 129193323Sedstatic void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 130194612Sed uint32_t, uint32_t, uint32_t, uint32_t); 131195340Sedstatic uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 132193323Sedstatic void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 133193323Sed uint8_t, sata_pkt_t *); 134193323Sedstatic void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 135193323Sed uint8_t, uint32_t); 136193323Sedstatic void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 137193323Sed uint8_t, uint32_t); 138193323Sedstatic void ahci_events_handler(void *); 139193323Sedstatic void ahci_watchdog_handler(ahci_ctl_t *); 140194612Sed 141193323Sedstatic uint_t ahci_intr(caddr_t, caddr_t); 142193323Sedstatic void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 143193323Sedstatic int ahci_add_intrs(ahci_ctl_t *, int); 144198090Srdivackystatic void ahci_rem_intrs(ahci_ctl_t *); 145195340Sedstatic void ahci_enable_all_intrs(ahci_ctl_t *); 146193323Sedstatic void ahci_disable_all_intrs(ahci_ctl_t *); 147193323Sedstatic void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 148193323Sedstatic void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 149193323Sed 150194612Sedstatic int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 151193323Sedstatic int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 152193323Sedstatic int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 153193323Sedstatic int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 154194612Sed ahci_port_t *, uint8_t); 155194612Sedstatic int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 156194612Sedstatic int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 157193323Sed uint8_t, uint32_t); 158193323Sedstatic int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 159193323Sed uint8_t, uint32_t); 160193323Sedstatic int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 161193323Sed 162193323Sedstatic int ahci_get_num_implemented_ports(uint32_t); 163193323Sedstatic void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 164193323Sed uint32_t); 165193323Sedstatic void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 166193323Sed#if AHCI_DEBUG 167193323Sedstatic void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 168193323Sed#endif 169193323Sed 170193323Sed 171195340Sed/* 172193323Sed * DMA attributes for the data buffer 173195340Sed * 174198090Srdivacky * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 175193323Sed * does not support 64-bit addressing 176195340Sed */ 177195340Sedstatic ddi_dma_attr_t buffer_dma_attr = { 178195340Sed DMA_ATTR_V0, /* dma_attr_version */ 179193323Sed 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 180193323Sed 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 181193323Sed 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 182193323Sed 0x2ull, /* dma_attr_align: word aligned */ 183193323Sed 1, /* dma_attr_burstsizes */ 184193323Sed 1, /* dma_attr_minxfer */ 185193323Sed 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 186193323Sed 0xffffffffull, /* dma_attr_seg */ 187193323Sed AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 188193323Sed 512, /* dma_attr_granular */ 189193323Sed 0, /* dma_attr_flags */ 190193323Sed}; 191193323Sed 192193323Sed/* 193193323Sed * DMA attributes for the rcvd FIS 194193323Sed * 195193323Sed * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 196193323Sed * does not support 64-bit addressing 197193323Sed */ 198193323Sedstatic ddi_dma_attr_t rcvd_fis_dma_attr = { 199193323Sed DMA_ATTR_V0, /* dma_attr_version */ 200193323Sed 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 201193323Sed 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 202193323Sed 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 203193323Sed 0x100ull, /* dma_attr_align: 256-byte aligned */ 204193323Sed 1, /* dma_attr_burstsizes */ 205193323Sed 1, /* dma_attr_minxfer */ 206193323Sed 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 207193323Sed 0xffffffffull, /* dma_attr_seg */ 208193323Sed 1, /* dma_attr_sgllen */ 209193323Sed 1, /* dma_attr_granular */ 210193323Sed 0, /* dma_attr_flags */ 211193323Sed}; 212193323Sed 213193323Sed/* 214193323Sed * DMA attributes for the command list 215193323Sed * 216198090Srdivacky * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 217198090Srdivacky * does not support 64-bit addressing 218198090Srdivacky */ 219193323Sedstatic ddi_dma_attr_t cmd_list_dma_attr = { 220193323Sed DMA_ATTR_V0, /* dma_attr_version */ 221193323Sed 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 222193323Sed 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 223193323Sed 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 224193323Sed 0x400ull, /* dma_attr_align: 1K-byte aligned */ 225193323Sed 1, /* dma_attr_burstsizes */ 226193323Sed 1, /* dma_attr_minxfer */ 227193323Sed 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 228193323Sed 0xffffffffull, /* dma_attr_seg */ 229193323Sed 1, /* dma_attr_sgllen */ 230193323Sed 1, /* dma_attr_granular */ 231193323Sed 0, /* dma_attr_flags */ 232193323Sed}; 233193323Sed 234193323Sed/* 235193323Sed * DMA attributes for cmd tables 236193323Sed * 237193323Sed * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 238193323Sed * does not support 64-bit addressing 239193323Sed */ 240193323Sedstatic ddi_dma_attr_t cmd_table_dma_attr = { 241193323Sed DMA_ATTR_V0, /* dma_attr_version */ 242193323Sed 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 243193323Sed 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 244193323Sed 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 245193323Sed 0x80ull, /* dma_attr_align: 128-byte aligned */ 246193323Sed 1, /* dma_attr_burstsizes */ 247193323Sed 1, /* dma_attr_minxfer */ 248193323Sed 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 249193323Sed 0xffffffffull, /* dma_attr_seg */ 250193323Sed 1, /* dma_attr_sgllen */ 251193323Sed 1, /* dma_attr_granular */ 252193323Sed 0, /* dma_attr_flags */ 253193323Sed}; 254193323Sed 255193323Sed 256195340Sed/* Device access attributes */ 257193323Sedstatic ddi_device_acc_attr_t accattr = { 258193323Sed DDI_DEVICE_ATTR_V0, 259193323Sed DDI_STRUCTURE_LE_ACC, 260193323Sed DDI_STRICTORDER_ACC 261195340Sed}; 262193323Sed 263193323Sed 264193323Sedstatic struct dev_ops ahcictl_dev_ops = { 265195340Sed DEVO_REV, /* devo_rev */ 266193323Sed 0, /* refcnt */ 267195340Sed ahci_getinfo, /* info */ 268193323Sed nulldev, /* identify */ 269195340Sed nulldev, /* probe */ 270193323Sed ahci_attach, /* attach */ 271193323Sed ahci_detach, /* detach */ 272195340Sed nodev, /* no reset */ 273193323Sed (struct cb_ops *)0, /* driver operations */ 274193323Sed NULL, /* bus operations */ 275193323Sed NULL, /* power */ 276193323Sed ahci_quiesce, /* quiesce */ 277193323Sed}; 278 279static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 280 SATA_TRAN_HOTPLUG_OPS_REV_1, 281 ahci_tran_hotplug_port_activate, 282 ahci_tran_hotplug_port_deactivate 283}; 284 285extern struct mod_ops mod_driverops; 286 287static struct modldrv modldrv = { 288 &mod_driverops, /* driverops */ 289 ahci_ident, /* short description */ 290 &ahcictl_dev_ops, /* driver ops */ 291}; 292 293static struct modlinkage modlinkage = { 294 MODREV_1, 295 &modldrv, 296 NULL 297}; 298 299/* The following variables are watchdog handler related */ 300static int ahci_watchdog_timeout = 5; /* 5 seconds */ 301static int ahci_watchdog_tick; 302 303/* 304 * This static variable indicates the size of command table, 305 * and it's changeable with prdt number, which ahci_dma_prdt_number 306 * indicates. 307 */ 308static size_t ahci_cmd_table_size; 309 310/* 311 * ahci_dma_prdt_number, ahci_msi_enabled and ahci_64bit_dma_addressed 312 * are global variables, and can be changed via /etc/system file. 313 */ 314 315/* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 316int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 317 318/* AHCI MSI is tunable */ 319boolean_t ahci_msi_enabled = B_TRUE; 320 321/* 64-bit dma addressing is tunable */ 322boolean_t ahci_64bit_dma_addressed = B_TRUE; 323 324#if AHCI_DEBUG 325uint32_t ahci_debug_flags = 0; 326 327/* The following is needed for ahci_log() */ 328static kmutex_t ahci_log_mutex; 329static char ahci_log_buf[512]; 330#endif 331 332/* Opaque state pointer initialized by ddi_soft_state_init() */ 333static void *ahci_statep = NULL; 334 335/* 336 * ahci module initialization. 337 */ 338int 339_init(void) 340{ 341 int ret; 342 343 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 344 if (ret != 0) { 345 goto err_out; 346 } 347 348#if AHCI_DEBUG 349 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 350#endif 351 352 if ((ret = sata_hba_init(&modlinkage)) != 0) { 353#if AHCI_DEBUG 354 mutex_destroy(&ahci_log_mutex); 355#endif 356 ddi_soft_state_fini(&ahci_statep); 357 goto err_out; 358 } 359 360 ret = mod_install(&modlinkage); 361 if (ret != 0) { 362 sata_hba_fini(&modlinkage); 363#if AHCI_DEBUG 364 mutex_destroy(&ahci_log_mutex); 365#endif 366 ddi_soft_state_fini(&ahci_statep); 367 goto err_out; 368 } 369 370 /* watchdog tick */ 371 ahci_watchdog_tick = drv_usectohz( 372 (clock_t)ahci_watchdog_timeout * 1000000); 373 return (ret); 374 375err_out: 376 cmn_err(CE_WARN, "!ahci: Module init failed"); 377 return (ret); 378} 379 380/* 381 * ahci module uninitialize. 382 */ 383int 384_fini(void) 385{ 386 int ret; 387 388 ret = mod_remove(&modlinkage); 389 if (ret != 0) { 390 return (ret); 391 } 392 393 /* Remove the resources allocated in _init(). */ 394 sata_hba_fini(&modlinkage); 395#if AHCI_DEBUG 396 mutex_destroy(&ahci_log_mutex); 397#endif 398 ddi_soft_state_fini(&ahci_statep); 399 400 return (ret); 401} 402 403/* 404 * _info entry point 405 */ 406int 407_info(struct modinfo *modinfop) 408{ 409 return (mod_info(&modlinkage, modinfop)); 410} 411 412/* 413 * The attach entry point for dev_ops. 414 */ 415static int 416ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 417{ 418 ahci_ctl_t *ahci_ctlp; 419 int instance = ddi_get_instance(dip); 420 int status; 421 int attach_state; 422 uint32_t cap_status, ahci_version; 423 int intr_types; 424 int i; 425 pci_regspec_t *regs; 426 int regs_length; 427 int rnumber; 428#if AHCI_DEBUG 429 int speed; 430#endif 431 432 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 433 434 switch (cmd) { 435 case DDI_ATTACH: 436 break; 437 438 case DDI_RESUME: 439 440 /* 441 * During DDI_RESUME, the hardware state of the device 442 * (power may have been removed from the device) must be 443 * restored, allow pending requests to continue, and 444 * service new requests. 445 */ 446 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 447 mutex_enter(&ahci_ctlp->ahcictl_mutex); 448 449 /* Restart watch thread */ 450 if (ahci_ctlp->ahcictl_timeout_id == 0) 451 ahci_ctlp->ahcictl_timeout_id = timeout( 452 (void (*)(void *))ahci_watchdog_handler, 453 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 454 455 mutex_exit(&ahci_ctlp->ahcictl_mutex); 456 457 /* 458 * Re-initialize the controller and enable the interrupts and 459 * restart all the ports. 460 * 461 * Note that so far we don't support hot-plug during 462 * suspend/resume. 463 */ 464 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 465 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 466 "Failed to initialize the controller " 467 "during DDI_RESUME"); 468 return (DDI_FAILURE); 469 } 470 471 mutex_enter(&ahci_ctlp->ahcictl_mutex); 472 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 473 mutex_exit(&ahci_ctlp->ahcictl_mutex); 474 475 return (DDI_SUCCESS); 476 477 default: 478 return (DDI_FAILURE); 479 } 480 481 attach_state = AHCI_ATTACH_STATE_NONE; 482 483 /* Allocate soft state */ 484 status = ddi_soft_state_zalloc(ahci_statep, instance); 485 if (status != DDI_SUCCESS) { 486 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 487 instance); 488 goto err_out; 489 } 490 491 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 492 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 493 ahci_ctlp->ahcictl_dip = dip; 494 495 /* Initialize the cport/port mapping */ 496 for (i = 0; i < AHCI_MAX_PORTS; i++) { 497 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 498 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 499 } 500 501 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 502 503 /* 504 * Now map the AHCI base address; which includes global 505 * registers and port control registers 506 * 507 * According to the spec, the AHCI Base Address is BAR5, 508 * but BAR0-BAR4 are optional, so we need to check which 509 * rnumber is used for BAR5. 510 */ 511 512 /* 513 * search through DDI "reg" property for the AHCI register set 514 */ 515 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 516 DDI_PROP_DONTPASS, "reg", (int **)®s, 517 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 518 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 519 instance); 520 goto err_out; 521 } 522 523 /* AHCI Base Address is located at 0x24 offset */ 524 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 525 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 526 == AHCI_PCI_RNUM) 527 break; 528 } 529 530 ddi_prop_free(regs); 531 532 if (rnumber == regs_length) { 533 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 534 instance); 535 goto err_out; 536 } 537 538 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 539 540 status = ddi_regs_map_setup(dip, 541 rnumber, 542 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 543 0, 544 0, 545 &accattr, 546 &ahci_ctlp->ahcictl_ahci_acc_handle); 547 if (status != DDI_SUCCESS) { 548 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 549 instance); 550 goto err_out; 551 } 552 553 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 554 555 /* Get the AHCI version information */ 556 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 557 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 558 559 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 560 (ahci_version & 0xffff0000) >> 16, 561 ((ahci_version & 0x0000ff00) >> 4 | 562 (ahci_version & 0x000000ff))); 563 564 /* We don't support controllers whose versions are lower than 1.0 */ 565 if (!(ahci_version & 0xffff0000)) { 566 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 567 "than version 1.0", instance); 568 goto err_out; 569 } 570 571 /* Get the HBA capabilities information */ 572 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 573 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 574 575 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 576 cap_status); 577 578#if AHCI_DEBUG 579 /* Get the interface speed supported by the HBA */ 580 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 581 if (speed == 0x01) { 582 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 583 "hba interface speed support: Gen 1 (1.5Gbps)"); 584 } else if (speed == 0x10) { 585 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 586 "hba interface speed support: Gen 2 (3 Gbps)"); 587 } else if (speed == 0x11) { 588 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 589 "hba interface speed support: Gen 3 (6 Gbps)"); 590 } 591#endif 592 593 /* Get the number of command slots supported by the HBA */ 594 ahci_ctlp->ahcictl_num_cmd_slots = 595 ((cap_status & AHCI_HBA_CAP_NCS) >> 596 AHCI_HBA_CAP_NCS_SHIFT) + 1; 597 598 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 599 ahci_ctlp->ahcictl_num_cmd_slots); 600 601 /* Get the bit map which indicates ports implemented by the HBA */ 602 ahci_ctlp->ahcictl_ports_implemented = 603 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 604 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 605 606 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 607 ahci_ctlp->ahcictl_ports_implemented); 608 609 /* 610 * According to the AHCI spec, CAP.NP should indicate the maximum 611 * number of ports supported by the HBA silicon, but we found 612 * this value of ICH8 chipset only indicates the number of ports 613 * implemented (exposed) by it. Therefore, the driver should calculate 614 * the potential maximum value by checking PI register, and use 615 * the maximum of this value and CAP.NP. 616 */ 617 ahci_ctlp->ahcictl_num_ports = max( 618 (cap_status & AHCI_HBA_CAP_NP) + 1, 619 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 620 621 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 622 ahci_ctlp->ahcictl_num_ports); 623 624 /* Get the number of implemented ports by the HBA */ 625 ahci_ctlp->ahcictl_num_implemented_ports = 626 ahci_get_num_implemented_ports( 627 ahci_ctlp->ahcictl_ports_implemented); 628 629 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 630 "hba number of implemented ports: %d", 631 ahci_ctlp->ahcictl_num_implemented_ports); 632 633 /* Check whether HBA supports 64bit DMA addressing */ 634 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 635 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 636 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 637 "hba does not support 64-bit addressing"); 638 } 639 640 /* Checking for Support Command List Override */ 641 if (cap_status & AHCI_HBA_CAP_SCLO) { 642 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SCLO; 643 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 644 "hba supports command list override."); 645 } 646 647 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 648 != DDI_SUCCESS) { 649 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 650 instance); 651 goto err_out; 652 } 653 654 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 655 656 /* 657 * Check the pci configuration space, and set caps. We also 658 * handle the hardware defect in this function. 659 * 660 * For example, force ATI SB600/SB700/SB750 to use 32-bit dma 661 * addressing since it doesn't support 64-bit dma though their 662 * registers declare they support. 663 */ 664 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 665 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 666 instance); 667 goto err_out; 668 } 669 670 /* 671 * Disable the whole controller interrupts before adding 672 * interrupt handlers(s). 673 */ 674 ahci_disable_all_intrs(ahci_ctlp); 675 676 /* Get supported interrupt types */ 677 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 678 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 679 instance); 680 goto err_out; 681 } 682 683 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 684 "ddi_intr_get_supported_types() returned: 0x%x", 685 intr_types); 686 687 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 688 /* 689 * Try MSI first, but fall back to FIXED if failed 690 */ 691 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_MSI) == 692 DDI_SUCCESS) { 693 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 694 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 695 "Using MSI interrupt type"); 696 goto intr_done; 697 } 698 699 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 700 "MSI registration failed, " 701 "trying FIXED interrupts"); 702 } 703 704 if (intr_types & DDI_INTR_TYPE_FIXED) { 705 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_FIXED) == 706 DDI_SUCCESS) { 707 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 708 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 709 "Using FIXED interrupt type"); 710 goto intr_done; 711 } 712 713 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 714 "FIXED interrupt registration failed"); 715 } 716 717 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 718 719 goto err_out; 720 721intr_done: 722 723 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 724 725 /* Initialize the controller mutex */ 726 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 727 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 728 729 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 730 731 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 732 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 733 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 734 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 735 } 736 737 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 738 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 739 sizeof (ahci_prdt_item_t)); 740 741 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 742 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 743 " ahci_cmd_table_size is 0x%x", 744 ahci_dma_prdt_number, ahci_cmd_table_size); 745 746 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 747 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 748 ahci_dma_prdt_number; 749 750 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 751 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 752 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 753 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 754 755 if ((ahci_64bit_dma_addressed == B_FALSE) || 756 (ahci_ctlp->ahcictl_cap & AHCI_CAP_32BIT_DMA)) { 757 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 758 0xffffffffull; 759 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 760 0xffffffffull; 761 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 762 0xffffffffull; 763 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 764 0xffffffffull; 765 } 766 767 /* Allocate the ports structure */ 768 status = ahci_alloc_ports_state(ahci_ctlp); 769 if (status != AHCI_SUCCESS) { 770 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 771 instance); 772 goto err_out; 773 } 774 775 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 776 777 /* 778 * Initialize the controller and ports. 779 */ 780 status = ahci_initialize_controller(ahci_ctlp); 781 if (status != AHCI_SUCCESS) { 782 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 783 instance); 784 goto err_out; 785 } 786 787 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 788 789 /* Start one thread to check packet timeouts */ 790 ahci_ctlp->ahcictl_timeout_id = timeout( 791 (void (*)(void *))ahci_watchdog_handler, 792 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 793 794 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 795 796 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 797 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 798 instance); 799 goto err_out; 800 } 801 802 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 803 804 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 805 806 return (DDI_SUCCESS); 807 808err_out: 809 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 810 mutex_enter(&ahci_ctlp->ahcictl_mutex); 811 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 812 ahci_ctlp->ahcictl_timeout_id = 0; 813 mutex_exit(&ahci_ctlp->ahcictl_mutex); 814 } 815 816 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 817 ahci_uninitialize_controller(ahci_ctlp); 818 } 819 820 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 821 ahci_dealloc_ports_state(ahci_ctlp); 822 } 823 824 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 825 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 826 } 827 828 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 829 ahci_rem_intrs(ahci_ctlp); 830 } 831 832 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 833 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 834 } 835 836 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 837 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 838 } 839 840 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 841 ddi_soft_state_free(ahci_statep, instance); 842 } 843 844 return (DDI_FAILURE); 845} 846 847/* 848 * The detach entry point for dev_ops. 849 */ 850static int 851ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 852{ 853 ahci_ctl_t *ahci_ctlp; 854 int instance; 855 int ret; 856 857 instance = ddi_get_instance(dip); 858 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 859 860 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 861 862 switch (cmd) { 863 case DDI_DETACH: 864 865 /* disable the interrupts for an uninterrupted detach */ 866 mutex_enter(&ahci_ctlp->ahcictl_mutex); 867 ahci_disable_all_intrs(ahci_ctlp); 868 mutex_exit(&ahci_ctlp->ahcictl_mutex); 869 870 /* unregister from the sata framework. */ 871 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 872 if (ret != AHCI_SUCCESS) { 873 mutex_enter(&ahci_ctlp->ahcictl_mutex); 874 ahci_enable_all_intrs(ahci_ctlp); 875 mutex_exit(&ahci_ctlp->ahcictl_mutex); 876 return (DDI_FAILURE); 877 } 878 879 mutex_enter(&ahci_ctlp->ahcictl_mutex); 880 881 /* stop the watchdog handler */ 882 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 883 ahci_ctlp->ahcictl_timeout_id = 0; 884 885 mutex_exit(&ahci_ctlp->ahcictl_mutex); 886 887 /* uninitialize the controller */ 888 ahci_uninitialize_controller(ahci_ctlp); 889 890 /* remove the interrupts */ 891 ahci_rem_intrs(ahci_ctlp); 892 893 /* deallocate the ports structures */ 894 ahci_dealloc_ports_state(ahci_ctlp); 895 896 /* destroy mutex */ 897 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 898 899 /* teardown the pci config */ 900 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 901 902 /* remove the reg maps. */ 903 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 904 905 /* free the soft state. */ 906 ddi_soft_state_free(ahci_statep, instance); 907 908 return (DDI_SUCCESS); 909 910 case DDI_SUSPEND: 911 912 /* 913 * The steps associated with suspension must include putting 914 * the underlying device into a quiescent state so that it 915 * will not generate interrupts or modify or access memory. 916 */ 917 mutex_enter(&ahci_ctlp->ahcictl_mutex); 918 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 919 mutex_exit(&ahci_ctlp->ahcictl_mutex); 920 return (DDI_SUCCESS); 921 } 922 923 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 924 925 /* stop the watchdog handler */ 926 if (ahci_ctlp->ahcictl_timeout_id) { 927 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 928 ahci_ctlp->ahcictl_timeout_id = 0; 929 } 930 931 mutex_exit(&ahci_ctlp->ahcictl_mutex); 932 933 /* 934 * drain the taskq 935 */ 936 ahci_drain_ports_taskq(ahci_ctlp); 937 938 /* 939 * Disable the interrupts and stop all the ports. 940 */ 941 ahci_uninitialize_controller(ahci_ctlp); 942 943 return (DDI_SUCCESS); 944 945 default: 946 return (DDI_FAILURE); 947 } 948} 949 950/* 951 * The info entry point for dev_ops. 952 * 953 */ 954static int 955ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 956 void *arg, void **result) 957{ 958#ifndef __lock_lint 959 _NOTE(ARGUNUSED(dip)) 960#endif /* __lock_lint */ 961 962 ahci_ctl_t *ahci_ctlp; 963 int instance; 964 dev_t dev; 965 966 dev = (dev_t)arg; 967 instance = getminor(dev); 968 969 switch (infocmd) { 970 case DDI_INFO_DEVT2DEVINFO: 971 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 972 if (ahci_ctlp != NULL) { 973 *result = ahci_ctlp->ahcictl_dip; 974 return (DDI_SUCCESS); 975 } else { 976 *result = NULL; 977 return (DDI_FAILURE); 978 } 979 case DDI_INFO_DEVT2INSTANCE: 980 *(int *)result = instance; 981 break; 982 default: 983 break; 984 } 985 986 return (DDI_SUCCESS); 987} 988 989/* 990 * Registers the ahci with sata framework. 991 */ 992static int 993ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 994{ 995 struct sata_hba_tran *sata_hba_tran; 996 997 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 998 "ahci_register_sata_hba_tran enter"); 999 1000 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1001 1002 /* Allocate memory for the sata_hba_tran */ 1003 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 1004 1005 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 1006 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 1007 sata_hba_tran->sata_tran_hba_dma_attr = 1008 &ahci_ctlp->ahcictl_buffer_dma_attr; 1009 1010 /* Report the number of implemented ports */ 1011 sata_hba_tran->sata_tran_hba_num_cports = 1012 ahci_ctlp->ahcictl_num_implemented_ports; 1013 1014 /* Support ATAPI device */ 1015 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1016 1017 /* Get the data transfer capability for PIO command by the HBA */ 1018 if (cap_status & AHCI_HBA_CAP_PMD) { 1019 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1020 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1021 "DRQ block data transfer for PIO command protocol"); 1022 } 1023 1024 /* 1025 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1026 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1027 * QUEUED (EXT), and SERVICE commands). Queued operations are 1028 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1029 * QUEUED commands when the HBA and device support native command 1030 * queuing(NCQ). 1031 * 1032 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1033 * CAP register of the HBA indicates NCQ is supported. 1034 * 1035 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1036 * set because the previous register content of PxCI can be re-written 1037 * in the register write. 1038 */ 1039 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1040 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1041 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1042 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1043 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1044 "Command Queuing"); 1045 } 1046 1047 /* Report the number of command slots */ 1048 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1049 1050 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1051 sata_hba_tran->sata_tran_start = ahci_tran_start; 1052 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1053 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1054 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1055#ifdef __lock_lint 1056 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1057#endif 1058 /* 1059 * When SATA framework adds support for pwrmgt the 1060 * pwrmgt_ops needs to be updated 1061 */ 1062 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1063 sata_hba_tran->sata_tran_ioctl = NULL; 1064 1065 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1066 1067 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1068 1069 /* Attach it to SATA framework */ 1070 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1071 != DDI_SUCCESS) { 1072 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1073 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1074 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1075 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1076 return (AHCI_FAILURE); 1077 } 1078 1079 return (AHCI_SUCCESS); 1080} 1081 1082/* 1083 * Unregisters the ahci with sata framework. 1084 */ 1085static int 1086ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1087{ 1088 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1089 "ahci_unregister_sata_hba_tran enter"); 1090 1091 /* Detach from the SATA framework. */ 1092 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1093 DDI_SUCCESS) { 1094 return (AHCI_FAILURE); 1095 } 1096 1097 /* Deallocate sata_hba_tran. */ 1098 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1099 sizeof (sata_hba_tran_t)); 1100 1101 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1102 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1103 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1104 1105 return (AHCI_SUCCESS); 1106} 1107 1108/* 1109 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1110 * port status registers and an attached device type via sata_device 1111 * structure. 1112 * 1113 * We return the cached information from a previous hardware probe. The 1114 * actual hardware probing itself was done either from within 1115 * ahci_initialize_controller() during the driver attach or from a phy 1116 * ready change interrupt handler. 1117 */ 1118static int 1119ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1120{ 1121 ahci_ctl_t *ahci_ctlp; 1122 ahci_port_t *ahci_portp; 1123 uint8_t cport = sd->satadev_addr.cport; 1124#if AHCI_DEBUG 1125 uint8_t pmport = sd->satadev_addr.pmport; 1126 uint8_t qual = sd->satadev_addr.qual; 1127#endif 1128 uint8_t device_type; 1129 uint32_t port_state; 1130 uint8_t port; 1131 1132 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1133 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1134 1135 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1136 "ahci_tran_probe_port enter: cport: %d, " 1137 "pmport: %d, qual: %d", cport, pmport, qual); 1138 1139 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1140 1141 mutex_enter(&ahci_portp->ahciport_mutex); 1142 1143 port_state = ahci_portp->ahciport_port_state; 1144 switch (port_state) { 1145 1146 case SATA_PSTATE_FAILED: 1147 sd->satadev_state = SATA_PSTATE_FAILED; 1148 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1149 "ahci_tran_probe_port: port %d PORT FAILED", port); 1150 goto out; 1151 1152 case SATA_PSTATE_SHUTDOWN: 1153 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1154 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1155 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1156 goto out; 1157 1158 case SATA_PSTATE_PWROFF: 1159 sd->satadev_state = SATA_PSTATE_PWROFF; 1160 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1161 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1162 goto out; 1163 1164 case SATA_PSTATE_PWRON: 1165 sd->satadev_state = SATA_PSTATE_PWRON; 1166 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1167 "ahci_tran_probe_port: port %d PORT PWRON", port); 1168 break; 1169 1170 default: 1171 sd->satadev_state = port_state; 1172 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1173 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1174 port, port_state); 1175 break; 1176 } 1177 1178 device_type = ahci_portp->ahciport_device_type; 1179 1180 switch (device_type) { 1181 1182 case SATA_DTYPE_ATADISK: 1183 sd->satadev_type = SATA_DTYPE_ATADISK; 1184 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1185 "ahci_tran_probe_port: port %d DISK found", port); 1186 break; 1187 1188 case SATA_DTYPE_ATAPI: 1189 /* 1190 * HBA driver only knows it's an ATAPI device, and don't know 1191 * it's CD/DVD, tape or ATAPI disk because the ATAPI device 1192 * type need to be determined by checking IDENTIFY PACKET 1193 * DEVICE data 1194 */ 1195 sd->satadev_type = SATA_DTYPE_ATAPI; 1196 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1197 "ahci_tran_probe_port: port %d ATAPI found", port); 1198 break; 1199 1200 case SATA_DTYPE_PMULT: 1201 sd->satadev_type = SATA_DTYPE_PMULT; 1202 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1203 "ahci_tran_probe_port: port %d Port Multiplier found", 1204 port); 1205 break; 1206 1207 case SATA_DTYPE_UNKNOWN: 1208 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1209 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1210 "ahci_tran_probe_port: port %d Unknown device found", port); 1211 break; 1212 1213 default: 1214 /* we don't support any other device types */ 1215 sd->satadev_type = SATA_DTYPE_NONE; 1216 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1217 "ahci_tran_probe_port: port %d No device found", port); 1218 break; 1219 } 1220 1221out: 1222 ahci_update_sata_registers(ahci_ctlp, port, sd); 1223 mutex_exit(&ahci_portp->ahciport_mutex); 1224 1225 return (SATA_SUCCESS); 1226} 1227 1228/* 1229 * There are four operation modes in sata framework: 1230 * SATA_OPMODE_INTERRUPTS 1231 * SATA_OPMODE_POLLING 1232 * SATA_OPMODE_ASYNCH 1233 * SATA_OPMODE_SYNCH 1234 * 1235 * Their combined meanings as following: 1236 * 1237 * SATA_OPMODE_SYNCH 1238 * The command has to be completed before sata_tran_start functions returns. 1239 * Either interrupts or polling could be used - it's up to the driver. 1240 * Mode used currently for internal, sata-module initiated operations. 1241 * 1242 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1243 * It is the same as the one above. 1244 * 1245 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1246 * The command has to be completed before sata_tran_start function returns. 1247 * No interrupt used, polling only. This should be the mode used for scsi 1248 * packets with FLAG_NOINTR. 1249 * 1250 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1251 * The command may be queued (callback function specified). Interrupts could 1252 * be used. It's normal operation mode. 1253 */ 1254/* 1255 * Called by sata framework to transport a sata packet down stream. 1256 */ 1257static int 1258ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1259{ 1260 ahci_ctl_t *ahci_ctlp; 1261 ahci_port_t *ahci_portp; 1262 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1263 uint8_t port; 1264 1265 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1266 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1267 1268 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1269 "ahci_tran_start enter: cport %d satapkt 0x%p", 1270 cport, (void *)spkt); 1271 1272 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1273 1274 mutex_enter(&ahci_portp->ahciport_mutex); 1275 1276 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1277 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1278 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1279 /* 1280 * In case the targer driver would send the packet before 1281 * sata framework can have the opportunity to process those 1282 * event reports. 1283 */ 1284 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1285 spkt->satapkt_device.satadev_state = 1286 ahci_portp->ahciport_port_state; 1287 ahci_update_sata_registers(ahci_ctlp, port, 1288 &spkt->satapkt_device); 1289 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1290 "ahci_tran_start returning PORT_ERROR while " 1291 "port in FAILED/SHUTDOWN/PWROFF state: " 1292 "port: %d", port); 1293 mutex_exit(&ahci_portp->ahciport_mutex); 1294 return (SATA_TRAN_PORT_ERROR); 1295 } 1296 1297 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1298 /* 1299 * ahci_intr_phyrdy_change() may have rendered it to 1300 * SATA_DTYPE_NONE. 1301 */ 1302 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1303 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1304 spkt->satapkt_device.satadev_state = 1305 ahci_portp->ahciport_port_state; 1306 ahci_update_sata_registers(ahci_ctlp, port, 1307 &spkt->satapkt_device); 1308 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1309 "ahci_tran_start returning PORT_ERROR while " 1310 "no device attached: port: %d", port); 1311 mutex_exit(&ahci_portp->ahciport_mutex); 1312 return (SATA_TRAN_PORT_ERROR); 1313 } 1314 1315 /* 1316 * SATA HBA driver should remember that a device was reset and it 1317 * is supposed to reject any packets which do not specify either 1318 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1319 * 1320 * This is to prevent a race condition when a device was arbitrarily 1321 * reset by the HBA driver (and lost it's setting) and a target 1322 * driver sending some commands to a device before the sata framework 1323 * has a chance to restore the device setting (such as cache enable/ 1324 * disable or other resettable stuff). 1325 */ 1326 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1327 ahci_portp->ahciport_reset_in_progress = 0; 1328 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1329 "ahci_tran_start clearing the " 1330 "reset_in_progress for port: %d", port); 1331 } 1332 1333 if (ahci_portp->ahciport_reset_in_progress && 1334 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1335 ! ddi_in_panic()) { 1336 spkt->satapkt_reason = SATA_PKT_BUSY; 1337 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1338 "ahci_tran_start returning BUSY while " 1339 "reset in progress: port: %d", port); 1340 mutex_exit(&ahci_portp->ahciport_mutex); 1341 return (SATA_TRAN_BUSY); 1342 } 1343 1344 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1345 spkt->satapkt_reason = SATA_PKT_BUSY; 1346 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1347 "ahci_tran_start returning BUSY while " 1348 "mopping in progress: port: %d", port); 1349 mutex_exit(&ahci_portp->ahciport_mutex); 1350 return (SATA_TRAN_BUSY); 1351 } 1352 1353 if (spkt->satapkt_op_mode & 1354 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1355 /* 1356 * If a SYNC command to be executed in interrupt context, 1357 * bounce it back to sata module. 1358 */ 1359 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) && 1360 servicing_interrupt()) { 1361 spkt->satapkt_reason = SATA_PKT_BUSY; 1362 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1363 "ahci_tran_start returning BUSY while " 1364 "sending SYNC mode under interrupt context: " 1365 "port : %d", port); 1366 mutex_exit(&ahci_portp->ahciport_mutex); 1367 return (SATA_TRAN_BUSY); 1368 } 1369 1370 /* We need to do the sync start now */ 1371 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1372 spkt) == AHCI_FAILURE) { 1373 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1374 "return QUEUE_FULL: port %d", port); 1375 mutex_exit(&ahci_portp->ahciport_mutex); 1376 return (SATA_TRAN_QUEUE_FULL); 1377 } 1378 } else { 1379 /* Async start, using interrupt */ 1380 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1381 == AHCI_FAILURE) { 1382 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1383 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1384 "returning QUEUE_FULL: port %d", port); 1385 mutex_exit(&ahci_portp->ahciport_mutex); 1386 return (SATA_TRAN_QUEUE_FULL); 1387 } 1388 } 1389 1390 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1391 "sata tran accepted: port %d", port); 1392 1393 mutex_exit(&ahci_portp->ahciport_mutex); 1394 return (SATA_TRAN_ACCEPTED); 1395} 1396 1397/* 1398 * SATA_OPMODE_SYNCH flag is set 1399 * 1400 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1401 * without interrupt, otherwise we can still use the interrupt. 1402 * 1403 * WARNING!!! ahciport_mutex should be acquired before the function 1404 * is called. 1405 */ 1406static int 1407ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1408 uint8_t port, sata_pkt_t *spkt) 1409{ 1410 int pkt_timeout_ticks; 1411 uint32_t timeout_tags; 1412 int rval; 1413 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1414 1415 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1416 "port %d spkt 0x%p", port, spkt); 1417 1418 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1419 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1420 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1421 port, spkt)) == AHCI_FAILURE) { 1422 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1423 return (rval); 1424 } 1425 1426 pkt_timeout_ticks = 1427 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1428 1429 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1430 mutex_exit(&ahci_portp->ahciport_mutex); 1431 1432 /* Simulate the interrupt */ 1433 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1434 1435 drv_usecwait(AHCI_1MS_USECS); 1436 1437 mutex_enter(&ahci_portp->ahciport_mutex); 1438 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1439 if (pkt_timeout_ticks < 0) { 1440 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1441 "port %d satapkt 0x%p timed out\n", 1442 instance, port, (void *)spkt); 1443 timeout_tags = (0x1 << rval); 1444 mutex_exit(&ahci_portp->ahciport_mutex); 1445 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1446 port, timeout_tags); 1447 mutex_enter(&ahci_portp->ahciport_mutex); 1448 } 1449 } 1450 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1451 return (AHCI_SUCCESS); 1452 1453 } else { 1454 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1455 port, spkt)) == AHCI_FAILURE) 1456 return (rval); 1457 1458#if AHCI_DEBUG 1459 /* 1460 * Note that the driver always uses the slot 0 to deliver 1461 * REQUEST SENSE or READ LOG EXT command 1462 */ 1463 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1464 ASSERT(rval == 0); 1465#endif 1466 1467 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1468 cv_wait(&ahci_portp->ahciport_cv, 1469 &ahci_portp->ahciport_mutex); 1470 1471 return (AHCI_SUCCESS); 1472 } 1473} 1474 1475#define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1476 if (satapkt) { \ 1477 satapkt->satapkt_reason = reason; \ 1478 /* \ 1479 * We set the satapkt_reason in both sync and \ 1480 * non-sync cases. \ 1481 */ \ 1482 } \ 1483 if (satapkt && \ 1484 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1485 satapkt->satapkt_comp) { \ 1486 mutex_exit(&ahci_portp->ahciport_mutex); \ 1487 (*satapkt->satapkt_comp)(satapkt); \ 1488 mutex_enter(&ahci_portp->ahciport_mutex); \ 1489 } else { \ 1490 if (satapkt && \ 1491 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1492 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1493 cv_broadcast(&ahci_portp->ahciport_cv); \ 1494 } 1495 1496/* 1497 * Searches for and claims a free command slot. 1498 * 1499 * Returns: 1500 * 1501 * AHCI_FAILURE if failed 1502 * 1. if no empty slot left 1503 * 2. non-queued command requested while queued command(s) is outstanding 1504 * 3. queued command requested whild non-queued command(s) is outstanding 1505 * 4. HBA doesn't support multiple-use of command list while already a 1506 * non-queued command is oustanding 1507 * 1508 * claimed slot number if succeeded 1509 * 1510 * NOTE: it will always return slot 0 during error recovery process for 1511 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1512 * 1513 * WARNING!!! ahciport_mutex should be acquired before the function 1514 * is called. 1515 */ 1516static int 1517ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1518 ahci_port_t *ahci_portp, int command_type) 1519{ 1520 uint32_t free_slots; 1521 int slot; 1522 1523 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1524 "ahciport_pending_tags = 0x%x " 1525 "ahciport_pending_ncq_tags = 0x%x", 1526 ahci_portp->ahciport_pending_tags, 1527 ahci_portp->ahciport_pending_ncq_tags); 1528 1529 /* 1530 * According to the AHCI spec, system software is responsible to 1531 * ensure that queued and non-queued commands are not mixed in 1532 * the command list. 1533 */ 1534 if (command_type == AHCI_NON_NCQ_CMD) { 1535 /* Non-NCQ command request */ 1536 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1537 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1538 "ahci_claim_free_slot: there is still pending " 1539 "queued command(s) in the command list, " 1540 "so no available slot for the non-queued " 1541 "command"); 1542 return (AHCI_FAILURE); 1543 } 1544 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1545 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1546 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1547 "ahci_claim_free_slot: HBA cannot support multiple-" 1548 "use of the command list for non-queued commands"); 1549 return (AHCI_FAILURE); 1550 } 1551 free_slots = (~ahci_portp->ahciport_pending_tags) & 1552 AHCI_SLOT_MASK(ahci_ctlp); 1553 } else if (command_type == AHCI_NCQ_CMD) { 1554 /* NCQ command request */ 1555 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1556 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1557 "ahci_claim_free_slot: there is still pending " 1558 "non-queued command(s) in the command list, " 1559 "so no available slot for the queued command"); 1560 return (AHCI_FAILURE); 1561 } 1562 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1563 AHCI_NCQ_SLOT_MASK(ahci_portp); 1564 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1565 /* Error retrieval command request */ 1566 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1567 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1568 "SENSE or READ LOG EXT command"); 1569 slot = 0; 1570 goto out; 1571 } 1572 1573 slot = ddi_ffs(free_slots) - 1; 1574 if (slot == -1) { 1575 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1576 "ahci_claim_free_slot: no empty slots"); 1577 return (AHCI_FAILURE); 1578 } 1579 1580 /* 1581 * According to the AHCI spec, to allow a simple mechanism for the 1582 * HBA to map command list slots to queue entries, software must 1583 * match the tag number it uses to the slot it is placing the command 1584 * in. For example, if a queued command is placed in slot 5, the tag 1585 * for that command must be 5. 1586 */ 1587 if (command_type == AHCI_NCQ_CMD) { 1588 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1589 } 1590 1591 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1592 1593out: 1594 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1595 "ahci_claim_free_slot: found slot: 0x%x", slot); 1596 1597 return (slot); 1598} 1599 1600/* 1601 * Builds the Command Table for the sata packet and delivers it to controller. 1602 * 1603 * Returns: 1604 * slot number if we can obtain a slot successfully 1605 * otherwise, return AHCI_FAILURE 1606 * 1607 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1608 */ 1609static int 1610ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1611 uint8_t port, sata_pkt_t *spkt) 1612{ 1613 int cmd_slot; 1614 sata_cmd_t *scmd; 1615 ahci_fis_h2d_register_t *h2d_register_fisp; 1616 ahci_cmd_table_t *cmd_table; 1617 ahci_cmd_header_t *cmd_header; 1618 int ncookies; 1619 int i; 1620 int command_type = AHCI_NON_NCQ_CMD; 1621 int ncq_qdepth; 1622 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1623#if AHCI_DEBUG 1624 uint32_t *ptr; 1625 uint8_t *ptr2; 1626#endif 1627 1628 spkt->satapkt_reason = SATA_PKT_BUSY; 1629 1630 scmd = &spkt->satapkt_cmd; 1631 1632 /* Check if the command is a NCQ command */ 1633 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1634 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1635 command_type = AHCI_NCQ_CMD; 1636 1637 /* 1638 * When NCQ is support, system software must determine the 1639 * maximum tag allowed by the device and the HBA, and it 1640 * must use a value not beyond of the lower bound of the two. 1641 * 1642 * Sata module is going to calculate the qdepth and send 1643 * down to HBA driver via sata_cmd. 1644 */ 1645 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1646 1647 /* 1648 * At the moment, the driver doesn't support the dynamic 1649 * setting of the maximum ncq depth, and the value can be 1650 * set either during the attach or after hot-plug insertion. 1651 */ 1652 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1653 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1654 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1655 "ahci_deliver_satapkt: port %d the max tags for " 1656 "NCQ command is %d", port, ncq_qdepth); 1657 } else { 1658 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1659 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1660 " port %d the max tag for NCQ command is " 1661 "requested to change from %d to %d, at the" 1662 " moment the driver doesn't support the " 1663 "dynamic change so it's going to " 1664 "still use the previous tag value", 1665 instance, port, 1666 ahci_portp->ahciport_max_ncq_tags, 1667 ncq_qdepth); 1668 } 1669 } 1670 } 1671 1672 /* Check if the command is an error retrieval command */ 1673 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1674 command_type = AHCI_ERR_RETRI_CMD; 1675 1676 /* Check if there is an empty command slot */ 1677 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1678 if (cmd_slot == AHCI_FAILURE) { 1679 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1680 return (AHCI_FAILURE); 1681 } 1682 1683 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1684 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1685 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1686 cmd_slot, port, (void *)spkt); 1687 1688 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1689 bzero((void *)cmd_table, ahci_cmd_table_size); 1690 1691 /* For data transfer operations, it is the H2D Register FIS */ 1692 h2d_register_fisp = 1693 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1694 1695 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1696 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1697 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1698 SET_FIS_PMP(h2d_register_fisp, 1699 spkt->satapkt_device.satadev_addr.pmport); 1700 } 1701 1702 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1703 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1704 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1705 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1706 1707 switch (scmd->satacmd_addr_type) { 1708 1709 case 0: 1710 /* 1711 * satacmd_addr_type will be 0 for the commands below: 1712 * ATAPI command 1713 * SATAC_IDLE_IM 1714 * SATAC_STANDBY_IM 1715 * SATAC_DOWNLOAD_MICROCODE 1716 * SATAC_FLUSH_CACHE 1717 * SATAC_SET_FEATURES 1718 * SATAC_SMART 1719 * SATAC_ID_PACKET_DEVICE 1720 * SATAC_ID_DEVICE 1721 */ 1722 /* FALLTHRU */ 1723 1724 case ATA_ADDR_LBA: 1725 /* FALLTHRU */ 1726 1727 case ATA_ADDR_LBA28: 1728 /* LBA[7:0] */ 1729 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1730 1731 /* LBA[15:8] */ 1732 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1733 1734 /* LBA[23:16] */ 1735 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1736 1737 /* LBA [27:24] (also called dev_head) */ 1738 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1739 1740 break; 1741 1742 case ATA_ADDR_LBA48: 1743 /* LBA[7:0] */ 1744 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1745 1746 /* LBA[15:8] */ 1747 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1748 1749 /* LBA[23:16] */ 1750 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1751 1752 /* LBA [31:24] */ 1753 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1754 scmd->satacmd_lba_low_msb); 1755 1756 /* LBA [39:32] */ 1757 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1758 scmd->satacmd_lba_mid_msb); 1759 1760 /* LBA [47:40] */ 1761 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1762 scmd->satacmd_lba_high_msb); 1763 1764 /* Set dev_head */ 1765 SET_FIS_DEV_HEAD(h2d_register_fisp, 1766 scmd->satacmd_device_reg); 1767 1768 /* Set the extended sector count and features */ 1769 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1770 scmd->satacmd_sec_count_msb); 1771 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1772 scmd->satacmd_features_reg_ext); 1773 break; 1774 } 1775 1776 /* 1777 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1778 * filled into features field, and sector count 8:15 is filled into 1779 * features (exp) field. TAG is filled into sector field. 1780 */ 1781 if (command_type == AHCI_NCQ_CMD) { 1782 SET_FIS_FEATURES(h2d_register_fisp, 1783 scmd->satacmd_sec_count_lsb); 1784 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1785 scmd->satacmd_sec_count_msb); 1786 1787 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1788 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1789 } 1790 1791 ncookies = scmd->satacmd_num_dma_cookies; 1792 AHCIDBG2(AHCIDBG_PRDT, ahci_ctlp, 1793 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1794 ncookies, ahci_dma_prdt_number); 1795 1796 ASSERT(ncookies <= ahci_dma_prdt_number); 1797 ahci_portp->ahciport_prd_bytecounts[cmd_slot] = 0; 1798 1799 /* *** now fill the scatter gather list ******* */ 1800 for (i = 0; i < ncookies; i++) { 1801 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1802 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1803 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1804 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1805 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1806 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1807 ahci_portp->ahciport_prd_bytecounts[cmd_slot] += 1808 scmd->satacmd_dma_cookie_list[i].dmac_size; 1809 } 1810 1811 AHCIDBG2(AHCIDBG_PRDT, ahci_ctlp, 1812 "ahciport_prd_bytecounts 0x%x for cmd_slot 0x%x", 1813 ahci_portp->ahciport_prd_bytecounts[cmd_slot], cmd_slot); 1814 1815 /* The ACMD field is filled in for ATAPI command */ 1816 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1817 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1818 SATA_ATAPI_MAX_CDB_LEN); 1819 } 1820 1821 /* Set Command Header in Command List */ 1822 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1823 BZERO_DESCR_INFO(cmd_header); 1824 BZERO_PRD_BYTE_COUNT(cmd_header); 1825 1826 /* Set the number of entries in the PRD table */ 1827 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1828 1829 /* Set the length of the command in the CFIS area */ 1830 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1831 1832 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1833 "sata_data_direction = 0x%x", 1834 scmd->satacmd_flags.sata_data_direction); 1835 1836 /* Set A bit if it is an ATAPI command */ 1837 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1838 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1839 1840 /* Set W bit if data is going to the device */ 1841 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1842 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1843 1844 /* 1845 * Set the prefetchable bit - this bit is only valid if the PRDTL 1846 * field is non-zero or the ATAPI 'A' bit is set in the command 1847 * header. This bit cannot be set when using native command 1848 * queuing commands or when using FIS-based switching with a Port 1849 * multiplier. 1850 */ 1851 if (command_type != AHCI_NCQ_CMD) 1852 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1853 1854 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1855 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1856 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1857 1858 /* 1859 * We are overloading satapkt_hba_driver_private with 1860 * watched_cycle count. 1861 */ 1862 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1863 1864#if AHCI_DEBUG 1865 if (ahci_debug_flags & AHCIDBG_ATACMD && 1866 scmd->satacmd_cmd_reg != SATAC_PACKET || 1867 ahci_debug_flags & AHCIDBG_ATAPICMD && 1868 scmd->satacmd_cmd_reg == SATAC_PACKET) { 1869 1870 /* Dump the command header and table */ 1871 ahci_log(ahci_ctlp, CE_WARN, "\n"); 1872 ahci_log(ahci_ctlp, CE_WARN, "Command header&table for spkt " 1873 "0x%p cmd_reg 0x%x port %d", spkt, 1874 scmd->satacmd_cmd_reg, port); 1875 ptr = (uint32_t *)cmd_header; 1876 ahci_log(ahci_ctlp, CE_WARN, 1877 " Command Header:%8x %8x %8x %8x", 1878 ptr[0], ptr[1], ptr[2], ptr[3]); 1879 1880 /* Dump the H2D register FIS */ 1881 ptr = (uint32_t *)h2d_register_fisp; 1882 ahci_log(ahci_ctlp, CE_WARN, 1883 " Command FIS: %8x %8x %8x %8x", 1884 ptr[0], ptr[1], ptr[2], ptr[3]); 1885 1886 /* Dump the ACMD register FIS */ 1887 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1888 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1889 if (ahci_debug_flags & AHCIDBG_ATAPICMD) 1890 ahci_log(ahci_ctlp, CE_WARN, 1891 " ATAPI command: %2x %2x %2x %2x " 1892 "%2x %2x %2x %2x", 1893 ptr2[8 * i], ptr2[8 * i + 1], 1894 ptr2[8 * i + 2], ptr2[8 * i + 3], 1895 ptr2[8 * i + 4], ptr2[8 * i + 5], 1896 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1897 1898 /* Dump the PRDT */ 1899 for (i = 0; i < ncookies; i++) { 1900 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1901 ahci_log(ahci_ctlp, CE_WARN, 1902 " Cookie %d: %8x %8x %8x %8x", 1903 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1904 } 1905 } 1906#endif 1907 1908 (void) ddi_dma_sync( 1909 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1910 0, 1911 ahci_cmd_table_size, 1912 DDI_DMA_SYNC_FORDEV); 1913 1914 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1915 cmd_slot * sizeof (ahci_cmd_header_t), 1916 sizeof (ahci_cmd_header_t), 1917 DDI_DMA_SYNC_FORDEV); 1918 1919 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1920 if (command_type == AHCI_NCQ_CMD) { 1921 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1922 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1923 (0x1 << cmd_slot)); 1924 } 1925 1926 /* Indicate to the HBA that a command is active. */ 1927 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1928 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1929 (0x1 << cmd_slot)); 1930 1931 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1932 "exit: port %d", port); 1933 1934 return (cmd_slot); 1935} 1936 1937/* 1938 * Called by the sata framework to abort the previously sent packet(s). 1939 * 1940 * Reset device to abort commands. 1941 */ 1942static int 1943ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1944{ 1945 ahci_ctl_t *ahci_ctlp; 1946 ahci_port_t *ahci_portp; 1947 uint32_t slot_status = 0; 1948 uint32_t aborted_tags = 0; 1949 uint32_t finished_tags = 0; 1950 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1951 uint8_t port; 1952 int tmp_slot; 1953 int instance = ddi_get_instance(dip); 1954 1955 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1956 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1957 1958 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1959 "ahci_tran_abort enter: port %d", port); 1960 1961 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1962 mutex_enter(&ahci_portp->ahciport_mutex); 1963 1964 /* 1965 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1966 * commands are being mopped, therefore there is nothing else to do 1967 */ 1968 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1969 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1970 "ahci_tran_abort: port %d is in " 1971 "mopping process, so just return directly ", port); 1972 mutex_exit(&ahci_portp->ahciport_mutex); 1973 return (SATA_SUCCESS); 1974 } 1975 1976 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1977 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1978 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1979 /* 1980 * In case the targer driver would send the request before 1981 * sata framework can have the opportunity to process those 1982 * event reports. 1983 */ 1984 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1985 spkt->satapkt_device.satadev_state = 1986 ahci_portp->ahciport_port_state; 1987 ahci_update_sata_registers(ahci_ctlp, port, 1988 &spkt->satapkt_device); 1989 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1990 "ahci_tran_abort returning SATA_FAILURE while " 1991 "port in FAILED/SHUTDOWN/PWROFF state: " 1992 "port: %d", port); 1993 mutex_exit(&ahci_portp->ahciport_mutex); 1994 return (SATA_FAILURE); 1995 } 1996 1997 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1998 /* 1999 * ahci_intr_phyrdy_change() may have rendered it to 2000 * AHCI_PORT_TYPE_NODEV. 2001 */ 2002 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2003 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 2004 spkt->satapkt_device.satadev_state = 2005 ahci_portp->ahciport_port_state; 2006 ahci_update_sata_registers(ahci_ctlp, port, 2007 &spkt->satapkt_device); 2008 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2009 "ahci_tran_abort returning SATA_FAILURE while " 2010 "no device attached: port: %d", port); 2011 mutex_exit(&ahci_portp->ahciport_mutex); 2012 return (SATA_FAILURE); 2013 } 2014 2015 if (flag == SATA_ABORT_ALL_PACKETS) { 2016 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2017 aborted_tags = ahci_portp->ahciport_pending_tags; 2018 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2019 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 2020 2021 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 2022 instance, port); 2023 } else { 2024 aborted_tags = 0xffffffff; 2025 /* 2026 * Aborting one specific packet, first search the 2027 * ahciport_slot_pkts[] list for matching spkt. 2028 */ 2029 for (tmp_slot = 0; 2030 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 2031 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 2032 aborted_tags = (0x1 << tmp_slot); 2033 break; 2034 } 2035 } 2036 2037 if (aborted_tags == 0xffffffff) { 2038 /* request packet is not on the pending list */ 2039 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2040 "Cannot find the aborting pkt 0x%p on the " 2041 "pending list", (void *)spkt); 2042 ahci_update_sata_registers(ahci_ctlp, port, 2043 &spkt->satapkt_device); 2044 mutex_exit(&ahci_portp->ahciport_mutex); 2045 return (SATA_FAILURE); 2046 } 2047 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 2048 instance, port, (void *)spkt); 2049 } 2050 2051 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2052 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2053 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2054 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2055 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2056 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2057 2058 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2059 ahci_portp->ahciport_mop_in_progress++; 2060 2061 /* 2062 * To abort the packet(s), first we are trying to clear PxCMD.ST 2063 * to stop the port, and if the port can be stopped 2064 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2065 * then we just send back the aborted packet(s) with ABORTED flag 2066 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2067 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2068 * perform a COMRESET. 2069 */ 2070 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2071 ahci_portp, port, NULL, NULL); 2072 2073 /* 2074 * Compute which have finished and which need to be retried. 2075 * 2076 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2077 * minus the slot_status. The aborted_tags has to be deducted by 2078 * finished_tags since we can't possibly abort a tag which had finished 2079 * already. 2080 */ 2081 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2082 finished_tags = ahci_portp->ahciport_pending_tags & 2083 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2084 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2085 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2086 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2087 2088 aborted_tags &= ~finished_tags; 2089 2090 ahci_mop_commands(ahci_ctlp, 2091 ahci_portp, 2092 slot_status, 2093 0, /* failed tags */ 2094 0, /* timeout tags */ 2095 aborted_tags, 2096 0); /* reset tags */ 2097 2098 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2099 mutex_exit(&ahci_portp->ahciport_mutex); 2100 2101 return (SATA_SUCCESS); 2102} 2103 2104/* 2105 * Used to do device reset and reject all the pending packets on a device 2106 * during the reset operation. 2107 * 2108 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2109 */ 2110static int 2111ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2112 ahci_port_t *ahci_portp, uint8_t port) 2113{ 2114 uint32_t slot_status = 0; 2115 uint32_t reset_tags = 0; 2116 uint32_t finished_tags = 0; 2117 sata_device_t sdevice; 2118 int ret; 2119 2120 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2121 "ahci_reset_device_reject_pkts on port: %d", port); 2122 2123 /* 2124 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2125 * commands are being mopped, therefore there is nothing else to do 2126 */ 2127 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2128 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2129 "ahci_reset_device_reject_pkts: port %d is in " 2130 "mopping process, so return directly ", port); 2131 return (SATA_SUCCESS); 2132 } 2133 2134 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2135 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2136 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2137 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2138 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2139 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2140 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2141 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2142 } 2143 2144 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2145 != AHCI_SUCCESS) { 2146 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2147 "Try to do a port reset after software " 2148 "reset failed", port); 2149 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2150 if (ret != AHCI_SUCCESS) { 2151 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2152 "ahci_reset_device_reject_pkts: port %d " 2153 "failed", port); 2154 return (SATA_FAILURE); 2155 } 2156 } 2157 /* Set the reset in progress flag */ 2158 ahci_portp->ahciport_reset_in_progress = 1; 2159 2160 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2161 ahci_portp->ahciport_mop_in_progress++; 2162 2163 /* Indicate to the framework that a reset has happened */ 2164 bzero((void *)&sdevice, sizeof (sata_device_t)); 2165 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2166 sdevice.satadev_addr.pmport = 0; 2167 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2168 2169 sdevice.satadev_state = SATA_DSTATE_RESET | 2170 SATA_DSTATE_PWR_ACTIVE; 2171 mutex_exit(&ahci_portp->ahciport_mutex); 2172 sata_hba_event_notify( 2173 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2174 &sdevice, 2175 SATA_EVNT_DEVICE_RESET); 2176 mutex_enter(&ahci_portp->ahciport_mutex); 2177 2178 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2179 "port %d sending event up: SATA_EVNT_RESET", port); 2180 2181 /* Next try to mop the pending commands */ 2182 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2183 finished_tags = ahci_portp->ahciport_pending_tags & 2184 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2185 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2186 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2187 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2188 2189 reset_tags &= ~finished_tags; 2190 2191 ahci_mop_commands(ahci_ctlp, 2192 ahci_portp, 2193 slot_status, 2194 0, /* failed tags */ 2195 0, /* timeout tags */ 2196 0, /* aborted tags */ 2197 reset_tags); /* reset tags */ 2198 2199 return (SATA_SUCCESS); 2200} 2201 2202/* 2203 * Used to do port reset and reject all the pending packets on a port during 2204 * the reset operation. 2205 * 2206 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2207 */ 2208static int 2209ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2210 ahci_port_t *ahci_portp, uint8_t port) 2211{ 2212 uint32_t slot_status = 0; 2213 uint32_t reset_tags = 0; 2214 uint32_t finished_tags = 0; 2215 2216 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2217 "ahci_reset_port_reject_pkts on port: %d", port); 2218 2219 /* 2220 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2221 * commands are being mopped, therefore there is nothing else to do 2222 */ 2223 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2224 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2225 "ahci_reset_port_reject_pkts: port %d is in " 2226 "mopping process, so return directly ", port); 2227 return (SATA_SUCCESS); 2228 } 2229 2230 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2231 ahci_portp->ahciport_mop_in_progress++; 2232 2233 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2234 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2235 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2236 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2237 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2238 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2239 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2240 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2241 } 2242 2243 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2244 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2245 NULL) != AHCI_SUCCESS) 2246 return (SATA_FAILURE); 2247 2248 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2249 finished_tags = ahci_portp->ahciport_pending_tags & 2250 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2251 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2252 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2253 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2254 2255 reset_tags &= ~finished_tags; 2256 2257 ahci_mop_commands(ahci_ctlp, 2258 ahci_portp, 2259 slot_status, 2260 0, /* failed tags */ 2261 0, /* timeout tags */ 2262 0, /* aborted tags */ 2263 reset_tags); /* reset tags */ 2264 2265 return (SATA_SUCCESS); 2266} 2267 2268/* 2269 * Used to do hba reset and reject all the pending packets on all ports 2270 * during the reset operation. 2271 */ 2272static int 2273ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2274{ 2275 ahci_port_t *ahci_portp; 2276 uint32_t slot_status[AHCI_MAX_PORTS]; 2277 uint32_t reset_tags[AHCI_MAX_PORTS]; 2278 uint32_t finished_tags[AHCI_MAX_PORTS]; 2279 uint8_t port; 2280 int ret = SATA_SUCCESS; 2281 2282 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2283 "ahci_reset_hba_reject_pkts enter"); 2284 2285 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2286 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2287 continue; 2288 } 2289 2290 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2291 2292 mutex_enter(&ahci_portp->ahciport_mutex); 2293 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2294 slot_status[port] = ddi_get32( 2295 ahci_ctlp->ahcictl_ahci_acc_handle, 2296 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2297 reset_tags[port] = slot_status[port] & 2298 AHCI_SLOT_MASK(ahci_ctlp); 2299 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2300 slot_status[port] = ddi_get32( 2301 ahci_ctlp->ahcictl_ahci_acc_handle, 2302 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2303 reset_tags[port] = slot_status[port] & 2304 AHCI_NCQ_SLOT_MASK(ahci_portp); 2305 } 2306 mutex_exit(&ahci_portp->ahciport_mutex); 2307 } 2308 2309 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2310 ret = SATA_FAILURE; 2311 goto out; 2312 } 2313 2314 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2315 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2316 continue; 2317 } 2318 2319 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2320 2321 mutex_enter(&ahci_portp->ahciport_mutex); 2322 /* 2323 * To prevent recursive enter to ahci_mop_commands, we need 2324 * check AHCI_PORT_FLAG_MOPPING flag. 2325 */ 2326 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2327 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2328 "ahci_reset_hba_reject_pkts: port %d is in " 2329 "mopping process, so return directly ", port); 2330 mutex_exit(&ahci_portp->ahciport_mutex); 2331 continue; 2332 } 2333 2334 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2335 ahci_portp->ahciport_mop_in_progress++; 2336 2337 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2338 finished_tags[port] = 2339 ahci_portp->ahciport_pending_tags & 2340 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2341 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2342 finished_tags[port] = 2343 ahci_portp->ahciport_pending_ncq_tags & 2344 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2345 2346 reset_tags[port] &= ~finished_tags[port]; 2347 2348 ahci_mop_commands(ahci_ctlp, 2349 ahci_portp, 2350 slot_status[port], 2351 0, /* failed tags */ 2352 0, /* timeout tags */ 2353 0, /* aborted tags */ 2354 reset_tags[port]); /* reset tags */ 2355 mutex_exit(&ahci_portp->ahciport_mutex); 2356 } 2357out: 2358 return (ret); 2359} 2360 2361/* 2362 * Called by sata framework to reset a port(s) or device. 2363 */ 2364static int 2365ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2366{ 2367 ahci_ctl_t *ahci_ctlp; 2368 ahci_port_t *ahci_portp; 2369 uint8_t cport = sd->satadev_addr.cport; 2370 uint8_t port; 2371 int ret = SATA_SUCCESS; 2372 int instance = ddi_get_instance(dip); 2373 2374 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2375 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2376 2377 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2378 "ahci_tran_reset_port enter: cport: %d", cport); 2379 2380 switch (sd->satadev_addr.qual) { 2381 case SATA_ADDR_CPORT: 2382 /* Port reset */ 2383 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2384 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2385 "reset port", instance, port); 2386 2387 mutex_enter(&ahci_portp->ahciport_mutex); 2388 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2389 mutex_exit(&ahci_portp->ahciport_mutex); 2390 2391 break; 2392 2393 case SATA_ADDR_DCPORT: 2394 /* Device reset */ 2395 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2396 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2397 "reset device", instance, port); 2398 2399 mutex_enter(&ahci_portp->ahciport_mutex); 2400 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2401 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2402 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2403 /* 2404 * In case the targer driver would send the request 2405 * before sata framework can have the opportunity to 2406 * process those event reports. 2407 */ 2408 sd->satadev_state = ahci_portp->ahciport_port_state; 2409 ahci_update_sata_registers(ahci_ctlp, port, sd); 2410 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2411 "ahci_tran_reset_dport returning SATA_FAILURE " 2412 "while port in FAILED/SHUTDOWN/PWROFF state: " 2413 "port: %d", port); 2414 mutex_exit(&ahci_portp->ahciport_mutex); 2415 ret = SATA_FAILURE; 2416 break; 2417 } 2418 2419 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2420 /* 2421 * ahci_intr_phyrdy_change() may have rendered it to 2422 * AHCI_PORT_TYPE_NODEV. 2423 */ 2424 sd->satadev_type = SATA_DTYPE_NONE; 2425 sd->satadev_state = ahci_portp->ahciport_port_state; 2426 ahci_update_sata_registers(ahci_ctlp, port, sd); 2427 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2428 "ahci_tran_reset_dport returning SATA_FAILURE " 2429 "while no device attached: port: %d", port); 2430 mutex_exit(&ahci_portp->ahciport_mutex); 2431 ret = SATA_FAILURE; 2432 break; 2433 } 2434 2435 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2436 ahci_portp, port); 2437 mutex_exit(&ahci_portp->ahciport_mutex); 2438 break; 2439 2440 case SATA_ADDR_CNTRL: 2441 /* Reset the whole controller */ 2442 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2443 "reset the whole hba", instance, port); 2444 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2445 break; 2446 2447 case SATA_ADDR_PMPORT: 2448 case SATA_ADDR_DPMPORT: 2449 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2450 "ahci_tran_reset_dport: port multiplier will be " 2451 "supported later"); 2452 /* FALLTHRU */ 2453 default: 2454 ret = SATA_FAILURE; 2455 } 2456 2457 return (ret); 2458} 2459 2460/* 2461 * Called by sata framework to activate a port as part of hotplug. 2462 * (cfgadm -c connect satax/y) 2463 * Note: Not port-mult aware. 2464 */ 2465static int 2466ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2467{ 2468 ahci_ctl_t *ahci_ctlp; 2469 ahci_port_t *ahci_portp; 2470 uint8_t cport = satadev->satadev_addr.cport; 2471 uint8_t port; 2472 int instance = ddi_get_instance(dip); 2473 2474 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2475 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2476 2477 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2478 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2479 2480 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2481 2482 mutex_enter(&ahci_portp->ahciport_mutex); 2483 ahci_enable_port_intrs(ahci_ctlp, port); 2484 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2485 2486 /* 2487 * Reset the port so that the PHY communication would be re-established. 2488 * But this reset is an internal operation and the sata module doesn't 2489 * need to know about it. Moreover, the port with a device attached will 2490 * be started too. 2491 */ 2492 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2493 ahci_portp, port, 2494 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2495 NULL); 2496 2497 /* 2498 * Need to check the link status and device status of the port 2499 * and consider raising power if the port was in D3 state 2500 */ 2501 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2502 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2503 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2504 2505 satadev->satadev_state = ahci_portp->ahciport_port_state; 2506 2507 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2508 2509 mutex_exit(&ahci_portp->ahciport_mutex); 2510 return (SATA_SUCCESS); 2511} 2512 2513/* 2514 * Called by sata framework to deactivate a port as part of hotplug. 2515 * (cfgadm -c disconnect satax/y) 2516 * Note: Not port-mult aware. 2517 */ 2518static int 2519ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2520{ 2521 ahci_ctl_t *ahci_ctlp; 2522 ahci_port_t *ahci_portp; 2523 uint8_t cport = satadev->satadev_addr.cport; 2524 uint8_t port; 2525 uint32_t port_scontrol; 2526 int instance = ddi_get_instance(dip); 2527 2528 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2529 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2530 2531 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2532 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2533 2534 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2535 2536 mutex_enter(&ahci_portp->ahciport_mutex); 2537 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2538 instance, port); 2539 2540 /* Disable the interrupts on the port */ 2541 ahci_disable_port_intrs(ahci_ctlp, port); 2542 2543 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2544 goto phy_offline; 2545 } 2546 2547 /* First to abort all the pending commands */ 2548 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2549 2550 /* Then stop the port */ 2551 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2552 ahci_portp, port); 2553 2554 /* Next put the PHY offline */ 2555 2556phy_offline: 2557 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2558 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2559 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2560 2561 /* Update ahciport_port_state */ 2562 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2563 satadev->satadev_state = ahci_portp->ahciport_port_state; 2564 2565 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2566 2567 mutex_exit(&ahci_portp->ahciport_mutex); 2568 return (SATA_SUCCESS); 2569} 2570 2571/* 2572 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2573 * when a device is unplugged or a port is deactivated. 2574 * 2575 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2576 */ 2577static void 2578ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2579 ahci_port_t *ahci_portp, uint8_t port) 2580{ 2581 uint32_t slot_status = 0; 2582 uint32_t abort_tags = 0; 2583 2584 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2585 "ahci_reject_all_abort_pkts on port: %d", port); 2586 2587 /* 2588 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2589 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2590 * to get the error data, if yes when the device is removed, the 2591 * command needs to be aborted too. 2592 */ 2593 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2594 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2595 slot_status = 0x1; 2596 abort_tags = 0x1; 2597 goto out; 2598 } else { 2599 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2600 "ahci_reject_all_abort_pkts return directly " 2601 "port %d no needs to reject any outstanding " 2602 "commands", port); 2603 return; 2604 } 2605 } 2606 2607 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2608 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2609 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2610 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2611 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2612 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2613 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2614 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2615 } 2616 2617out: 2618 /* No need to do mop when there is no outstanding commands */ 2619 if (slot_status != 0) { 2620 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2621 ahci_portp->ahciport_mop_in_progress++; 2622 2623 ahci_mop_commands(ahci_ctlp, 2624 ahci_portp, 2625 slot_status, 2626 0, /* failed tags */ 2627 0, /* timeout tags */ 2628 abort_tags, /* aborting tags */ 2629 0); /* reset tags */ 2630 } 2631} 2632 2633#if defined(__lock_lint) 2634static int 2635ahci_selftest(dev_info_t *dip, sata_device_t *device) 2636{ 2637 return (SATA_SUCCESS); 2638} 2639#endif 2640 2641/* 2642 * Allocate the ports structure, only called by ahci_attach 2643 */ 2644static int 2645ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2646{ 2647 int port, cport = 0; 2648 2649 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2650 "ahci_alloc_ports_state enter"); 2651 2652 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2653 2654 /* Allocate structures only for the implemented ports */ 2655 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2656 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2657 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2658 "hba port %d not implemented", port); 2659 continue; 2660 } 2661 2662 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2663 ahci_ctlp->ahcictl_port_to_cport[port] = 2664 (uint8_t)cport++; 2665 2666 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2667 goto err_out; 2668 } 2669 } 2670 2671 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2672 return (AHCI_SUCCESS); 2673 2674err_out: 2675 for (port--; port >= 0; port--) { 2676 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2677 ahci_dealloc_port_state(ahci_ctlp, port); 2678 } 2679 } 2680 2681 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2682 return (AHCI_FAILURE); 2683} 2684 2685/* 2686 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2687 */ 2688static void 2689ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2690{ 2691 int port; 2692 2693 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2694 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2695 /* if this port is implemented by the HBA */ 2696 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2697 ahci_dealloc_port_state(ahci_ctlp, port); 2698 } 2699 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2700} 2701 2702/* 2703 * Drain the taskq. 2704 */ 2705static void 2706ahci_drain_ports_taskq(ahci_ctl_t *ahci_ctlp) 2707{ 2708 ahci_port_t *ahci_portp; 2709 int port; 2710 2711 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2712 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2713 continue; 2714 } 2715 2716 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2717 2718 mutex_enter(&ahci_portp->ahciport_mutex); 2719 ddi_taskq_wait(ahci_portp->ahciport_event_taskq); 2720 mutex_exit(&ahci_portp->ahciport_mutex); 2721 } 2722} 2723 2724/* 2725 * Initialize the controller and all ports. And then try to start the ports 2726 * if there are devices attached. 2727 * 2728 * This routine can be called from three seperate cases: DDI_ATTACH, 2729 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2730 * other two cases; device signature probing are attempted only during 2731 * DDI_ATTACH case. 2732 * 2733 * WARNING!!! Disable the whole controller's interrupts before calling and 2734 * the interrupts will be enabled upon successfully return. 2735 */ 2736static int 2737ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2738{ 2739 ahci_port_t *ahci_portp; 2740 uint32_t ghc_control; 2741 int port; 2742 2743 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2744 "ahci_initialize_controller enter"); 2745 2746 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2747 2748 /* 2749 * Indicate that system software is AHCI aware by setting 2750 * GHC.AE to 1 2751 */ 2752 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2753 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2754 2755 ghc_control |= AHCI_HBA_GHC_AE; 2756 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2757 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2758 ghc_control); 2759 2760 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2761 2762 /* Initialize the implemented ports and structures */ 2763 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2764 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2765 continue; 2766 } 2767 2768 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2769 mutex_enter(&ahci_portp->ahciport_mutex); 2770 2771 /* 2772 * Ensure that the controller is not in the running state 2773 * by checking every implemented port's PxCMD register 2774 */ 2775 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2776 != AHCI_SUCCESS) { 2777 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2778 "ahci_initialize_controller: failed to " 2779 "initialize port %d", port); 2780 /* 2781 * Set the port state to SATA_PSTATE_FAILED if 2782 * failed to initialize it. 2783 */ 2784 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2785 } 2786 2787 mutex_exit(&ahci_portp->ahciport_mutex); 2788 } 2789 2790 /* Enable the whole controller interrupts */ 2791 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2792 ahci_enable_all_intrs(ahci_ctlp); 2793 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2794 2795 return (AHCI_SUCCESS); 2796} 2797 2798/* 2799 * Reverse of ahci_initialize_controller() 2800 * 2801 * We only need to stop the ports and disable the interrupt. 2802 */ 2803static void 2804ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2805{ 2806 ahci_port_t *ahci_portp; 2807 int port; 2808 2809 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2810 "ahci_uninitialize_controller enter"); 2811 2812 /* disable all the interrupts. */ 2813 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2814 ahci_disable_all_intrs(ahci_ctlp); 2815 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2816 2817 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2818 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2819 continue; 2820 } 2821 2822 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2823 2824 /* Stop the port by clearing PxCMD.ST */ 2825 mutex_enter(&ahci_portp->ahciport_mutex); 2826 2827 /* 2828 * Here we must disable the port interrupt because 2829 * ahci_disable_all_intrs only clear GHC.IE, and IS 2830 * register will be still set if PxIE is enabled. 2831 * When ahci shares one IRQ with other drivers, the 2832 * intr handler may claim the intr mistakenly. 2833 */ 2834 ahci_disable_port_intrs(ahci_ctlp, port); 2835 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2836 ahci_portp, port); 2837 mutex_exit(&ahci_portp->ahciport_mutex); 2838 } 2839} 2840 2841/* 2842 * The routine is to initialize the port. First put the port in NOTRunning 2843 * state, then enable port interrupt and clear Serror register. And under 2844 * AHCI_ATTACH case, find device signature and then try to start the port. 2845 * 2846 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2847 */ 2848static int 2849ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2850 ahci_port_t *ahci_portp, uint8_t port) 2851{ 2852 uint32_t port_sstatus, port_task_file, port_cmd_status; 2853 int ret; 2854 2855 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2856 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2857 2858 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2859 "ahci_initialize_port: port %d " 2860 "port_cmd_status = 0x%x", port, port_cmd_status); 2861 /* 2862 * Check whether the port is in NotRunning state, if not, 2863 * put the port in NotRunning state 2864 */ 2865 if (port_cmd_status & 2866 (AHCI_CMD_STATUS_ST | 2867 AHCI_CMD_STATUS_CR | 2868 AHCI_CMD_STATUS_FRE | 2869 AHCI_CMD_STATUS_FR)) { 2870 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2871 ahci_portp, port); 2872 } 2873 2874 /* Device is unknown at first */ 2875 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 2876 2877 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2878 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 2879 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2880 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2881 2882 /* Check physcial link status */ 2883 if (SSTATUS_GET_IPM(port_sstatus) == SSTATUS_IPM_NODEV_NOPHYCOM || 2884 SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_NOPHYCOM || 2885 2886 /* Check interface status */ 2887 port_task_file & AHCI_TFD_STS_BSY || 2888 port_task_file & AHCI_TFD_STS_DRQ) { 2889 2890 /* Incorrect task file state, we need to reset port */ 2891 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2892 2893 /* Does port reset succeed on HBA port? */ 2894 if (ret != AHCI_SUCCESS) { 2895 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 2896 "ahci_initialize_port:" 2897 "port reset faild at port %d", port); 2898 return (AHCI_FAILURE); 2899 } 2900 2901 /* Is port failed? */ 2902 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 2903 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 2904 "ahci_initialize_port: port %d state 0x%x", 2905 port, ahci_portp->ahciport_port_state); 2906 return (AHCI_FAILURE); 2907 } 2908 2909 /* Is there any device attached? */ 2910 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2911 2912 /* Do not waste time on empty port */ 2913 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 2914 "ahci_initialize_port: No device is found " 2915 "at port %d", port); 2916 goto out; 2917 } 2918 } 2919 ahci_portp->ahciport_port_state = SATA_STATE_READY; 2920 2921 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "port %d is ready now.", port); 2922 2923 /* 2924 * At the time being, only probe ports/devices and get the types of 2925 * attached devices during DDI_ATTACH. In fact, the device can be 2926 * changed during power state changes, but at the time being, we 2927 * don't support the situation. 2928 */ 2929 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2930 /* 2931 * Till now we can assure a device attached to that HBA port 2932 * and work correctly. Now try to get the device signature. 2933 */ 2934 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2935 } else { 2936 2937 /* 2938 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2939 * and PxFBU registers in case these registers were cleared 2940 * during the suspend. 2941 */ 2942 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2943 "ahci_initialize_port: port %d " 2944 "reset the port during resume", port); 2945 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2946 2947 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2948 "ahci_initialize_port: port %d " 2949 "set PxCLB, PxCLBU, PxFB and PxFBU " 2950 "during resume", port); 2951 2952 /* Config Port Received FIS Base Address */ 2953 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2954 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2955 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2956 2957 /* Config Port Command List Base Address */ 2958 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2959 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2960 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2961 } 2962 2963 /* Disable the interface power management */ 2964 ahci_disable_interface_pm(ahci_ctlp, port); 2965 2966 /* Return directly if no device connected */ 2967 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2968 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2969 "No device connected to port %d", port); 2970 goto out; 2971 } 2972 2973 /* Try to start the port */ 2974 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2975 != AHCI_SUCCESS) { 2976 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2977 "failed to start port %d", port); 2978 return (AHCI_FAILURE); 2979 } 2980out: 2981 /* Enable port interrupts */ 2982 ahci_enable_port_intrs(ahci_ctlp, port); 2983 2984 return (AHCI_SUCCESS); 2985} 2986 2987/* 2988 * Check the hardware defects and the power management capability. 2989 */ 2990static int 2991ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2992{ 2993 ushort_t venid, devid; 2994 ushort_t caps_ptr, cap_count, cap; 2995#if AHCI_DEBUG 2996 ushort_t pmcap, pmcsr; 2997 ushort_t msimc; 2998#endif 2999 uint8_t revision; 3000 3001 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3002 PCI_CONF_VENID); 3003 3004 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3005 PCI_CONF_DEVID); 3006 3007 /* 3008 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 3009 * controllers with 0x00 revision id work on 4-byte aligned buffer, 3010 * which is a bug and was fixed after 0x00 revision id controllers. 3011 * 3012 * Moreover, VT8251 cannot use multiple command slots in the command 3013 * list for non-queued commands because the previous register content 3014 * of PxCI can be re-written in the register write, so a flag will be 3015 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 3016 */ 3017 if (venid == VIA_VENID) { 3018 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3019 PCI_CONF_REVID); 3020 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3021 "revision id = 0x%x", revision); 3022 if (revision == 0x00) { 3023 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 3024 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3025 "change ddi_attr_align to 0x4"); 3026 } 3027 3028 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 3029 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3030 "VT8251 cannot use multiple command lists for " 3031 "non-queued commands"); 3032 } 3033 3034 /* 3035 * ATI SB600 (1002,4380) and SB700/750 (1002,4391) AHCI chipsets don't 3036 * support 64-bit DMA addressing though they declare the support, 3037 * so we need to set AHCI_CAP_32BIT_DMA flag to force 32-bit DMA. 3038 */ 3039 if (venid == 0x1002 && (devid == 0x4380 || devid == 0x4391)) { 3040 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3041 "ATI SB600/700/750 cannot do 64-bit DMA though CAP " 3042 "indicates support, so force it to use 32-bit DMA"); 3043 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 3044 } 3045 3046 /* ASUS M3N-HT (NVidia 780a) does not support MSI */ 3047 if (venid == 0x10de && devid == 0x0ad4) { 3048 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3049 "ASUS M3N-HT (NVidia 780a) does not support MSI " 3050 "interrupts, so force it to use fixed interrupts."); 3051 ahci_msi_enabled = B_FALSE; 3052 } 3053 3054 /* 3055 * Check if capabilities list is supported and if so, 3056 * get initial capabilities pointer and clear bits 0,1. 3057 */ 3058 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3059 PCI_CONF_STAT) & PCI_STAT_CAP) { 3060 caps_ptr = P2ALIGN(pci_config_get8( 3061 ahci_ctlp->ahcictl_pci_conf_handle, 3062 PCI_CONF_CAP_PTR), 4); 3063 } else { 3064 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 3065 } 3066 3067 /* 3068 * Walk capabilities if supported. 3069 */ 3070 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 3071 3072 /* 3073 * Check that we haven't exceeded the maximum number of 3074 * capabilities and that the pointer is in a valid range. 3075 */ 3076 if (++cap_count > PCI_CAP_MAX_PTR) { 3077 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3078 "too many device capabilities"); 3079 return (AHCI_FAILURE); 3080 } 3081 if (caps_ptr < PCI_CAP_PTR_OFF) { 3082 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3083 "capabilities pointer 0x%x out of range", 3084 caps_ptr); 3085 return (AHCI_FAILURE); 3086 } 3087 3088 /* 3089 * Get next capability and check that it is valid. 3090 * For now, we only support power management. 3091 */ 3092 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3093 caps_ptr); 3094 switch (cap) { 3095 case PCI_CAP_ID_PM: 3096 3097 /* power management supported */ 3098 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 3099 3100 /* Save PMCSR offset */ 3101 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 3102 3103#if AHCI_DEBUG 3104 pmcap = pci_config_get16( 3105 ahci_ctlp->ahcictl_pci_conf_handle, 3106 caps_ptr + PCI_PMCAP); 3107 pmcsr = pci_config_get16( 3108 ahci_ctlp->ahcictl_pci_conf_handle, 3109 ahci_ctlp->ahcictl_pmcsr_offset); 3110 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 3111 "Power Management capability found PCI_PMCAP " 3112 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 3113 if ((pmcap & 0x3) == 0x3) 3114 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3115 "PCI Power Management Interface " 3116 "spec 1.2 compliant"); 3117#endif 3118 break; 3119 3120 case PCI_CAP_ID_MSI: 3121#if AHCI_DEBUG 3122 msimc = pci_config_get16( 3123 ahci_ctlp->ahcictl_pci_conf_handle, 3124 caps_ptr + PCI_MSI_CTRL); 3125 AHCIDBG1(AHCIDBG_MSI, ahci_ctlp, 3126 "Message Signaled Interrupt capability found " 3127 "MSICAP_MC.MMC = 0x%x", (msimc & 0xe) >> 1); 3128#endif 3129 AHCIDBG0(AHCIDBG_MSI, ahci_ctlp, 3130 "MSI capability found"); 3131 break; 3132 3133 case PCI_CAP_ID_PCIX: 3134 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3135 "PCI-X capability found"); 3136 break; 3137 3138 case PCI_CAP_ID_PCI_E: 3139 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3140 "PCI Express capability found"); 3141 break; 3142 3143 case PCI_CAP_ID_MSI_X: 3144 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3145 "MSI-X capability found"); 3146 break; 3147 3148 case PCI_CAP_ID_SATA: 3149 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3150 "SATA capability found"); 3151 break; 3152 3153 case PCI_CAP_ID_VS: 3154 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3155 "Vendor Specific capability found"); 3156 break; 3157 3158 default: 3159 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3160 "unrecognized capability 0x%x", cap); 3161 break; 3162 } 3163 3164 /* 3165 * Get next capabilities pointer and clear bits 0,1. 3166 */ 3167 caps_ptr = P2ALIGN(pci_config_get8( 3168 ahci_ctlp->ahcictl_pci_conf_handle, 3169 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3170 } 3171 3172 return (AHCI_SUCCESS); 3173} 3174 3175/* 3176 * AHCI device reset ...; a single device on one of the ports is reset, 3177 * but the HBA and physical communication remain intact. This is the 3178 * least intrusive. 3179 * 3180 * When issuing a software reset sequence, there should not be other 3181 * commands in the command list, so we will first clear and then re-set 3182 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3183 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3184 * cleared unless command list override (PxCMD.CLO) is supported. 3185 * 3186 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3187 * set before the function is called. 3188 */ 3189static int 3190ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3191 uint8_t port) 3192{ 3193 ahci_fis_h2d_register_t *h2d_register_fisp; 3194 ahci_cmd_table_t *cmd_table; 3195 ahci_cmd_header_t *cmd_header; 3196 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3197 int slot, loop_count; 3198 int rval = AHCI_FAILURE; 3199 3200 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3201 "Port %d device resetting", port); 3202 3203 /* First clear PxCMD.ST (AHCI v1.2 10.4.1) */ 3204 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 3205 port) != AHCI_SUCCESS) { 3206 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3207 "ahci_software_reset: cannot stop HBA port %d.", port); 3208 goto out; 3209 } 3210 3211 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3212 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3213 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3214 3215 if (port_task_file & AHCI_TFD_STS_BSY || 3216 port_task_file & AHCI_TFD_STS_DRQ) { 3217 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_SCLO)) { 3218 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3219 "PxTFD.STS.BSY/DRQ is set (PxTFD=0x%x), " 3220 "cannot issue a software reset.", port_task_file); 3221 goto out; 3222 } 3223 3224 /* 3225 * If HBA Support CLO, as Command List Override (CAP.SCLO is 3226 * set), PxCMD.CLO bit should be set before set PxCMD.ST, in 3227 * order to clear PxTFD.STS.BSY and PxTFD.STS.DRQ. 3228 */ 3229 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3230 "PxTFD.STS.BSY/DRQ is set, try SCLO.") 3231 3232 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3233 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3234 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3235 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3236 port_cmd_status|AHCI_CMD_STATUS_CLO); 3237 3238 /* Waiting till PxCMD.SCLO bit is cleared */ 3239 loop_count = 0; 3240 do { 3241 /* Wait for 10 millisec */ 3242 drv_usecwait(AHCI_10MS_USECS); 3243 3244 /* We are effectively timing out after 1 sec. */ 3245 if (loop_count++ > 100) { 3246 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3247 "SCLO time out. port %d is busy.", port); 3248 goto out; 3249 } 3250 3251 port_cmd_status = 3252 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3253 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3254 } while (port_cmd_status & AHCI_CMD_STATUS_CLO); 3255 3256 /* Re-check */ 3257 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3258 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3259 if (port_task_file & AHCI_TFD_STS_BSY || 3260 port_task_file & AHCI_TFD_STS_DRQ) { 3261 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3262 "SCLO cannot clear PxTFD.STS.BSY/DRQ (PxTFD=0x%x)", 3263 port_task_file); 3264 goto out; 3265 } 3266 } 3267 3268 /* Then start port */ 3269 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 3270 != AHCI_SUCCESS) { 3271 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3272 "ahci_software_reset: cannot start AHCI port %d.", port); 3273 goto out; 3274 } 3275 3276 /* 3277 * When ahci_port.ahciport_mop_in_progress is set, A non-zero 3278 * ahci_port.ahciport_pending_ncq_tags may fail 3279 * ahci_claim_free_slot(). Actually according to spec, by clearing 3280 * PxCMD.ST there is no command outstanding while executing software 3281 * reseting. Hence we directly use slot 0 instead of 3282 * ahci_claim_free_slot(). 3283 */ 3284 slot = 0; 3285 3286 /* Now send the first H2D Register FIS with SRST set to 1 */ 3287 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3288 bzero((void *)cmd_table, ahci_cmd_table_size); 3289 3290 h2d_register_fisp = 3291 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3292 3293 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3294 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3295 3296 /* Set Command Header in Command List */ 3297 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3298 BZERO_DESCR_INFO(cmd_header); 3299 BZERO_PRD_BYTE_COUNT(cmd_header); 3300 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3301 3302 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3303 SET_RESET(cmd_header, 1); 3304 SET_WRITE(cmd_header, 1); 3305 3306 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3307 0, 3308 ahci_cmd_table_size, 3309 DDI_DMA_SYNC_FORDEV); 3310 3311 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3312 slot * sizeof (ahci_cmd_header_t), 3313 sizeof (ahci_cmd_header_t), 3314 DDI_DMA_SYNC_FORDEV); 3315 3316 /* Indicate to the HBA that a command is active. */ 3317 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3318 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3319 (0x1 << slot)); 3320 3321 loop_count = 0; 3322 3323 /* Loop till the first command is finished */ 3324 do { 3325 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3326 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3327 3328 /* We are effectively timing out after 1 sec. */ 3329 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3330 goto out; 3331 } 3332 /* Wait for 10 millisec */ 3333 delay(AHCI_10MS_TICKS); 3334 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3335 3336 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3337 "ahci_software_reset: 1st loop count: %d, " 3338 "port_cmd_issue = 0x%x, slot = 0x%x", 3339 loop_count, port_cmd_issue, slot); 3340 3341 /* Now send the second H2D Register FIS with SRST cleard to zero */ 3342 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3343 bzero((void *)cmd_table, ahci_cmd_table_size); 3344 3345 h2d_register_fisp = 3346 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3347 3348 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3349 3350 /* Set Command Header in Command List */ 3351 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3352 BZERO_DESCR_INFO(cmd_header); 3353 BZERO_PRD_BYTE_COUNT(cmd_header); 3354 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3355 3356 SET_WRITE(cmd_header, 1); 3357 3358 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3359 0, 3360 ahci_cmd_table_size, 3361 DDI_DMA_SYNC_FORDEV); 3362 3363 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3364 slot * sizeof (ahci_cmd_header_t), 3365 sizeof (ahci_cmd_header_t), 3366 DDI_DMA_SYNC_FORDEV); 3367 3368 /* Indicate to the HBA that a command is active. */ 3369 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3370 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3371 (0x1 << slot)); 3372 3373 loop_count = 0; 3374 3375 /* Loop till the second command is finished */ 3376 do { 3377 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3378 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3379 3380 /* We are effectively timing out after 1 sec. */ 3381 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3382 goto out; 3383 } 3384 /* Wait for 10 millisec */ 3385 delay(AHCI_10MS_TICKS); 3386 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3387 3388 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3389 "ahci_software_reset: 2nd loop count: %d, " 3390 "port_cmd_issue = 0x%x, slot = 0x%x", 3391 loop_count, port_cmd_issue, slot); 3392 3393 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3394 3395 rval = AHCI_SUCCESS; 3396out: 3397 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3398 "ahci_software_reset: %s at port %d", 3399 rval == AHCI_SUCCESS ? "succeed" : "failed", 3400 port); 3401 3402 return (rval); 3403} 3404 3405/* 3406 * AHCI port reset ...; the physical communication between the HBA and device 3407 * on a port are disabled. This is more intrusive. 3408 * 3409 * When an HBA or port reset occurs, Phy communication is going to 3410 * be re-established with the device through a COMRESET followed by the 3411 * normal out-of-band communication sequence defined in Serial ATA. AT 3412 * the end of reset, the device, if working properly, will send a D2H 3413 * Register FIS, which contains the device signature. When the HBA receives 3414 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3415 * the PxSIG register with the signature. 3416 * 3417 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3418 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3419 * AHCI 1.0 spec. 3420 */ 3421/* 3422 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3423 * cleared before the function is called. 3424 */ 3425static int 3426ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3427{ 3428 uint32_t cap_status, port_cmd_status; 3429 uint32_t port_scontrol, port_sstatus, port_serror; 3430 uint32_t port_intr_status, port_task_file; 3431 3432 int loop_count; 3433 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3434 3435 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3436 "Port %d port resetting...", port); 3437 ahci_portp->ahciport_port_state = 0; 3438 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3439 3440 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3441 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3442 3443 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3444 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3445 3446 if (cap_status & AHCI_HBA_CAP_SSS) { 3447 /* 3448 * HBA support staggered spin-up, if the port has 3449 * not spin up yet, then force it to do spin-up 3450 */ 3451 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3452 if (!(ahci_portp->ahciport_flags 3453 & AHCI_PORT_FLAG_SPINUP)) { 3454 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3455 "Port %d PxCMD.SUD is zero, force " 3456 "it to do spin-up", port); 3457 ahci_portp->ahciport_flags |= 3458 AHCI_PORT_FLAG_SPINUP; 3459 } 3460 } 3461 } else { 3462 /* 3463 * HBA doesn't support stagger spin-up, force it 3464 * to do normal COMRESET 3465 */ 3466 if (ahci_portp->ahciport_flags & 3467 AHCI_PORT_FLAG_SPINUP) { 3468 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3469 "HBA does not support staggered spin-up " 3470 "force it to do normal COMRESET"); 3471 ahci_portp->ahciport_flags &= 3472 ~AHCI_PORT_FLAG_SPINUP; 3473 } 3474 } 3475 3476 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3477 /* Do normal COMRESET */ 3478 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3479 "ahci_port_reset: do normal COMRESET", port); 3480 3481 /* 3482 * According to the spec, SUD bit should be set here, 3483 * but JMicron JMB363 doesn't follow it, so remove 3484 * the assertion, and just print a debug message. 3485 */ 3486#if AHCI_DEBUG 3487 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3488 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3489 "port %d SUD bit not set", port) 3490#endif 3491 3492 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3493 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3494 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3495 3496 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3497 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3498 port_scontrol); 3499 3500 /* Enable PxCMD.FRE to read device */ 3501 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3502 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3503 port_cmd_status|AHCI_CMD_STATUS_FRE); 3504 3505 /* 3506 * Give time for COMRESET to percolate, according to the AHCI 3507 * spec, software shall wait at least 1 millisecond before 3508 * clearing PxSCTL.DET 3509 */ 3510 delay(AHCI_1MS_TICKS*2); 3511 3512 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3513 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3514 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3515 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3516 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3517 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3518 port_scontrol); 3519 } else { 3520 /* Do staggered spin-up */ 3521 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3522 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3523 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3524 3525 /* PxSCTL.DET must be 0 */ 3526 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3527 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3528 port_scontrol); 3529 3530 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3531 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3532 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3533 port_cmd_status); 3534 3535 /* 0 -> 1 edge */ 3536 delay(AHCI_1MS_TICKS*2); 3537 3538 /* Set PxCMD.SUD to 1 */ 3539 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3540 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3541 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3542 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3543 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3544 port_cmd_status); 3545 3546 /* Enable PxCMD.FRE to read device */ 3547 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3548 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3549 port_cmd_status|AHCI_CMD_STATUS_FRE); 3550 } 3551 3552 /* 3553 * The port enters P:StartComm state, and HBA tells link layer to 3554 * start communication, which involves sending COMRESET to device. 3555 * And the HBA resets PxTFD.STS to 7Fh. 3556 * 3557 * When a COMINIT is received from the device, then the port enters 3558 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3559 * PxSSTS.DET to 1h to indicate a device is detected but communication 3560 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3561 * a COMINIT has been received. 3562 */ 3563 /* 3564 * The DET field is valid only if IPM field indicates 3565 * that the interface is in active state. 3566 */ 3567 loop_count = 0; 3568 do { 3569 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3570 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3571 3572 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3573 /* 3574 * If the interface is not active, the DET field 3575 * is considered not accurate. So we want to 3576 * continue looping. 3577 */ 3578 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3579 } 3580 3581 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3582 /* 3583 * We are effectively timing out after 0.1 sec. 3584 */ 3585 break; 3586 } 3587 3588 /* Wait for 10 millisec */ 3589 delay(AHCI_10MS_TICKS); 3590 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3591 3592 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3593 "ahci_port_reset: 1st loop count: %d, " 3594 "port_sstatus = 0x%x port %d", 3595 loop_count, port_sstatus, port); 3596 3597 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3598 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3599 /* 3600 * Either the port is not active or there 3601 * is no device present. 3602 */ 3603 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3604 return (AHCI_SUCCESS); 3605 } 3606 3607 /* Now we can make sure there is a device connected to the port */ 3608 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3609 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3610 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3611 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 3612 3613 /* 3614 * A COMINIT signal is supposed to be received 3615 * PxSERR.DIAG.X or PxIS.PCS should be set 3616 */ 3617 if (!(port_intr_status & AHCI_INTR_STATUS_PCS) && 3618 !(port_serror & SERROR_EXCHANGED_ERR)) { 3619 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3620 "COMINIT signal from the device not received", 3621 instance, port); 3622 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3623 return (AHCI_FAILURE); 3624 } 3625 3626 /* 3627 * According to the spec, when PxSCTL.DET is set to 0h, upon 3628 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3629 * shall be set to '1' by the HBA. 3630 * 3631 * However, we found JMicron JMB363 doesn't follow this, so 3632 * remove this check, and just print a debug message. 3633 */ 3634#if AHCI_DEBUG 3635 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3636 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3637 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3638 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3639 "port %d BSY bit is not set after COMINIT signal " 3640 "is received", port); 3641 } 3642#endif 3643 3644 /* 3645 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3646 * the D2H FIS received by HBA. 3647 */ 3648 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3649 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3650 SERROR_EXCHANGED_ERR); 3651 3652 /* 3653 * Devices should return a FIS contains its signature to HBA after 3654 * COMINIT signal. Check whether a D2H FIS is received by polling 3655 * PxTFD.STS.ERR bit. 3656 */ 3657 loop_count = 0; 3658 do { 3659 /* Wait for 10 millisec */ 3660 delay(AHCI_10MS_TICKS); 3661 3662 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3663 /* 3664 * We are effectively timing out after 11 sec. 3665 */ 3666 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3667 "the device hardware has been initialized and " 3668 "the power-up diagnostics failed", 3669 instance, port); 3670 3671 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3672 "port %d PxTFD.STS.ERR is not set, we need another " 3673 "software reset.", port); 3674 3675 /* Clear port serror register for the port */ 3676 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3677 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3678 AHCI_SERROR_CLEAR_ALL); 3679 3680 /* Try another software reset. */ 3681 if (ahci_software_reset(ahci_ctlp, ahci_portp, 3682 port) != AHCI_SUCCESS) { 3683 ahci_portp->ahciport_port_state |= 3684 SATA_PSTATE_FAILED; 3685 return (AHCI_FAILURE); 3686 } 3687 break; 3688 } 3689 3690 /* 3691 * The Error bit '1' means COMRESET is finished successfully 3692 * The device hardware has been initialized and the power-up 3693 * diagnostics successfully completed. The device requests 3694 * that the Transport layer transmit a Register - D2H FIS to 3695 * the host. (SATA spec 11.5, v2.6) 3696 */ 3697 port_task_file = 3698 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3699 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3700 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3701 >> AHCI_TFD_ERR_SHIFT) != AHCI_TFD_ERR_SGS); 3702 3703 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3704 "ahci_port_reset: 2nd loop count: %d, " 3705 "port_task_file = 0x%x port %d", 3706 loop_count, port_task_file, port); 3707 3708 /* Clear port serror register for the port */ 3709 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3710 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3711 AHCI_SERROR_CLEAR_ALL); 3712 3713 /* Set port as ready */ 3714 ahci_portp->ahciport_port_state |= SATA_STATE_READY; 3715 3716 AHCIDBG1(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp, 3717 "ahci_port_reset: succeed at port %d.", port); 3718 return (AHCI_SUCCESS); 3719} 3720 3721/* 3722 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3723 * This is the most intrusive. 3724 * 3725 * When an HBA reset occurs, Phy communication will be re-established with 3726 * the device through a COMRESET followed by the normal out-of-band 3727 * communication sequence defined in Serial ATA. AT the end of reset, the 3728 * device, if working properly, will send a D2H Register FIS, which contains 3729 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3730 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3731 * signature. 3732 * 3733 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3734 */ 3735static int 3736ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3737{ 3738 ahci_port_t *ahci_portp; 3739 uint32_t ghc_control; 3740 uint8_t port; 3741 int loop_count; 3742 int rval = AHCI_SUCCESS; 3743 3744 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3745 3746 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3747 3748 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3749 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3750 3751 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3752 ghc_control |= AHCI_HBA_GHC_HR; 3753 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3754 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3755 3756 /* 3757 * Wait until HBA Reset complete or timeout 3758 */ 3759 loop_count = 0; 3760 do { 3761 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3762 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3763 3764 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3765 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3766 "ahci hba reset is timing out, " 3767 "ghc_control = 0x%x", ghc_control); 3768 /* We are effectively timing out after 1 sec. */ 3769 break; 3770 } 3771 3772 /* Wait for 10 millisec */ 3773 delay(AHCI_10MS_TICKS); 3774 } while (ghc_control & AHCI_HBA_GHC_HR); 3775 3776 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3777 "ahci_hba_reset: 1st loop count: %d, " 3778 "ghc_control = 0x%x", loop_count, ghc_control); 3779 3780 if (ghc_control & AHCI_HBA_GHC_HR) { 3781 /* The hba is not reset for some reasons */ 3782 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3783 "hba reset failed: HBA in a hung or locked state"); 3784 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3785 return (AHCI_FAILURE); 3786 } 3787 3788 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3789 /* Only check implemented ports */ 3790 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3791 continue; 3792 } 3793 3794 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3795 mutex_enter(&ahci_portp->ahciport_mutex); 3796 3797 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3798 != AHCI_SUCCESS) { 3799 rval = AHCI_FAILURE; 3800 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3801 "ahci_hba_reset: port %d failed", port); 3802 } 3803 3804 mutex_exit(&ahci_portp->ahciport_mutex); 3805 } 3806 3807 /* 3808 * Indicate that system software is AHCI aware by setting 3809 * GHC.AE to 1 3810 */ 3811 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3812 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3813 3814 ghc_control |= AHCI_HBA_GHC_AE; 3815 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3816 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3817 3818 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3819 3820 return (rval); 3821} 3822 3823/* 3824 * This routine is only called from AHCI_ATTACH or phyrdy change 3825 * case. It first calls software reset, then stop the port and try to 3826 * read PxSIG register to find the type of device attached to the port. 3827 * 3828 * The caller should make sure a valid device exists on specified port and 3829 * physical communication has been established so that the signature could 3830 * be retrieved by software reset. 3831 * 3832 * WARNING!!! ahciport_mutex should be acquired before the function 3833 * is called. And the port interrupt is disabled. 3834 */ 3835static void 3836ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3837 ahci_port_t *ahci_portp, uint8_t port) 3838{ 3839 uint32_t signature; 3840 3841 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3842 "ahci_find_dev_signature enter: port %d", port); 3843 3844 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3845 3846 /* Issue a software reset to get the signature */ 3847 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 3848 != AHCI_SUCCESS) { 3849 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3850 "ahci_find_dev_signature: software reset failed " 3851 "at port %d. cannot get signature.", port); 3852 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 3853 return; 3854 } 3855 3856 /* 3857 * ahci_software_reset has started the port, so we need manually stop 3858 * the port again. 3859 */ 3860 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, port) 3861 != AHCI_SUCCESS) { 3862 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3863 "ahci_find_dev_signature: cannot stop port %d.", port); 3864 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 3865 return; 3866 } 3867 3868 /* Now we can make sure that a valid signature is received. */ 3869 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3870 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3871 3872 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3873 "ahci_find_dev_signature: port %d signature = 0x%x", 3874 port, signature); 3875 3876 switch (signature) { 3877 3878 case AHCI_SIGNATURE_DISK: 3879 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3880 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3881 "Disk is found at port: %d", port); 3882 break; 3883 3884 case AHCI_SIGNATURE_ATAPI: 3885 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPI; 3886 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3887 "ATAPI device is found at port: %d", port); 3888 break; 3889 3890 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3891 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3892 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3893 "Port Multiplier is found at port: %d", port); 3894 break; 3895 3896 default: 3897 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3898 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3899 "Unknown device is found at port: %d", port); 3900 } 3901} 3902 3903/* 3904 * According to the spec, to reliably detect hot plug removals, software 3905 * must disable interface power management. Software should perform the 3906 * following initialization on a port after a device is attached: 3907 * Set PxSCTL.IPM to 3h to disable interface state transitions 3908 * Set PxCMD.ALPE to '0' to disable aggressive power management 3909 * Disable device initiated interface power management by SET FEATURE 3910 * 3911 * We can ignore the last item because by default the feature is disabled 3912 */ 3913static void 3914ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3915{ 3916 uint32_t port_scontrol, port_cmd_status; 3917 3918 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3919 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3920 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3921 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3922 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3923 3924 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3925 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3926 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3927 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3928 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3929} 3930 3931/* 3932 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3933 * to 1, then set it firstly. 3934 * 3935 * Each port contains two major DMA engines. One DMA engine walks through 3936 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3937 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3938 * 3939 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3940 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3941 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3942 * 3943 * Software shall not set PxCMD.ST to '1' unless a functional device is 3944 * present on the port(as determined by PxTFD.STS.BSY = '0', 3945 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3946 * 3947 * WARNING!!! ahciport_mutex should be acquired before the function 3948 * is called. 3949 */ 3950static int 3951ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3952{ 3953 uint32_t port_cmd_status; 3954 3955 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3956 3957 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3958 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3959 "the state for port %d is 0x%x", 3960 port, ahci_portp->ahciport_port_state); 3961 return (AHCI_FAILURE); 3962 } 3963 3964 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3965 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3966 "no device is attached at port %d", port); 3967 return (AHCI_FAILURE); 3968 } 3969 3970 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3971 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3972 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3973 3974 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3975 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3976 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3977 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3978 port_cmd_status); 3979 } 3980 3981 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3982 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3983 3984 port_cmd_status |= AHCI_CMD_STATUS_ST; 3985 3986 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3987 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3988 port_cmd_status); 3989 3990 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3991 3992 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port: " 3993 "PxCMD.ST set to '1' at port %d", port); 3994 3995 return (AHCI_SUCCESS); 3996} 3997 3998/* 3999 * Allocate the ahci_port_t including Received FIS and Command List. 4000 * The argument - port is the physical port number, and not logical 4001 * port number seen by the SATA framework. 4002 * 4003 * WARNING!!! ahcictl_mutex should be acquired before the function 4004 * is called. 4005 */ 4006static int 4007ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 4008{ 4009 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 4010 ahci_port_t *ahci_portp; 4011 char taskq_name[64] = "event_handle_taskq"; 4012 4013 ahci_portp = 4014 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 4015 4016 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 4017 ahci_portp->ahciport_port_num = port; 4018 4019 /* Intialize the port condition variable */ 4020 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 4021 4022 /* Initialize the port mutex */ 4023 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 4024 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 4025 4026 mutex_enter(&ahci_portp->ahciport_mutex); 4027 4028 /* 4029 * Allocate memory for received FIS structure and 4030 * command list for this port 4031 */ 4032 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 4033 goto err_case1; 4034 } 4035 4036 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 4037 goto err_case2; 4038 } 4039 4040 (void) snprintf(taskq_name + strlen(taskq_name), 4041 sizeof (taskq_name) - strlen(taskq_name), 4042 "_port%d", port); 4043 4044 /* Create the taskq for the port */ 4045 if ((ahci_portp->ahciport_event_taskq = ddi_taskq_create(dip, 4046 taskq_name, 2, TASKQ_DEFAULTPRI, 0)) == NULL) { 4047 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 4048 "handle", ddi_get_instance(ahci_ctlp->ahcictl_dip)); 4049 goto err_case3; 4050 } 4051 4052 /* Allocate the argument for the taskq */ 4053 ahci_portp->ahciport_event_args = 4054 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 4055 4056 if (ahci_portp->ahciport_event_args == NULL) 4057 goto err_case4; 4058 4059 mutex_exit(&ahci_portp->ahciport_mutex); 4060 4061 return (AHCI_SUCCESS); 4062 4063err_case4: 4064 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq); 4065 4066err_case3: 4067 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 4068 4069err_case2: 4070 ahci_dealloc_rcvd_fis(ahci_portp); 4071 4072err_case1: 4073 mutex_exit(&ahci_portp->ahciport_mutex); 4074 mutex_destroy(&ahci_portp->ahciport_mutex); 4075 cv_destroy(&ahci_portp->ahciport_cv); 4076 4077 kmem_free(ahci_portp, sizeof (ahci_port_t)); 4078 4079 return (AHCI_FAILURE); 4080} 4081 4082/* 4083 * Reverse of ahci_dealloc_port_state(). 4084 * 4085 * WARNING!!! ahcictl_mutex should be acquired before the function 4086 * is called. 4087 */ 4088static void 4089ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 4090{ 4091 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4092 4093 ASSERT(ahci_portp != NULL); 4094 4095 mutex_enter(&ahci_portp->ahciport_mutex); 4096 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 4097 ahci_portp->ahciport_event_args = NULL; 4098 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq); 4099 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 4100 ahci_dealloc_rcvd_fis(ahci_portp); 4101 mutex_exit(&ahci_portp->ahciport_mutex); 4102 4103 mutex_destroy(&ahci_portp->ahciport_mutex); 4104 cv_destroy(&ahci_portp->ahciport_cv); 4105 4106 kmem_free(ahci_portp, sizeof (ahci_port_t)); 4107 4108 ahci_ctlp->ahcictl_ports[port] = NULL; 4109} 4110 4111/* 4112 * Allocates memory for the Received FIS Structure 4113 * 4114 * WARNING!!! ahciport_mutex should be acquired before the function 4115 * is called. 4116 */ 4117static int 4118ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4119 uint8_t port) 4120{ 4121 size_t rcvd_fis_size; 4122 size_t ret_len; 4123 uint_t cookie_count; 4124 4125 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 4126 4127 /* allocate rcvd FIS dma handle. */ 4128 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4129 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 4130 DDI_DMA_SLEEP, 4131 NULL, 4132 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 4133 DDI_SUCCESS) { 4134 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4135 "rcvd FIS dma handle alloc failed"); 4136 4137 return (AHCI_FAILURE); 4138 } 4139 4140 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 4141 rcvd_fis_size, 4142 &accattr, 4143 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4144 DDI_DMA_SLEEP, 4145 NULL, 4146 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 4147 &ret_len, 4148 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 4149 4150 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4151 "rcvd FIS dma mem alloc fail"); 4152 /* error.. free the dma handle. */ 4153 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4154 return (AHCI_FAILURE); 4155 } 4156 4157 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 4158 NULL, 4159 (caddr_t)ahci_portp->ahciport_rcvd_fis, 4160 rcvd_fis_size, 4161 DDI_DMA_CONSISTENT, 4162 DDI_DMA_SLEEP, 4163 NULL, 4164 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 4165 &cookie_count) != DDI_DMA_MAPPED) { 4166 4167 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4168 "rcvd FIS dma handle bind fail"); 4169 /* error.. free the dma handle & free the memory. */ 4170 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4171 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4172 return (AHCI_FAILURE); 4173 } 4174 4175 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 4176 4177 /* Config Port Received FIS Base Address */ 4178 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4179 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 4180 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4181 4182 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4183 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4184 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4185 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 4186 4187 return (AHCI_SUCCESS); 4188} 4189 4190/* 4191 * Deallocates the Received FIS Structure 4192 * 4193 * WARNING!!! ahciport_mutex should be acquired before the function 4194 * is called. 4195 */ 4196static void 4197ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 4198{ 4199 /* Unbind the cmd list dma handle first. */ 4200 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4201 4202 /* Then free the underlying memory. */ 4203 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4204 4205 /* Now free the handle itself. */ 4206 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4207} 4208 4209/* 4210 * Allocates memory for the Command List, which contains up to 32 entries. 4211 * Each entry contains a command header, which is a 32-byte structure that 4212 * includes the pointer to the command table. 4213 * 4214 * WARNING!!! ahciport_mutex should be acquired before the function 4215 * is called. 4216 */ 4217static int 4218ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4219 uint8_t port) 4220{ 4221 size_t cmd_list_size; 4222 size_t ret_len; 4223 uint_t cookie_count; 4224 4225 cmd_list_size = 4226 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4227 4228 /* allocate cmd list dma handle. */ 4229 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4230 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4231 DDI_DMA_SLEEP, 4232 NULL, 4233 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4234 4235 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4236 "cmd list dma handle alloc failed"); 4237 return (AHCI_FAILURE); 4238 } 4239 4240 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4241 cmd_list_size, 4242 &accattr, 4243 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4244 DDI_DMA_SLEEP, 4245 NULL, 4246 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4247 &ret_len, 4248 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4249 4250 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4251 "cmd list dma mem alloc fail"); 4252 /* error.. free the dma handle. */ 4253 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4254 return (AHCI_FAILURE); 4255 } 4256 4257 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4258 NULL, 4259 (caddr_t)ahci_portp->ahciport_cmd_list, 4260 cmd_list_size, 4261 DDI_DMA_CONSISTENT, 4262 DDI_DMA_SLEEP, 4263 NULL, 4264 &ahci_portp->ahciport_cmd_list_dma_cookie, 4265 &cookie_count) != DDI_DMA_MAPPED) { 4266 4267 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4268 "cmd list dma handle bind fail"); 4269 /* error.. free the dma handle & free the memory. */ 4270 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4271 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4272 return (AHCI_FAILURE); 4273 } 4274 4275 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4276 4277 /* Config Port Command List Base Address */ 4278 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4279 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4280 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4281 4282 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4283 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4284 4285 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4286 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4287 4288 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4289 goto err_out; 4290 } 4291 4292 return (AHCI_SUCCESS); 4293 4294err_out: 4295 /* Unbind the cmd list dma handle first. */ 4296 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4297 4298 /* Then free the underlying memory. */ 4299 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4300 4301 /* Now free the handle itself. */ 4302 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4303 4304 return (AHCI_FAILURE); 4305} 4306 4307/* 4308 * Deallocates the Command List 4309 * 4310 * WARNING!!! ahciport_mutex should be acquired before the function 4311 * is called. 4312 */ 4313static void 4314ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4315{ 4316 /* First dealloc command table */ 4317 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4318 4319 /* Unbind the cmd list dma handle first. */ 4320 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4321 4322 /* Then free the underlying memory. */ 4323 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4324 4325 /* Now free the handle itself. */ 4326 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4327} 4328 4329/* 4330 * Allocates memory for all Command Tables, which contains Command FIS, 4331 * ATAPI Command and Physical Region Descriptor Table. 4332 * 4333 * WARNING!!! ahciport_mutex should be acquired before the function 4334 * is called. 4335 */ 4336static int 4337ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4338{ 4339 size_t ret_len; 4340 ddi_dma_cookie_t cmd_table_dma_cookie; 4341 uint_t cookie_count; 4342 int slot; 4343 4344 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4345 "ahci_alloc_cmd_tables: port %d enter", 4346 ahci_portp->ahciport_port_num); 4347 4348 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4349 /* Allocate cmd table dma handle. */ 4350 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4351 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4352 DDI_DMA_SLEEP, 4353 NULL, 4354 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4355 DDI_SUCCESS) { 4356 4357 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4358 "cmd table dma handle alloc failed"); 4359 4360 goto err_out; 4361 } 4362 4363 if (ddi_dma_mem_alloc( 4364 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4365 ahci_cmd_table_size, 4366 &accattr, 4367 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4368 DDI_DMA_SLEEP, 4369 NULL, 4370 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4371 &ret_len, 4372 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4373 NULL) { 4374 4375 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4376 "cmd table dma mem alloc fail"); 4377 4378 /* error.. free the dma handle. */ 4379 ddi_dma_free_handle( 4380 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4381 goto err_out; 4382 } 4383 4384 if (ddi_dma_addr_bind_handle( 4385 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4386 NULL, 4387 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4388 ahci_cmd_table_size, 4389 DDI_DMA_CONSISTENT, 4390 DDI_DMA_SLEEP, 4391 NULL, 4392 &cmd_table_dma_cookie, 4393 &cookie_count) != DDI_DMA_MAPPED) { 4394 4395 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4396 "cmd table dma handle bind fail"); 4397 /* error.. free the dma handle & free the memory. */ 4398 ddi_dma_mem_free( 4399 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4400 ddi_dma_free_handle( 4401 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4402 goto err_out; 4403 } 4404 4405 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4406 ahci_cmd_table_size); 4407 4408 /* Config Port Command Table Base Address */ 4409 SET_COMMAND_TABLE_BASE_ADDR( 4410 (&ahci_portp->ahciport_cmd_list[slot]), 4411 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4412 4413#ifndef __lock_lint 4414 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4415 (&ahci_portp->ahciport_cmd_list[slot]), 4416 cmd_table_dma_cookie.dmac_laddress >> 32); 4417#endif 4418 } 4419 4420 return (AHCI_SUCCESS); 4421err_out: 4422 4423 for (slot--; slot >= 0; slot--) { 4424 /* Unbind the cmd table dma handle first */ 4425 (void) ddi_dma_unbind_handle( 4426 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4427 4428 /* Then free the underlying memory */ 4429 ddi_dma_mem_free( 4430 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4431 4432 /* Now free the handle itself */ 4433 ddi_dma_free_handle( 4434 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4435 } 4436 4437 return (AHCI_FAILURE); 4438} 4439 4440/* 4441 * Deallocates memory for all Command Tables. 4442 * 4443 * WARNING!!! ahciport_mutex should be acquired before the function 4444 * is called. 4445 */ 4446static void 4447ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4448{ 4449 int slot; 4450 4451 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4452 "ahci_dealloc_cmd_tables: %d enter", 4453 ahci_portp->ahciport_port_num); 4454 4455 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4456 /* Unbind the cmd table dma handle first. */ 4457 (void) ddi_dma_unbind_handle( 4458 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4459 4460 /* Then free the underlying memory. */ 4461 ddi_dma_mem_free( 4462 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4463 4464 /* Now free the handle itself. */ 4465 ddi_dma_free_handle( 4466 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4467 } 4468} 4469 4470/* 4471 * WARNING!!! ahciport_mutex should be acquired before the function 4472 * is called. 4473 */ 4474static void 4475ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4476 sata_device_t *sd) 4477{ 4478 sd->satadev_scr.sstatus = 4479 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4480 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4481 sd->satadev_scr.serror = 4482 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4483 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4484 sd->satadev_scr.scontrol = 4485 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4486 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4487 sd->satadev_scr.sactive = 4488 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4489 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4490} 4491 4492/* 4493 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4494 */ 4495static void 4496ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4497{ 4498 uint32_t port_intr_status; 4499 uint32_t port_intr_enable; 4500 4501 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4502 "ahci_port_intr enter: port %d", port); 4503 4504 mutex_enter(&ahci_portp->ahciport_mutex); 4505 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4506 /* For SATA_OPMODE_POLLING commands */ 4507 port_intr_enable = 4508 (AHCI_INTR_STATUS_DHRS | 4509 AHCI_INTR_STATUS_PSS | 4510 AHCI_INTR_STATUS_SDBS | 4511 AHCI_INTR_STATUS_UFS | 4512 AHCI_INTR_STATUS_PCS | 4513 AHCI_INTR_STATUS_PRCS | 4514 AHCI_INTR_STATUS_OFS | 4515 AHCI_INTR_STATUS_INFS | 4516 AHCI_INTR_STATUS_IFS | 4517 AHCI_INTR_STATUS_HBDS | 4518 AHCI_INTR_STATUS_HBFS | 4519 AHCI_INTR_STATUS_TFES); 4520 mutex_exit(&ahci_portp->ahciport_mutex); 4521 goto next; 4522 } 4523 mutex_exit(&ahci_portp->ahciport_mutex); 4524 4525 /* 4526 * port_intr_enable indicates that the corresponding interrrupt 4527 * reporting is enabled. 4528 */ 4529 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4530 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4531next: 4532 /* 4533 * port_intr_stats indicates that the corresponding interrupt 4534 * condition is active. 4535 */ 4536 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4537 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4538 4539 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4540 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4541 "port_intr_enable = 0x%x", 4542 port, port_intr_status, port_intr_enable); 4543 4544 port_intr_status &= port_intr_enable; 4545 4546 /* First clear the port interrupts status */ 4547 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4548 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4549 port_intr_status); 4550 4551 /* Check the completed non-queued commands */ 4552 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4553 AHCI_INTR_STATUS_PSS)) { 4554 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4555 ahci_portp, port); 4556 } 4557 4558 /* Check the completed queued commands */ 4559 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4560 (void) ahci_intr_set_device_bits(ahci_ctlp, 4561 ahci_portp, port); 4562 } 4563 4564 /* Check the port connect change status interrupt bit */ 4565 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4566 (void) ahci_intr_port_connect_change(ahci_ctlp, 4567 ahci_portp, port); 4568 } 4569 4570 /* Check the device mechanical presence status interrupt bit */ 4571 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4572 (void) ahci_intr_device_mechanical_presence_status( 4573 ahci_ctlp, ahci_portp, port); 4574 } 4575 4576 /* Check the PhyRdy change status interrupt bit */ 4577 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4578 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4579 port); 4580 } 4581 4582 /* 4583 * Check the non-fatal error interrupt bits, there are three 4584 * kinds of non-fatal errors at the time being: 4585 * 4586 * PxIS.UFS - Unknown FIS Error 4587 * PxIS.OFS - Overflow Error 4588 * PxIS.INFS - Interface Non-Fatal Error 4589 * 4590 * For these non-fatal errors, the HBA can continue to operate, 4591 * so the driver just log the error messages. 4592 */ 4593 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4594 AHCI_INTR_STATUS_OFS | 4595 AHCI_INTR_STATUS_INFS)) { 4596 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4597 port, port_intr_status); 4598 } 4599 4600 /* 4601 * Check the fatal error interrupt bits, there are four kinds 4602 * of fatal errors for AHCI controllers: 4603 * 4604 * PxIS.HBFS - Host Bus Fatal Error 4605 * PxIS.HBDS - Host Bus Data Error 4606 * PxIS.IFS - Interface Fatal Error 4607 * PxIS.TFES - Task File Error 4608 * 4609 * The fatal error means the HBA can not recover from it by 4610 * itself, and it will try to abort the transfer, and the software 4611 * must intervene to restart the port. 4612 */ 4613 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4614 AHCI_INTR_STATUS_HBDS | 4615 AHCI_INTR_STATUS_HBFS | 4616 AHCI_INTR_STATUS_TFES)) 4617 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4618 port, port_intr_status); 4619 4620 /* Check the cold port detect interrupt bit */ 4621 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4622 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4623 } 4624 4625 /* Second clear the corresponding bit in IS.IPS */ 4626 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4627 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4628} 4629 4630/* 4631 * Interrupt service handler 4632 */ 4633static uint_t 4634ahci_intr(caddr_t arg1, caddr_t arg2) 4635{ 4636#ifndef __lock_lint 4637 _NOTE(ARGUNUSED(arg2)) 4638#endif 4639 /* LINTED */ 4640 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4641 ahci_port_t *ahci_portp; 4642 int32_t global_intr_status; 4643 uint8_t port; 4644 4645 /* 4646 * global_intr_status indicates that the corresponding port has 4647 * an interrupt pending. 4648 */ 4649 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4650 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4651 4652 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4653 /* The interrupt is not ours */ 4654 return (DDI_INTR_UNCLAIMED); 4655 } 4656 4657 /* Loop for all the ports */ 4658 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4659 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4660 continue; 4661 } 4662 if (!((0x1 << port) & global_intr_status)) { 4663 continue; 4664 } 4665 4666 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4667 4668 /* Call ahci_port_intr */ 4669 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4670 } 4671 4672 return (DDI_INTR_CLAIMED); 4673} 4674 4675/* 4676 * For non-queued commands, when the corresponding bit in the PxCI register 4677 * is cleared, it means the command is completed successfully. And according 4678 * to the HBA state machine, there are three conditions which possibly will 4679 * try to clear the PxCI register bit. 4680 * 1. Receive one D2H Register FIS which is with 'I' bit set 4681 * 2. Update PIO Setup FIS 4682 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4683 * 4684 * Process completed non-queued commands when the interrupt status bit - 4685 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4686 * 4687 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4688 * with the 'I' bit set. And the following commands will send thus 4689 * FIS with 'I' bit set upon the successful completion: 4690 * 1. Non-data commands 4691 * 2. DMA data-in command 4692 * 3. DMA data-out command 4693 * 4. PIO data-out command 4694 * 5. PACKET non-data commands 4695 * 6. PACKET PIO data-in command 4696 * 7. PACKET PIO data-out command 4697 * 8. PACKET DMA data-in command 4698 * 9. PACKET DMA data-out command 4699 * 4700 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4701 * with the 'I' bit set. And the following commands will send this 4702 * FIS upon the successful completion: 4703 * 1. PIO data-in command 4704 */ 4705static int 4706ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4707 ahci_port_t *ahci_portp, uint8_t port) 4708{ 4709 uint32_t port_cmd_issue = 0; 4710 uint32_t finished_tags; 4711 int finished_slot; 4712 sata_pkt_t *satapkt; 4713 ahci_fis_d2h_register_t *rcvd_fisp; 4714#if AHCI_DEBUG 4715 ahci_cmd_header_t *cmd_header; 4716 uint32_t cmd_dmacount; 4717#endif 4718 4719 mutex_enter(&ahci_portp->ahciport_mutex); 4720 4721 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4722 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4723 /* 4724 * Spurious interrupt. Nothing to be done. 4725 */ 4726 mutex_exit(&ahci_portp->ahciport_mutex); 4727 return (AHCI_SUCCESS); 4728 } 4729 4730 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4731 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4732 4733 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4734 /* Slot 0 is always used during error recovery */ 4735 finished_tags = 0x1 & ~port_cmd_issue; 4736 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4737 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4738 "retrieval is finished, and finished_tags = 0x%x", 4739 port, finished_tags); 4740 } else { 4741 finished_tags = ahci_portp->ahciport_pending_tags & 4742 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4743 } 4744 4745 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4746 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4747 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4748 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4749 finished_tags); 4750 4751 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4752 (finished_tags == 0x1)) { 4753 satapkt = ahci_portp->ahciport_err_retri_pkt; 4754 ASSERT(satapkt != NULL); 4755 4756 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4757 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4758 "with SATA_PKT_COMPLETED", (void *)satapkt); 4759 4760 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4761 goto out; 4762 } 4763 4764 while (finished_tags) { 4765 finished_slot = ddi_ffs(finished_tags) - 1; 4766 if (finished_slot == -1) { 4767 goto out; 4768 } 4769 4770 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4771 ASSERT(satapkt != NULL); 4772#if AHCI_DEBUG 4773 /* 4774 * For non-native queued commands, the PRD byte count field 4775 * shall contain an accurate count of the number of bytes 4776 * transferred for the command before the PxCI bit is cleared 4777 * to '0' for the command. 4778 * 4779 * The purpose of this field is to let software know how many 4780 * bytes transferred for a given operation in order to 4781 * determine if underflow occurred. When issuing native command 4782 * queuing commands, this field should not be used and is not 4783 * required to be valid since in this case underflow is always 4784 * illegal. 4785 * 4786 * For data reads, the HBA will update its PRD byte count with 4787 * the total number of bytes received from the last FIS, and 4788 * may be able to continue normally. For data writes, the 4789 * device will detect an error, and HBA most likely will get 4790 * a fatal error. 4791 * 4792 * Therefore, here just put code to debug part. And please 4793 * refer to the comment above ahci_intr_fatal_error for the 4794 * definition of underflow error. 4795 */ 4796 cmd_dmacount = 4797 ahci_portp->ahciport_prd_bytecounts[finished_slot]; 4798 if (cmd_dmacount) { 4799 cmd_header = 4800 &ahci_portp->ahciport_cmd_list[finished_slot]; 4801 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_PRDT, ahci_ctlp, 4802 "ahci_intr_cmd_cmplt: port %d, " 4803 "PRD Byte Count = 0x%x, " 4804 "ahciport_prd_bytecounts = 0x%x", port, 4805 cmd_header->ahcich_prd_byte_count, 4806 cmd_dmacount); 4807 4808 if (cmd_header->ahcich_prd_byte_count != cmd_dmacount) { 4809 AHCIDBG1(AHCIDBG_UNDERFLOW, ahci_ctlp, 4810 "ahci_intr_cmd_cmplt: port %d, " 4811 "an underflow occurred", port); 4812 } 4813 } 4814#endif 4815 4816 /* 4817 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4818 * feature, sata_special_regs flag will be set, and the 4819 * driver should copy the status and the other corresponding 4820 * register values in the D2H Register FIS received (It's 4821 * working on Non-data protocol) from the device back to 4822 * the sata_cmd. 4823 * 4824 * For every AHCI port, there is only one Received FIS 4825 * structure, which contains the FISes received from the 4826 * device, So we're trying to copy the content of D2H 4827 * Register FIS in the Received FIS structure back to 4828 * the sata_cmd. 4829 */ 4830 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4831 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4832 ahcirf_d2h_register_fis); 4833 satapkt->satapkt_cmd.satacmd_status_reg = 4834 GET_RFIS_STATUS(rcvd_fisp); 4835 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4836 } 4837 4838 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4839 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4840 "with SATA_PKT_COMPLETED", (void *)satapkt); 4841 4842 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4843 CLEAR_BIT(finished_tags, finished_slot); 4844 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4845 4846 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4847 } 4848out: 4849 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4850 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4851 ahci_portp->ahciport_pending_tags); 4852 4853 mutex_exit(&ahci_portp->ahciport_mutex); 4854 4855 return (AHCI_SUCCESS); 4856} 4857 4858/* 4859 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4860 * with the 'I' bit set and has been copied into system memory. It will 4861 * be sent under the following situations: 4862 * 4863 * 1. NCQ command is completed 4864 * 2. Asynchronous notification 4865 * 4866 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4867 * via the Set Device Bits FIS. When such event is generated, the software 4868 * needs to read PxSACT register and compares the current value to the 4869 * list of commands previously issue by software. ahciport_pending_ncq_tags 4870 * keeps the tags of previously issued commands. 4871 * 4872 * Asynchronous Notification is a feature in SATA II, which allows an 4873 * ATAPI device to send a signal to the host when media is inserted or 4874 * removed and avoids polling the device for media changes. The signal 4875 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4876 * set to '1'. At the moment, it's not supported yet. 4877 */ 4878static int 4879ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4880 ahci_port_t *ahci_portp, uint8_t port) 4881{ 4882 uint32_t port_sactive; 4883 uint32_t port_cmd_issue; 4884 uint32_t issued_tags; 4885 int issued_slot; 4886 uint32_t finished_tags; 4887 int finished_slot; 4888 sata_pkt_t *satapkt; 4889 4890 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4891 "ahci_intr_set_device_bits enter: port %d", port); 4892 4893 mutex_enter(&ahci_portp->ahciport_mutex); 4894 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4895 mutex_exit(&ahci_portp->ahciport_mutex); 4896 return (AHCI_SUCCESS); 4897 } 4898 4899 /* 4900 * First the handler got which commands are finished by checking 4901 * PxSACT register 4902 */ 4903 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4904 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4905 4906 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4907 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4908 4909 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4910 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4911 "port_sactive = 0x%x", port, 4912 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4913 4914 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4915 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4916 4917 /* 4918 * For NCQ commands, the software can determine which command has 4919 * already been transmitted to the device by checking PxCI register. 4920 */ 4921 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4922 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4923 4924 issued_tags = ahci_portp->ahciport_pending_tags & 4925 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4926 4927 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4928 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4929 "port_cmd_issue = 0x%x", port, 4930 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4931 4932 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4933 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4934 4935 /* 4936 * Clear ahciport_pending_tags bit when the corresponding command 4937 * is already sent down to the device. 4938 */ 4939 while (issued_tags) { 4940 issued_slot = ddi_ffs(issued_tags) - 1; 4941 if (issued_slot == -1) { 4942 goto next; 4943 } 4944 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4945 CLEAR_BIT(issued_tags, issued_slot); 4946 } 4947 4948next: 4949 while (finished_tags) { 4950 finished_slot = ddi_ffs(finished_tags) - 1; 4951 if (finished_slot == -1) { 4952 goto out; 4953 } 4954 4955 /* The command is certainly transmitted to the device */ 4956 ASSERT(!(ahci_portp->ahciport_pending_tags & 4957 (0x1 << finished_slot))); 4958 4959 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4960 ASSERT(satapkt != NULL); 4961 4962 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4963 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4964 "with SATA_PKT_COMPLETED", (void *)satapkt); 4965 4966 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4967 CLEAR_BIT(finished_tags, finished_slot); 4968 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4969 4970 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4971 } 4972out: 4973 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4974 "ahci_intr_set_device_bits: port %d " 4975 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4976 port, ahci_portp->ahciport_pending_ncq_tags, 4977 ahci_portp->ahciport_pending_tags); 4978 4979 mutex_exit(&ahci_portp->ahciport_mutex); 4980 4981 return (AHCI_SUCCESS); 4982} 4983 4984/* 4985 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4986 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4987 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4988 * indicates a COMINIT signal was received. 4989 * 4990 * Hot plug insertion is detected by reception of a COMINIT signal from the 4991 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4992 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4993 * begin the normal communication negotiation sequence as outlined in the 4994 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4995 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4996 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4997 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4998 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4999 * to handle hot plug insertion. In this interrupt handler, just do nothing 5000 * but print some log message and clear the bit. 5001 */ 5002static int 5003ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 5004 ahci_port_t *ahci_portp, uint8_t port) 5005{ 5006#if AHCI_DEBUG 5007 uint32_t port_serror; 5008#endif 5009 5010 mutex_enter(&ahci_portp->ahciport_mutex); 5011 5012#if AHCI_DEBUG 5013 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5014 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5015 5016 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 5017 "ahci_intr_port_connect_change: port %d, " 5018 "port_serror = 0x%x", port, port_serror); 5019#endif 5020 5021 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 5022 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5023 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5024 SERROR_EXCHANGED_ERR); 5025 5026 mutex_exit(&ahci_portp->ahciport_mutex); 5027 5028 return (AHCI_SUCCESS); 5029} 5030 5031/* 5032 * Hot Plug Operation for platforms that support Mechanical Presence 5033 * Switches. 5034 * 5035 * When set, it indicates that a mechanical presence switch attached to this 5036 * port has been opened or closed, which may lead to a change in the connection 5037 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 5038 * are set to '1'. 5039 * 5040 * At the moment, this interrupt is not needed and disabled and we just log 5041 * the debug message. 5042 */ 5043static int 5044ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 5045 ahci_port_t *ahci_portp, uint8_t port) 5046{ 5047 uint32_t cap_status, port_cmd_status; 5048 5049 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 5050 "ahci_intr_device_mechanical_presence_status enter, " 5051 "port %d", port); 5052 5053 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5054 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 5055 5056 mutex_enter(&ahci_portp->ahciport_mutex); 5057 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5058 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5059 5060 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 5061 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 5062 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 5063 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 5064 "the interrupt: cap_status = 0x%x, " 5065 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 5066 mutex_exit(&ahci_portp->ahciport_mutex); 5067 5068 return (AHCI_SUCCESS); 5069 } 5070 5071#if AHCI_DEBUG 5072 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 5073 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 5074 "The mechanical presence switch is open: " 5075 "port %d, port_cmd_status = 0x%x", 5076 port, port_cmd_status); 5077 } else { 5078 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 5079 "The mechanical presence switch is close: " 5080 "port %d, port_cmd_status = 0x%x", 5081 port, port_cmd_status); 5082 } 5083#endif 5084 5085 mutex_exit(&ahci_portp->ahciport_mutex); 5086 5087 return (AHCI_SUCCESS); 5088} 5089 5090/* 5091 * Native Hot Plug Support. 5092 * 5093 * When set, it indicates that the internal PHYRDY signal changed state. 5094 * This bit reflects the state of PxSERR.DIAG.N. 5095 * 5096 * There are three kinds of conditions to generate this interrupt event: 5097 * 1. a device is inserted 5098 * 2. a device is disconnected 5099 * 3. when the link enters/exits a Partial or Slumber interface power 5100 * management state 5101 * 5102 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 5103 * bit may be set due to the link entering the Partial or Slumber power 5104 * management state, rather than due to a hot plug insertion or removal 5105 * event. So far, the interface power management is disabled, so the 5106 * driver can reliably get removal detection notification via the 5107 * PxSERR.DIAG.N bit. 5108 */ 5109static int 5110ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 5111 ahci_port_t *ahci_portp, uint8_t port) 5112{ 5113 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 5114 sata_device_t sdevice; 5115 int dev_exists_now = 0; 5116 int dev_existed_previously = 0; 5117 5118 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 5119 "ahci_intr_phyrdy_change enter, port %d", port); 5120 5121 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 5122 mutex_enter(&ahci_portp->ahciport_mutex); 5123 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5124 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5125 SERROR_PHY_RDY_CHG); 5126 mutex_exit(&ahci_portp->ahciport_mutex); 5127 5128 mutex_enter(&ahci_ctlp->ahcictl_mutex); 5129 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 5130 (ahci_portp == NULL)) { 5131 /* The whole controller setup is not yet done. */ 5132 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5133 return (AHCI_SUCCESS); 5134 } 5135 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5136 5137 mutex_enter(&ahci_portp->ahciport_mutex); 5138 5139 /* SStatus tells the presence of device. */ 5140 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5141 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 5142 5143 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 5144 dev_exists_now = 1; 5145 } 5146 5147 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 5148 dev_existed_previously = 1; 5149 } 5150 5151 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 5152 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 5153 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5154 "ahci_intr_phyrdy_change: port %d " 5155 "AHCI_PORT_FLAG_NODEV is cleared", port); 5156 if (dev_exists_now == 0) 5157 dev_existed_previously = 1; 5158 } 5159 5160 bzero((void *)&sdevice, sizeof (sata_device_t)); 5161 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5162 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5163 sdevice.satadev_addr.pmport = 0; 5164 sdevice.satadev_state = SATA_PSTATE_PWRON; 5165 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 5166 5167 if (dev_exists_now) { 5168 if (dev_existed_previously) { 5169 /* Things are fine now. The loss was temporary. */ 5170 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5171 "ahci_intr_phyrdy_change port %d " 5172 "device link lost/established", port); 5173 5174 mutex_exit(&ahci_portp->ahciport_mutex); 5175 sata_hba_event_notify( 5176 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5177 &sdevice, 5178 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 5179 mutex_enter(&ahci_portp->ahciport_mutex); 5180 5181 } else { 5182 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5183 "ahci_intr_phyrdy_change: port %d " 5184 "device link established", port); 5185 5186 /* A new device has been detected. */ 5187 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 5188 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 5189 5190 /* Try to start the port */ 5191 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 5192 != AHCI_SUCCESS) { 5193 sdevice.satadev_state |= SATA_PSTATE_FAILED; 5194 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5195 "ahci_intr_phyrdy_change: port %d failed " 5196 "at start port", port); 5197 } 5198 5199 /* Clear the max queue depth for inserted device */ 5200 ahci_portp->ahciport_max_ncq_tags = 0; 5201 5202 mutex_exit(&ahci_portp->ahciport_mutex); 5203 sata_hba_event_notify( 5204 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5205 &sdevice, 5206 SATA_EVNT_LINK_ESTABLISHED); 5207 mutex_enter(&ahci_portp->ahciport_mutex); 5208 5209 } 5210 } else { /* No device exists now */ 5211 5212 if (dev_existed_previously) { 5213 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5214 "ahci_intr_phyrdy_change: port %d " 5215 "device link lost", port); 5216 5217 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 5218 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 5219 ahci_portp, port); 5220 5221 /* An existing device is lost. */ 5222 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 5223 5224 mutex_exit(&ahci_portp->ahciport_mutex); 5225 sata_hba_event_notify( 5226 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5227 &sdevice, 5228 SATA_EVNT_LINK_LOST); 5229 mutex_enter(&ahci_portp->ahciport_mutex); 5230 } 5231 } 5232 5233 mutex_exit(&ahci_portp->ahciport_mutex); 5234 5235 return (AHCI_SUCCESS); 5236} 5237 5238/* 5239 * PxIS.UFS - Unknown FIS Error 5240 * 5241 * This interrupt event means an unknown FIS was received and has been 5242 * copied into system memory. An unknown FIS is not considered an illegal 5243 * FIS, unless the length received is more than 64 bytes. If an unknown 5244 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5245 * normal operation. If the unknown FIS is more than 64 bytes, then it 5246 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5247 * a fatal error. 5248 * 5249 * PxIS.OFS - Overflow Error 5250 * 5251 * Command list overflow is defined as software building a command table 5252 * that has fewer total bytes than the transaction given to the device. 5253 * On device writes, the HBA will run out of data, and on reads, there 5254 * will be no room to put the data. 5255 * 5256 * For an overflow on data read, either PIO or DMA, the HBA will set 5257 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5258 * non-fatal error when the HBA can continues. Sometimes, it will cause 5259 * a fatal error and need the software to do something. 5260 * 5261 * For an overflow on data write, setting PxIS.OFS is optional for both 5262 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5263 * software to clean up from this serious error. 5264 * 5265 * PxIS.INFS - Interface Non-Fatal Error 5266 * 5267 * This interrupt event indicates that the HBA encountered an error on 5268 * the Serial ATA interface but was able to continue operation. The kind 5269 * of error usually occurred during a non-Data FIS, and under this condition 5270 * the FIS will be re-transmitted by HBA automatically. 5271 * 5272 * When the FMA is implemented, there should be a stat structure to 5273 * record how many every kind of error happens. 5274 */ 5275static int 5276ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5277 uint8_t port, uint32_t intr_status) 5278{ 5279 uint32_t port_serror; 5280#if AHCI_DEBUG 5281 uint32_t port_cmd_status; 5282 uint32_t port_cmd_issue; 5283 uint32_t port_sactive; 5284 int current_slot; 5285 uint32_t current_tags; 5286 sata_pkt_t *satapkt; 5287 ahci_cmd_header_t *cmd_header; 5288 uint32_t cmd_dmacount; 5289#endif 5290 5291 mutex_enter(&ahci_portp->ahciport_mutex); 5292 5293 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5294 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5295 5296 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5297 "ahci_intr_non_fatal_error: port %d, " 5298 "port_serror = 0x%x", port, port_serror); 5299 5300 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5301 5302 if (intr_status & AHCI_INTR_STATUS_UFS) { 5303 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5304 "ahci port %d has unknown FIS error", port); 5305 5306 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5307 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5308 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5309 SERROR_FIS_TYPE); 5310 } 5311 5312#if AHCI_DEBUG 5313 if (intr_status & AHCI_INTR_STATUS_OFS) { 5314 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5315 "ahci port %d has overflow error", port); 5316 } 5317 5318 if (intr_status & AHCI_INTR_STATUS_INFS) { 5319 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5320 "ahci port %d has interface non fatal error", port); 5321 } 5322 5323 /* 5324 * Record the error occurred command's slot. 5325 */ 5326 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5327 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5328 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5329 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5330 5331 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5332 AHCI_CMD_STATUS_CCS_SHIFT; 5333 5334 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5335 satapkt = ahci_portp->ahciport_err_retri_pkt; 5336 ASSERT(satapkt != NULL); 5337 ASSERT(current_slot == 0); 5338 } else { 5339 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5340 } 5341 5342 if (satapkt != NULL) { 5343 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5344 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5345 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5346 satapkt->satapkt_cmd.satacmd_cmd_reg); 5347 5348 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5349 "ahci_intr_non_fatal_error: port %d, " 5350 "satapkt 0x%p is being processed when error occurs", 5351 port, (void *)satapkt); 5352 5353 /* 5354 * PRD Byte Count field of command header is not 5355 * required to reflect the total number of bytes 5356 * transferred when an overflow occurs, so here 5357 * just log the value. 5358 */ 5359 cmd_dmacount = 5360 ahci_portp->ahciport_prd_bytecounts[current_slot]; 5361 if (cmd_dmacount) { 5362 cmd_header = &ahci_portp-> 5363 ahciport_cmd_list[current_slot]; 5364 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5365 "ahci_intr_non_fatal_error: port %d, " 5366 "PRD Byte Count = 0x%x, " 5367 "ahciport_prd_bytecounts = 0x%x", port, 5368 cmd_header->ahcich_prd_byte_count, 5369 cmd_dmacount); 5370 } 5371 } 5372 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5373 /* 5374 * For queued command, list those command which have already 5375 * been transmitted to the device and still not completed. 5376 */ 5377 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5378 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5379 5380 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5381 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5382 5383 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5384 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5385 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5386 ahci_portp->ahciport_pending_ncq_tags, 5387 port_sactive, port_cmd_issue); 5388 5389 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5390 port_sactive & ~port_cmd_issue & 5391 AHCI_NCQ_SLOT_MASK(ahci_portp); 5392 5393 while (current_tags) { 5394 current_slot = ddi_ffs(current_tags) - 1; 5395 if (current_slot == -1) { 5396 goto out; 5397 } 5398 5399 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5400 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5401 ahci_ctlp, "ahci_intr_non_fatal_error: " 5402 "port %d, satapkt 0x%p is outstanding when " 5403 "error occurs", port, (void *)satapkt); 5404 } 5405 } 5406out: 5407#endif 5408 mutex_exit(&ahci_portp->ahciport_mutex); 5409 5410 return (AHCI_SUCCESS); 5411} 5412 5413/* 5414 * According to the AHCI spec, the error types include system memory 5415 * errors, interface errors, port multiplier errors, device errors, 5416 * command list overflow, command list underflow, native command 5417 * queuing tag errors and pio data transfer errors. 5418 * 5419 * System memory errors such as target abort, master abort, and parity 5420 * may cause the host to stop, and they are serious errors and needed 5421 * to be recovered with software intervention. When system software 5422 * has given a pointer to the HBA that doesn't exist in physical memory, 5423 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5424 * data error such as CRC or parity occurs, the HBA aborts the transfer 5425 * (if necessary) and PxIS.HBDS will be set. 5426 * 5427 * Interface errors are errors that occur due to electrical issues on 5428 * the interface, or protocol miscommunication between the device and 5429 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5430 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5431 * causes PxIS.IFS/PxIS.INFS to be set are 5432 * 1. in PxSERR.ERR, P bit is set to '1' 5433 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5434 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5435 * If the error occurred during a non-data FIS, the FIS must be 5436 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5437 * the error occurred during a data FIS, the transfer will stop, so 5438 * the error is fatal and PxIS.IFS is set. 5439 * 5440 * When a FIS arrives that updates the taskfile, the HBA checks to see 5441 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5442 * stops processing any more commands. 5443 * 5444 * Command list overflow is defined as software building a command table 5445 * that has fewer total bytes than the transaction given to the device. 5446 * On device writes, the HBA will run out of data, and on reads, there 5447 * will be no room to put the data. For an overflow on data read, either 5448 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5449 * For an overflow on data write, setting PxIS.OFS is optional for both 5450 * DMA and PIO, and a COMRESET is required by software to clean up from 5451 * this serious error. 5452 * 5453 * Command list underflow is defined as software building a command 5454 * table that has more total bytes than the transaction given to the 5455 * device. For data writes, both PIO and DMA, the device will detect 5456 * an error and end the transfer. And these errors are most likely going 5457 * to be fatal errors that will cause the port to be restarted. For 5458 * data reads, the HBA updates its PRD byte count, and may be 5459 * able to continue normally, but is not required to. And The HBA is 5460 * not required to detect underflow conditions for native command 5461 * queuing command. 5462 * 5463 * The HBA does not actively check incoming DMA Setup FISes to ensure 5464 * that the PxSACT register bit for that slot is set. Existing error 5465 * mechanisms, such as host bus failure, or bad protocol, are used to 5466 * recover from this case. 5467 * 5468 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5469 * DATA FIS must be an integral number of Dwords. If the HBA receives 5470 * a request which is not an integral number of Dwords, the HBA 5471 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5472 * software restarts the port. And the HBA ensures that the size 5473 * of the DATA FIS received during a PIO command matches the size in 5474 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5475 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5476 * stop running until software restarts the port. 5477 */ 5478/* 5479 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5480 * 5481 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5482 * interface which caused the transfer to stop. 5483 * 5484 * PxIS.HBDS indicates that the hba encountered a data error 5485 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5486 * 5487 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5488 * cannot recover from, such as a bad software pointer. 5489 * 5490 * PxIS.TFES is set whenever the status register is updated by the device 5491 * and the error bit (bit 0) is set. 5492 */ 5493static int 5494ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5495 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5496{ 5497 uint32_t port_cmd_status; 5498 uint32_t port_serror; 5499 uint32_t task_file_status; 5500 int failed_slot; 5501 sata_pkt_t *spkt = NULL; 5502 uint8_t err_byte; 5503 ahci_event_arg_t *args; 5504 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5505 5506 mutex_enter(&ahci_portp->ahciport_mutex); 5507 5508 /* 5509 * ahci_intr_phyrdy_change() may have rendered it to 5510 * SATA_DTYPE_NONE. 5511 */ 5512 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5513 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5514 "ahci_intr_fatal_error: port %d no device attached, " 5515 "and just return without doing anything", port); 5516 goto out0; 5517 } 5518 5519 if (intr_status & AHCI_INTR_STATUS_TFES) { 5520 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5521 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5522 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5523 "ahci_intr_fatal_error: port %d " 5524 "task_file_status = 0x%x", port, task_file_status); 5525 } 5526 5527 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5528 /* 5529 * Read PxCMD.CCS to determine the slot that the HBA 5530 * was processing when the error occurred. 5531 */ 5532 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5533 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5534 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5535 AHCI_CMD_STATUS_CCS_SHIFT; 5536 5537 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5538 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5539 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5540 "fatal error occurred for port %d", spkt, port); 5541 5542 if (intr_status & AHCI_INTR_STATUS_TFES) { 5543 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5544 >> AHCI_TFD_ERR_SHIFT; 5545 5546 /* 5547 * Won't emit the error message if it is an IDENTIFY 5548 * DEVICE command sent to an ATAPI device. 5549 */ 5550 if ((spkt != NULL) && 5551 (spkt->satapkt_cmd.satacmd_cmd_reg == 5552 SATAC_ID_DEVICE) && 5553 (err_byte == SATA_ERROR_ABORT)) 5554 goto out1; 5555 5556 /* 5557 * Won't emit the error message if it is an ATAPI PACKET 5558 * command 5559 */ 5560 if ((spkt != NULL) && 5561 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5562 goto out1; 5563 } 5564 } 5565 5566 /* print the fatal error type */ 5567 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5568 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5569 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5570 5571 /* print PxSERR related error message */ 5572 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5573 5574 /* print task file register value */ 5575 if (intr_status & AHCI_INTR_STATUS_TFES) { 5576 cmn_err(CE_WARN, "!ahci%d: ahci port %d task_file_status " 5577 "= 0x%x", instance, port, task_file_status); 5578 } 5579 5580out1: 5581 /* Prepare the argument for the taskq */ 5582 args = ahci_portp->ahciport_event_args; 5583 args->ahciea_ctlp = (void *)ahci_ctlp; 5584 args->ahciea_portp = (void *)ahci_portp; 5585 args->ahciea_event = intr_status; 5586 5587 /* Start the taskq to handle error recovery */ 5588 if ((ddi_taskq_dispatch(ahci_portp->ahciport_event_taskq, 5589 ahci_events_handler, 5590 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5591 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5592 "failed", instance); 5593 } 5594out0: 5595 mutex_exit(&ahci_portp->ahciport_mutex); 5596 5597 return (AHCI_SUCCESS); 5598} 5599 5600/* 5601 * Hot Plug Operation for platforms that support Cold Presence Detect. 5602 * 5603 * When set, a device status has changed as detected by the cold presence 5604 * detect logic. This bit can either be set due to a non-connected port 5605 * receiving a device, or a connected port having its device removed. 5606 * This bit is only valid if the port supports cold presence detect as 5607 * indicated by PxCMD.CPD set to '1'. 5608 * 5609 * At the moment, this interrupt is not needed and disabled and we just 5610 * log the debug message. 5611 */ 5612static int 5613ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5614 ahci_port_t *ahci_portp, uint8_t port) 5615{ 5616 uint32_t port_cmd_status; 5617 sata_device_t sdevice; 5618 5619 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5620 "ahci_intr_cold_port_detect enter, port %d", port); 5621 5622 mutex_enter(&ahci_portp->ahciport_mutex); 5623 5624 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5625 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5626 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5627 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5628 "port %d does not support cold presence detect, so " 5629 "we just ignore this interrupt", port); 5630 mutex_exit(&ahci_portp->ahciport_mutex); 5631 return (AHCI_SUCCESS); 5632 } 5633 5634 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5635 "port %d device status has changed", port); 5636 5637 bzero((void *)&sdevice, sizeof (sata_device_t)); 5638 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5639 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5640 sdevice.satadev_addr.pmport = 0; 5641 sdevice.satadev_state = SATA_PSTATE_PWRON; 5642 5643 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5644 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5645 "port %d: a device is hot plugged", port); 5646 mutex_exit(&ahci_portp->ahciport_mutex); 5647 sata_hba_event_notify( 5648 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5649 &sdevice, 5650 SATA_EVNT_DEVICE_ATTACHED); 5651 mutex_enter(&ahci_portp->ahciport_mutex); 5652 5653 } else { 5654 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5655 "port %d: a device is hot unplugged", port); 5656 mutex_exit(&ahci_portp->ahciport_mutex); 5657 sata_hba_event_notify( 5658 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5659 &sdevice, 5660 SATA_EVNT_DEVICE_DETACHED); 5661 mutex_enter(&ahci_portp->ahciport_mutex); 5662 } 5663 5664 mutex_exit(&ahci_portp->ahciport_mutex); 5665 5666 return (AHCI_SUCCESS); 5667} 5668 5669/* 5670 * Enable the interrupts for a particular port. 5671 * 5672 * WARNING!!! ahciport_mutex should be acquired before the function 5673 * is called. 5674 */ 5675static void 5676ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5677{ 5678 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5679 "ahci_enable_port_intrs enter, port %d", port); 5680 5681 /* 5682 * Clear port interrupt status before enabling interrupt 5683 */ 5684 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5685 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5686 AHCI_PORT_INTR_MASK); 5687 5688 /* 5689 * Clear the pending bit from IS.IPS 5690 */ 5691 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5692 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5693 5694 /* 5695 * Enable the following interrupts: 5696 * Device to Host Register FIS Interrupt (DHRS) 5697 * PIO Setup FIS Interrupt (PSS) 5698 * Set Device Bits Interrupt (SDBS) 5699 * Unknown FIS Interrupt (UFS) 5700 * Port Connect Change Status (PCS) 5701 * PhyRdy Change Status (PRCS) 5702 * Overflow Status (OFS) 5703 * Interface Non-fatal Error Status (INFS) 5704 * Interface Fatal Error Status (IFS) 5705 * Host Bus Data Error Status (HBDS) 5706 * Host Bus Fatal Error Status (HBFS) 5707 * Task File Error Status (TFES) 5708 */ 5709 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5710 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5711 (AHCI_INTR_STATUS_DHRS | 5712 AHCI_INTR_STATUS_PSS | 5713 AHCI_INTR_STATUS_SDBS | 5714 AHCI_INTR_STATUS_UFS | 5715 AHCI_INTR_STATUS_DPS | 5716 AHCI_INTR_STATUS_PCS | 5717 AHCI_INTR_STATUS_PRCS | 5718 AHCI_INTR_STATUS_OFS | 5719 AHCI_INTR_STATUS_INFS | 5720 AHCI_INTR_STATUS_IFS | 5721 AHCI_INTR_STATUS_HBDS | 5722 AHCI_INTR_STATUS_HBFS | 5723 AHCI_INTR_STATUS_TFES)); 5724} 5725 5726/* 5727 * Enable interrupts for all the ports. 5728 * 5729 * WARNING!!! ahcictl_mutex should be acquired before the function 5730 * is called. 5731 */ 5732static void 5733ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5734{ 5735 uint32_t ghc_control; 5736 5737 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5738 5739 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5740 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5741 5742 ghc_control |= AHCI_HBA_GHC_IE; 5743 5744 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5745 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5746} 5747 5748/* 5749 * Disable interrupts for a particular port. 5750 * 5751 * WARNING!!! ahciport_mutex should be acquired before the function 5752 * is called. 5753 */ 5754static void 5755ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5756{ 5757 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5758 "ahci_disable_port_intrs enter, port %d", port); 5759 5760 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5761 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5762} 5763 5764/* 5765 * Disable interrupts for the whole HBA. 5766 * 5767 * The global bit is cleared, then all interrupt sources from all 5768 * ports are disabled. 5769 * 5770 * WARNING!!! ahcictl_mutex should be acquired before the function 5771 * is called. 5772 */ 5773static void 5774ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5775{ 5776 uint32_t ghc_control; 5777 5778 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5779 5780 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5781 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5782 5783 ghc_control &= ~ AHCI_HBA_GHC_IE; 5784 5785 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5786 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5787} 5788 5789/* 5790 * Handle FIXED or MSI interrupts. 5791 */ 5792/* 5793 * According to AHCI spec, the HBA may support several interrupt modes: 5794 * * pin based interrupts (FIXED) 5795 * * single MSI message interrupts 5796 * * multiple MSI based message interrupts 5797 * 5798 * For pin based interrupts, the software interrupt handler need to check IS 5799 * register to find out which port has pending interrupts. And then check 5800 * PxIS register to find out which interrupt events happened on that port. 5801 * 5802 * For single MSI message interrupts, MSICAP.MC.MSIE is set with '1', and 5803 * MSICAP.MC.MME is set with '0'. This mode is similar to pin based interrupts 5804 * in that software interrupt handler need to check IS register to determine 5805 * which port triggered the interrupts since it uses a single message for all 5806 * port interrupts. 5807 * 5808 * HBA may optionally support multiple MSI message for better performance. In 5809 * this mode, each port may have its own interrupt message, and thus generation 5810 * of interrupts is no longer controlled through the IS register. MSICAP.MC.MMC 5811 * represents a power-of-2 wrapper on the number of implemented ports, and 5812 * the mapping of ports to interrupts is done in a 1-1 relationship, up to the 5813 * maximum number of assigned interrupts. When the number of MSI messages 5814 * allocated is less than the number requested, then hardware may have two 5815 * implementation behaviors: 5816 * * assign each ports its own interrupt and then force all additional 5817 * ports to share the last interrupt message, and this condition is 5818 * indicated by clearing GHC.MRSM to '0' 5819 * * revert to single MSI mode, indicated by setting GHC.MRSM to '1' 5820 * When multiple-message MSI is enabled, hardware will still set IS register 5821 * as single message case. And this IS register may be used by software when 5822 * fewer than the requested number of messages is granted in order to determine 5823 * which port had the interrupt. 5824 * 5825 * Note: The current ahci driver only supports the first two interrupt modes: 5826 * pin based interrupts and single MSI message interrupts, and the reason 5827 * is indicated in below code. 5828 */ 5829static int 5830ahci_add_intrs(ahci_ctl_t *ahci_ctlp, int intr_type) 5831{ 5832 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5833 int count, avail, actual; 5834 int i, rc; 5835 5836 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 5837 "ahci_add_intrs enter interrupt type 0x%x", intr_type); 5838 5839 /* get number of interrupts. */ 5840 rc = ddi_intr_get_nintrs(dip, intr_type, &count); 5841 if ((rc != DDI_SUCCESS) || (count == 0)) { 5842 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5843 "ddi_intr_get_nintrs() failed, " 5844 "rc %d count %d\n", rc, count); 5845 return (DDI_FAILURE); 5846 } 5847 5848 /* get number of available interrupts. */ 5849 rc = ddi_intr_get_navail(dip, intr_type, &avail); 5850 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5851 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5852 "ddi_intr_get_navail() failed, " 5853 "rc %d avail %d\n", rc, avail); 5854 return (DDI_FAILURE); 5855 } 5856 5857#if AHCI_DEBUG 5858 if (avail < count) { 5859 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5860 "ddi_intr_get_nintrs returned %d, navail() returned %d", 5861 count, avail); 5862 } 5863#endif 5864 5865 /* 5866 * Note: So far Solaris restricts the maximum number of messages for 5867 * x86 to 2, that is avail is 2, so here we set the count with 1 to 5868 * force the driver to use single MSI message interrupt. In future if 5869 * Solaris remove the restriction, then we need to delete the below 5870 * code and try to use multiple interrupt routine to gain better 5871 * performance. 5872 */ 5873 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 5874 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5875 "force to use one interrupt routine though the " 5876 "HBA supports %d interrupt", count); 5877 count = 1; 5878 } 5879 5880 /* Allocate an array of interrupt handles. */ 5881 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5882 ahci_ctlp->ahcictl_intr_htable = 5883 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5884 5885 /* call ddi_intr_alloc(). */ 5886 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5887 intr_type, 0, count, &actual, DDI_INTR_ALLOC_NORMAL); 5888 5889 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5890 AHCIDBG4(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5891 "ddi_intr_alloc() failed, rc %d count %d actual %d " 5892 "avail %d\n", rc, count, actual, avail); 5893 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5894 ahci_ctlp->ahcictl_intr_size); 5895 return (DDI_FAILURE); 5896 } 5897 5898 /* use interrupt count returned */ 5899#if AHCI_DEBUG 5900 if (actual < count) { 5901 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5902 "Requested: %d, Received: %d", count, actual); 5903 } 5904#endif 5905 5906 ahci_ctlp->ahcictl_intr_cnt = actual; 5907 5908 /* 5909 * Get priority for first, assume remaining are all the same. 5910 */ 5911 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5912 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5913 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5914 "ddi_intr_get_pri() failed"); 5915 5916 /* Free already allocated intr. */ 5917 for (i = 0; i < actual; i++) { 5918 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]); 5919 } 5920 5921 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5922 ahci_ctlp->ahcictl_intr_size); 5923 return (DDI_FAILURE); 5924 } 5925 5926 /* Test for high level interrupt. */ 5927 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5928 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5929 "ahci_add_intrs: Hi level intr not supported"); 5930 5931 /* Free already allocated intr. */ 5932 for (i = 0; i < actual; i++) { 5933 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]); 5934 } 5935 5936 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5937 sizeof (ddi_intr_handle_t)); 5938 5939 return (DDI_FAILURE); 5940 } 5941 5942 /* Call ddi_intr_add_handler(). */ 5943 for (i = 0; i < actual; i++) { 5944 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[i], 5945 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5946 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5947 "ddi_intr_add_handler() failed"); 5948 5949 /* Free already allocated intr. */ 5950 for (i = 0; i < actual; i++) { 5951 (void) ddi_intr_free( 5952 ahci_ctlp->ahcictl_intr_htable[i]); 5953 } 5954 5955 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5956 ahci_ctlp->ahcictl_intr_size); 5957 return (DDI_FAILURE); 5958 } 5959 } 5960 5961 if (ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5962 &ahci_ctlp->ahcictl_intr_cap) != DDI_SUCCESS) { 5963 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5964 "ddi_intr_get_cap() failed"); 5965 5966 /* Free already allocated intr. */ 5967 for (i = 0; i < actual; i++) { 5968 (void) ddi_intr_free( 5969 ahci_ctlp->ahcictl_intr_htable[i]); 5970 } 5971 5972 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5973 ahci_ctlp->ahcictl_intr_size); 5974 return (DDI_FAILURE); 5975 } 5976 5977 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5978 /* Call ddi_intr_block_enable() for MSI. */ 5979 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5980 ahci_ctlp->ahcictl_intr_cnt); 5981 } else { 5982 /* Call ddi_intr_enable() for FIXED or MSI non block enable. */ 5983 for (i = 0; i < ahci_ctlp->ahcictl_intr_cnt; i++) { 5984 (void) ddi_intr_enable( 5985 ahci_ctlp->ahcictl_intr_htable[i]); 5986 } 5987 } 5988 5989 return (DDI_SUCCESS); 5990} 5991 5992/* 5993 * Removes the registered interrupts irrespective of whether they 5994 * were legacy or MSI. 5995 * 5996 * WARNING!!! The controller interrupts must be disabled before calling 5997 * this routine. 5998 */ 5999static void 6000ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 6001{ 6002 int x; 6003 6004 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 6005 6006 /* Disable all interrupts. */ 6007 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 6008 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 6009 /* Call ddi_intr_block_disable(). */ 6010 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 6011 ahci_ctlp->ahcictl_intr_cnt); 6012 } else { 6013 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 6014 (void) ddi_intr_disable( 6015 ahci_ctlp->ahcictl_intr_htable[x]); 6016 } 6017 } 6018 6019 /* Call ddi_intr_remove_handler(). */ 6020 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 6021 (void) ddi_intr_remove_handler( 6022 ahci_ctlp->ahcictl_intr_htable[x]); 6023 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 6024 } 6025 6026 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 6027} 6028 6029/* 6030 * This routine tries to put port into P:NotRunning state by clearing 6031 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 6032 * and PxCMD.CR to '0'. 6033 * 6034 * WARNING!!! ahciport_mutex should be acquired before the function 6035 * is called. 6036 */ 6037static int 6038ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 6039 ahci_port_t *ahci_portp, uint8_t port) 6040{ 6041 uint32_t port_cmd_status; 6042 int loop_count; 6043 6044 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6045 "ahci_put_port_into_notrunning_state enter: port %d", port); 6046 6047 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6048 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6049 6050 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 6051 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6052 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 6053 6054 /* Wait until PxCMD.CR is cleared */ 6055 loop_count = 0; 6056 do { 6057 port_cmd_status = 6058 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6059 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6060 6061 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 6062 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 6063 "clearing port %d CMD.CR timeout, " 6064 "port_cmd_status = 0x%x", port, 6065 port_cmd_status); 6066 /* 6067 * We are effectively timing out after 0.5 sec. 6068 * This value is specified in AHCI spec. 6069 */ 6070 break; 6071 } 6072 6073 /* Wait for 10 millisec */ 6074 drv_usecwait(10000); 6075 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 6076 6077 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 6078 6079 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 6080 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 6081 "ahci_put_port_into_notrunning_state: failed to clear " 6082 "PxCMD.CR to '0' after loop count: %d, and " 6083 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 6084 return (AHCI_FAILURE); 6085 } else { 6086 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 6087 "ahci_put_port_into_notrunning_state: succeeded to clear " 6088 "PxCMD.CR to '0' after loop count: %d, and " 6089 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 6090 return (AHCI_SUCCESS); 6091 } 6092} 6093 6094/* 6095 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 6096 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 6097 * stable state, then set PxCMD.ST to '1' to start the port directly. 6098 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 6099 * COMRESET to the device to put it in an idle state. 6100 * 6101 * The fifth argument returns whether the port reset is involved during 6102 * the process. 6103 * 6104 * The routine will be called under following scenarios: 6105 * + To abort the packet(s) 6106 * + To reset the port 6107 * + To activate the port 6108 * + Fatal error recovery 6109 * + To abort the timeout packet(s) 6110 * 6111 * WARNING!!! ahciport_mutex should be acquired before the function 6112 * is called. And ahciport_mutex will be released before the reset 6113 * event is reported to sata module by calling sata_hba_event_notify, 6114 * and then be acquired again later. 6115 * 6116 * NOTES!!! During this procedure, PxSERR register will be cleared, and 6117 * according to the spec, the clearance of three bits will also clear 6118 * three interrupt status bits. 6119 * 1. PxSERR.DIAG.F will clear PxIS.UFS 6120 * 2. PxSERR.DIAG.X will clear PxIS.PCS 6121 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 6122 * 6123 * Among these three interrupt events, the driver needs to take care of 6124 * PxIS.PRCS, which is the hot plug event. When the driver found out 6125 * a device was unplugged, it will call the interrupt handler. 6126 */ 6127static int 6128ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 6129 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 6130{ 6131 uint32_t port_sstatus; 6132 uint32_t task_file_status; 6133 sata_device_t sdevice; 6134 int rval; 6135 int dev_exists_begin = 0; 6136 int dev_exists_end = 0; 6137 6138 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6139 "ahci_restart_port_wait_till_ready: port %d enter", port); 6140 6141 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 6142 dev_exists_begin = 1; 6143 6144 /* First clear PxCMD.ST */ 6145 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 6146 port); 6147 if (rval != AHCI_SUCCESS) 6148 /* 6149 * If PxCMD.CR does not clear within a reasonable time, it 6150 * may assume the interface is in a hung condition and may 6151 * continue with issuing the port reset. 6152 */ 6153 goto reset; 6154 6155 /* Then clear PxSERR */ 6156 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6157 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 6158 AHCI_SERROR_CLEAR_ALL); 6159 6160 /* Then get PxTFD */ 6161 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6162 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 6163 6164 /* 6165 * Check whether the device is in a stable status, if yes, 6166 * then start the port directly. However for ahci_tran_dport_reset, 6167 * we may have to perform a port reset. 6168 */ 6169 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 6170 !(flag & AHCI_PORT_RESET)) 6171 goto out; 6172 6173reset: 6174 /* 6175 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 6176 * a COMRESET to the device 6177 */ 6178 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 6179 6180 if (reset_flag != NULL) 6181 *reset_flag = 1; 6182 6183 /* Indicate to the framework that a reset has happened. */ 6184 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 6185 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 6186 /* Set the reset in progress flag */ 6187 ahci_portp->ahciport_reset_in_progress = 1; 6188 6189 bzero((void *)&sdevice, sizeof (sata_device_t)); 6190 sdevice.satadev_addr.cport = 6191 ahci_ctlp->ahcictl_port_to_cport[port]; 6192 sdevice.satadev_addr.pmport = 0; 6193 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6194 6195 sdevice.satadev_state = SATA_DSTATE_RESET | 6196 SATA_DSTATE_PWR_ACTIVE; 6197 if (ahci_ctlp->ahcictl_sata_hba_tran) { 6198 mutex_exit(&ahci_portp->ahciport_mutex); 6199 sata_hba_event_notify( 6200 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6201 &sdevice, 6202 SATA_EVNT_DEVICE_RESET); 6203 mutex_enter(&ahci_portp->ahciport_mutex); 6204 } 6205 6206 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 6207 "port %d sending event up: SATA_EVNT_RESET", port); 6208 } else { 6209 ahci_portp->ahciport_reset_in_progress = 0; 6210 } 6211 6212out: 6213 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6214 6215 /* SStatus tells the presence of device. */ 6216 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6217 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6218 6219 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6220 dev_exists_end = 1; 6221 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6222 } 6223 6224 /* Check whether a hot plug event happened */ 6225 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6226 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6227 "ahci_restart_port_wait_till_ready: port %d " 6228 "device is removed", port); 6229 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6230 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6231 "ahci_restart_port_wait_till_ready: port %d " 6232 "AHCI_PORT_FLAG_NODEV flag is set", port); 6233 mutex_exit(&ahci_portp->ahciport_mutex); 6234 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6235 mutex_enter(&ahci_portp->ahciport_mutex); 6236 } 6237 6238 return (rval); 6239} 6240 6241/* 6242 * This routine may be called under four scenarios: 6243 * a) do the recovery from fatal error 6244 * b) or we need to timeout some commands 6245 * c) or we need to abort some commands 6246 * d) or we need reset device/port/controller 6247 * 6248 * In all these scenarios, we need to send any pending unfinished 6249 * commands up to sata framework. 6250 * 6251 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6252 */ 6253static void 6254ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6255 ahci_port_t *ahci_portp, 6256 uint32_t slot_status, 6257 uint32_t failed_tags, 6258 uint32_t timeout_tags, 6259 uint32_t aborted_tags, 6260 uint32_t reset_tags) 6261{ 6262 uint32_t finished_tags = 0; 6263 uint32_t unfinished_tags = 0; 6264 int tmp_slot; 6265 sata_pkt_t *satapkt; 6266 int ncq_cmd_in_progress = 0; 6267 int err_retri_cmd_in_progress = 0; 6268 6269 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6270 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6271 ahci_portp->ahciport_port_num, slot_status); 6272 6273 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6274 "ahci_mop_commands: failed_tags: 0x%x, " 6275 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6276 "reset_tags: 0x%x", failed_tags, 6277 timeout_tags, aborted_tags, reset_tags); 6278 6279 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6280 finished_tags = ahci_portp->ahciport_pending_tags & 6281 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6282 6283 unfinished_tags = slot_status & 6284 AHCI_SLOT_MASK(ahci_ctlp) & 6285 ~failed_tags & 6286 ~aborted_tags & 6287 ~reset_tags & 6288 ~timeout_tags; 6289 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6290 ncq_cmd_in_progress = 1; 6291 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6292 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6293 6294 unfinished_tags = slot_status & 6295 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6296 ~failed_tags & 6297 ~aborted_tags & 6298 ~reset_tags & 6299 ~timeout_tags; 6300 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6301 6302 /* 6303 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6304 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6305 * complete successfully due to one of the following three 6306 * conditions: 6307 * 6308 * 1. Fatal error - failed_tags includes its slot 6309 * 2. Timed out - timeout_tags includes its slot 6310 * 3. Aborted when hot unplug - aborted_tags includes its 6311 * slot 6312 * 6313 * Please note that the command is always sent down in Slot 0 6314 */ 6315 err_retri_cmd_in_progress = 1; 6316 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6317 "ahci_mop_commands is called for port %d while " 6318 "REQUEST SENSE or READ LOG EXT for error retrieval " 6319 "is being executed slot_status = 0x%x", 6320 ahci_portp->ahciport_port_num, slot_status); 6321 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6322 ASSERT(slot_status == 0x1); 6323 } 6324 6325 /* Send up finished packets with SATA_PKT_COMPLETED */ 6326 while (finished_tags) { 6327 tmp_slot = ddi_ffs(finished_tags) - 1; 6328 if (tmp_slot == -1) { 6329 break; 6330 } 6331 6332 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6333 ASSERT(satapkt != NULL); 6334 6335 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6336 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6337 (void *)satapkt); 6338 6339 /* 6340 * Cannot fetch the return register content since the port 6341 * was restarted, so the corresponding tag will be set to 6342 * aborted tags. 6343 */ 6344 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6345 CLEAR_BIT(finished_tags, tmp_slot); 6346 aborted_tags |= tmp_slot; 6347 continue; 6348 } 6349 6350 if (ncq_cmd_in_progress) 6351 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6352 tmp_slot); 6353 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6354 CLEAR_BIT(finished_tags, tmp_slot); 6355 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6356 6357 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6358 } 6359 6360 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6361 while (failed_tags) { 6362 if (err_retri_cmd_in_progress) { 6363 satapkt = ahci_portp->ahciport_err_retri_pkt; 6364 ASSERT(satapkt != NULL); 6365 ASSERT(failed_tags == 0x1); 6366 6367 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6368 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6369 (void *)satapkt); 6370 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6371 break; 6372 } 6373 6374 tmp_slot = ddi_ffs(failed_tags) - 1; 6375 if (tmp_slot == -1) { 6376 break; 6377 } 6378 6379 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6380 ASSERT(satapkt != NULL); 6381 6382 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6383 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6384 (void *)satapkt); 6385 6386 if (ncq_cmd_in_progress) 6387 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6388 tmp_slot); 6389 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6390 CLEAR_BIT(failed_tags, tmp_slot); 6391 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6392 6393 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6394 } 6395 6396 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6397 while (timeout_tags) { 6398 if (err_retri_cmd_in_progress) { 6399 satapkt = ahci_portp->ahciport_err_retri_pkt; 6400 ASSERT(satapkt != NULL); 6401 ASSERT(timeout_tags == 0x1); 6402 6403 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6404 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6405 (void *)satapkt); 6406 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6407 break; 6408 } 6409 6410 tmp_slot = ddi_ffs(timeout_tags) - 1; 6411 if (tmp_slot == -1) { 6412 break; 6413 } 6414 6415 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6416 ASSERT(satapkt != NULL); 6417 6418 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6419 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6420 (void *)satapkt); 6421 6422 if (ncq_cmd_in_progress) 6423 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6424 tmp_slot); 6425 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6426 CLEAR_BIT(timeout_tags, tmp_slot); 6427 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6428 6429 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6430 } 6431 6432 /* Send up aborted packets with SATA_PKT_ABORTED */ 6433 while (aborted_tags) { 6434 if (err_retri_cmd_in_progress) { 6435 satapkt = ahci_portp->ahciport_err_retri_pkt; 6436 ASSERT(satapkt != NULL); 6437 ASSERT(aborted_tags == 0x1); 6438 6439 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6440 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6441 (void *)satapkt); 6442 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6443 break; 6444 } 6445 6446 tmp_slot = ddi_ffs(aborted_tags) - 1; 6447 if (tmp_slot == -1) { 6448 break; 6449 } 6450 6451 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6452 ASSERT(satapkt != NULL); 6453 6454 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6455 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6456 (void *)satapkt); 6457 6458 if (ncq_cmd_in_progress) 6459 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6460 tmp_slot); 6461 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6462 CLEAR_BIT(aborted_tags, tmp_slot); 6463 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6464 6465 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6466 } 6467 6468 /* Send up reset packets with SATA_PKT_RESET. */ 6469 while (reset_tags) { 6470 tmp_slot = ddi_ffs(reset_tags) - 1; 6471 if (tmp_slot == -1) { 6472 break; 6473 } 6474 6475 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6476 ASSERT(satapkt != NULL); 6477 6478 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6479 "sending up pkt 0x%p with SATA_PKT_RESET", 6480 (void *)satapkt); 6481 6482 if (ncq_cmd_in_progress) 6483 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6484 tmp_slot); 6485 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6486 CLEAR_BIT(reset_tags, tmp_slot); 6487 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6488 6489 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6490 } 6491 6492 /* Send up unfinished packets with SATA_PKT_RESET */ 6493 while (unfinished_tags) { 6494 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6495 if (tmp_slot == -1) { 6496 break; 6497 } 6498 6499 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6500 ASSERT(satapkt != NULL); 6501 6502 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6503 "sending up pkt 0x%p with SATA_PKT_RESET", 6504 (void *)satapkt); 6505 6506 if (ncq_cmd_in_progress) 6507 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6508 tmp_slot); 6509 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6510 CLEAR_BIT(unfinished_tags, tmp_slot); 6511 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6512 6513 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6514 } 6515 6516 ahci_portp->ahciport_mop_in_progress--; 6517 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6518 6519 if (ahci_portp->ahciport_mop_in_progress == 0) 6520 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6521} 6522 6523/* 6524 * This routine is going to first request a READ LOG EXT sata pkt from sata 6525 * module, and then deliver it to the HBA to get the ncq failure context. 6526 * The return value is the exactly failed tags. 6527 */ 6528static uint32_t 6529ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6530 uint8_t port) 6531{ 6532 sata_device_t sdevice; 6533 sata_pkt_t *rdlog_spkt, *spkt; 6534 ddi_dma_handle_t buf_dma_handle; 6535 int loop_count; 6536 int rval; 6537 int failed_slot; 6538 uint32_t failed_tags = 0; 6539 struct sata_ncq_error_recovery_page *ncq_err_page; 6540 6541 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6542 "ahci_get_rdlogext_data enter: port %d", port); 6543 6544 /* Prepare the sdevice data */ 6545 bzero((void *)&sdevice, sizeof (sata_device_t)); 6546 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6547 6548 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6549 sdevice.satadev_addr.pmport = 0; 6550 6551 /* 6552 * Call the sata hba interface to get a rdlog spkt 6553 */ 6554 loop_count = 0; 6555loop: 6556 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6557 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6558 if (rdlog_spkt == NULL) { 6559 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6560 /* Sleep for a while */ 6561 delay(AHCI_10MS_TICKS); 6562 goto loop; 6563 } 6564 /* Timed out after 1s */ 6565 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6566 "failed to get rdlog spkt for port %d", port); 6567 return (failed_tags); 6568 } 6569 6570 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6571 6572 /* 6573 * This flag is used to handle the specific error recovery when the 6574 * READ LOG EXT command gets a failure (fatal error or time-out). 6575 */ 6576 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6577 6578 /* 6579 * This start is not supposed to fail because after port is restarted, 6580 * the whole command list is empty. 6581 */ 6582 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6583 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6584 ahci_portp->ahciport_err_retri_pkt = NULL; 6585 6586 /* Remove the flag after READ LOG EXT command is completed */ 6587 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6588 6589 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6590 /* Update the request log data */ 6591 buf_dma_handle = *(ddi_dma_handle_t *) 6592 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6593 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6594 DDI_DMA_SYNC_FORKERNEL); 6595 if (rval == DDI_SUCCESS) { 6596 ncq_err_page = 6597 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6598 satapkt_cmd.satacmd_bp->b_un.b_addr; 6599 6600 /* Get the failed tag */ 6601 failed_slot = ncq_err_page->ncq_tag; 6602 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6603 "ahci_get_rdlogext_data: port %d " 6604 "failed slot %d", port, failed_slot); 6605 if (failed_slot & NQ) { 6606 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6607 "the failed slot is not a valid tag"); 6608 goto out; 6609 } 6610 6611 failed_slot &= NCQ_TAG_MASK; 6612 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6613 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6614 "ahci_get_rdlogext_data: failed spkt 0x%p", 6615 (void *)spkt); 6616 if (spkt == NULL) { 6617 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6618 "the failed slot spkt is NULL") 6619 goto out; 6620 } 6621 6622 failed_tags = 0x1 << failed_slot; 6623 6624 /* Fill out the error context */ 6625 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6626 ncq_err_page); 6627 ahci_update_sata_registers(ahci_ctlp, port, 6628 &spkt->satapkt_device); 6629 } 6630 } 6631out: 6632 sata_free_error_retrieval_pkt(rdlog_spkt); 6633 6634 return (failed_tags); 6635} 6636 6637/* 6638 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6639 * module, and then deliver it to the HBA to get the sense data and copy 6640 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6641 * SENSE sata pkt later. 6642 */ 6643static void 6644ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6645 uint8_t port, sata_pkt_t *spkt) 6646{ 6647 sata_device_t sdevice; 6648 sata_pkt_t *rs_spkt; 6649 sata_cmd_t *sata_cmd; 6650 ddi_dma_handle_t buf_dma_handle; 6651 int loop_count; 6652#if AHCI_DEBUG 6653 struct scsi_extended_sense *rqsense; 6654#endif 6655 6656 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6657 "ahci_get_rqsense_data enter: port %d", port); 6658 6659 /* Prepare the sdevice data */ 6660 bzero((void *)&sdevice, sizeof (sata_device_t)); 6661 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6662 6663 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6664 sdevice.satadev_addr.pmport = 0; 6665 6666 sata_cmd = &spkt->satapkt_cmd; 6667 6668 /* 6669 * Call the sata hba interface to get a rs spkt 6670 */ 6671 loop_count = 0; 6672loop: 6673 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6674 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6675 if (rs_spkt == NULL) { 6676 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6677 /* Sleep for a while */ 6678 delay(AHCI_10MS_TICKS); 6679 goto loop; 6680 6681 } 6682 /* Timed out after 1s */ 6683 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6684 "failed to get rs spkt for port %d", port); 6685 return; 6686 } 6687 6688 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6689 6690 /* 6691 * This flag is used to handle the specific error recovery when the 6692 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6693 */ 6694 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6695 6696 /* 6697 * This start is not supposed to fail because after port is restarted, 6698 * the whole command list is empty. 6699 */ 6700 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6701 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6702 ahci_portp->ahciport_err_retri_pkt = NULL; 6703 6704 /* Remove the flag after REQUEST SENSE command is completed */ 6705 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6706 6707 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6708 /* Update the request sense data */ 6709 buf_dma_handle = *(ddi_dma_handle_t *) 6710 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6711 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6712 DDI_DMA_SYNC_FORKERNEL); 6713 /* Copy the request sense data */ 6714 bcopy(rs_spkt-> 6715 satapkt_cmd.satacmd_bp->b_un.b_addr, 6716 &sata_cmd->satacmd_rqsense, 6717 SATA_ATAPI_MIN_RQSENSE_LEN); 6718#if AHCI_DEBUG 6719 rqsense = (struct scsi_extended_sense *) 6720 sata_cmd->satacmd_rqsense; 6721 6722 /* Dump the sense data */ 6723 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6724 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6725 "Sense data for satapkt %p ATAPI cmd 0x%x", 6726 spkt, sata_cmd->satacmd_acdb[0]); 6727 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6728 " es_code 0x%x es_class 0x%x " 6729 "es_key 0x%x es_add_code 0x%x " 6730 "es_qual_code 0x%x", 6731 rqsense->es_code, rqsense->es_class, 6732 rqsense->es_key, rqsense->es_add_code, 6733 rqsense->es_qual_code); 6734#endif 6735 } 6736 6737 sata_free_error_retrieval_pkt(rs_spkt); 6738} 6739 6740/* 6741 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6742 * the port must be restarted. When the HBA detects thus error, it may try 6743 * to abort a transfer. And if the transfer was aborted, the device is 6744 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6745 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6746 * that the device is in a stable status and transfers may be restarted without 6747 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6748 * then the software will send the COMRESET to do the port reset. 6749 * 6750 * Software should perform the appropriate error recovery actions based on 6751 * whether non-queued commands were being issued or natived command queuing 6752 * commands were being issued. 6753 * 6754 * And software will complete the command that had the error with error mark 6755 * to higher level software. 6756 * 6757 * Fatal errors include the following: 6758 * PxIS.IFS - Interface Fatal Error Status 6759 * PxIS.HBDS - Host Bus Data Error Status 6760 * PxIS.HBFS - Host Bus Fatal Error Status 6761 * PxIS.TFES - Task File Error Status 6762 * 6763 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6764 */ 6765static void 6766ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6767 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6768{ 6769 uint32_t port_cmd_status; 6770 uint32_t slot_status = 0; 6771 uint32_t failed_tags = 0; 6772 int failed_slot; 6773 int reset_flag = 0; 6774 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6775 sata_cmd_t *sata_cmd = NULL; 6776 sata_pkt_t *spkt = NULL; 6777#if AHCI_DEBUG 6778 ahci_cmd_header_t *cmd_header; 6779#endif 6780 6781 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6782 "ahci_fatal_error_recovery_handler enter: port %d", port); 6783 6784 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6785 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6786 6787 /* Read PxCI to see which commands are still outstanding */ 6788 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6789 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6790 6791 /* 6792 * Read PxCMD.CCS to determine the slot that the HBA 6793 * was processing when the error occurred. 6794 */ 6795 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6796 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6797 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6798 AHCI_CMD_STATUS_CCS_SHIFT; 6799 6800 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6801 spkt = ahci_portp->ahciport_err_retri_pkt; 6802 ASSERT(spkt != NULL); 6803 } else { 6804 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6805 if (spkt == NULL) { 6806 /* May happen when interface errors occur? */ 6807 goto next; 6808 } 6809 } 6810 6811#if AHCI_DEBUG 6812 /* 6813 * Debugging purpose... 6814 */ 6815 if (ahci_portp->ahciport_prd_bytecounts[failed_slot]) { 6816 cmd_header = 6817 &ahci_portp->ahciport_cmd_list[failed_slot]; 6818 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 6819 "ahci_fatal_error_recovery_handler: port %d, " 6820 "PRD Byte Count = 0x%x, " 6821 "ahciport_prd_bytecounts = 0x%x", port, 6822 cmd_header->ahcich_prd_byte_count, 6823 ahci_portp->ahciport_prd_bytecounts[failed_slot]); 6824 } 6825#endif 6826 6827 sata_cmd = &spkt->satapkt_cmd; 6828 6829 /* Fill out the status and error registers for PxIS.TFES */ 6830 if (intr_status & AHCI_INTR_STATUS_TFES) { 6831 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6832 ahcirf_d2h_register_fis); 6833 6834 /* Copy the error context back to the sata_cmd */ 6835 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6836 } 6837 6838 /* The failed command must be one of the outstanding commands */ 6839 failed_tags = 0x1 << failed_slot; 6840 ASSERT(failed_tags & slot_status); 6841 6842 /* Update the sata registers, especially PxSERR register */ 6843 ahci_update_sata_registers(ahci_ctlp, port, 6844 &spkt->satapkt_device); 6845 6846 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6847 /* Read PxSACT to see which commands are still outstanding */ 6848 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6849 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6850 } 6851next: 6852 6853#if AHCI_DEBUG 6854 /* 6855 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6856 * set, it means a fatal error happened after REQUEST SENSE command 6857 * or READ LOG EXT command is delivered to the HBA during the error 6858 * recovery process. At this time, the only outstanding command is 6859 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6860 */ 6861 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6862 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6863 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6864 "command or READ LOG EXT command for error data retrieval " 6865 "failed", port); 6866 ASSERT(slot_status == 0x1); 6867 ASSERT(failed_slot == 0); 6868 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6869 SCMD_REQUEST_SENSE || 6870 spkt->satapkt_cmd.satacmd_cmd_reg == 6871 SATAC_READ_LOG_EXT); 6872 } 6873#endif 6874 6875 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6876 ahci_portp->ahciport_mop_in_progress++; 6877 6878 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6879 port, NULL, &reset_flag); 6880 6881 /* 6882 * Won't retrieve error information: 6883 * 1. Port reset was involved to recover 6884 * 2. Device is gone 6885 * 3. IDENTIFY DEVICE command sent to ATAPI device 6886 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6887 */ 6888 if (reset_flag || 6889 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6890 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6891 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6892 goto out; 6893 6894 /* 6895 * Deliver READ LOG EXT to gather information about the error when 6896 * a COMRESET has not been performed as part of the error recovery 6897 * during NCQ command processing. 6898 */ 6899 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6900 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6901 ahci_portp, port); 6902 goto out; 6903 } 6904 6905 /* 6906 * Deliver REQUEST SENSE for ATAPI command to gather information about 6907 * the error when a COMRESET has not been performed as part of the 6908 * error recovery. 6909 */ 6910 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI) 6911 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6912out: 6913 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6914 "ahci_fatal_error_recovery_handler: port %d fatal error " 6915 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6916 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6917 port, slot_status, ahci_portp->ahciport_pending_tags, 6918 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6919 6920 ahci_mop_commands(ahci_ctlp, 6921 ahci_portp, 6922 slot_status, 6923 failed_tags, /* failed tags */ 6924 0, /* timeout tags */ 6925 0, /* aborted tags */ 6926 0); /* reset tags */ 6927} 6928 6929/* 6930 * Handle events - fatal error recovery 6931 */ 6932static void 6933ahci_events_handler(void *args) 6934{ 6935 ahci_event_arg_t *ahci_event_arg; 6936 ahci_ctl_t *ahci_ctlp; 6937 ahci_port_t *ahci_portp; 6938 uint32_t event; 6939 uint8_t port; 6940 6941 ahci_event_arg = (ahci_event_arg_t *)args; 6942 6943 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6944 ahci_portp = ahci_event_arg->ahciea_portp; 6945 event = ahci_event_arg->ahciea_event; 6946 port = ahci_portp->ahciport_port_num; 6947 6948 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 6949 "ahci_events_handler enter: port %d intr_status = 0x%x", 6950 port, event); 6951 6952 mutex_enter(&ahci_portp->ahciport_mutex); 6953 6954 /* 6955 * ahci_intr_phyrdy_change() may have rendered it to 6956 * SATA_DTYPE_NONE. 6957 */ 6958 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6959 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6960 "ahci_events_handler: port %d no device attached, " 6961 "and just return without doing anything", port); 6962 goto out; 6963 } 6964 6965 if (event & (AHCI_INTR_STATUS_IFS | 6966 AHCI_INTR_STATUS_HBDS | 6967 AHCI_INTR_STATUS_HBFS | 6968 AHCI_INTR_STATUS_TFES)) 6969 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6970 port, event); 6971 6972out: 6973 mutex_exit(&ahci_portp->ahciport_mutex); 6974} 6975 6976/* 6977 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6978 * detect there are some commands which are timed out. 6979 */ 6980static void 6981ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6982 uint8_t port, uint32_t tmp_timeout_tags) 6983{ 6984 uint32_t slot_status = 0; 6985 uint32_t finished_tags = 0; 6986 uint32_t timeout_tags = 0; 6987 6988 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6989 "ahci_timeout_pkts enter: port %d", port); 6990 6991 mutex_enter(&ahci_portp->ahciport_mutex); 6992 6993 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6994 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6995 /* Read PxCI to see which commands are still outstanding */ 6996 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6997 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6998 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6999 /* Read PxSACT to see which commands are still outstanding */ 7000 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7001 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 7002 } 7003 7004#if AHCI_DEBUG 7005 /* 7006 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 7007 * set, it means a fatal error happened after REQUEST SENSE command 7008 * or READ LOG EXT command is delivered to the HBA during the error 7009 * recovery process. At this time, the only outstanding command is 7010 * supposed to be REQUEST SENSE command or READ LOG EXT command. 7011 */ 7012 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7013 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 7014 "ahci_timeout_pkts called while REQUEST SENSE " 7015 "command or READ LOG EXT command for error recovery " 7016 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 7017 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 7018 tmp_timeout_tags, slot_status, 7019 ahci_portp->ahciport_pending_tags, 7020 ahci_portp->ahciport_pending_ncq_tags); 7021 ASSERT(slot_status == 0x1); 7022 } 7023#endif 7024 7025 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 7026 ahci_portp->ahciport_mop_in_progress++; 7027 7028 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 7029 port, NULL, NULL); 7030 7031 /* 7032 * Re-identify timeout tags because some previously checked commands 7033 * could already complete. 7034 */ 7035 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7036 finished_tags = ahci_portp->ahciport_pending_tags & 7037 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 7038 timeout_tags = tmp_timeout_tags & ~finished_tags; 7039 7040 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 7041 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 7042 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 7043 "pending_tags = 0x%x ", 7044 port, finished_tags, timeout_tags, 7045 slot_status, ahci_portp->ahciport_pending_tags); 7046 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7047 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 7048 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 7049 timeout_tags = tmp_timeout_tags & ~finished_tags; 7050 7051 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 7052 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 7053 "timeout_tags = 0x%x, port_sactive = 0x%x, " 7054 "pending_ncq_tags = 0x%x ", 7055 port, finished_tags, timeout_tags, 7056 slot_status, ahci_portp->ahciport_pending_ncq_tags); 7057 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7058 timeout_tags = tmp_timeout_tags; 7059 } 7060 7061 ahci_mop_commands(ahci_ctlp, 7062 ahci_portp, 7063 slot_status, 7064 0, /* failed tags */ 7065 timeout_tags, /* timeout tags */ 7066 0, /* aborted tags */ 7067 0); /* reset tags */ 7068 7069 mutex_exit(&ahci_portp->ahciport_mutex); 7070} 7071 7072/* 7073 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 7074 * for long time. 7075 */ 7076static void 7077ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 7078{ 7079 ahci_port_t *ahci_portp; 7080 sata_pkt_t *spkt; 7081 uint32_t pending_tags; 7082 uint32_t timeout_tags; 7083 uint32_t port_cmd_status; 7084 uint32_t port_sactive; 7085 uint8_t port; 7086 int tmp_slot; 7087 int current_slot; 7088 uint32_t current_tags; 7089 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7090 /* max number of cycles this packet should survive */ 7091 int max_life_cycles; 7092 7093 /* how many cycles this packet survived so far */ 7094 int watched_cycles; 7095 7096 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7097 7098 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 7099 "ahci_watchdog_handler entered"); 7100 7101 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 7102 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 7103 continue; 7104 } 7105 7106 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 7107 7108 mutex_enter(&ahci_portp->ahciport_mutex); 7109 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 7110 mutex_exit(&ahci_portp->ahciport_mutex); 7111 continue; 7112 } 7113 7114 /* Skip the check for those ports in error recovery */ 7115 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 7116 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 7117 mutex_exit(&ahci_portp->ahciport_mutex); 7118 continue; 7119 } 7120 7121 pending_tags = 0; 7122 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7123 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7124 7125 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7126 current_slot = 0; 7127 pending_tags = 0x1; 7128 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7129 current_slot = 7130 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 7131 AHCI_CMD_STATUS_CCS_SHIFT; 7132 pending_tags = ahci_portp->ahciport_pending_tags; 7133 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7134 port_sactive = ddi_get32( 7135 ahci_ctlp->ahcictl_ahci_acc_handle, 7136 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 7137 current_tags = port_sactive & 7138 ~port_cmd_status & 7139 AHCI_NCQ_SLOT_MASK(ahci_portp); 7140 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 7141 } 7142 7143 timeout_tags = 0; 7144 while (pending_tags) { 7145 tmp_slot = ddi_ffs(pending_tags) - 1; 7146 if (tmp_slot == -1) { 7147 break; 7148 } 7149 7150 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 7151 spkt = ahci_portp->ahciport_err_retri_pkt; 7152 else 7153 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 7154 7155 if ((spkt != NULL) && spkt->satapkt_time && 7156 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 7157 /* 7158 * We are overloading satapkt_hba_driver_private 7159 * with watched_cycle count. 7160 * 7161 * If a packet has survived for more than it's 7162 * max life cycles, it is a candidate for time 7163 * out. 7164 */ 7165 watched_cycles = (int)(intptr_t) 7166 spkt->satapkt_hba_driver_private; 7167 watched_cycles++; 7168 max_life_cycles = (spkt->satapkt_time + 7169 ahci_watchdog_timeout - 1) / 7170 ahci_watchdog_timeout; 7171 7172 spkt->satapkt_hba_driver_private = 7173 (void *)(intptr_t)watched_cycles; 7174 7175 if (watched_cycles <= max_life_cycles) 7176 goto next; 7177 7178 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, 7179 ahci_ctlp, "the current slot is %d", 7180 current_slot); 7181 /* 7182 * We need to check whether the HBA has 7183 * begun to execute the command, if not, 7184 * then re-set the timer of the command. 7185 */ 7186 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 7187 (tmp_slot != current_slot) || 7188 NCQ_CMD_IN_PROGRESS(ahci_portp) && 7189 ((0x1 << tmp_slot) & current_tags)) { 7190 spkt->satapkt_hba_driver_private = 7191 (void *)(intptr_t)0; 7192 } else { 7193 timeout_tags |= (0x1 << tmp_slot); 7194 cmn_err(CE_WARN, "!ahci%d: watchdog " 7195 "port %d satapkt 0x%p timed out\n", 7196 instance, port, (void *)spkt); 7197 } 7198 } 7199next: 7200 CLEAR_BIT(pending_tags, tmp_slot); 7201 } 7202 7203 if (timeout_tags) { 7204 mutex_exit(&ahci_portp->ahciport_mutex); 7205 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7206 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 7207 port, timeout_tags); 7208 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7209 mutex_enter(&ahci_portp->ahciport_mutex); 7210 } 7211 7212 mutex_exit(&ahci_portp->ahciport_mutex); 7213 } 7214 7215 /* Re-install the watchdog timeout handler */ 7216 if (ahci_ctlp->ahcictl_timeout_id != 0) { 7217 ahci_ctlp->ahcictl_timeout_id = 7218 timeout((void (*)(void *))ahci_watchdog_handler, 7219 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 7220 } 7221 7222 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7223} 7224 7225/* 7226 * Fill the error context into sata_cmd for non-queued command error. 7227 */ 7228static void 7229ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7230{ 7231 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7232 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7233 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7234 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7235 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7236 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7237 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7238 7239 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7240 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7241 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7242 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7243 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7244 } 7245} 7246 7247/* 7248 * Fill the ncq error page into sata_cmd for queued command error. 7249 */ 7250static void 7251ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7252 struct sata_ncq_error_recovery_page *ncq_err_page) 7253{ 7254 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7255 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7256 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7257 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7258 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7259 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7260 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7261 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7262 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7263 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7264 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7265} 7266 7267/* 7268 * Put the respective register value to sata_cmd_t for satacmd_flags. 7269 */ 7270static void 7271ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7272{ 7273 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7274 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7275 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7276 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7277 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7278 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7279 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7280 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7281 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7282 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7283 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7284 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7285 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7286 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7287 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7288 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7289 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7290 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7291 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7292 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7293} 7294 7295static void 7296ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7297 uint32_t intr_status) 7298{ 7299 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7300 7301 if (intr_status & AHCI_INTR_STATUS_IFS) 7302 cmn_err(CE_WARN, "!ahci%d: ahci port %d has interface fatal " 7303 "error", instance, port); 7304 7305 if (intr_status & AHCI_INTR_STATUS_HBDS) 7306 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus data error", 7307 instance, port); 7308 7309 if (intr_status & AHCI_INTR_STATUS_HBFS) 7310 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus fatal error", 7311 instance, port); 7312 7313 if (intr_status & AHCI_INTR_STATUS_TFES) 7314 cmn_err(CE_WARN, "!ahci%d: ahci port %d has task file error", 7315 instance, port); 7316 7317 cmn_err(CE_WARN, "!ahci%d: ahci port %d is trying to do error " 7318 "recovery", instance, port); 7319} 7320 7321/* 7322 * Dump the serror message to the log. 7323 */ 7324static void 7325ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7326 uint32_t port_serror, int debug_only) 7327{ 7328 static char err_buf[512]; 7329 static char err_msg_header[16]; 7330 char *err_msg = err_buf; 7331 7332 *err_buf = '\0'; 7333 *err_msg_header = '\0'; 7334 7335 if (port_serror & SERROR_DATA_ERR_FIXED) { 7336 err_msg = strcat(err_msg, 7337 "\tRecovered Data Integrity Error (I)\n"); 7338 } 7339 7340 if (port_serror & SERROR_COMM_ERR_FIXED) { 7341 err_msg = strcat(err_msg, 7342 "\tRecovered Communication Error (M)\n"); 7343 } 7344 7345 if (port_serror & SERROR_DATA_ERR) { 7346 err_msg = strcat(err_msg, 7347 "\tTransient Data Integrity Error (T)\n"); 7348 } 7349 7350 if (port_serror & SERROR_PERSISTENT_ERR) { 7351 err_msg = strcat(err_msg, 7352 "\tPersistent Communication or Data Integrity Error (C)\n"); 7353 } 7354 7355 if (port_serror & SERROR_PROTOCOL_ERR) { 7356 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7357 } 7358 7359 if (port_serror & SERROR_INT_ERR) { 7360 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7361 } 7362 7363 if (port_serror & SERROR_PHY_RDY_CHG) { 7364 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7365 } 7366 7367 if (port_serror & SERROR_PHY_INT_ERR) { 7368 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7369 } 7370 7371 if (port_serror & SERROR_COMM_WAKE) { 7372 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7373 } 7374 7375 if (port_serror & SERROR_10B_TO_8B_ERR) { 7376 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7377 } 7378 7379 if (port_serror & SERROR_DISPARITY_ERR) { 7380 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7381 } 7382 7383 if (port_serror & SERROR_CRC_ERR) { 7384 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7385 } 7386 7387 if (port_serror & SERROR_HANDSHAKE_ERR) { 7388 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7389 } 7390 7391 if (port_serror & SERROR_LINK_SEQ_ERR) { 7392 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7393 } 7394 7395 if (port_serror & SERROR_TRANS_ERR) { 7396 err_msg = strcat(err_msg, 7397 "\tTransport state transition error (T)\n"); 7398 } 7399 7400 if (port_serror & SERROR_FIS_TYPE) { 7401 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7402 } 7403 7404 if (port_serror & SERROR_EXCHANGED_ERR) { 7405 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7406 } 7407 7408 if (err_msg == NULL) 7409 return; 7410 7411 if (debug_only) { 7412 (void) sprintf(err_msg_header, "port %d", port); 7413 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7414 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7415 } else if (ahci_ctlp) { 7416 cmn_err(CE_WARN, "!ahci%d: %s %s", 7417 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7418 err_msg_header, err_msg); 7419 } else { 7420 cmn_err(CE_WARN, "!ahci: %s %s", err_msg_header, err_msg); 7421 } 7422} 7423 7424/* 7425 * This routine is to calculate the total number of ports implemented 7426 * by the HBA. 7427 */ 7428static int 7429ahci_get_num_implemented_ports(uint32_t ports_implemented) 7430{ 7431 uint8_t i; 7432 int num = 0; 7433 7434 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7435 if (((uint32_t)0x1 << i) & ports_implemented) 7436 num++; 7437 } 7438 7439 return (num); 7440} 7441 7442#if AHCI_DEBUG 7443static void 7444ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7445{ 7446 static char name[16]; 7447 va_list ap; 7448 7449 mutex_enter(&ahci_log_mutex); 7450 7451 va_start(ap, fmt); 7452 if (ahci_ctlp) { 7453 (void) sprintf(name, "ahci%d: ", 7454 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7455 } else { 7456 (void) sprintf(name, "ahci: "); 7457 } 7458 7459 (void) vsprintf(ahci_log_buf, fmt, ap); 7460 va_end(ap); 7461 7462 cmn_err(level, "%s%s", name, ahci_log_buf); 7463 7464 mutex_exit(&ahci_log_mutex); 7465} 7466#endif 7467 7468/* 7469 * quiesce(9E) entry point. 7470 * 7471 * This function is called when the system is single-threaded at high 7472 * PIL with preemption disabled. Therefore, this function must not be 7473 * blocked. 7474 * 7475 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 7476 * DDI_FAILURE indicates an error condition and should almost never happen. 7477 */ 7478static int 7479ahci_quiesce(dev_info_t *dip) 7480{ 7481 ahci_ctl_t *ahci_ctlp; 7482 ahci_port_t *ahci_portp; 7483 int instance, port; 7484 7485 instance = ddi_get_instance(dip); 7486 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 7487 7488 if (ahci_ctlp == NULL) 7489 return (DDI_FAILURE); 7490 7491#if AHCI_DEBUG 7492 ahci_debug_flags = 0; 7493#endif 7494 7495 /* disable all the interrupts. */ 7496 ahci_disable_all_intrs(ahci_ctlp); 7497 7498 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 7499 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 7500 continue; 7501 } 7502 7503 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 7504 7505 /* 7506 * Stop the port by clearing PxCMD.ST 7507 * 7508 * Here we must disable the port interrupt because 7509 * ahci_disable_all_intrs only clear GHC.IE, and IS 7510 * register will be still set if PxIE is enabled. 7511 * When ahci shares one IRQ with other drivers, the 7512 * intr handler may claim the intr mistakenly. 7513 */ 7514 ahci_disable_port_intrs(ahci_ctlp, port); 7515 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 7516 ahci_portp, port); 7517 } 7518 7519 return (DDI_SUCCESS); 7520} 7521