ahci.c revision 7623:76bac10725f1
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 29 * 30 * Power Management Support 31 * ------------------------ 32 * 33 * At the moment, the ahci driver only implements suspend/resume to 34 * support Suspend to RAM on X86 feature. Device power management isn't 35 * implemented, link power management is disabled, and hot plug isn't 36 * allowed during the period from suspend to resume. 37 * 38 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 39 * and DDI_RESUME entries, and don't need to take care of new requests 40 * sent down after suspend because the target driver (sd) has already 41 * handled these conditions, and blocked these requests. For the detailed 42 * information, please check with sdopen, sdclose and sdioctl routines. 43 * 44 */ 45 46#include <sys/note.h> 47#include <sys/scsi/scsi.h> 48#include <sys/pci.h> 49#include <sys/disp.h> 50#include <sys/sata/sata_hba.h> 51#include <sys/sata/adapters/ahci/ahcireg.h> 52#include <sys/sata/adapters/ahci/ahcivar.h> 53 54/* 55 * Function prototypes for driver entry points 56 */ 57static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 58static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 59static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 60 61/* 62 * Function prototypes for SATA Framework interfaces 63 */ 64static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 65static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 66 67static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 68static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 69static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 70static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 71static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 72static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 73#if defined(__lock_lint) 74static int ahci_selftest(dev_info_t *, sata_device_t *); 75#endif 76 77/* 78 * Local function prototypes 79 */ 80static int ahci_alloc_ports_state(ahci_ctl_t *); 81static void ahci_dealloc_ports_state(ahci_ctl_t *); 82static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 83static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 84static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 85static void ahci_dealloc_rcvd_fis(ahci_port_t *); 86static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 87static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 88static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 89static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 90 91static int ahci_initialize_controller(ahci_ctl_t *); 92static void ahci_uninitialize_controller(ahci_ctl_t *); 93static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 94static int ahci_config_space_init(ahci_ctl_t *); 95 96static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 97static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 98static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 99static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 100static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 101 uint8_t, sata_pkt_t *); 102static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 103 uint8_t, sata_pkt_t *); 104static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 105static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 106static void ahci_copy_ncq_err_page(sata_cmd_t *, 107 struct sata_ncq_error_recovery_page *); 108static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 109 110static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 111static int ahci_hba_reset(ahci_ctl_t *); 112static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 113static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 114static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 115static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 116static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 117static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 118 uint8_t); 119static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 120 uint8_t, int, int *); 121static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 122 uint32_t, uint32_t, uint32_t, uint32_t); 123static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 124static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 125 uint8_t, sata_pkt_t *); 126static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 127 uint8_t, uint32_t); 128static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 129 uint8_t, uint32_t); 130static void ahci_events_handler(void *); 131static void ahci_watchdog_handler(ahci_ctl_t *); 132 133static uint_t ahci_intr(caddr_t, caddr_t); 134static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 135static int ahci_add_legacy_intrs(ahci_ctl_t *); 136static int ahci_add_msi_intrs(ahci_ctl_t *); 137static void ahci_rem_intrs(ahci_ctl_t *); 138static void ahci_enable_all_intrs(ahci_ctl_t *); 139static void ahci_disable_all_intrs(ahci_ctl_t *); 140static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 141static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 142 143static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 144static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 145static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 146static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 147 ahci_port_t *, uint8_t); 148static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 149static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 150 uint8_t, uint32_t); 151static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 152 uint8_t, uint32_t); 153static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 154 155static int ahci_get_num_implemented_ports(uint32_t); 156static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 157 uint32_t); 158static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 159#if AHCI_DEBUG 160static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 161#endif 162 163 164/* 165 * DMA attributes for the data buffer 166 * 167 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 168 * does not support 64-bit addressing 169 */ 170static ddi_dma_attr_t buffer_dma_attr = { 171 DMA_ATTR_V0, /* dma_attr_version */ 172 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 173 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 174 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 175 0x2ull, /* dma_attr_align: word aligned */ 176 1, /* dma_attr_burstsizes */ 177 1, /* dma_attr_minxfer */ 178 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 179 0xffffffffull, /* dma_attr_seg */ 180 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 181 512, /* dma_attr_granular */ 182 0, /* dma_attr_flags */ 183}; 184 185/* 186 * DMA attributes for the rcvd FIS 187 * 188 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 189 * does not support 64-bit addressing 190 */ 191static ddi_dma_attr_t rcvd_fis_dma_attr = { 192 DMA_ATTR_V0, /* dma_attr_version */ 193 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 194 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 195 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 196 0x100ull, /* dma_attr_align: 256-byte aligned */ 197 1, /* dma_attr_burstsizes */ 198 1, /* dma_attr_minxfer */ 199 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 200 0xffffffffull, /* dma_attr_seg */ 201 1, /* dma_attr_sgllen */ 202 1, /* dma_attr_granular */ 203 0, /* dma_attr_flags */ 204}; 205 206/* 207 * DMA attributes for the command list 208 * 209 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 210 * does not support 64-bit addressing 211 */ 212static ddi_dma_attr_t cmd_list_dma_attr = { 213 DMA_ATTR_V0, /* dma_attr_version */ 214 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 215 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 216 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 217 0x400ull, /* dma_attr_align: 1K-byte aligned */ 218 1, /* dma_attr_burstsizes */ 219 1, /* dma_attr_minxfer */ 220 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 221 0xffffffffull, /* dma_attr_seg */ 222 1, /* dma_attr_sgllen */ 223 1, /* dma_attr_granular */ 224 0, /* dma_attr_flags */ 225}; 226 227/* 228 * DMA attributes for cmd tables 229 * 230 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 231 * does not support 64-bit addressing 232 */ 233static ddi_dma_attr_t cmd_table_dma_attr = { 234 DMA_ATTR_V0, /* dma_attr_version */ 235 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 236 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 237 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 238 0x80ull, /* dma_attr_align: 128-byte aligned */ 239 1, /* dma_attr_burstsizes */ 240 1, /* dma_attr_minxfer */ 241 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 242 0xffffffffull, /* dma_attr_seg */ 243 1, /* dma_attr_sgllen */ 244 1, /* dma_attr_granular */ 245 0, /* dma_attr_flags */ 246}; 247 248 249/* Device access attributes */ 250static ddi_device_acc_attr_t accattr = { 251 DDI_DEVICE_ATTR_V0, 252 DDI_STRUCTURE_LE_ACC, 253 DDI_STRICTORDER_ACC 254}; 255 256 257static struct dev_ops ahcictl_dev_ops = { 258 DEVO_REV, /* devo_rev */ 259 0, /* refcnt */ 260 ahci_getinfo, /* info */ 261 nulldev, /* identify */ 262 nulldev, /* probe */ 263 ahci_attach, /* attach */ 264 ahci_detach, /* detach */ 265 nodev, /* no reset */ 266 (struct cb_ops *)0, /* driver operations */ 267 NULL, /* bus operations */ 268 NULL /* power */ 269}; 270 271static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 272 SATA_TRAN_HOTPLUG_OPS_REV_1, 273 ahci_tran_hotplug_port_activate, 274 ahci_tran_hotplug_port_deactivate 275}; 276 277extern struct mod_ops mod_driverops; 278 279static struct modldrv modldrv = { 280 &mod_driverops, /* driverops */ 281 "ahci driver", 282 &ahcictl_dev_ops, /* driver ops */ 283}; 284 285static struct modlinkage modlinkage = { 286 MODREV_1, 287 &modldrv, 288 NULL 289}; 290 291static int ahci_watchdog_timeout = 5; /* 5 seconds */ 292static int ahci_watchdog_tick; 293 294static size_t ahci_cmd_table_size; 295 296/* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 297int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 298 299/* 300 * AHCI MSI tunable: 301 * 302 * MSI will be enabled in phase 2. 303 */ 304boolean_t ahci_msi_enabled = B_FALSE; 305 306#if AHCI_DEBUG 307uint32_t ahci_debug_flags = 0; 308 309/* The following is needed for ahci_log() */ 310static kmutex_t ahci_log_mutex; 311static char ahci_log_buf[512]; 312#endif 313 314/* Opaque state pointer initialized by ddi_soft_state_init() */ 315static void *ahci_statep = NULL; 316 317/* 318 * ahci module initialization. 319 */ 320int 321_init(void) 322{ 323 int ret; 324 325 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 326 if (ret != 0) { 327 goto err_out; 328 } 329 330#if AHCI_DEBUG 331 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 332#endif 333 334 if ((ret = sata_hba_init(&modlinkage)) != 0) { 335#if AHCI_DEBUG 336 mutex_destroy(&ahci_log_mutex); 337#endif 338 ddi_soft_state_fini(&ahci_statep); 339 goto err_out; 340 } 341 342 ret = mod_install(&modlinkage); 343 if (ret != 0) { 344 sata_hba_fini(&modlinkage); 345#if AHCI_DEBUG 346 mutex_destroy(&ahci_log_mutex); 347#endif 348 ddi_soft_state_fini(&ahci_statep); 349 goto err_out; 350 } 351 352 /* watchdog tick */ 353 ahci_watchdog_tick = drv_usectohz( 354 (clock_t)ahci_watchdog_timeout * 1000000); 355 return (ret); 356 357err_out: 358 cmn_err(CE_WARN, "!ahci: Module init failed"); 359 return (ret); 360} 361 362/* 363 * ahci module uninitialize. 364 */ 365int 366_fini(void) 367{ 368 int ret; 369 370 ret = mod_remove(&modlinkage); 371 if (ret != 0) { 372 return (ret); 373 } 374 375 /* Remove the resources allocated in _init(). */ 376 sata_hba_fini(&modlinkage); 377#if AHCI_DEBUG 378 mutex_destroy(&ahci_log_mutex); 379#endif 380 ddi_soft_state_fini(&ahci_statep); 381 382 return (ret); 383} 384 385/* 386 * _info entry point 387 */ 388int 389_info(struct modinfo *modinfop) 390{ 391 return (mod_info(&modlinkage, modinfop)); 392} 393 394/* 395 * The attach entry point for dev_ops. 396 */ 397static int 398ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 399{ 400 ahci_ctl_t *ahci_ctlp; 401 int instance = ddi_get_instance(dip); 402 int status; 403 int attach_state; 404 uint32_t cap_status, ahci_version; 405 int intr_types; 406 int i; 407 pci_regspec_t *regs; 408 int regs_length; 409 int rnumber; 410#if AHCI_DEBUG 411 int speed; 412#endif 413 414 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 415 416 switch (cmd) { 417 case DDI_ATTACH: 418 break; 419 420 case DDI_RESUME: 421 422 /* 423 * During DDI_RESUME, the hardware state of the device 424 * (power may have been removed from the device) must be 425 * restored, allow pending requests to continue, and 426 * service new requests. 427 */ 428 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 429 mutex_enter(&ahci_ctlp->ahcictl_mutex); 430 431 /* Restart watch thread */ 432 if (ahci_ctlp->ahcictl_timeout_id == 0) 433 ahci_ctlp->ahcictl_timeout_id = timeout( 434 (void (*)(void *))ahci_watchdog_handler, 435 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 436 437 mutex_exit(&ahci_ctlp->ahcictl_mutex); 438 439 /* 440 * Re-initialize the controller and enable the interrupts and 441 * restart all the ports. 442 * 443 * Note that so far we don't support hot-plug during 444 * suspend/resume. 445 */ 446 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 447 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 448 "Failed to initialize the controller " 449 "during DDI_RESUME"); 450 return (DDI_FAILURE); 451 } 452 453 mutex_enter(&ahci_ctlp->ahcictl_mutex); 454 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 455 mutex_exit(&ahci_ctlp->ahcictl_mutex); 456 457 return (DDI_SUCCESS); 458 459 default: 460 return (DDI_FAILURE); 461 } 462 463 attach_state = AHCI_ATTACH_STATE_NONE; 464 465 /* Allocate soft state */ 466 status = ddi_soft_state_zalloc(ahci_statep, instance); 467 if (status != DDI_SUCCESS) { 468 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 469 instance); 470 goto err_out; 471 } 472 473 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 474 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 475 ahci_ctlp->ahcictl_dip = dip; 476 477 /* Initialize the cport/port mapping */ 478 for (i = 0; i < AHCI_MAX_PORTS; i++) { 479 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 480 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 481 } 482 483 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 484 485 /* 486 * Now map the AHCI base address; which includes global 487 * registers and port control registers 488 * 489 * According to the spec, the AHCI Base Address is BAR5, 490 * but BAR0-BAR4 are optional, so we need to check which 491 * rnumber is used for BAR5. 492 */ 493 494 /* 495 * search through DDI "reg" property for the AHCI register set 496 */ 497 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 498 DDI_PROP_DONTPASS, "reg", (int **)®s, 499 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 500 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 501 instance); 502 goto err_out; 503 } 504 505 /* AHCI Base Address is located at 0x24 offset */ 506 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 507 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 508 == AHCI_PCI_RNUM) 509 break; 510 } 511 512 ddi_prop_free(regs); 513 514 if (rnumber == regs_length) { 515 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 516 instance); 517 goto err_out; 518 } 519 520 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 521 522 status = ddi_regs_map_setup(dip, 523 rnumber, 524 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 525 0, 526 0, 527 &accattr, 528 &ahci_ctlp->ahcictl_ahci_acc_handle); 529 if (status != DDI_SUCCESS) { 530 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 531 instance); 532 goto err_out; 533 } 534 535 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 536 537 /* Get the AHCI version information */ 538 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 539 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 540 541 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 542 (ahci_version & 0xffff0000) >> 16, 543 ((ahci_version & 0x0000ff00) >> 4 | 544 (ahci_version & 0x000000ff))); 545 546 /* We don't support controllers whose versions are lower than 1.0 */ 547 if (!(ahci_version & 0xffff0000)) { 548 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 549 "than version 1.0", instance); 550 goto err_out; 551 } 552 553 /* Get the HBA capabilities information */ 554 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 555 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 556 557 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 558 cap_status); 559 560#if AHCI_DEBUG 561 /* Get the interface speed supported by the HBA */ 562 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 563 if (speed == 0x01) { 564 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 565 "hba interface speed support: Gen 1 (1.5Gbps)"); 566 } else if (speed == 0x10) { 567 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 568 "hba interface speed support: Gen 2 (3 Gbps)"); 569 } else if (speed == 0x11) { 570 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 571 "hba interface speed support: Gen 3 (6 Gbps)"); 572 } 573#endif 574 575 /* Get the number of command slots supported by the HBA */ 576 ahci_ctlp->ahcictl_num_cmd_slots = 577 ((cap_status & AHCI_HBA_CAP_NCS) >> 578 AHCI_HBA_CAP_NCS_SHIFT) + 1; 579 580 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 581 ahci_ctlp->ahcictl_num_cmd_slots); 582 583 /* Get the bit map which indicates ports implemented by the HBA */ 584 ahci_ctlp->ahcictl_ports_implemented = 585 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 586 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 587 588 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 589 ahci_ctlp->ahcictl_ports_implemented); 590 591 /* 592 * According to the AHCI spec, CAP.NP should indicate the maximum 593 * number of ports supported by the HBA silicon, but we found 594 * this value of ICH8 chipset only indicates the number of ports 595 * implemented (exposed) by it. Therefore, the driver should calculate 596 * the potential maximum value by checking PI register, and use 597 * the maximum of this value and CAP.NP. 598 */ 599 ahci_ctlp->ahcictl_num_ports = max( 600 (cap_status & AHCI_HBA_CAP_NP) + 1, 601 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 602 603 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 604 ahci_ctlp->ahcictl_num_ports); 605 606 /* Get the number of implemented ports by the HBA */ 607 ahci_ctlp->ahcictl_num_implemented_ports = 608 ahci_get_num_implemented_ports( 609 ahci_ctlp->ahcictl_ports_implemented); 610 611 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 612 "hba number of implemented ports: %d", 613 ahci_ctlp->ahcictl_num_implemented_ports); 614 615 /* Check whether HBA supports 64bit DMA addressing */ 616 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 617 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 618 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 619 "hba does not support 64-bit addressing"); 620 } 621 622 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 623 != DDI_SUCCESS) { 624 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 625 instance); 626 goto err_out; 627 } 628 629 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 630 631 /* Check the pci configuration space, and set caps */ 632 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 633 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 634 instance); 635 goto err_out; 636 } 637 638 /* 639 * Disable the whole controller interrupts before adding 640 * interrupt handlers(s). 641 */ 642 ahci_disable_all_intrs(ahci_ctlp); 643 644 /* Get supported interrupt types */ 645 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 646 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 647 instance); 648 goto err_out; 649 } 650 651 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 652 "ddi_intr_get_supported_types() returned: 0x%x", 653 intr_types); 654 655 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 656 /* 657 * Try MSI first, but fall back to FIXED if failed 658 */ 659 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 660 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 661 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 662 "Using MSI interrupt type"); 663 goto intr_done; 664 } 665 666 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 667 "MSI registration failed, " 668 "trying FIXED interrupts"); 669 } 670 671 if (intr_types & DDI_INTR_TYPE_FIXED) { 672 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 673 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 674 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 675 "Using FIXED interrupt type"); 676 goto intr_done; 677 } 678 679 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 680 "FIXED interrupt registration failed"); 681 } 682 683 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 684 685 goto err_out; 686 687intr_done: 688 689 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 690 691 /* Initialize the controller mutex */ 692 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 693 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 694 695 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 696 697 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 698 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 699 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 700 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 701 } 702 703 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 704 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 705 sizeof (ahci_prdt_item_t)); 706 707 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 708 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 709 " ahci_cmd_table_size is 0x%x", 710 ahci_dma_prdt_number, ahci_cmd_table_size); 711 712 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 713 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 714 ahci_dma_prdt_number; 715 716 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 717 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 718 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 719 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 720 721 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_32BIT_DMA) { 722 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 723 0xffffffffull; 724 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 725 0xffffffffull; 726 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 727 0xffffffffull; 728 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 729 0xffffffffull; 730 } 731 732 /* Allocate the ports structure */ 733 status = ahci_alloc_ports_state(ahci_ctlp); 734 if (status != AHCI_SUCCESS) { 735 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 736 instance); 737 goto err_out; 738 } 739 740 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 741 742 /* 743 * A taskq is created for dealing with events 744 */ 745 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 746 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 747 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 748 "handle", instance); 749 goto err_out; 750 } 751 752 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 753 754 /* 755 * Initialize the controller and ports. 756 */ 757 status = ahci_initialize_controller(ahci_ctlp); 758 if (status != AHCI_SUCCESS) { 759 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 760 instance); 761 goto err_out; 762 } 763 764 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 765 766 /* Start one thread to check packet timeouts */ 767 ahci_ctlp->ahcictl_timeout_id = timeout( 768 (void (*)(void *))ahci_watchdog_handler, 769 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 770 771 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 772 773 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 774 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 775 instance); 776 goto err_out; 777 } 778 779 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 780 781 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 782 783 return (DDI_SUCCESS); 784 785err_out: 786 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 787 mutex_enter(&ahci_ctlp->ahcictl_mutex); 788 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 789 ahci_ctlp->ahcictl_timeout_id = 0; 790 mutex_exit(&ahci_ctlp->ahcictl_mutex); 791 } 792 793 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 794 ahci_uninitialize_controller(ahci_ctlp); 795 } 796 797 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 798 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 799 } 800 801 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 802 ahci_dealloc_ports_state(ahci_ctlp); 803 } 804 805 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 806 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 807 } 808 809 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 810 ahci_rem_intrs(ahci_ctlp); 811 } 812 813 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 814 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 815 } 816 817 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 818 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 819 } 820 821 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 822 ddi_soft_state_free(ahci_statep, instance); 823 } 824 825 return (DDI_FAILURE); 826} 827 828/* 829 * The detach entry point for dev_ops. 830 */ 831static int 832ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 833{ 834 ahci_ctl_t *ahci_ctlp; 835 int instance; 836 int ret; 837 838 instance = ddi_get_instance(dip); 839 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 840 841 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 842 843 switch (cmd) { 844 case DDI_DETACH: 845 846 /* disable the interrupts for an uninterrupted detach */ 847 mutex_enter(&ahci_ctlp->ahcictl_mutex); 848 ahci_disable_all_intrs(ahci_ctlp); 849 mutex_exit(&ahci_ctlp->ahcictl_mutex); 850 851 /* unregister from the sata framework. */ 852 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 853 if (ret != AHCI_SUCCESS) { 854 mutex_enter(&ahci_ctlp->ahcictl_mutex); 855 ahci_enable_all_intrs(ahci_ctlp); 856 mutex_exit(&ahci_ctlp->ahcictl_mutex); 857 return (DDI_FAILURE); 858 } 859 860 mutex_enter(&ahci_ctlp->ahcictl_mutex); 861 862 /* stop the watchdog handler */ 863 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 864 ahci_ctlp->ahcictl_timeout_id = 0; 865 866 mutex_exit(&ahci_ctlp->ahcictl_mutex); 867 868 /* uninitialize the controller */ 869 ahci_uninitialize_controller(ahci_ctlp); 870 871 /* remove the interrupts */ 872 ahci_rem_intrs(ahci_ctlp); 873 874 /* destroy the taskq */ 875 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 876 877 /* deallocate the ports structures */ 878 ahci_dealloc_ports_state(ahci_ctlp); 879 880 /* destroy mutex */ 881 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 882 883 /* teardown the pci config */ 884 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 885 886 /* remove the reg maps. */ 887 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 888 889 /* free the soft state. */ 890 ddi_soft_state_free(ahci_statep, instance); 891 892 return (DDI_SUCCESS); 893 894 case DDI_SUSPEND: 895 896 /* 897 * The steps associated with suspension must include putting 898 * the underlying device into a quiescent state so that it 899 * will not generate interrupts or modify or access memory. 900 */ 901 mutex_enter(&ahci_ctlp->ahcictl_mutex); 902 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 903 mutex_exit(&ahci_ctlp->ahcictl_mutex); 904 return (DDI_SUCCESS); 905 } 906 907 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 908 909 /* stop the watchdog handler */ 910 if (ahci_ctlp->ahcictl_timeout_id) { 911 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 912 ahci_ctlp->ahcictl_timeout_id = 0; 913 } 914 915 mutex_exit(&ahci_ctlp->ahcictl_mutex); 916 917 /* 918 * drain the taskq 919 */ 920 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 921 922 /* 923 * Disable the interrupts and stop all the ports. 924 */ 925 ahci_uninitialize_controller(ahci_ctlp); 926 927 return (DDI_SUCCESS); 928 929 default: 930 return (DDI_FAILURE); 931 } 932} 933 934/* 935 * The info entry point for dev_ops. 936 * 937 */ 938static int 939ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 940 void *arg, void **result) 941{ 942#ifndef __lock_lint 943 _NOTE(ARGUNUSED(dip)) 944#endif /* __lock_lint */ 945 946 ahci_ctl_t *ahci_ctlp; 947 int instance; 948 dev_t dev; 949 950 dev = (dev_t)arg; 951 instance = getminor(dev); 952 953 switch (infocmd) { 954 case DDI_INFO_DEVT2DEVINFO: 955 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 956 if (ahci_ctlp != NULL) { 957 *result = ahci_ctlp->ahcictl_dip; 958 return (DDI_SUCCESS); 959 } else { 960 *result = NULL; 961 return (DDI_FAILURE); 962 } 963 case DDI_INFO_DEVT2INSTANCE: 964 *(int *)result = instance; 965 break; 966 default: 967 break; 968 } 969 970 return (DDI_SUCCESS); 971} 972 973/* 974 * Registers the ahci with sata framework. 975 */ 976static int 977ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 978{ 979 struct sata_hba_tran *sata_hba_tran; 980 981 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 982 "ahci_register_sata_hba_tran enter"); 983 984 mutex_enter(&ahci_ctlp->ahcictl_mutex); 985 986 /* Allocate memory for the sata_hba_tran */ 987 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 988 989 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 990 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 991 sata_hba_tran->sata_tran_hba_dma_attr = 992 &ahci_ctlp->ahcictl_buffer_dma_attr; 993 994 /* Report the number of implemented ports */ 995 sata_hba_tran->sata_tran_hba_num_cports = 996 ahci_ctlp->ahcictl_num_implemented_ports; 997 998 /* Support ATAPI device */ 999 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1000 1001 /* Get the data transfer capability for PIO command by the HBA */ 1002 if (cap_status & AHCI_HBA_CAP_PMD) { 1003 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1004 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1005 "DRQ block data transfer for PIO command protocol"); 1006 } 1007 1008 /* 1009 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1010 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1011 * QUEUED (EXT), and SERVICE commands). Queued operations are 1012 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1013 * QUEUED commands when the HBA and device support native command 1014 * queuing(NCQ). 1015 * 1016 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1017 * CAP register of the HBA indicates NCQ is supported. 1018 * 1019 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1020 * set because the previous register content of PxCI can be re-written 1021 * in the register write. 1022 */ 1023 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1024 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1025 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1026 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1027 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1028 "Command Queuing"); 1029 } 1030 1031 /* Report the number of command slots */ 1032 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1033 1034 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1035 sata_hba_tran->sata_tran_start = ahci_tran_start; 1036 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1037 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1038 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1039#ifdef __lock_lint 1040 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1041#endif 1042 /* 1043 * When SATA framework adds support for pwrmgt the 1044 * pwrmgt_ops needs to be updated 1045 */ 1046 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1047 sata_hba_tran->sata_tran_ioctl = NULL; 1048 1049 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1050 1051 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1052 1053 /* Attach it to SATA framework */ 1054 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1055 != DDI_SUCCESS) { 1056 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1057 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1058 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1059 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1060 return (AHCI_FAILURE); 1061 } 1062 1063 return (AHCI_SUCCESS); 1064} 1065 1066/* 1067 * Unregisters the ahci with sata framework. 1068 */ 1069static int 1070ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1071{ 1072 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1073 "ahci_unregister_sata_hba_tran enter"); 1074 1075 /* Detach from the SATA framework. */ 1076 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1077 DDI_SUCCESS) { 1078 return (AHCI_FAILURE); 1079 } 1080 1081 /* Deallocate sata_hba_tran. */ 1082 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1083 sizeof (sata_hba_tran_t)); 1084 1085 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1086 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1087 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1088 1089 return (AHCI_SUCCESS); 1090} 1091 1092/* 1093 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1094 * port status registers and an attached device type via sata_device 1095 * structure. 1096 * 1097 * We return the cached information from a previous hardware probe. The 1098 * actual hardware probing itself was done either from within 1099 * ahci_initialize_controller() during the driver attach or from a phy 1100 * ready change interrupt handler. 1101 */ 1102static int 1103ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1104{ 1105 ahci_ctl_t *ahci_ctlp; 1106 ahci_port_t *ahci_portp; 1107 uint8_t cport = sd->satadev_addr.cport; 1108#if AHCI_DEBUG 1109 uint8_t pmport = sd->satadev_addr.pmport; 1110 uint8_t qual = sd->satadev_addr.qual; 1111#endif 1112 uint8_t device_type; 1113 uint32_t port_state; 1114 uint8_t port; 1115 1116 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1117 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1118 1119 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1120 "ahci_tran_probe_port enter: cport: %d, " 1121 "pmport: %d, qual: %d", cport, pmport, qual); 1122 1123 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1124 1125 mutex_enter(&ahci_portp->ahciport_mutex); 1126 1127 port_state = ahci_portp->ahciport_port_state; 1128 switch (port_state) { 1129 1130 case SATA_PSTATE_FAILED: 1131 sd->satadev_state = SATA_PSTATE_FAILED; 1132 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1133 "ahci_tran_probe_port: port %d PORT FAILED", port); 1134 goto out; 1135 1136 case SATA_PSTATE_SHUTDOWN: 1137 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1138 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1139 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1140 goto out; 1141 1142 case SATA_PSTATE_PWROFF: 1143 sd->satadev_state = SATA_PSTATE_PWROFF; 1144 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1145 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1146 goto out; 1147 1148 case SATA_PSTATE_PWRON: 1149 sd->satadev_state = SATA_PSTATE_PWRON; 1150 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1151 "ahci_tran_probe_port: port %d PORT PWRON", port); 1152 break; 1153 1154 default: 1155 sd->satadev_state = port_state; 1156 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1157 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1158 port, port_state); 1159 break; 1160 } 1161 1162 device_type = ahci_portp->ahciport_device_type; 1163 1164 switch (device_type) { 1165 1166 case SATA_DTYPE_ATADISK: 1167 sd->satadev_type = SATA_DTYPE_ATADISK; 1168 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1169 "ahci_tran_probe_port: port %d DISK found", port); 1170 break; 1171 1172 case SATA_DTYPE_ATAPICD: 1173 sd->satadev_type = SATA_DTYPE_ATAPICD; 1174 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1175 "ahci_tran_probe_port: port %d ATAPI found", port); 1176 break; 1177 1178 case SATA_DTYPE_PMULT: 1179 sd->satadev_type = SATA_DTYPE_PMULT; 1180 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1181 "ahci_tran_probe_port: port %d Port Multiplier found", 1182 port); 1183 break; 1184 1185 case SATA_DTYPE_UNKNOWN: 1186 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1187 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1188 "ahci_tran_probe_port: port %d Unknown device found", port); 1189 break; 1190 1191 default: 1192 /* we don't support any other device types */ 1193 sd->satadev_type = SATA_DTYPE_NONE; 1194 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1195 "ahci_tran_probe_port: port %d No device found", port); 1196 break; 1197 } 1198 1199out: 1200 ahci_update_sata_registers(ahci_ctlp, port, sd); 1201 mutex_exit(&ahci_portp->ahciport_mutex); 1202 1203 return (SATA_SUCCESS); 1204} 1205 1206/* 1207 * There are four operation modes in sata framework: 1208 * SATA_OPMODE_INTERRUPTS 1209 * SATA_OPMODE_POLLING 1210 * SATA_OPMODE_ASYNCH 1211 * SATA_OPMODE_SYNCH 1212 * 1213 * Their combined meanings as following: 1214 * 1215 * SATA_OPMODE_SYNCH 1216 * The command has to be completed before sata_tran_start functions returns. 1217 * Either interrupts or polling could be used - it's up to the driver. 1218 * Mode used currently for internal, sata-module initiated operations. 1219 * 1220 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1221 * It is the same as the one above. 1222 * 1223 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1224 * The command has to be completed before sata_tran_start function returns. 1225 * No interrupt used, polling only. This should be the mode used for scsi 1226 * packets with FLAG_NOINTR. 1227 * 1228 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1229 * The command may be queued (callback function specified). Interrupts could 1230 * be used. It's normal operation mode. 1231 */ 1232/* 1233 * Called by sata framework to transport a sata packet down stream. 1234 */ 1235static int 1236ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1237{ 1238 ahci_ctl_t *ahci_ctlp; 1239 ahci_port_t *ahci_portp; 1240 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1241 uint8_t port; 1242 1243 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1244 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1245 1246 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1247 "ahci_tran_start enter: cport %d satapkt 0x%p", 1248 cport, (void *)spkt); 1249 1250 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1251 1252 mutex_enter(&ahci_portp->ahciport_mutex); 1253 1254 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1255 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1256 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1257 /* 1258 * In case the targer driver would send the packet before 1259 * sata framework can have the opportunity to process those 1260 * event reports. 1261 */ 1262 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1263 spkt->satapkt_device.satadev_state = 1264 ahci_portp->ahciport_port_state; 1265 ahci_update_sata_registers(ahci_ctlp, port, 1266 &spkt->satapkt_device); 1267 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1268 "ahci_tran_start returning PORT_ERROR while " 1269 "port in FAILED/SHUTDOWN/PWROFF state: " 1270 "port: %d", port); 1271 mutex_exit(&ahci_portp->ahciport_mutex); 1272 return (SATA_TRAN_PORT_ERROR); 1273 } 1274 1275 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1276 /* 1277 * ahci_intr_phyrdy_change() may have rendered it to 1278 * SATA_DTYPE_NONE. 1279 */ 1280 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1281 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1282 spkt->satapkt_device.satadev_state = 1283 ahci_portp->ahciport_port_state; 1284 ahci_update_sata_registers(ahci_ctlp, port, 1285 &spkt->satapkt_device); 1286 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1287 "ahci_tran_start returning PORT_ERROR while " 1288 "no device attached: port: %d", port); 1289 mutex_exit(&ahci_portp->ahciport_mutex); 1290 return (SATA_TRAN_PORT_ERROR); 1291 } 1292 1293 /* 1294 * SATA HBA driver should remember that a device was reset and it 1295 * is supposed to reject any packets which do not specify either 1296 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1297 * 1298 * This is to prevent a race condition when a device was arbitrarily 1299 * reset by the HBA driver (and lost it's setting) and a target 1300 * driver sending some commands to a device before the sata framework 1301 * has a chance to restore the device setting (such as cache enable/ 1302 * disable or other resettable stuff). 1303 */ 1304 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1305 ahci_portp->ahciport_reset_in_progress = 0; 1306 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1307 "ahci_tran_start clearing the " 1308 "reset_in_progress for port: %d", port); 1309 } 1310 1311 if (ahci_portp->ahciport_reset_in_progress && 1312 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1313 ! ddi_in_panic()) { 1314 spkt->satapkt_reason = SATA_PKT_BUSY; 1315 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1316 "ahci_tran_start returning BUSY while " 1317 "reset in progress: port: %d", port); 1318 mutex_exit(&ahci_portp->ahciport_mutex); 1319 return (SATA_TRAN_BUSY); 1320 } 1321 1322 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1323 spkt->satapkt_reason = SATA_PKT_BUSY; 1324 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1325 "ahci_tran_start returning BUSY while " 1326 "mopping in progress: port: %d", port); 1327 mutex_exit(&ahci_portp->ahciport_mutex); 1328 return (SATA_TRAN_BUSY); 1329 } 1330 1331 if (spkt->satapkt_op_mode & 1332 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1333 /* 1334 * If a SYNC command to be executed in interrupt context, 1335 * bounce it back to sata module. 1336 */ 1337 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) && 1338 servicing_interrupt()) { 1339 spkt->satapkt_reason = SATA_PKT_BUSY; 1340 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1341 "ahci_tran_start returning BUSY while " 1342 "sending SYNC mode under interrupt context: " 1343 "port : %d", port); 1344 mutex_exit(&ahci_portp->ahciport_mutex); 1345 return (SATA_TRAN_BUSY); 1346 } 1347 1348 /* We need to do the sync start now */ 1349 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1350 spkt) == AHCI_FAILURE) { 1351 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1352 "return QUEUE_FULL: port %d", port); 1353 mutex_exit(&ahci_portp->ahciport_mutex); 1354 return (SATA_TRAN_QUEUE_FULL); 1355 } 1356 } else { 1357 /* Async start, using interrupt */ 1358 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1359 == AHCI_FAILURE) { 1360 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1361 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1362 "returning QUEUE_FULL: port %d", port); 1363 mutex_exit(&ahci_portp->ahciport_mutex); 1364 return (SATA_TRAN_QUEUE_FULL); 1365 } 1366 } 1367 1368 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1369 "sata tran accepted: port %d", port); 1370 1371 mutex_exit(&ahci_portp->ahciport_mutex); 1372 return (SATA_TRAN_ACCEPTED); 1373} 1374 1375/* 1376 * SATA_OPMODE_SYNCH flag is set 1377 * 1378 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1379 * without interrupt, otherwise we can still use the interrupt. 1380 * 1381 * WARNING!!! ahciport_mutex should be acquired before the function 1382 * is called. 1383 */ 1384static int 1385ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1386 uint8_t port, sata_pkt_t *spkt) 1387{ 1388 int pkt_timeout_ticks; 1389 uint32_t timeout_tags; 1390 int rval; 1391 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1392 1393 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1394 "port %d spkt 0x%p", port, spkt); 1395 1396 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1397 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1398 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1399 port, spkt)) == AHCI_FAILURE) { 1400 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1401 return (rval); 1402 } 1403 1404 pkt_timeout_ticks = 1405 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1406 1407 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1408 mutex_exit(&ahci_portp->ahciport_mutex); 1409 1410 /* Simulate the interrupt */ 1411 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1412 1413 drv_usecwait(AHCI_1MS_USECS); 1414 1415 mutex_enter(&ahci_portp->ahciport_mutex); 1416 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1417 if (pkt_timeout_ticks < 0) { 1418 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1419 "port %d satapkt 0x%p timed out\n", 1420 instance, port, (void *)spkt); 1421 timeout_tags = (0x1 << rval); 1422 mutex_exit(&ahci_portp->ahciport_mutex); 1423 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1424 port, timeout_tags); 1425 mutex_enter(&ahci_portp->ahciport_mutex); 1426 } 1427 } 1428 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1429 return (AHCI_SUCCESS); 1430 1431 } else { 1432 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1433 port, spkt)) == AHCI_FAILURE) 1434 return (rval); 1435 1436#if AHCI_DEBUG 1437 /* 1438 * Note that the driver always uses the slot 0 to deliver 1439 * REQUEST SENSE or READ LOG EXT command 1440 */ 1441 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1442 ASSERT(rval == 0); 1443#endif 1444 1445 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1446 cv_wait(&ahci_portp->ahciport_cv, 1447 &ahci_portp->ahciport_mutex); 1448 1449 return (AHCI_SUCCESS); 1450 } 1451} 1452 1453#define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1454 if (satapkt) { \ 1455 satapkt->satapkt_reason = reason; \ 1456 /* \ 1457 * We set the satapkt_reason in both sync and \ 1458 * non-sync cases. \ 1459 */ \ 1460 } \ 1461 if (satapkt && \ 1462 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1463 satapkt->satapkt_comp) { \ 1464 mutex_exit(&ahci_portp->ahciport_mutex); \ 1465 (*satapkt->satapkt_comp)(satapkt); \ 1466 mutex_enter(&ahci_portp->ahciport_mutex); \ 1467 } else { \ 1468 if (satapkt && \ 1469 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1470 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1471 cv_signal(&ahci_portp->ahciport_cv); \ 1472 } 1473 1474/* 1475 * Searches for and claims a free command slot. 1476 * 1477 * Returns: 1478 * 1479 * AHCI_FAILURE if failed 1480 * 1. if no empty slot left 1481 * 2. non-queued command requested while queued command(s) is outstanding 1482 * 3. queued command requested whild non-queued command(s) is outstanding 1483 * 4. HBA doesn't support multiple-use of command list while already a 1484 * non-queued command is oustanding 1485 * 1486 * claimed slot number if succeeded 1487 * 1488 * NOTE: it will always return slot 0 during error recovery process for 1489 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1490 * 1491 * WARNING!!! ahciport_mutex should be acquired before the function 1492 * is called. 1493 */ 1494static int 1495ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1496 ahci_port_t *ahci_portp, int command_type) 1497{ 1498 uint32_t free_slots; 1499 int slot; 1500 1501 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1502 "ahciport_pending_tags = 0x%x " 1503 "ahciport_pending_ncq_tags = 0x%x", 1504 ahci_portp->ahciport_pending_tags, 1505 ahci_portp->ahciport_pending_ncq_tags); 1506 1507 /* 1508 * According to the AHCI spec, system software is responsible to 1509 * ensure that queued and non-queued commands are not mixed in 1510 * the command list. 1511 */ 1512 if (command_type == AHCI_NON_NCQ_CMD) { 1513 /* Non-NCQ command request */ 1514 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1515 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1516 "ahci_claim_free_slot: there is still pending " 1517 "queued command(s) in the command list, " 1518 "so no available slot for the non-queued " 1519 "command"); 1520 return (AHCI_FAILURE); 1521 } 1522 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1523 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1524 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1525 "ahci_claim_free_slot: HBA cannot support multiple-" 1526 "use of the command list for non-queued commands"); 1527 return (AHCI_FAILURE); 1528 } 1529 free_slots = (~ahci_portp->ahciport_pending_tags) & 1530 AHCI_SLOT_MASK(ahci_ctlp); 1531 } else if (command_type == AHCI_NCQ_CMD) { 1532 /* NCQ command request */ 1533 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1534 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1535 "ahci_claim_free_slot: there is still pending " 1536 "non-queued command(s) in the command list, " 1537 "so no available slot for the queued command"); 1538 return (AHCI_FAILURE); 1539 } 1540 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1541 AHCI_NCQ_SLOT_MASK(ahci_portp); 1542 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1543 /* Error retrieval command request */ 1544 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1545 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1546 "SENSE or READ LOG EXT command"); 1547 slot = 0; 1548 goto out; 1549 } 1550 1551 slot = ddi_ffs(free_slots) - 1; 1552 if (slot == -1) { 1553 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1554 "ahci_claim_free_slot: no empty slots"); 1555 return (AHCI_FAILURE); 1556 } 1557 1558 /* 1559 * According to the AHCI spec, to allow a simple mechanism for the 1560 * HBA to map command list slots to queue entries, software must 1561 * match the tag number it uses to the slot it is placing the command 1562 * in. For example, if a queued command is placed in slot 5, the tag 1563 * for that command must be 5. 1564 */ 1565 if (command_type == AHCI_NCQ_CMD) { 1566 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1567 } 1568 1569 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1570 1571out: 1572 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1573 "ahci_claim_free_slot: found slot: 0x%x", slot); 1574 1575 return (slot); 1576} 1577 1578/* 1579 * Builds the Command Table for the sata packet and delivers it to controller. 1580 * 1581 * Returns: 1582 * slot number if we can obtain a slot successfully 1583 * otherwise, return AHCI_FAILURE 1584 * 1585 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1586 */ 1587static int 1588ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1589 uint8_t port, sata_pkt_t *spkt) 1590{ 1591 int cmd_slot; 1592 sata_cmd_t *scmd; 1593 ahci_fis_h2d_register_t *h2d_register_fisp; 1594 ahci_cmd_table_t *cmd_table; 1595 ahci_cmd_header_t *cmd_header; 1596 int ncookies; 1597 int i; 1598 int command_type = AHCI_NON_NCQ_CMD; 1599 int ncq_qdepth; 1600 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1601#if AHCI_DEBUG 1602 uint32_t *ptr; 1603 uint8_t *ptr2; 1604#endif 1605 1606 spkt->satapkt_reason = SATA_PKT_BUSY; 1607 1608 scmd = &spkt->satapkt_cmd; 1609 1610 /* Check if the command is a NCQ command */ 1611 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1612 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1613 command_type = AHCI_NCQ_CMD; 1614 1615 /* 1616 * When NCQ is support, system software must determine the 1617 * maximum tag allowed by the device and the HBA, and it 1618 * must use a value not beyond of the lower bound of the two. 1619 * 1620 * Sata module is going to calculate the qdepth and send 1621 * down to HBA driver via sata_cmd. 1622 */ 1623 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1624 1625 /* 1626 * At the moment, the driver doesn't support the dynamic 1627 * setting of the maximum ncq depth, and the value can be 1628 * set either during the attach or after hot-plug insertion. 1629 */ 1630 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1631 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1632 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1633 "ahci_deliver_satapkt: port %d the max tags for " 1634 "NCQ command is %d", port, ncq_qdepth); 1635 } else { 1636 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1637 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1638 " port %d the max tag for NCQ command is " 1639 "requested to change from %d to %d, at the" 1640 " moment the driver doesn't support the " 1641 "dynamic change so it's going to " 1642 "still use the previous tag value", 1643 instance, port, 1644 ahci_portp->ahciport_max_ncq_tags, 1645 ncq_qdepth); 1646 } 1647 } 1648 } 1649 1650 /* Check if the command is an error retrieval command */ 1651 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1652 command_type = AHCI_ERR_RETRI_CMD; 1653 1654 /* Check if there is an empty command slot */ 1655 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1656 if (cmd_slot == AHCI_FAILURE) { 1657 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1658 return (AHCI_FAILURE); 1659 } 1660 1661 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1662 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1663 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1664 cmd_slot, port, (void *)spkt); 1665 1666 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1667 bzero((void *)cmd_table, ahci_cmd_table_size); 1668 1669 /* For data transfer operations, it is the H2D Register FIS */ 1670 h2d_register_fisp = 1671 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1672 1673 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1674 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1675 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1676 SET_FIS_PMP(h2d_register_fisp, 1677 spkt->satapkt_device.satadev_addr.pmport); 1678 } 1679 1680 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1681 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1682 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1683 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1684 1685 switch (scmd->satacmd_addr_type) { 1686 1687 case 0: 1688 /* 1689 * satacmd_addr_type will be 0 for the commands below: 1690 * ATAPI command 1691 * SATAC_IDLE_IM 1692 * SATAC_STANDBY_IM 1693 * SATAC_DOWNLOAD_MICROCODE 1694 * SATAC_FLUSH_CACHE 1695 * SATAC_SET_FEATURES 1696 * SATAC_SMART 1697 * SATAC_ID_PACKET_DEVICE 1698 * SATAC_ID_DEVICE 1699 */ 1700 /* FALLTHRU */ 1701 1702 case ATA_ADDR_LBA: 1703 /* FALLTHRU */ 1704 1705 case ATA_ADDR_LBA28: 1706 /* LBA[7:0] */ 1707 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1708 1709 /* LBA[15:8] */ 1710 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1711 1712 /* LBA[23:16] */ 1713 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1714 1715 /* LBA [27:24] (also called dev_head) */ 1716 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1717 1718 break; 1719 1720 case ATA_ADDR_LBA48: 1721 /* LBA[7:0] */ 1722 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1723 1724 /* LBA[15:8] */ 1725 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1726 1727 /* LBA[23:16] */ 1728 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1729 1730 /* LBA [31:24] */ 1731 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1732 scmd->satacmd_lba_low_msb); 1733 1734 /* LBA [39:32] */ 1735 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1736 scmd->satacmd_lba_mid_msb); 1737 1738 /* LBA [47:40] */ 1739 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1740 scmd->satacmd_lba_high_msb); 1741 1742 /* Set dev_head */ 1743 SET_FIS_DEV_HEAD(h2d_register_fisp, 1744 scmd->satacmd_device_reg); 1745 1746 /* Set the extended sector count and features */ 1747 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1748 scmd->satacmd_sec_count_msb); 1749 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1750 scmd->satacmd_features_reg_ext); 1751 break; 1752 } 1753 1754 /* 1755 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1756 * filled into features field, and sector count 8:15 is filled into 1757 * features (exp) field. TAG is filled into sector field. 1758 */ 1759 if (command_type == AHCI_NCQ_CMD) { 1760 SET_FIS_FEATURES(h2d_register_fisp, 1761 scmd->satacmd_sec_count_lsb); 1762 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1763 scmd->satacmd_sec_count_msb); 1764 1765 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1766 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1767 } 1768 1769 ncookies = scmd->satacmd_num_dma_cookies; 1770 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1771 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1772 ncookies, ahci_dma_prdt_number); 1773 1774 ASSERT(ncookies <= ahci_dma_prdt_number); 1775 1776 /* *** now fill the scatter gather list ******* */ 1777 for (i = 0; i < ncookies; i++) { 1778 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1779 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1780 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1781 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1782 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1783 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1784 } 1785 1786 /* The ACMD field is filled in for ATAPI command */ 1787 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1788 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1789 SATA_ATAPI_MAX_CDB_LEN); 1790 } 1791 1792 /* Set Command Header in Command List */ 1793 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1794 BZERO_DESCR_INFO(cmd_header); 1795 BZERO_PRD_BYTE_COUNT(cmd_header); 1796 1797 /* Set the number of entries in the PRD table */ 1798 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1799 1800 /* Set the length of the command in the CFIS area */ 1801 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1802 1803 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1804 "sata_data_direction = 0x%x", 1805 scmd->satacmd_flags.sata_data_direction); 1806 1807 /* Set A bit if it is an ATAPI command */ 1808 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1809 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1810 1811 /* Set W bit if data is going to the device */ 1812 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1813 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1814 1815 /* 1816 * Set the prefetchable bit - this bit is only valid if the PRDTL 1817 * field is non-zero or the ATAPI 'A' bit is set in the command 1818 * header. This bit cannot be set when using native command 1819 * queuing commands or when using FIS-based switching with a Port 1820 * multiplier. 1821 */ 1822 if (command_type != AHCI_NCQ_CMD) 1823 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1824 1825 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1826 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1827 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1828 1829 /* 1830 * We are overloading satapkt_hba_driver_private with 1831 * watched_cycle count. 1832 */ 1833 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1834 1835#if AHCI_DEBUG 1836 /* Dump the command header and table */ 1837 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1838 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1839 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1840 spkt, scmd->satacmd_cmd_reg, port); 1841 ptr = (uint32_t *)cmd_header; 1842 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1843 " Command Header:%8x %8x %8x %8x", 1844 ptr[0], ptr[1], ptr[2], ptr[3]); 1845 1846 /* Dump the H2D register FIS */ 1847 ptr = (uint32_t *)h2d_register_fisp; 1848 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1849 " Command FIS: %8x %8x %8x %8x", 1850 ptr[0], ptr[1], ptr[2], ptr[3]); 1851 1852 /* Dump the ACMD register FIS */ 1853 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1854 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1855 if (ahci_debug_flags & AHCIDBG_COMMAND) 1856 ahci_log(ahci_ctlp, CE_WARN, 1857 " ATAPI command: %2x %2x %2x %2x " 1858 "%2x %2x %2x %2x", 1859 ptr2[8 * i], ptr2[8 * i + 1], 1860 ptr2[8 * i + 2], ptr2[8 * i + 3], 1861 ptr2[8 * i + 4], ptr2[8 * i + 5], 1862 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1863 1864 /* Dump the PRDT */ 1865 for (i = 0; i < ncookies; i++) { 1866 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1867 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1868 " Cookie %d: %8x %8x %8x %8x", 1869 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1870 } 1871#endif 1872 1873 (void) ddi_dma_sync( 1874 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1875 0, 1876 ahci_cmd_table_size, 1877 DDI_DMA_SYNC_FORDEV); 1878 1879 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1880 cmd_slot * sizeof (ahci_cmd_header_t), 1881 sizeof (ahci_cmd_header_t), 1882 DDI_DMA_SYNC_FORDEV); 1883 1884 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1885 if (command_type == AHCI_NCQ_CMD) { 1886 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1887 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1888 (0x1 << cmd_slot)); 1889 } 1890 1891 /* Indicate to the HBA that a command is active. */ 1892 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1893 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1894 (0x1 << cmd_slot)); 1895 1896 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1897 "exit: port %d", port); 1898 1899 return (cmd_slot); 1900} 1901 1902/* 1903 * Called by the sata framework to abort the previously sent packet(s). 1904 * 1905 * Reset device to abort commands. 1906 */ 1907static int 1908ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1909{ 1910 ahci_ctl_t *ahci_ctlp; 1911 ahci_port_t *ahci_portp; 1912 uint32_t slot_status = 0; 1913 uint32_t aborted_tags = 0; 1914 uint32_t finished_tags = 0; 1915 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1916 uint8_t port; 1917 int tmp_slot; 1918 int instance = ddi_get_instance(dip); 1919 1920 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1921 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1922 1923 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1924 "ahci_tran_abort enter: port %d", port); 1925 1926 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1927 mutex_enter(&ahci_portp->ahciport_mutex); 1928 1929 /* 1930 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1931 * commands are being mopped, therefore there is nothing else to do 1932 */ 1933 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1934 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1935 "ahci_tran_abort: port %d is in " 1936 "mopping process, so just return directly ", port); 1937 mutex_exit(&ahci_portp->ahciport_mutex); 1938 return (SATA_SUCCESS); 1939 } 1940 1941 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1942 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1943 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1944 /* 1945 * In case the targer driver would send the request before 1946 * sata framework can have the opportunity to process those 1947 * event reports. 1948 */ 1949 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1950 spkt->satapkt_device.satadev_state = 1951 ahci_portp->ahciport_port_state; 1952 ahci_update_sata_registers(ahci_ctlp, port, 1953 &spkt->satapkt_device); 1954 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1955 "ahci_tran_abort returning SATA_FAILURE while " 1956 "port in FAILED/SHUTDOWN/PWROFF state: " 1957 "port: %d", port); 1958 mutex_exit(&ahci_portp->ahciport_mutex); 1959 return (SATA_FAILURE); 1960 } 1961 1962 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1963 /* 1964 * ahci_intr_phyrdy_change() may have rendered it to 1965 * AHCI_PORT_TYPE_NODEV. 1966 */ 1967 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1968 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1969 spkt->satapkt_device.satadev_state = 1970 ahci_portp->ahciport_port_state; 1971 ahci_update_sata_registers(ahci_ctlp, port, 1972 &spkt->satapkt_device); 1973 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1974 "ahci_tran_abort returning SATA_FAILURE while " 1975 "no device attached: port: %d", port); 1976 mutex_exit(&ahci_portp->ahciport_mutex); 1977 return (SATA_FAILURE); 1978 } 1979 1980 if (flag == SATA_ABORT_ALL_PACKETS) { 1981 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1982 aborted_tags = ahci_portp->ahciport_pending_tags; 1983 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1984 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1985 1986 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 1987 instance, port); 1988 } else { 1989 aborted_tags = 0xffffffff; 1990 /* 1991 * Aborting one specific packet, first search the 1992 * ahciport_slot_pkts[] list for matching spkt. 1993 */ 1994 for (tmp_slot = 0; 1995 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1996 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1997 aborted_tags = (0x1 << tmp_slot); 1998 break; 1999 } 2000 } 2001 2002 if (aborted_tags == 0xffffffff) { 2003 /* request packet is not on the pending list */ 2004 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2005 "Cannot find the aborting pkt 0x%p on the " 2006 "pending list", (void *)spkt); 2007 ahci_update_sata_registers(ahci_ctlp, port, 2008 &spkt->satapkt_device); 2009 mutex_exit(&ahci_portp->ahciport_mutex); 2010 return (SATA_FAILURE); 2011 } 2012 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 2013 instance, port, (void *)spkt); 2014 } 2015 2016 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2017 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2018 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2019 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2020 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2021 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2022 2023 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2024 ahci_portp->ahciport_mop_in_progress++; 2025 2026 /* 2027 * To abort the packet(s), first we are trying to clear PxCMD.ST 2028 * to stop the port, and if the port can be stopped 2029 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2030 * then we just send back the aborted packet(s) with ABORTED flag 2031 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2032 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2033 * perform a COMRESET. 2034 */ 2035 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2036 ahci_portp, port, NULL, NULL); 2037 2038 /* 2039 * Compute which have finished and which need to be retried. 2040 * 2041 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2042 * minus the slot_status. The aborted_tags has to be deducted by 2043 * finished_tags since we can't possibly abort a tag which had finished 2044 * already. 2045 */ 2046 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2047 finished_tags = ahci_portp->ahciport_pending_tags & 2048 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2049 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2050 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2051 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2052 2053 aborted_tags &= ~finished_tags; 2054 2055 ahci_mop_commands(ahci_ctlp, 2056 ahci_portp, 2057 slot_status, 2058 0, /* failed tags */ 2059 0, /* timeout tags */ 2060 aborted_tags, 2061 0); /* reset tags */ 2062 2063 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2064 mutex_exit(&ahci_portp->ahciport_mutex); 2065 2066 return (SATA_SUCCESS); 2067} 2068 2069/* 2070 * Used to do device reset and reject all the pending packets on a device 2071 * during the reset operation. 2072 * 2073 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2074 */ 2075static int 2076ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2077 ahci_port_t *ahci_portp, uint8_t port) 2078{ 2079 uint32_t slot_status = 0; 2080 uint32_t reset_tags = 0; 2081 uint32_t finished_tags = 0; 2082 sata_device_t sdevice; 2083 int ret; 2084 2085 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2086 "ahci_reset_device_reject_pkts on port: %d", port); 2087 2088 /* 2089 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2090 * commands are being mopped, therefore there is nothing else to do 2091 */ 2092 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2093 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2094 "ahci_reset_device_reject_pkts: port %d is in " 2095 "mopping process, so return directly ", port); 2096 return (SATA_SUCCESS); 2097 } 2098 2099 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2100 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2101 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2102 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2103 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2104 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2105 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2106 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2107 } 2108 2109 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2110 != AHCI_SUCCESS) { 2111 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2112 "Try to do a port reset after software " 2113 "reset failed", port); 2114 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2115 if (ret != AHCI_SUCCESS) { 2116 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2117 "ahci_reset_device_reject_pkts: port %d " 2118 "failed", port); 2119 return (SATA_FAILURE); 2120 } 2121 } 2122 /* Set the reset in progress flag */ 2123 ahci_portp->ahciport_reset_in_progress = 1; 2124 2125 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2126 ahci_portp->ahciport_mop_in_progress++; 2127 2128 /* Indicate to the framework that a reset has happened */ 2129 bzero((void *)&sdevice, sizeof (sata_device_t)); 2130 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2131 sdevice.satadev_addr.pmport = 0; 2132 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2133 2134 sdevice.satadev_state = SATA_DSTATE_RESET | 2135 SATA_DSTATE_PWR_ACTIVE; 2136 mutex_exit(&ahci_portp->ahciport_mutex); 2137 sata_hba_event_notify( 2138 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2139 &sdevice, 2140 SATA_EVNT_DEVICE_RESET); 2141 mutex_enter(&ahci_portp->ahciport_mutex); 2142 2143 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2144 "port %d sending event up: SATA_EVNT_RESET", port); 2145 2146 /* Next try to mop the pending commands */ 2147 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2148 finished_tags = ahci_portp->ahciport_pending_tags & 2149 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2150 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2151 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2152 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2153 2154 reset_tags &= ~finished_tags; 2155 2156 ahci_mop_commands(ahci_ctlp, 2157 ahci_portp, 2158 slot_status, 2159 0, /* failed tags */ 2160 0, /* timeout tags */ 2161 0, /* aborted tags */ 2162 reset_tags); /* reset tags */ 2163 2164 return (SATA_SUCCESS); 2165} 2166 2167/* 2168 * Used to do port reset and reject all the pending packets on a port during 2169 * the reset operation. 2170 * 2171 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2172 */ 2173static int 2174ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2175 ahci_port_t *ahci_portp, uint8_t port) 2176{ 2177 uint32_t slot_status = 0; 2178 uint32_t reset_tags = 0; 2179 uint32_t finished_tags = 0; 2180 2181 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2182 "ahci_reset_port_reject_pkts on port: %d", port); 2183 2184 /* 2185 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2186 * commands are being mopped, therefore there is nothing else to do 2187 */ 2188 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2189 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2190 "ahci_reset_port_reject_pkts: port %d is in " 2191 "mopping process, so return directly ", port); 2192 return (SATA_SUCCESS); 2193 } 2194 2195 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2196 ahci_portp->ahciport_mop_in_progress++; 2197 2198 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2199 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2200 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2201 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2202 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2203 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2204 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2205 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2206 } 2207 2208 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2209 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2210 NULL) != AHCI_SUCCESS) 2211 return (SATA_FAILURE); 2212 2213 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2214 finished_tags = ahci_portp->ahciport_pending_tags & 2215 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2216 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2217 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2218 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2219 2220 reset_tags &= ~finished_tags; 2221 2222 ahci_mop_commands(ahci_ctlp, 2223 ahci_portp, 2224 slot_status, 2225 0, /* failed tags */ 2226 0, /* timeout tags */ 2227 0, /* aborted tags */ 2228 reset_tags); /* reset tags */ 2229 2230 return (SATA_SUCCESS); 2231} 2232 2233/* 2234 * Used to do hba reset and reject all the pending packets on all ports 2235 * during the reset operation. 2236 */ 2237static int 2238ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2239{ 2240 ahci_port_t *ahci_portp; 2241 uint32_t slot_status[AHCI_MAX_PORTS]; 2242 uint32_t reset_tags[AHCI_MAX_PORTS]; 2243 uint32_t finished_tags[AHCI_MAX_PORTS]; 2244 uint8_t port; 2245 int ret = SATA_SUCCESS; 2246 2247 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2248 "ahci_reset_hba_reject_pkts enter"); 2249 2250 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2251 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2252 continue; 2253 } 2254 2255 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2256 2257 mutex_enter(&ahci_portp->ahciport_mutex); 2258 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2259 slot_status[port] = ddi_get32( 2260 ahci_ctlp->ahcictl_ahci_acc_handle, 2261 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2262 reset_tags[port] = slot_status[port] & 2263 AHCI_SLOT_MASK(ahci_ctlp); 2264 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2265 slot_status[port] = ddi_get32( 2266 ahci_ctlp->ahcictl_ahci_acc_handle, 2267 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2268 reset_tags[port] = slot_status[port] & 2269 AHCI_NCQ_SLOT_MASK(ahci_portp); 2270 } 2271 mutex_exit(&ahci_portp->ahciport_mutex); 2272 } 2273 2274 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2275 ret = SATA_FAILURE; 2276 goto out; 2277 } 2278 2279 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2280 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2281 continue; 2282 } 2283 2284 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2285 2286 mutex_enter(&ahci_portp->ahciport_mutex); 2287 /* 2288 * To prevent recursive enter to ahci_mop_commands, we need 2289 * check AHCI_PORT_FLAG_MOPPING flag. 2290 */ 2291 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2292 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2293 "ahci_reset_hba_reject_pkts: port %d is in " 2294 "mopping process, so return directly ", port); 2295 mutex_exit(&ahci_portp->ahciport_mutex); 2296 continue; 2297 } 2298 2299 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2300 ahci_portp->ahciport_mop_in_progress++; 2301 2302 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2303 finished_tags[port] = 2304 ahci_portp->ahciport_pending_tags & 2305 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2306 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2307 finished_tags[port] = 2308 ahci_portp->ahciport_pending_ncq_tags & 2309 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2310 2311 reset_tags[port] &= ~finished_tags[port]; 2312 2313 ahci_mop_commands(ahci_ctlp, 2314 ahci_portp, 2315 slot_status[port], 2316 0, /* failed tags */ 2317 0, /* timeout tags */ 2318 0, /* aborted tags */ 2319 reset_tags[port]); /* reset tags */ 2320 mutex_exit(&ahci_portp->ahciport_mutex); 2321 } 2322out: 2323 return (ret); 2324} 2325 2326/* 2327 * Called by sata framework to reset a port(s) or device. 2328 */ 2329static int 2330ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2331{ 2332 ahci_ctl_t *ahci_ctlp; 2333 ahci_port_t *ahci_portp; 2334 uint8_t cport = sd->satadev_addr.cport; 2335 uint8_t port; 2336 int ret = SATA_SUCCESS; 2337 int instance = ddi_get_instance(dip); 2338 2339 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2340 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2341 2342 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2343 "ahci_tran_reset_port enter: cport: %d", cport); 2344 2345 switch (sd->satadev_addr.qual) { 2346 case SATA_ADDR_CPORT: 2347 /* Port reset */ 2348 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2349 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2350 "reset port", instance, port); 2351 2352 mutex_enter(&ahci_portp->ahciport_mutex); 2353 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2354 mutex_exit(&ahci_portp->ahciport_mutex); 2355 2356 break; 2357 2358 case SATA_ADDR_DCPORT: 2359 /* Device reset */ 2360 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2361 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2362 "reset device", instance, port); 2363 2364 mutex_enter(&ahci_portp->ahciport_mutex); 2365 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2366 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2367 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2368 /* 2369 * In case the targer driver would send the request 2370 * before sata framework can have the opportunity to 2371 * process those event reports. 2372 */ 2373 sd->satadev_state = ahci_portp->ahciport_port_state; 2374 ahci_update_sata_registers(ahci_ctlp, port, sd); 2375 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2376 "ahci_tran_reset_dport returning SATA_FAILURE " 2377 "while port in FAILED/SHUTDOWN/PWROFF state: " 2378 "port: %d", port); 2379 mutex_exit(&ahci_portp->ahciport_mutex); 2380 ret = SATA_FAILURE; 2381 break; 2382 } 2383 2384 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2385 /* 2386 * ahci_intr_phyrdy_change() may have rendered it to 2387 * AHCI_PORT_TYPE_NODEV. 2388 */ 2389 sd->satadev_type = SATA_DTYPE_NONE; 2390 sd->satadev_state = ahci_portp->ahciport_port_state; 2391 ahci_update_sata_registers(ahci_ctlp, port, sd); 2392 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2393 "ahci_tran_reset_dport returning SATA_FAILURE " 2394 "while no device attached: port: %d", port); 2395 mutex_exit(&ahci_portp->ahciport_mutex); 2396 ret = SATA_FAILURE; 2397 break; 2398 } 2399 2400 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2401 ahci_portp, port); 2402 mutex_exit(&ahci_portp->ahciport_mutex); 2403 break; 2404 2405 case SATA_ADDR_CNTRL: 2406 /* Reset the whole controller */ 2407 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2408 "reset the whole hba", instance, port); 2409 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2410 break; 2411 2412 case SATA_ADDR_PMPORT: 2413 case SATA_ADDR_DPMPORT: 2414 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2415 "ahci_tran_reset_dport: port multiplier will be " 2416 "supported later"); 2417 /* FALLTHRU */ 2418 default: 2419 ret = SATA_FAILURE; 2420 } 2421 2422 return (ret); 2423} 2424 2425/* 2426 * Called by sata framework to activate a port as part of hotplug. 2427 * (cfgadm -c connect satax/y) 2428 * Note: Not port-mult aware. 2429 */ 2430static int 2431ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2432{ 2433 ahci_ctl_t *ahci_ctlp; 2434 ahci_port_t *ahci_portp; 2435 uint8_t cport = satadev->satadev_addr.cport; 2436 uint8_t port; 2437 int instance = ddi_get_instance(dip); 2438 2439 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2440 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2441 2442 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2443 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2444 2445 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2446 2447 mutex_enter(&ahci_portp->ahciport_mutex); 2448 ahci_enable_port_intrs(ahci_ctlp, port); 2449 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2450 2451 /* 2452 * Reset the port so that the PHY communication would be re-established. 2453 * But this reset is an internal operation and the sata module doesn't 2454 * need to know about it. Moreover, the port with a device attached will 2455 * be started too. 2456 */ 2457 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2458 ahci_portp, port, 2459 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2460 NULL); 2461 2462 /* 2463 * Need to check the link status and device status of the port 2464 * and consider raising power if the port was in D3 state 2465 */ 2466 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2467 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2468 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2469 2470 satadev->satadev_state = ahci_portp->ahciport_port_state; 2471 2472 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2473 2474 mutex_exit(&ahci_portp->ahciport_mutex); 2475 return (SATA_SUCCESS); 2476} 2477 2478/* 2479 * Called by sata framework to deactivate a port as part of hotplug. 2480 * (cfgadm -c disconnect satax/y) 2481 * Note: Not port-mult aware. 2482 */ 2483static int 2484ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2485{ 2486 ahci_ctl_t *ahci_ctlp; 2487 ahci_port_t *ahci_portp; 2488 uint8_t cport = satadev->satadev_addr.cport; 2489 uint8_t port; 2490 uint32_t port_scontrol; 2491 int instance = ddi_get_instance(dip); 2492 2493 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2494 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2495 2496 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2497 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2498 2499 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2500 2501 mutex_enter(&ahci_portp->ahciport_mutex); 2502 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2503 instance, port); 2504 2505 /* Disable the interrupts on the port */ 2506 ahci_disable_port_intrs(ahci_ctlp, port); 2507 2508 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2509 goto phy_offline; 2510 } 2511 2512 /* First to abort all the pending commands */ 2513 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2514 2515 /* Then stop the port */ 2516 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2517 ahci_portp, port); 2518 2519 /* Next put the PHY offline */ 2520 2521phy_offline: 2522 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2523 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2524 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2525 2526 /* Update ahciport_port_state */ 2527 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2528 satadev->satadev_state = ahci_portp->ahciport_port_state; 2529 2530 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2531 2532 mutex_exit(&ahci_portp->ahciport_mutex); 2533 return (SATA_SUCCESS); 2534} 2535 2536/* 2537 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2538 * when a device is unplugged or a port is deactivated. 2539 * 2540 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2541 */ 2542static void 2543ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2544 ahci_port_t *ahci_portp, uint8_t port) 2545{ 2546 uint32_t slot_status = 0; 2547 uint32_t abort_tags = 0; 2548 2549 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2550 "ahci_reject_all_abort_pkts on port: %d", port); 2551 2552 /* 2553 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2554 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2555 * to get the error data, if yes when the device is removed, the 2556 * command needs to be aborted too. 2557 */ 2558 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2559 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2560 slot_status = 0x1; 2561 abort_tags = 0x1; 2562 goto out; 2563 } else { 2564 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2565 "ahci_reject_all_abort_pkts return directly " 2566 "port %d no needs to reject any outstanding " 2567 "commands", port); 2568 return; 2569 } 2570 } 2571 2572 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2573 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2574 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2575 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2576 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2577 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2578 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2579 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2580 } 2581 2582out: 2583 /* No need to do mop when there is no outstanding commands */ 2584 if (slot_status != 0) { 2585 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2586 ahci_portp->ahciport_mop_in_progress++; 2587 2588 ahci_mop_commands(ahci_ctlp, 2589 ahci_portp, 2590 slot_status, 2591 0, /* failed tags */ 2592 0, /* timeout tags */ 2593 abort_tags, /* aborting tags */ 2594 0); /* reset tags */ 2595 } 2596} 2597 2598#if defined(__lock_lint) 2599static int 2600ahci_selftest(dev_info_t *dip, sata_device_t *device) 2601{ 2602 return (SATA_SUCCESS); 2603} 2604#endif 2605 2606/* 2607 * Allocate the ports structure, only called by ahci_attach 2608 */ 2609static int 2610ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2611{ 2612 int port, cport = 0; 2613 2614 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2615 "ahci_alloc_ports_state enter"); 2616 2617 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2618 2619 /* Allocate structures only for the implemented ports */ 2620 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2621 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2622 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2623 "hba port %d not implemented", port); 2624 continue; 2625 } 2626 2627 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2628 ahci_ctlp->ahcictl_port_to_cport[port] = 2629 (uint8_t)cport++; 2630 2631 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2632 goto err_out; 2633 } 2634 } 2635 2636 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2637 return (AHCI_SUCCESS); 2638 2639err_out: 2640 for (port--; port >= 0; port--) { 2641 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2642 ahci_dealloc_port_state(ahci_ctlp, port); 2643 } 2644 } 2645 2646 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2647 return (AHCI_FAILURE); 2648} 2649 2650/* 2651 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2652 */ 2653static void 2654ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2655{ 2656 int port; 2657 2658 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2659 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2660 /* if this port is implemented by the HBA */ 2661 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2662 ahci_dealloc_port_state(ahci_ctlp, port); 2663 } 2664 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2665} 2666 2667/* 2668 * Initialize the controller and all ports. And then try to start the ports 2669 * if there are devices attached. 2670 * 2671 * This routine can be called from three seperate cases: DDI_ATTACH, 2672 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2673 * other two cases; device signature probing are attempted only during 2674 * DDI_ATTACH case. 2675 * 2676 * WARNING!!! Disable the whole controller's interrupts before calling and 2677 * the interrupts will be enabled upon successfully return. 2678 */ 2679static int 2680ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2681{ 2682 ahci_port_t *ahci_portp; 2683 uint32_t ghc_control; 2684 int port; 2685 2686 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2687 "ahci_initialize_controller enter"); 2688 2689 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2690 2691 /* 2692 * Indicate that system software is AHCI aware by setting 2693 * GHC.AE to 1 2694 */ 2695 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2696 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2697 2698 ghc_control |= AHCI_HBA_GHC_AE; 2699 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2700 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2701 ghc_control); 2702 2703 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2704 2705 /* Initialize the implemented ports and structures */ 2706 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2707 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2708 continue; 2709 } 2710 2711 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2712 mutex_enter(&ahci_portp->ahciport_mutex); 2713 2714 /* 2715 * Ensure that the controller is not in the running state 2716 * by checking every implemented port's PxCMD register 2717 */ 2718 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2719 != AHCI_SUCCESS) { 2720 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2721 "ahci_initialize_controller: failed to " 2722 "initialize port %d", port); 2723 /* 2724 * Set the port state to SATA_PSTATE_FAILED if 2725 * failed to initialize it. 2726 */ 2727 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2728 } 2729 2730 mutex_exit(&ahci_portp->ahciport_mutex); 2731 } 2732 2733 /* Enable the whole controller interrupts */ 2734 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2735 ahci_enable_all_intrs(ahci_ctlp); 2736 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2737 2738 return (AHCI_SUCCESS); 2739} 2740 2741/* 2742 * Reverse of ahci_initialize_controller() 2743 * 2744 * We only need to stop the ports and disable the interrupt. 2745 */ 2746static void 2747ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2748{ 2749 ahci_port_t *ahci_portp; 2750 int port; 2751 2752 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2753 "ahci_uninitialize_controller enter"); 2754 2755 /* disable all the interrupts. */ 2756 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2757 ahci_disable_all_intrs(ahci_ctlp); 2758 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2759 2760 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2761 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2762 continue; 2763 } 2764 2765 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2766 2767 /* Stop the port by clearing PxCMD.ST */ 2768 mutex_enter(&ahci_portp->ahciport_mutex); 2769 2770 /* 2771 * Here we must disable the port interrupt because 2772 * ahci_disable_all_intrs only clear GHC.IE, and IS 2773 * register will be still set if PxIE is enabled. 2774 * When ahci shares one IRQ with other drivers, the 2775 * intr handler may claim the intr mistakenly. 2776 */ 2777 ahci_disable_port_intrs(ahci_ctlp, port); 2778 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2779 ahci_portp, port); 2780 mutex_exit(&ahci_portp->ahciport_mutex); 2781 } 2782} 2783 2784/* 2785 * The routine is to initialize the port. First put the port in NOTRunning 2786 * state, then enable port interrupt and clear Serror register. And under 2787 * AHCI_ATTACH case, find device signature and then try to start the port. 2788 * 2789 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2790 */ 2791static int 2792ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2793 ahci_port_t *ahci_portp, uint8_t port) 2794{ 2795 uint32_t port_cmd_status; 2796 2797 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2798 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2799 2800 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2801 "ahci_initialize_port: port %d " 2802 "port_cmd_status = 0x%x", port, port_cmd_status); 2803 /* 2804 * Check whether the port is in NotRunning state, if not, 2805 * put the port in NotRunning state 2806 */ 2807 if (!(port_cmd_status & 2808 (AHCI_CMD_STATUS_ST | 2809 AHCI_CMD_STATUS_CR | 2810 AHCI_CMD_STATUS_FRE | 2811 AHCI_CMD_STATUS_FR))) { 2812 2813 goto next; 2814 } 2815 2816 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2817 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2818 return (AHCI_FAILURE); 2819 2820next: 2821 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2822 "port %d is in NotRunning state now", port); 2823 2824 /* 2825 * At the time being, only probe ports/devices and get the types of 2826 * attached devices during DDI_ATTACH. In fact, the device can be 2827 * changed during power state changes, but at the time being, we 2828 * don't support the situation. 2829 */ 2830 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2831 /* Try to get the device signature */ 2832 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2833 } else { 2834 2835 /* 2836 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2837 * and PxFBU registers in case these registers were cleared 2838 * during the suspend. 2839 */ 2840 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2841 "ahci_initialize_port: port %d " 2842 "reset the port during resume", port); 2843 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2844 2845 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2846 "ahci_initialize_port: port %d " 2847 "set PxCLB, PxCLBU, PxFB and PxFBU " 2848 "during resume", port); 2849 2850 /* Config Port Received FIS Base Address */ 2851 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2852 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2853 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2854 2855 /* Config Port Command List Base Address */ 2856 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2857 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2858 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2859 } 2860 2861 /* Disable the interface power management */ 2862 ahci_disable_interface_pm(ahci_ctlp, port); 2863 2864 /* Return directly if no device connected */ 2865 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2866 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2867 "No device connected to port %d", port); 2868 goto out; 2869 } 2870 2871 /* Try to start the port */ 2872 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2873 != AHCI_SUCCESS) { 2874 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2875 "failed to start port %d", port); 2876 return (AHCI_FAILURE); 2877 } 2878out: 2879 /* Enable port interrupts */ 2880 ahci_enable_port_intrs(ahci_ctlp, port); 2881 2882 return (AHCI_SUCCESS); 2883} 2884 2885/* 2886 * Figure out which chip and set flag for VT8251; Also check 2887 * the power management capability. 2888 */ 2889static int 2890ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2891{ 2892 ushort_t venid, devid; 2893 ushort_t caps_ptr, cap_count, cap; 2894#if AHCI_DEBUG 2895 ushort_t pmcap, pmcsr; 2896#endif 2897 uint8_t revision; 2898 2899 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2900 PCI_CONF_VENID); 2901 2902 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2903 PCI_CONF_DEVID); 2904 2905 /* 2906 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2907 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2908 * which is a bug and was fixed after 0x00 revision id controllers. 2909 * 2910 * Moreover, VT8251 cannot use multiple command slots in the command 2911 * list for non-queued commands because the previous register content 2912 * of PxCI can be re-written in the register write, so a flag will be 2913 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2914 */ 2915 if (venid == VIA_VENID) { 2916 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2917 PCI_CONF_REVID); 2918 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2919 "revision id = 0x%x", revision); 2920 if (revision == 0x00) { 2921 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2922 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2923 "change ddi_attr_align to 0x4"); 2924 } 2925 2926 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2927 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2928 "VT8251 cannot use multiple command lists for " 2929 "non-queued commands"); 2930 } 2931 2932 /* 2933 * ATI SB600 (1002,4380) doesn't support 64-bit DMA addressing though it 2934 * declares support, so we need to set AHCI_CAP_32BIT_DMA flag to force 2935 * 32-bit DMA. 2936 */ 2937 if (venid == 0x1002 && devid == 0x4380) { 2938 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2939 "ATI SB600 cannot do 64-bit DMA though CAP indicates " 2940 "support, so force it to use 32-bit DMA"); 2941 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 2942 } 2943 2944 /* 2945 * Check if capabilities list is supported and if so, 2946 * get initial capabilities pointer and clear bits 0,1. 2947 */ 2948 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2949 PCI_CONF_STAT) & PCI_STAT_CAP) { 2950 caps_ptr = P2ALIGN(pci_config_get8( 2951 ahci_ctlp->ahcictl_pci_conf_handle, 2952 PCI_CONF_CAP_PTR), 4); 2953 } else { 2954 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2955 } 2956 2957 /* 2958 * Walk capabilities if supported. 2959 */ 2960 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2961 2962 /* 2963 * Check that we haven't exceeded the maximum number of 2964 * capabilities and that the pointer is in a valid range. 2965 */ 2966 if (++cap_count > PCI_CAP_MAX_PTR) { 2967 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2968 "too many device capabilities"); 2969 return (AHCI_FAILURE); 2970 } 2971 if (caps_ptr < PCI_CAP_PTR_OFF) { 2972 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2973 "capabilities pointer 0x%x out of range", 2974 caps_ptr); 2975 return (AHCI_FAILURE); 2976 } 2977 2978 /* 2979 * Get next capability and check that it is valid. 2980 * For now, we only support power management. 2981 */ 2982 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2983 caps_ptr); 2984 switch (cap) { 2985 case PCI_CAP_ID_PM: 2986 2987 /* power management supported */ 2988 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 2989 2990 /* Save PMCSR offset */ 2991 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 2992 2993#if AHCI_DEBUG 2994 pmcap = pci_config_get16( 2995 ahci_ctlp->ahcictl_pci_conf_handle, 2996 caps_ptr + PCI_PMCAP); 2997 pmcsr = pci_config_get16( 2998 ahci_ctlp->ahcictl_pci_conf_handle, 2999 ahci_ctlp->ahcictl_pmcsr_offset); 3000 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 3001 "Power Management capability found PCI_PMCAP " 3002 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 3003 if ((pmcap & 0x3) == 0x3) 3004 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3005 "PCI Power Management Interface " 3006 "spec 1.2 compliant"); 3007#endif 3008 break; 3009 3010 case PCI_CAP_ID_MSI: 3011 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 3012 break; 3013 3014 case PCI_CAP_ID_PCIX: 3015 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3016 "PCI-X capability found"); 3017 break; 3018 3019 case PCI_CAP_ID_PCI_E: 3020 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3021 "PCI Express capability found"); 3022 break; 3023 3024 case PCI_CAP_ID_MSI_X: 3025 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3026 "MSI-X capability found"); 3027 break; 3028 3029 case PCI_CAP_ID_SATA: 3030 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3031 "SATA capability found"); 3032 break; 3033 3034 case PCI_CAP_ID_VS: 3035 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3036 "Vendor Specific capability found"); 3037 break; 3038 3039 default: 3040 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3041 "unrecognized capability 0x%x", cap); 3042 break; 3043 } 3044 3045 /* 3046 * Get next capabilities pointer and clear bits 0,1. 3047 */ 3048 caps_ptr = P2ALIGN(pci_config_get8( 3049 ahci_ctlp->ahcictl_pci_conf_handle, 3050 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3051 } 3052 3053 return (AHCI_SUCCESS); 3054} 3055 3056/* 3057 * AHCI device reset ...; a single device on one of the ports is reset, 3058 * but the HBA and physical communication remain intact. This is the 3059 * least intrusive. 3060 * 3061 * When issuing a software reset sequence, there should not be other 3062 * commands in the command list, so we will first clear and then re-set 3063 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3064 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3065 * cleared unless command list override (PxCMD.CLO) is supported. 3066 * 3067 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3068 * set before the function is called. 3069 */ 3070static int 3071ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3072 uint8_t port) 3073{ 3074 ahci_fis_h2d_register_t *h2d_register_fisp; 3075 ahci_cmd_table_t *cmd_table; 3076 ahci_cmd_header_t *cmd_header; 3077 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3078 int slot, loop_count; 3079 3080 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3081 "Port %d device resetting", port); 3082 3083 /* First clear PxCMD.ST */ 3084 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 3085 ahci_portp, port); 3086 3087 /* Then re-set PxCMD.ST */ 3088 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 3089 3090 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3091 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3092 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3093 3094 if (port_task_file & AHCI_TFD_STS_BSY || 3095 port_task_file & AHCI_TFD_STS_DRQ) { 3096 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3097 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3098 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3099 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3100 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3101 "but PxCMD.CLO isn't supported, so a port " 3102 "reset is needed."); 3103 return (AHCI_FAILURE); 3104 } 3105 } 3106 3107 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3108 if (slot == AHCI_FAILURE) { 3109 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3110 "ahci_software_reset: no free slot"); 3111 return (AHCI_FAILURE); 3112 } 3113 3114 /* Now send the first H2D Register FIS with SRST set to 1 */ 3115 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3116 bzero((void *)cmd_table, ahci_cmd_table_size); 3117 3118 h2d_register_fisp = 3119 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3120 3121 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3122 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3123 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3124 3125 /* Set Command Header in Command List */ 3126 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3127 BZERO_DESCR_INFO(cmd_header); 3128 BZERO_PRD_BYTE_COUNT(cmd_header); 3129 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3130 3131 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3132 SET_RESET(cmd_header, 1); 3133 SET_WRITE(cmd_header, 1); 3134 3135 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3136 0, 3137 ahci_cmd_table_size, 3138 DDI_DMA_SYNC_FORDEV); 3139 3140 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3141 slot * sizeof (ahci_cmd_header_t), 3142 sizeof (ahci_cmd_header_t), 3143 DDI_DMA_SYNC_FORDEV); 3144 3145 /* Indicate to the HBA that a command is active. */ 3146 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3147 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3148 (0x1 << slot)); 3149 3150 loop_count = 0; 3151 3152 /* Loop till the first command is finished */ 3153 do { 3154 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3155 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3156 3157 /* We are effectively timing out after 1 sec. */ 3158 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3159 break; 3160 } 3161 /* Wait for 10 millisec */ 3162 delay(AHCI_10MS_TICKS); 3163 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3164 3165 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3166 "ahci_software_reset: 1st loop count: %d, " 3167 "port_cmd_issue = 0x%x, slot = 0x%x", 3168 loop_count, port_cmd_issue, slot); 3169 3170 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3171 3172 /* Now send the second H2D Register FIS with SRST cleard to zero */ 3173 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3174 bzero((void *)cmd_table, ahci_cmd_table_size); 3175 3176 h2d_register_fisp = 3177 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3178 3179 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3180 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3181 3182 /* Set Command Header in Command List */ 3183 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3184 BZERO_DESCR_INFO(cmd_header); 3185 BZERO_PRD_BYTE_COUNT(cmd_header); 3186 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3187 3188 SET_WRITE(cmd_header, 1); 3189 3190 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3191 0, 3192 ahci_cmd_table_size, 3193 DDI_DMA_SYNC_FORDEV); 3194 3195 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3196 slot * sizeof (ahci_cmd_header_t), 3197 sizeof (ahci_cmd_header_t), 3198 DDI_DMA_SYNC_FORDEV); 3199 3200 /* Indicate to the HBA that a command is active. */ 3201 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3202 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3203 (0x1 << slot)); 3204 3205 loop_count = 0; 3206 3207 /* Loop till the second command is finished */ 3208 do { 3209 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3210 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3211 3212 /* We are effectively timing out after 1 sec. */ 3213 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3214 break; 3215 } 3216 /* Wait for 10 millisec */ 3217 delay(AHCI_10MS_TICKS); 3218 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3219 3220 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3221 "ahci_software_reset: 2nd loop count: %d, " 3222 "port_cmd_issue = 0x%x, slot = 0x%x", 3223 loop_count, port_cmd_issue, slot); 3224 3225 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3226 3227 return (AHCI_SUCCESS); 3228} 3229 3230/* 3231 * AHCI port reset ...; the physical communication between the HBA and device 3232 * on a port are disabled. This is more intrusive. 3233 * 3234 * When an HBA or port reset occurs, Phy communication is going to 3235 * be re-established with the device through a COMRESET followed by the 3236 * normal out-of-band communication sequence defined in Serial ATA. AT 3237 * the end of reset, the device, if working properly, will send a D2H 3238 * Register FIS, which contains the device signature. When the HBA receives 3239 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3240 * the PxSIG register with the signature. 3241 * 3242 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3243 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3244 * AHCI 1.0 spec. 3245 */ 3246/* 3247 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3248 * cleared before the function is called. 3249 */ 3250static int 3251ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3252{ 3253 uint32_t cap_status, port_cmd_status; 3254 uint32_t port_scontrol, port_sstatus; 3255 uint32_t port_intr_status, port_task_file; 3256#if AHCI_DEBUG 3257 uint32_t port_signature; 3258#endif 3259 int loop_count; 3260 int rval = AHCI_SUCCESS; 3261 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3262 3263 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3264 "Port %d port resetting...", port); 3265 ahci_portp->ahciport_port_state = 0; 3266 3267 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3268 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3269 3270 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3271 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3272 3273 if (cap_status & AHCI_HBA_CAP_SSS) { 3274 /* 3275 * HBA support staggered spin-up, if the port has 3276 * not spin up yet, then force it to do spin-up 3277 */ 3278 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3279 if (!(ahci_portp->ahciport_flags 3280 & AHCI_PORT_FLAG_SPINUP)) { 3281 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3282 "Port %d PxCMD.SUD is zero, force " 3283 "it to do spin-up", port); 3284 ahci_portp->ahciport_flags |= 3285 AHCI_PORT_FLAG_SPINUP; 3286 } 3287 } 3288 } else { 3289 /* 3290 * HBA doesn't support stagger spin-up, force it 3291 * to do normal COMRESET 3292 */ 3293 if (ahci_portp->ahciport_flags & 3294 AHCI_PORT_FLAG_SPINUP) { 3295 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3296 "HBA does not support staggered spin-up " 3297 "force it to do normal COMRESET"); 3298 ahci_portp->ahciport_flags &= 3299 ~AHCI_PORT_FLAG_SPINUP; 3300 } 3301 } 3302 3303 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3304 /* Do normal COMRESET */ 3305 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3306 "ahci_port_reset: do normal COMRESET", port); 3307 3308 /* 3309 * According to the spec, SUD bit should be set here, 3310 * but JMicron JMB363 doesn't follow it, so remove 3311 * the assertion, and just print a debug message. 3312 */ 3313#if AHCI_DEBUG 3314 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3315 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3316 "port %d SUD bit not set", port) 3317#endif 3318 3319 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3320 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3321 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3322 3323 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3324 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3325 port_scontrol); 3326 3327 /* Enable PxCMD.FRE to read device */ 3328 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3329 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3330 port_cmd_status|AHCI_CMD_STATUS_FRE); 3331 3332 /* 3333 * Give time for COMRESET to percolate, according to the AHCI 3334 * spec, software shall wait at least 1 millisecond before 3335 * clearing PxSCTL.DET 3336 */ 3337 delay(AHCI_1MS_TICKS*2); 3338 3339 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3340 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3341 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3342 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3343 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3344 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3345 port_scontrol); 3346 } else { 3347 /* Do staggered spin-up */ 3348 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3349 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3350 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3351 3352 /* PxSCTL.DET must be 0 */ 3353 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3354 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3355 port_scontrol); 3356 3357 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3358 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3359 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3360 port_cmd_status); 3361 3362 /* 0 -> 1 edge */ 3363 delay(AHCI_1MS_TICKS*2); 3364 3365 /* Set PxCMD.SUD to 1 */ 3366 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3367 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3368 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3369 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3370 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3371 port_cmd_status); 3372 3373 /* Enable PxCMD.FRE to read device */ 3374 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3375 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3376 port_cmd_status|AHCI_CMD_STATUS_FRE); 3377 } 3378 3379 /* 3380 * The port enters P:StartComm state, and HBA tells link layer to 3381 * start communication, which involves sending COMRESET to device. 3382 * And the HBA resets PxTFD.STS to 7Fh. 3383 * 3384 * When a COMINIT is received from the device, then the port enters 3385 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3386 * PxSSTS.DET to 1h to indicate a device is detected but communication 3387 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3388 * a COMINIT has been received. 3389 */ 3390 /* 3391 * The DET field is valid only if IPM field indicates 3392 * that the interface is in active state. 3393 */ 3394 loop_count = 0; 3395 do { 3396 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3397 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3398 3399 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3400 /* 3401 * If the interface is not active, the DET field 3402 * is considered not accurate. So we want to 3403 * continue looping. 3404 */ 3405 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3406 } 3407 3408 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3409 /* 3410 * We are effectively timing out after 0.1 sec. 3411 */ 3412 break; 3413 } 3414 3415 /* Wait for 10 millisec */ 3416 delay(AHCI_10MS_TICKS); 3417 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3418 3419 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3420 "ahci_port_reset: 1st loop count: %d, " 3421 "port_sstatus = 0x%x port %d", 3422 loop_count, port_sstatus, port); 3423 3424 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3425 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3426 /* 3427 * Either the port is not active or there 3428 * is no device present. 3429 */ 3430 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3431 goto out; 3432 } 3433 3434 /* Now we can make sure there is a device connected to the port */ 3435 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3436 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3437 3438 /* a COMINIT signal is supposed to be received */ 3439 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3440 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3441 "COMINIT signal from the device not received", 3442 instance, port); 3443 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3444 rval = AHCI_FAILURE; 3445 goto out; 3446 } 3447 3448 /* 3449 * According to the spec, when PxSCTL.DET is set to 0h, upon 3450 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3451 * shall be set to '1' by the HBA. 3452 * 3453 * However, we found JMicron JMB363 doesn't follow this, so 3454 * remove this check, and just print a debug message. 3455 */ 3456#if AHCI_DEBUG 3457 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3458 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3459 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3460 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3461 "port %d BSY bit is not set after COMINIT signal " 3462 "is received", port); 3463 } 3464#endif 3465 3466 /* 3467 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3468 * the D2H FIS received by HBA. 3469 */ 3470 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3471 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3472 SERROR_EXCHANGED_ERR); 3473 3474 /* 3475 * Next check whether COMRESET is completed successfully 3476 */ 3477 loop_count = 0; 3478 do { 3479 port_task_file = 3480 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3481 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3482 3483 /* 3484 * The Error bit '1' means COMRESET is finished successfully 3485 * The device hardware has been initialized and the power-up 3486 * diagnostics successfully completed. 3487 */ 3488 if (((port_task_file & AHCI_TFD_ERR_MASK) 3489 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3490#if AHCI_DEBUG 3491 port_signature = ddi_get32( 3492 ahci_ctlp->ahcictl_ahci_acc_handle, 3493 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3494 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3495 "COMRESET success, D2H register FIS " 3496 "post to received FIS structure " 3497 "port %d signature = 0x%x", 3498 port, port_signature); 3499#endif 3500 goto out_check; 3501 } 3502 3503 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3504 /* 3505 * We are effectively timing out after 11 sec. 3506 */ 3507 break; 3508 } 3509 3510 /* Wait for 10 millisec */ 3511 delay(AHCI_10MS_TICKS); 3512 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3513 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3514 3515 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3516 "count: %d, port_task_file = 0x%x port %d", 3517 loop_count, port_task_file, port); 3518 3519 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d the device hardware " 3520 "has been initialized and the power-up diagnostics failed", 3521 instance, port); 3522 3523 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3524 rval = AHCI_FAILURE; 3525 3526out: 3527 /* Clear port serror register for the port */ 3528 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3529 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3530 AHCI_SERROR_CLEAR_ALL); 3531 3532 return (rval); 3533 3534out_check: 3535 /* 3536 * Check device status, if keep busy or COMRESET error 3537 * do device reset to patch some SATA disks' issue 3538 * 3539 * For VT8251, sometimes need to do the device reset 3540 */ 3541 if ((port_task_file & AHCI_TFD_STS_BSY) || 3542 (port_task_file & AHCI_TFD_STS_DRQ)) { 3543 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3544 "need to do device reset", port); 3545 3546 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3547 3548 port_task_file = 3549 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3550 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3551 3552 if (port_task_file & AHCI_TFD_STS_BSY || 3553 port_task_file & AHCI_TFD_STS_DRQ) { 3554 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset: port %d " 3555 "BSY/DRQ still set after device reset " 3556 "port_task_file = 0x%x", instance, 3557 port, port_task_file); 3558 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3559 rval = AHCI_FAILURE; 3560 } 3561 } 3562 3563 goto out; 3564} 3565 3566/* 3567 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3568 * This is the most intrusive. 3569 * 3570 * When an HBA reset occurs, Phy communication will be re-established with 3571 * the device through a COMRESET followed by the normal out-of-band 3572 * communication sequence defined in Serial ATA. AT the end of reset, the 3573 * device, if working properly, will send a D2H Register FIS, which contains 3574 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3575 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3576 * signature. 3577 * 3578 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3579 */ 3580static int 3581ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3582{ 3583 ahci_port_t *ahci_portp; 3584 uint32_t ghc_control; 3585 uint8_t port; 3586 int loop_count; 3587 int rval = AHCI_SUCCESS; 3588 3589 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3590 3591 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3592 3593 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3594 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3595 3596 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3597 ghc_control |= AHCI_HBA_GHC_HR; 3598 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3599 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3600 3601 /* 3602 * Wait until HBA Reset complete or timeout 3603 */ 3604 loop_count = 0; 3605 do { 3606 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3607 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3608 3609 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3610 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3611 "ahci hba reset is timing out, " 3612 "ghc_control = 0x%x", ghc_control); 3613 /* We are effectively timing out after 1 sec. */ 3614 break; 3615 } 3616 3617 /* Wait for 10 millisec */ 3618 delay(AHCI_10MS_TICKS); 3619 } while (ghc_control & AHCI_HBA_GHC_HR); 3620 3621 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3622 "ahci_hba_reset: 1st loop count: %d, " 3623 "ghc_control = 0x%x", loop_count, ghc_control); 3624 3625 if (ghc_control & AHCI_HBA_GHC_HR) { 3626 /* The hba is not reset for some reasons */ 3627 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3628 "hba reset failed: HBA in a hung or locked state"); 3629 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3630 return (AHCI_FAILURE); 3631 } 3632 3633 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3634 /* Only check implemented ports */ 3635 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3636 continue; 3637 } 3638 3639 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3640 mutex_enter(&ahci_portp->ahciport_mutex); 3641 3642 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3643 != AHCI_SUCCESS) { 3644 rval = AHCI_FAILURE; 3645 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3646 "ahci_hba_reset: port %d failed", port); 3647 } 3648 3649 mutex_exit(&ahci_portp->ahciport_mutex); 3650 } 3651 3652 /* 3653 * Indicate that system software is AHCI aware by setting 3654 * GHC.AE to 1 3655 */ 3656 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3657 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3658 3659 ghc_control |= AHCI_HBA_GHC_AE; 3660 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3661 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3662 3663 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3664 3665 return (rval); 3666} 3667 3668/* 3669 * This routine is only called from AHCI_ATTACH or phyrdy change 3670 * case. It first calls port reset to initialize port, probe port and probe 3671 * device, then try to read PxSIG register to find the type of device 3672 * attached to the port. 3673 * 3674 * WARNING!!! ahciport_mutex should be acquired before the function 3675 * is called. And the port interrupt is disabled. 3676 */ 3677static void 3678ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3679 ahci_port_t *ahci_portp, uint8_t port) 3680{ 3681 uint32_t signature; 3682 3683 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3684 "ahci_find_dev_signature enter: port %d", port); 3685 3686 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3687 3688 /* Call port reset to check link status and get device signature */ 3689 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3690 3691 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3692 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3693 "ahci_find_dev_signature: No device is found " 3694 "at port %d", port); 3695 return; 3696 } 3697 3698 /* Check the port state */ 3699 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3700 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3701 "ahci_find_dev_signature: port %d state 0x%x", 3702 port, ahci_portp->ahciport_port_state); 3703 return; 3704 } 3705 3706 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3707 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3708 3709 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3710 "ahci_find_dev_signature: port %d signature = 0x%x", 3711 port, signature); 3712 3713 switch (signature) { 3714 3715 case AHCI_SIGNATURE_DISK: 3716 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3717 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3718 "Disk is found at port: %d", port); 3719 break; 3720 3721 case AHCI_SIGNATURE_ATAPI: 3722 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3723 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3724 "ATAPI device is found at port: %d", port); 3725 break; 3726 3727 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3728 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3729 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3730 "Port Multiplier is found at port: %d", port); 3731 break; 3732 3733 default: 3734 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3735 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3736 "Unknown device is found at port: %d", port); 3737 } 3738} 3739 3740/* 3741 * According to the spec, to reliably detect hot plug removals, software 3742 * must disable interface power management. Software should perform the 3743 * following initialization on a port after a device is attached: 3744 * Set PxSCTL.IPM to 3h to disable interface state transitions 3745 * Set PxCMD.ALPE to '0' to disable aggressive power management 3746 * Disable device initiated interface power management by SET FEATURE 3747 * 3748 * We can ignore the last item because by default the feature is disabled 3749 */ 3750static void 3751ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3752{ 3753 uint32_t port_scontrol, port_cmd_status; 3754 3755 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3756 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3757 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3758 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3759 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3760 3761 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3762 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3763 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3764 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3765 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3766} 3767 3768/* 3769 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3770 * to 1, then set it firstly. 3771 * 3772 * Each port contains two major DMA engines. One DMA engine walks through 3773 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3774 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3775 * 3776 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3777 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3778 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3779 * 3780 * Software shall not set PxCMD.ST to '1' unless a functional device is 3781 * present on the port(as determined by PxTFD.STS.BSY = '0', 3782 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3783 * 3784 * WARNING!!! ahciport_mutex should be acquired before the function 3785 * is called. 3786 */ 3787static int 3788ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3789{ 3790 uint32_t port_cmd_status; 3791 3792 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3793 3794 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3795 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3796 "the state for port %d is 0x%x", 3797 port, ahci_portp->ahciport_port_state); 3798 return (AHCI_FAILURE); 3799 } 3800 3801 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3802 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3803 "no device is attached at port %d", port); 3804 return (AHCI_FAILURE); 3805 } 3806 3807 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3808 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3809 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3810 3811 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3812 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3813 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3814 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3815 port_cmd_status); 3816 } 3817 3818 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3819 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3820 3821 port_cmd_status |= AHCI_CMD_STATUS_ST; 3822 3823 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3824 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3825 port_cmd_status); 3826 3827 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3828 3829 return (AHCI_SUCCESS); 3830} 3831 3832/* 3833 * Allocate the ahci_port_t including Received FIS and Command List. 3834 * The argument - port is the physical port number, and not logical 3835 * port number seen by the SATA framework. 3836 * 3837 * WARNING!!! ahcictl_mutex should be acquired before the function 3838 * is called. 3839 */ 3840static int 3841ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3842{ 3843 ahci_port_t *ahci_portp; 3844 3845 ahci_portp = 3846 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3847 3848 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3849 ahci_portp->ahciport_port_num = port; 3850 3851 /* Intialize the port condition variable */ 3852 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3853 3854 /* Initialize the port mutex */ 3855 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3856 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3857 3858 mutex_enter(&ahci_portp->ahciport_mutex); 3859 3860 /* 3861 * Allocate memory for received FIS structure and 3862 * command list for this port 3863 */ 3864 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3865 goto err_case1; 3866 } 3867 3868 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3869 goto err_case2; 3870 } 3871 3872 ahci_portp->ahciport_event_args = 3873 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3874 3875 if (ahci_portp->ahciport_event_args == NULL) 3876 goto err_case3; 3877 3878 mutex_exit(&ahci_portp->ahciport_mutex); 3879 3880 return (AHCI_SUCCESS); 3881 3882err_case3: 3883 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3884 3885err_case2: 3886 ahci_dealloc_rcvd_fis(ahci_portp); 3887 3888err_case1: 3889 mutex_exit(&ahci_portp->ahciport_mutex); 3890 mutex_destroy(&ahci_portp->ahciport_mutex); 3891 cv_destroy(&ahci_portp->ahciport_cv); 3892 3893 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3894 3895 return (AHCI_FAILURE); 3896} 3897 3898/* 3899 * Reverse of ahci_dealloc_port_state(). 3900 * 3901 * WARNING!!! ahcictl_mutex should be acquired before the function 3902 * is called. 3903 */ 3904static void 3905ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3906{ 3907 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3908 3909 ASSERT(ahci_portp != NULL); 3910 3911 mutex_enter(&ahci_portp->ahciport_mutex); 3912 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3913 ahci_portp->ahciport_event_args = NULL; 3914 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3915 ahci_dealloc_rcvd_fis(ahci_portp); 3916 mutex_exit(&ahci_portp->ahciport_mutex); 3917 3918 mutex_destroy(&ahci_portp->ahciport_mutex); 3919 cv_destroy(&ahci_portp->ahciport_cv); 3920 3921 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3922 3923 ahci_ctlp->ahcictl_ports[port] = NULL; 3924} 3925 3926/* 3927 * Allocates memory for the Received FIS Structure 3928 * 3929 * WARNING!!! ahciport_mutex should be acquired before the function 3930 * is called. 3931 */ 3932static int 3933ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3934 uint8_t port) 3935{ 3936 size_t rcvd_fis_size; 3937 size_t ret_len; 3938 uint_t cookie_count; 3939 3940 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3941 3942 /* allocate rcvd FIS dma handle. */ 3943 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3944 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3945 DDI_DMA_SLEEP, 3946 NULL, 3947 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3948 DDI_SUCCESS) { 3949 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3950 "rcvd FIS dma handle alloc failed"); 3951 3952 return (AHCI_FAILURE); 3953 } 3954 3955 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3956 rcvd_fis_size, 3957 &accattr, 3958 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3959 DDI_DMA_SLEEP, 3960 NULL, 3961 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3962 &ret_len, 3963 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3964 3965 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3966 "rcvd FIS dma mem alloc fail"); 3967 /* error.. free the dma handle. */ 3968 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3969 return (AHCI_FAILURE); 3970 } 3971 3972 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3973 NULL, 3974 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3975 rcvd_fis_size, 3976 DDI_DMA_CONSISTENT, 3977 DDI_DMA_SLEEP, 3978 NULL, 3979 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 3980 &cookie_count) != DDI_DMA_MAPPED) { 3981 3982 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3983 "rcvd FIS dma handle bind fail"); 3984 /* error.. free the dma handle & free the memory. */ 3985 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3986 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3987 return (AHCI_FAILURE); 3988 } 3989 3990 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3991 3992 /* Config Port Received FIS Base Address */ 3993 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3994 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3995 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3996 3997 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3998 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3999 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4000 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 4001 4002 return (AHCI_SUCCESS); 4003} 4004 4005/* 4006 * Deallocates the Received FIS Structure 4007 * 4008 * WARNING!!! ahciport_mutex should be acquired before the function 4009 * is called. 4010 */ 4011static void 4012ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 4013{ 4014 /* Unbind the cmd list dma handle first. */ 4015 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4016 4017 /* Then free the underlying memory. */ 4018 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4019 4020 /* Now free the handle itself. */ 4021 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4022} 4023 4024/* 4025 * Allocates memory for the Command List, which contains up to 32 entries. 4026 * Each entry contains a command header, which is a 32-byte structure that 4027 * includes the pointer to the command table. 4028 * 4029 * WARNING!!! ahciport_mutex should be acquired before the function 4030 * is called. 4031 */ 4032static int 4033ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4034 uint8_t port) 4035{ 4036 size_t cmd_list_size; 4037 size_t ret_len; 4038 uint_t cookie_count; 4039 4040 cmd_list_size = 4041 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4042 4043 /* allocate cmd list dma handle. */ 4044 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4045 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4046 DDI_DMA_SLEEP, 4047 NULL, 4048 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4049 4050 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4051 "cmd list dma handle alloc failed"); 4052 return (AHCI_FAILURE); 4053 } 4054 4055 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4056 cmd_list_size, 4057 &accattr, 4058 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4059 DDI_DMA_SLEEP, 4060 NULL, 4061 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4062 &ret_len, 4063 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4064 4065 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4066 "cmd list dma mem alloc fail"); 4067 /* error.. free the dma handle. */ 4068 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4069 return (AHCI_FAILURE); 4070 } 4071 4072 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4073 NULL, 4074 (caddr_t)ahci_portp->ahciport_cmd_list, 4075 cmd_list_size, 4076 DDI_DMA_CONSISTENT, 4077 DDI_DMA_SLEEP, 4078 NULL, 4079 &ahci_portp->ahciport_cmd_list_dma_cookie, 4080 &cookie_count) != DDI_DMA_MAPPED) { 4081 4082 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4083 "cmd list dma handle bind fail"); 4084 /* error.. free the dma handle & free the memory. */ 4085 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4086 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4087 return (AHCI_FAILURE); 4088 } 4089 4090 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4091 4092 /* Config Port Command List Base Address */ 4093 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4094 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4095 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4096 4097 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4098 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4099 4100 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4101 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4102 4103 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4104 goto err_out; 4105 } 4106 4107 return (AHCI_SUCCESS); 4108 4109err_out: 4110 /* Unbind the cmd list dma handle first. */ 4111 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4112 4113 /* Then free the underlying memory. */ 4114 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4115 4116 /* Now free the handle itself. */ 4117 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4118 4119 return (AHCI_FAILURE); 4120} 4121 4122/* 4123 * Deallocates the Command List 4124 * 4125 * WARNING!!! ahciport_mutex should be acquired before the function 4126 * is called. 4127 */ 4128static void 4129ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4130{ 4131 /* First dealloc command table */ 4132 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4133 4134 /* Unbind the cmd list dma handle first. */ 4135 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4136 4137 /* Then free the underlying memory. */ 4138 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4139 4140 /* Now free the handle itself. */ 4141 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4142} 4143 4144/* 4145 * Allocates memory for all Command Tables, which contains Command FIS, 4146 * ATAPI Command and Physical Region Descriptor Table. 4147 * 4148 * WARNING!!! ahciport_mutex should be acquired before the function 4149 * is called. 4150 */ 4151static int 4152ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4153{ 4154 size_t ret_len; 4155 ddi_dma_cookie_t cmd_table_dma_cookie; 4156 uint_t cookie_count; 4157 int slot; 4158 4159 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4160 "ahci_alloc_cmd_tables: port %d enter", 4161 ahci_portp->ahciport_port_num); 4162 4163 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4164 /* Allocate cmd table dma handle. */ 4165 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4166 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4167 DDI_DMA_SLEEP, 4168 NULL, 4169 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4170 DDI_SUCCESS) { 4171 4172 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4173 "cmd table dma handle alloc failed"); 4174 4175 goto err_out; 4176 } 4177 4178 if (ddi_dma_mem_alloc( 4179 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4180 ahci_cmd_table_size, 4181 &accattr, 4182 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4183 DDI_DMA_SLEEP, 4184 NULL, 4185 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4186 &ret_len, 4187 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4188 NULL) { 4189 4190 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4191 "cmd table dma mem alloc fail"); 4192 4193 /* error.. free the dma handle. */ 4194 ddi_dma_free_handle( 4195 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4196 goto err_out; 4197 } 4198 4199 if (ddi_dma_addr_bind_handle( 4200 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4201 NULL, 4202 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4203 ahci_cmd_table_size, 4204 DDI_DMA_CONSISTENT, 4205 DDI_DMA_SLEEP, 4206 NULL, 4207 &cmd_table_dma_cookie, 4208 &cookie_count) != DDI_DMA_MAPPED) { 4209 4210 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4211 "cmd table dma handle bind fail"); 4212 /* error.. free the dma handle & free the memory. */ 4213 ddi_dma_mem_free( 4214 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4215 ddi_dma_free_handle( 4216 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4217 goto err_out; 4218 } 4219 4220 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4221 ahci_cmd_table_size); 4222 4223 /* Config Port Command Table Base Address */ 4224 SET_COMMAND_TABLE_BASE_ADDR( 4225 (&ahci_portp->ahciport_cmd_list[slot]), 4226 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4227 4228#ifndef __lock_lint 4229 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4230 (&ahci_portp->ahciport_cmd_list[slot]), 4231 cmd_table_dma_cookie.dmac_laddress >> 32); 4232#endif 4233 } 4234 4235 return (AHCI_SUCCESS); 4236err_out: 4237 4238 for (slot--; slot >= 0; slot--) { 4239 /* Unbind the cmd table dma handle first */ 4240 (void) ddi_dma_unbind_handle( 4241 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4242 4243 /* Then free the underlying memory */ 4244 ddi_dma_mem_free( 4245 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4246 4247 /* Now free the handle itself */ 4248 ddi_dma_free_handle( 4249 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4250 } 4251 4252 return (AHCI_FAILURE); 4253} 4254 4255/* 4256 * Deallocates memory for all Command Tables. 4257 * 4258 * WARNING!!! ahciport_mutex should be acquired before the function 4259 * is called. 4260 */ 4261static void 4262ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4263{ 4264 int slot; 4265 4266 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4267 "ahci_dealloc_cmd_tables: %d enter", 4268 ahci_portp->ahciport_port_num); 4269 4270 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4271 /* Unbind the cmd table dma handle first. */ 4272 (void) ddi_dma_unbind_handle( 4273 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4274 4275 /* Then free the underlying memory. */ 4276 ddi_dma_mem_free( 4277 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4278 4279 /* Now free the handle itself. */ 4280 ddi_dma_free_handle( 4281 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4282 } 4283} 4284 4285/* 4286 * WARNING!!! ahciport_mutex should be acquired before the function 4287 * is called. 4288 */ 4289static void 4290ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4291 sata_device_t *sd) 4292{ 4293 sd->satadev_scr.sstatus = 4294 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4295 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4296 sd->satadev_scr.serror = 4297 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4298 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4299 sd->satadev_scr.scontrol = 4300 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4301 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4302 sd->satadev_scr.sactive = 4303 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4304 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4305} 4306 4307/* 4308 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4309 */ 4310static void 4311ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4312{ 4313 uint32_t port_intr_status; 4314 uint32_t port_intr_enable; 4315 4316 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4317 "ahci_port_intr enter: port %d", port); 4318 4319 mutex_enter(&ahci_portp->ahciport_mutex); 4320 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4321 /* For SATA_OPMODE_POLLING commands */ 4322 port_intr_enable = 4323 (AHCI_INTR_STATUS_DHRS | 4324 AHCI_INTR_STATUS_PSS | 4325 AHCI_INTR_STATUS_SDBS | 4326 AHCI_INTR_STATUS_UFS | 4327 AHCI_INTR_STATUS_PCS | 4328 AHCI_INTR_STATUS_PRCS | 4329 AHCI_INTR_STATUS_OFS | 4330 AHCI_INTR_STATUS_INFS | 4331 AHCI_INTR_STATUS_IFS | 4332 AHCI_INTR_STATUS_HBDS | 4333 AHCI_INTR_STATUS_HBFS | 4334 AHCI_INTR_STATUS_TFES); 4335 mutex_exit(&ahci_portp->ahciport_mutex); 4336 goto next; 4337 } 4338 mutex_exit(&ahci_portp->ahciport_mutex); 4339 4340 /* 4341 * port_intr_enable indicates that the corresponding interrrupt 4342 * reporting is enabled. 4343 */ 4344 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4345 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4346next: 4347 /* 4348 * port_intr_stats indicates that the corresponding interrupt 4349 * condition is active. 4350 */ 4351 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4352 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4353 4354 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4355 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4356 "port_intr_enable = 0x%x", 4357 port, port_intr_status, port_intr_enable); 4358 4359 port_intr_status &= port_intr_enable; 4360 4361 /* First clear the port interrupts status */ 4362 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4363 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4364 port_intr_status); 4365 4366 /* Check the completed non-queued commands */ 4367 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4368 AHCI_INTR_STATUS_PSS)) { 4369 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4370 ahci_portp, port); 4371 } 4372 4373 /* Check the completed queued commands */ 4374 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4375 (void) ahci_intr_set_device_bits(ahci_ctlp, 4376 ahci_portp, port); 4377 } 4378 4379 /* Check the port connect change status interrupt bit */ 4380 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4381 (void) ahci_intr_port_connect_change(ahci_ctlp, 4382 ahci_portp, port); 4383 } 4384 4385 /* Check the device mechanical presence status interrupt bit */ 4386 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4387 (void) ahci_intr_device_mechanical_presence_status( 4388 ahci_ctlp, ahci_portp, port); 4389 } 4390 4391 /* Check the PhyRdy change status interrupt bit */ 4392 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4393 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4394 port); 4395 } 4396 4397 /* 4398 * Check the non-fatal error interrupt bits, there are three 4399 * kinds of non-fatal errors at the time being: 4400 * 4401 * PxIS.UFS - Unknown FIS Error 4402 * PxIS.OFS - Overflow Error 4403 * PxIS.INFS - Interface Non-Fatal Error 4404 * 4405 * For these non-fatal errors, the HBA can continue to operate, 4406 * so the driver just log the error messages. 4407 */ 4408 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4409 AHCI_INTR_STATUS_OFS | 4410 AHCI_INTR_STATUS_INFS)) { 4411 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4412 port, port_intr_status); 4413 } 4414 4415 /* 4416 * Check the fatal error interrupt bits, there are four kinds 4417 * of fatal errors for AHCI controllers: 4418 * 4419 * PxIS.HBFS - Host Bus Fatal Error 4420 * PxIS.HBDS - Host Bus Data Error 4421 * PxIS.IFS - Interface Fatal Error 4422 * PxIS.TFES - Task File Error 4423 * 4424 * The fatal error means the HBA can not recover from it by 4425 * itself, and it will try to abort the transfer, and the software 4426 * must intervene to restart the port. 4427 */ 4428 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4429 AHCI_INTR_STATUS_HBDS | 4430 AHCI_INTR_STATUS_HBFS | 4431 AHCI_INTR_STATUS_TFES)) 4432 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4433 port, port_intr_status); 4434 4435 /* Check the cold port detect interrupt bit */ 4436 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4437 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4438 } 4439 4440 /* Second clear the corresponding bit in IS.IPS */ 4441 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4442 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4443} 4444 4445/* 4446 * Interrupt service handler 4447 */ 4448static uint_t 4449ahci_intr(caddr_t arg1, caddr_t arg2) 4450{ 4451#ifndef __lock_lint 4452 _NOTE(ARGUNUSED(arg2)) 4453#endif 4454 /* LINTED */ 4455 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4456 ahci_port_t *ahci_portp; 4457 int32_t global_intr_status; 4458 uint8_t port; 4459 4460 /* 4461 * global_intr_status indicates that the corresponding port has 4462 * an interrupt pending. 4463 */ 4464 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4465 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4466 4467 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4468 /* The interrupt is not ours */ 4469 return (DDI_INTR_UNCLAIMED); 4470 } 4471 4472 /* Loop for all the ports */ 4473 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4474 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4475 continue; 4476 } 4477 if (!((0x1 << port) & global_intr_status)) { 4478 continue; 4479 } 4480 4481 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4482 4483 /* Call ahci_port_intr */ 4484 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4485 } 4486 4487 return (DDI_INTR_CLAIMED); 4488} 4489 4490/* 4491 * For non-queued commands, when the corresponding bit in the PxCI register 4492 * is cleared, it means the command is completed successfully. And according 4493 * to the HBA state machine, there are three conditions which possibly will 4494 * try to clear the PxCI register bit. 4495 * 1. Receive one D2H Register FIS which is with 'I' bit set 4496 * 2. Update PIO Setup FIS 4497 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4498 * 4499 * Process completed non-queued commands when the interrupt status bit - 4500 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4501 * 4502 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4503 * with the 'I' bit set. And the following commands will send thus 4504 * FIS with 'I' bit set upon the successful completion: 4505 * 1. Non-data commands 4506 * 2. DMA data-in command 4507 * 3. DMA data-out command 4508 * 4. PIO data-out command 4509 * 5. PACKET non-data commands 4510 * 6. PACKET PIO data-in command 4511 * 7. PACKET PIO data-out command 4512 * 8. PACKET DMA data-in command 4513 * 9. PACKET DMA data-out command 4514 * 4515 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4516 * with the 'I' bit set. And the following commands will send this 4517 * FIS upon the successful completion: 4518 * 1. PIO data-in command 4519 */ 4520static int 4521ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4522 ahci_port_t *ahci_portp, uint8_t port) 4523{ 4524 uint32_t port_cmd_issue = 0; 4525 uint32_t finished_tags; 4526 int finished_slot; 4527 sata_pkt_t *satapkt; 4528 ahci_fis_d2h_register_t *rcvd_fisp; 4529 4530 mutex_enter(&ahci_portp->ahciport_mutex); 4531 4532 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4533 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4534 /* 4535 * Spurious interrupt. Nothing to be done. 4536 */ 4537 mutex_exit(&ahci_portp->ahciport_mutex); 4538 return (AHCI_SUCCESS); 4539 } 4540 4541 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4542 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4543 4544 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4545 /* Slot 0 is always used during error recovery */ 4546 finished_tags = 0x1 & ~port_cmd_issue; 4547 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4548 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4549 "retrieval is finished, and finished_tags = 0x%x", 4550 port, finished_tags); 4551 } else { 4552 finished_tags = ahci_portp->ahciport_pending_tags & 4553 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4554 } 4555 4556 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4557 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4558 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4559 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4560 finished_tags); 4561 4562 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4563 (finished_tags == 0x1)) { 4564 satapkt = ahci_portp->ahciport_err_retri_pkt; 4565 ASSERT(satapkt != NULL); 4566 4567 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4568 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4569 "with SATA_PKT_COMPLETED", (void *)satapkt); 4570 4571 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4572 goto out; 4573 } 4574 4575 while (finished_tags) { 4576 finished_slot = ddi_ffs(finished_tags) - 1; 4577 if (finished_slot == -1) { 4578 goto out; 4579 } 4580 4581 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4582 ASSERT(satapkt != NULL); 4583 4584 /* 4585 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4586 * feature, sata_special_regs flag will be set, and the 4587 * driver should copy the status and the other corresponding 4588 * register values in the D2H Register FIS received (It's 4589 * working on Non-data protocol) from the device back to 4590 * the sata_cmd. 4591 * 4592 * For every AHCI port, there is only one Received FIS 4593 * structure, which contains the FISes received from the 4594 * device, So we're trying to copy the content of D2H 4595 * Register FIS in the Received FIS structure back to 4596 * the sata_cmd. 4597 */ 4598 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4599 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4600 ahcirf_d2h_register_fis); 4601 satapkt->satapkt_cmd.satacmd_status_reg = 4602 GET_RFIS_STATUS(rcvd_fisp); 4603 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4604 } 4605 4606 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4607 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4608 "with SATA_PKT_COMPLETED", (void *)satapkt); 4609 4610 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4611 CLEAR_BIT(finished_tags, finished_slot); 4612 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4613 4614 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4615 } 4616out: 4617 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4618 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4619 ahci_portp->ahciport_pending_tags); 4620 4621 mutex_exit(&ahci_portp->ahciport_mutex); 4622 4623 return (AHCI_SUCCESS); 4624} 4625 4626/* 4627 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4628 * with the 'I' bit set and has been copied into system memory. It will 4629 * be sent under the following situations: 4630 * 4631 * 1. NCQ command is completed 4632 * 2. Asynchronous notification 4633 * 4634 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4635 * via the Set Device Bits FIS. When such event is generated, the software 4636 * needs to read PxSACT register and compares the current value to the 4637 * list of commands previously issue by software. ahciport_pending_ncq_tags 4638 * keeps the tags of previously issued commands. 4639 * 4640 * Asynchronous Notification is a feature in SATA II, which allows an 4641 * ATAPI device to send a signal to the host when media is inserted or 4642 * removed and avoids polling the device for media changes. The signal 4643 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4644 * set to '1'. At the moment, it's not supported yet. 4645 */ 4646static int 4647ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4648 ahci_port_t *ahci_portp, uint8_t port) 4649{ 4650 uint32_t port_sactive; 4651 uint32_t port_cmd_issue; 4652 uint32_t issued_tags; 4653 int issued_slot; 4654 uint32_t finished_tags; 4655 int finished_slot; 4656 sata_pkt_t *satapkt; 4657 4658 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4659 "ahci_intr_set_device_bits enter: port %d", port); 4660 4661 mutex_enter(&ahci_portp->ahciport_mutex); 4662 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4663 mutex_exit(&ahci_portp->ahciport_mutex); 4664 return (AHCI_SUCCESS); 4665 } 4666 4667 /* 4668 * First the handler got which commands are finished by checking 4669 * PxSACT register 4670 */ 4671 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4672 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4673 4674 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4675 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4676 4677 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4678 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4679 "port_sactive = 0x%x", port, 4680 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4681 4682 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4683 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4684 4685 /* 4686 * For NCQ commands, the software can determine which command has 4687 * already been transmitted to the device by checking PxCI register. 4688 */ 4689 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4690 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4691 4692 issued_tags = ahci_portp->ahciport_pending_tags & 4693 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4694 4695 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4696 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4697 "port_cmd_issue = 0x%x", port, 4698 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4699 4700 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4701 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4702 4703 /* 4704 * Clear ahciport_pending_tags bit when the corresponding command 4705 * is already sent down to the device. 4706 */ 4707 while (issued_tags) { 4708 issued_slot = ddi_ffs(issued_tags) - 1; 4709 if (issued_slot == -1) { 4710 goto next; 4711 } 4712 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4713 CLEAR_BIT(issued_tags, issued_slot); 4714 } 4715 4716next: 4717 while (finished_tags) { 4718 finished_slot = ddi_ffs(finished_tags) - 1; 4719 if (finished_slot == -1) { 4720 goto out; 4721 } 4722 4723 /* The command is certainly transmitted to the device */ 4724 ASSERT(!(ahci_portp->ahciport_pending_tags & 4725 (0x1 << finished_slot))); 4726 4727 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4728 ASSERT(satapkt != NULL); 4729 4730 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4731 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4732 "with SATA_PKT_COMPLETED", (void *)satapkt); 4733 4734 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4735 CLEAR_BIT(finished_tags, finished_slot); 4736 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4737 4738 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4739 } 4740out: 4741 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4742 "ahci_intr_set_device_bits: port %d " 4743 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4744 port, ahci_portp->ahciport_pending_ncq_tags, 4745 ahci_portp->ahciport_pending_tags); 4746 4747 mutex_exit(&ahci_portp->ahciport_mutex); 4748 4749 return (AHCI_SUCCESS); 4750} 4751 4752/* 4753 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4754 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4755 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4756 * indicates a COMINIT signal was received. 4757 * 4758 * Hot plug insertion is detected by reception of a COMINIT signal from the 4759 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4760 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4761 * begin the normal communication negotiation sequence as outlined in the 4762 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4763 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4764 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4765 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4766 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4767 * to handle hot plug insertion. In this interrupt handler, just do nothing 4768 * but print some log message and clear the bit. 4769 */ 4770static int 4771ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4772 ahci_port_t *ahci_portp, uint8_t port) 4773{ 4774#if AHCI_DEBUG 4775 uint32_t port_serror; 4776#endif 4777 4778 mutex_enter(&ahci_portp->ahciport_mutex); 4779 4780#if AHCI_DEBUG 4781 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4782 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4783 4784 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4785 "ahci_intr_port_connect_change: port %d, " 4786 "port_serror = 0x%x", port, port_serror); 4787#endif 4788 4789 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4790 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4791 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4792 SERROR_EXCHANGED_ERR); 4793 4794 mutex_exit(&ahci_portp->ahciport_mutex); 4795 4796 return (AHCI_SUCCESS); 4797} 4798 4799/* 4800 * Hot Plug Operation for platforms that support Mechanical Presence 4801 * Switches. 4802 * 4803 * When set, it indicates that a mechanical presence switch attached to this 4804 * port has been opened or closed, which may lead to a change in the connection 4805 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4806 * are set to '1'. 4807 * 4808 * At the moment, this interrupt is not needed and disabled and we just log 4809 * the debug message. 4810 */ 4811static int 4812ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4813 ahci_port_t *ahci_portp, uint8_t port) 4814{ 4815 uint32_t cap_status, port_cmd_status; 4816 4817 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4818 "ahci_intr_device_mechanical_presence_status enter, " 4819 "port %d", port); 4820 4821 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4822 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4823 4824 mutex_enter(&ahci_portp->ahciport_mutex); 4825 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4826 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4827 4828 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4829 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4830 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4831 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4832 "the interrupt: cap_status = 0x%x, " 4833 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4834 mutex_exit(&ahci_portp->ahciport_mutex); 4835 4836 return (AHCI_SUCCESS); 4837 } 4838 4839#if AHCI_DEBUG 4840 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4841 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4842 "The mechanical presence switch is open: " 4843 "port %d, port_cmd_status = 0x%x", 4844 port, port_cmd_status); 4845 } else { 4846 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4847 "The mechanical presence switch is close: " 4848 "port %d, port_cmd_status = 0x%x", 4849 port, port_cmd_status); 4850 } 4851#endif 4852 4853 mutex_exit(&ahci_portp->ahciport_mutex); 4854 4855 return (AHCI_SUCCESS); 4856} 4857 4858/* 4859 * Native Hot Plug Support. 4860 * 4861 * When set, it indicates that the internal PHYRDY signal changed state. 4862 * This bit reflects the state of PxSERR.DIAG.N. 4863 * 4864 * There are three kinds of conditions to generate this interrupt event: 4865 * 1. a device is inserted 4866 * 2. a device is disconnected 4867 * 3. when the link enters/exits a Partial or Slumber interface power 4868 * management state 4869 * 4870 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4871 * bit may be set due to the link entering the Partial or Slumber power 4872 * management state, rather than due to a hot plug insertion or removal 4873 * event. So far, the interface power management is disabled, so the 4874 * driver can reliably get removal detection notification via the 4875 * PxSERR.DIAG.N bit. 4876 */ 4877static int 4878ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4879 ahci_port_t *ahci_portp, uint8_t port) 4880{ 4881 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4882 sata_device_t sdevice; 4883 int dev_exists_now = 0; 4884 int dev_existed_previously = 0; 4885 4886 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4887 "ahci_intr_phyrdy_change enter, port %d", port); 4888 4889 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4890 mutex_enter(&ahci_portp->ahciport_mutex); 4891 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4892 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4893 SERROR_PHY_RDY_CHG); 4894 mutex_exit(&ahci_portp->ahciport_mutex); 4895 4896 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4897 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4898 (ahci_portp == NULL)) { 4899 /* The whole controller setup is not yet done. */ 4900 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4901 return (AHCI_SUCCESS); 4902 } 4903 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4904 4905 mutex_enter(&ahci_portp->ahciport_mutex); 4906 4907 /* SStatus tells the presence of device. */ 4908 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4909 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4910 4911 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4912 dev_exists_now = 1; 4913 } 4914 4915 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4916 dev_existed_previously = 1; 4917 } 4918 4919 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4920 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4921 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4922 "ahci_intr_phyrdy_change: port %d " 4923 "AHCI_PORT_FLAG_NODEV is cleared", port); 4924 if (dev_exists_now == 0) 4925 dev_existed_previously = 1; 4926 } 4927 4928 bzero((void *)&sdevice, sizeof (sata_device_t)); 4929 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4930 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4931 sdevice.satadev_addr.pmport = 0; 4932 sdevice.satadev_state = SATA_PSTATE_PWRON; 4933 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4934 4935 if (dev_exists_now) { 4936 if (dev_existed_previously) { 4937 /* Things are fine now. The loss was temporary. */ 4938 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4939 "ahci_intr_phyrdy_change port %d " 4940 "device link lost/established", port); 4941 4942 mutex_exit(&ahci_portp->ahciport_mutex); 4943 sata_hba_event_notify( 4944 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4945 &sdevice, 4946 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4947 mutex_enter(&ahci_portp->ahciport_mutex); 4948 4949 } else { 4950 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4951 "ahci_intr_phyrdy_change: port %d " 4952 "device link established", port); 4953 4954 /* A new device has been detected. */ 4955 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4956 4957 /* Try to start the port */ 4958 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4959 != AHCI_SUCCESS) { 4960 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4961 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4962 "ahci_intr_phyrdy_change: port %d failed " 4963 "at start port", port); 4964 } 4965 4966 /* Clear the max queue depth for inserted device */ 4967 ahci_portp->ahciport_max_ncq_tags = 0; 4968 4969 mutex_exit(&ahci_portp->ahciport_mutex); 4970 sata_hba_event_notify( 4971 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4972 &sdevice, 4973 SATA_EVNT_LINK_ESTABLISHED); 4974 mutex_enter(&ahci_portp->ahciport_mutex); 4975 4976 } 4977 } else { /* No device exists now */ 4978 4979 if (dev_existed_previously) { 4980 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4981 "ahci_intr_phyrdy_change: port %d " 4982 "device link lost", port); 4983 4984 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4985 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 4986 ahci_portp, port); 4987 4988 /* An existing device is lost. */ 4989 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4990 4991 mutex_exit(&ahci_portp->ahciport_mutex); 4992 sata_hba_event_notify( 4993 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4994 &sdevice, 4995 SATA_EVNT_LINK_LOST); 4996 mutex_enter(&ahci_portp->ahciport_mutex); 4997 } 4998 } 4999 5000 mutex_exit(&ahci_portp->ahciport_mutex); 5001 5002 return (AHCI_SUCCESS); 5003} 5004 5005/* 5006 * PxIS.UFS - Unknown FIS Error 5007 * 5008 * This interrupt event means an unknown FIS was received and has been 5009 * copied into system memory. An unknown FIS is not considered an illegal 5010 * FIS, unless the length received is more than 64 bytes. If an unknown 5011 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5012 * normal operation. If the unknown FIS is more than 64 bytes, then it 5013 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5014 * a fatal error. 5015 * 5016 * PxIS.OFS - Overflow Error 5017 * 5018 * Command list overflow is defined as software building a command table 5019 * that has fewer total bytes than the transaction given to the device. 5020 * On device writes, the HBA will run out of data, and on reads, there 5021 * will be no room to put the data. 5022 * 5023 * For an overflow on data read, either PIO or DMA, the HBA will set 5024 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5025 * non-fatal error when the HBA can continues. Sometimes, it will cause 5026 * a fatal error and need the software to do something. 5027 * 5028 * For an overflow on data write, setting PxIS.OFS is optional for both 5029 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5030 * software to clean up from this serious error. 5031 * 5032 * PxIS.INFS - Interface Non-Fatal Error 5033 * 5034 * This interrupt event indicates that the HBA encountered an error on 5035 * the Serial ATA interface but was able to continue operation. The kind 5036 * of error usually occurred during a non-Data FIS, and under this condition 5037 * the FIS will be re-transmitted by HBA automatically. 5038 * 5039 * When the FMA is implemented, there should be a stat structure to 5040 * record how many every kind of error happens. 5041 */ 5042static int 5043ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5044 uint8_t port, uint32_t intr_status) 5045{ 5046 uint32_t port_serror; 5047#if AHCI_DEBUG 5048 uint32_t port_cmd_status; 5049 uint32_t port_cmd_issue; 5050 uint32_t port_sactive; 5051 int current_slot; 5052 uint32_t current_tags; 5053 sata_pkt_t *satapkt; 5054#endif 5055 5056 mutex_enter(&ahci_portp->ahciport_mutex); 5057 5058 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5059 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5060 5061 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5062 "ahci_intr_non_fatal_error: port %d, " 5063 "port_serror = 0x%x", port, port_serror); 5064 5065 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5066 5067 if (intr_status & AHCI_INTR_STATUS_UFS) { 5068 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5069 "ahci port %d has unknown FIS error", port); 5070 5071 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5072 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5073 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5074 SERROR_FIS_TYPE); 5075 } 5076 5077#if AHCI_DEBUG 5078 if (intr_status & AHCI_INTR_STATUS_OFS) { 5079 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5080 "ahci port %d has overflow error", port); 5081 } 5082 5083 if (intr_status & AHCI_INTR_STATUS_INFS) { 5084 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5085 "ahci port %d has interface non fatal error", port); 5086 } 5087 5088 /* 5089 * Record the error occurred command's slot. 5090 */ 5091 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5092 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5093 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5094 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5095 5096 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5097 AHCI_CMD_STATUS_CCS_SHIFT; 5098 5099 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5100 satapkt = ahci_portp->ahciport_err_retri_pkt; 5101 ASSERT(satapkt != NULL); 5102 ASSERT(current_slot == 0); 5103 } else { 5104 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5105 } 5106 5107 if (satapkt != NULL) { 5108 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5109 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5110 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5111 satapkt->satapkt_cmd.satacmd_cmd_reg); 5112 5113 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5114 "ahci_intr_non_fatal_error: port %d, " 5115 "satapkt 0x%p is being processed when error occurs", 5116 port, (void *)satapkt); 5117 } 5118 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5119 /* 5120 * For queued command, list those command which have already 5121 * been transmitted to the device and still not completed. 5122 */ 5123 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5124 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5125 5126 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5127 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5128 5129 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5130 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5131 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5132 ahci_portp->ahciport_pending_ncq_tags, 5133 port_sactive, port_cmd_issue); 5134 5135 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5136 port_sactive & ~port_cmd_issue & 5137 AHCI_NCQ_SLOT_MASK(ahci_portp); 5138 5139 while (current_tags) { 5140 current_slot = ddi_ffs(current_tags) - 1; 5141 if (current_slot == -1) { 5142 goto out; 5143 } 5144 5145 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5146 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5147 ahci_ctlp, "ahci_intr_non_fatal_error: " 5148 "port %d, satapkt 0x%p is outstanding when " 5149 "error occurs", port, (void *)satapkt); 5150 } 5151 } 5152out: 5153#endif 5154 mutex_exit(&ahci_portp->ahciport_mutex); 5155 5156 return (AHCI_SUCCESS); 5157} 5158 5159/* 5160 * According to the AHCI spec, the error types include system memory 5161 * errors, interface errors, port multiplier errors, device errors, 5162 * command list overflow, command list underflow, native command 5163 * queuing tag errors and pio data transfer errors. 5164 * 5165 * System memory errors such as target abort, master abort, and parity 5166 * may cause the host to stop, and they are serious errors and needed 5167 * to be recovered with software intervention. When system software 5168 * has given a pointer to the HBA that doesn't exist in physical memory, 5169 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5170 * data error such as CRC or parity occurs, the HBA aborts the transfer 5171 * (if necessary) and PxIS.HBDS will be set. 5172 * 5173 * Interface errors are errors that occur due to electrical issues on 5174 * the interface, or protocol miscommunication between the device and 5175 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5176 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5177 * causes PxIS.IFS/PxIS.INFS to be set are 5178 * 1. in PxSERR.ERR, P bit is set to '1' 5179 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5180 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5181 * If the error occurred during a non-data FIS, the FIS must be 5182 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5183 * the error occurred during a data FIS, the transfer will stop, so 5184 * the error is fatal and PxIS.IFS is set. 5185 * 5186 * When a FIS arrives that updates the taskfile, the HBA checks to see 5187 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5188 * stops processing any more commands. 5189 * 5190 * Command list overflow is defined as software building a command table 5191 * that has fewer total bytes than the transaction given to the device. 5192 * On device writes, the HBA will run out of data, and on reads, there 5193 * will be no room to put the data. For an overflow on data read, either 5194 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5195 * For an overflow on data write, setting PxIS.OFS is optional for both 5196 * DMA and PIO, and a COMRESET is required by software to clean up from 5197 * this serious error. 5198 * 5199 * Command list underflow is defined as software building a command 5200 * table that has more total bytes than the transaction given to the 5201 * device. For data writes, both PIO and DMA, the device will detect 5202 * an error and end the transfer. And these errors are most likely going 5203 * to be fatal errors that will cause the port to be restarted. For 5204 * data reads, the HBA updates its PRD byte count, and may be 5205 * able to continue normally, but is not required to. And The HBA is 5206 * not required to detect underflow conditions for native command 5207 * queuing command. 5208 * 5209 * The HBA does not actively check incoming DMA Setup FISes to ensure 5210 * that the PxSACT register bit for that slot is set. Existing error 5211 * mechanisms, such as host bus failure, or bad protocol, are used to 5212 * recover from this case. 5213 * 5214 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5215 * DATA FIS must be an integral number of Dwords. If the HBA receives 5216 * a request which is not an integral number of Dwords, the HBA 5217 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5218 * software restarts the port. And the HBA ensures that the size 5219 * of the DATA FIS received during a PIO command matches the size in 5220 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5221 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5222 * stop running until software restarts the port. 5223 */ 5224/* 5225 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5226 * 5227 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5228 * interface which caused the transfer to stop. 5229 * 5230 * PxIS.HBDS indicates that the hba encountered a data error 5231 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5232 * 5233 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5234 * cannot recover from, such as a bad software pointer. 5235 * 5236 * PxIS.TFES is set whenever the status register is updated by the device 5237 * and the error bit (bit 0) is set. 5238 */ 5239static int 5240ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5241 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5242{ 5243 uint32_t port_cmd_status; 5244 uint32_t port_serror; 5245 uint32_t task_file_status; 5246 int failed_slot; 5247 sata_pkt_t *spkt = NULL; 5248 uint8_t err_byte; 5249 ahci_event_arg_t *args; 5250 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5251 5252 mutex_enter(&ahci_portp->ahciport_mutex); 5253 5254 /* 5255 * ahci_intr_phyrdy_change() may have rendered it to 5256 * SATA_DTYPE_NONE. 5257 */ 5258 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5259 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5260 "ahci_intr_fatal_error: port %d no device attached, " 5261 "and just return without doing anything", port); 5262 goto out0; 5263 } 5264 5265 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5266 /* 5267 * Read PxCMD.CCS to determine the slot that the HBA 5268 * was processing when the error occurred. 5269 */ 5270 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5271 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5272 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5273 AHCI_CMD_STATUS_CCS_SHIFT; 5274 5275 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5276 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5277 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5278 "fatal error occurred for port %d", spkt, port); 5279 5280 if (intr_status & AHCI_INTR_STATUS_TFES) { 5281 task_file_status = ddi_get32( 5282 ahci_ctlp->ahcictl_ahci_acc_handle, 5283 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5284 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5285 "ahci_intr_fatal_error: port %d " 5286 "task_file_status = 0x%x", port, task_file_status); 5287 5288 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5289 >> AHCI_TFD_ERR_SHIFT; 5290 5291 /* 5292 * Won't emit the error message if it is an IDENTIFY 5293 * DEVICE command sent to an ATAPI device. 5294 */ 5295 if ((spkt != NULL) && 5296 (spkt->satapkt_cmd.satacmd_cmd_reg == 5297 SATAC_ID_DEVICE) && 5298 (err_byte == SATA_ERROR_ABORT)) 5299 goto out1; 5300 5301 /* 5302 * Won't emit the error message if it is an ATAPI PACKET 5303 * command 5304 */ 5305 if ((spkt != NULL) && 5306 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5307 goto out1; 5308 } 5309 } 5310 5311 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5312 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5313 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5314 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5315out1: 5316 /* Prepare the argument for the taskq */ 5317 args = ahci_portp->ahciport_event_args; 5318 args->ahciea_ctlp = (void *)ahci_ctlp; 5319 args->ahciea_portp = (void *)ahci_portp; 5320 args->ahciea_event = intr_status; 5321 5322 /* Start the taskq to handle error recovery */ 5323 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5324 ahci_events_handler, 5325 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5326 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5327 "failed", instance); 5328 } 5329out0: 5330 mutex_exit(&ahci_portp->ahciport_mutex); 5331 5332 return (AHCI_SUCCESS); 5333} 5334 5335/* 5336 * Hot Plug Operation for platforms that support Cold Presence Detect. 5337 * 5338 * When set, a device status has changed as detected by the cold presence 5339 * detect logic. This bit can either be set due to a non-connected port 5340 * receiving a device, or a connected port having its device removed. 5341 * This bit is only valid if the port supports cold presence detect as 5342 * indicated by PxCMD.CPD set to '1'. 5343 * 5344 * At the moment, this interrupt is not needed and disabled and we just 5345 * log the debug message. 5346 */ 5347static int 5348ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5349 ahci_port_t *ahci_portp, uint8_t port) 5350{ 5351 uint32_t port_cmd_status; 5352 sata_device_t sdevice; 5353 5354 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5355 "ahci_intr_cold_port_detect enter, port %d", port); 5356 5357 mutex_enter(&ahci_portp->ahciport_mutex); 5358 5359 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5360 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5361 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5362 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5363 "port %d does not support cold presence detect, so " 5364 "we just ignore this interrupt", port); 5365 mutex_exit(&ahci_portp->ahciport_mutex); 5366 return (AHCI_SUCCESS); 5367 } 5368 5369 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5370 "port %d device status has changed", port); 5371 5372 bzero((void *)&sdevice, sizeof (sata_device_t)); 5373 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5374 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5375 sdevice.satadev_addr.pmport = 0; 5376 sdevice.satadev_state = SATA_PSTATE_PWRON; 5377 5378 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5379 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5380 "port %d: a device is hot plugged", port); 5381 mutex_exit(&ahci_portp->ahciport_mutex); 5382 sata_hba_event_notify( 5383 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5384 &sdevice, 5385 SATA_EVNT_DEVICE_ATTACHED); 5386 mutex_enter(&ahci_portp->ahciport_mutex); 5387 5388 } else { 5389 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5390 "port %d: a device is hot unplugged", port); 5391 mutex_exit(&ahci_portp->ahciport_mutex); 5392 sata_hba_event_notify( 5393 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5394 &sdevice, 5395 SATA_EVNT_DEVICE_DETACHED); 5396 mutex_enter(&ahci_portp->ahciport_mutex); 5397 } 5398 5399 mutex_exit(&ahci_portp->ahciport_mutex); 5400 5401 return (AHCI_SUCCESS); 5402} 5403 5404/* 5405 * Enable the interrupts for a particular port. 5406 * 5407 * WARNING!!! ahciport_mutex should be acquired before the function 5408 * is called. 5409 */ 5410static void 5411ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5412{ 5413 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5414 "ahci_enable_port_intrs enter, port %d", port); 5415 5416 /* 5417 * Clear port interrupt status before enabling interrupt 5418 */ 5419 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5420 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5421 AHCI_PORT_INTR_MASK); 5422 5423 /* 5424 * Clear the pending bit from IS.IPS 5425 */ 5426 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5427 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5428 5429 /* 5430 * Enable the following interrupts: 5431 * Device to Host Register FIS Interrupt (DHRS) 5432 * PIO Setup FIS Interrupt (PSS) 5433 * Set Device Bits Interrupt (SDBS) 5434 * Unknown FIS Interrupt (UFS) 5435 * Port Connect Change Status (PCS) 5436 * PhyRdy Change Status (PRCS) 5437 * Overflow Status (OFS) 5438 * Interface Non-fatal Error Status (INFS) 5439 * Interface Fatal Error Status (IFS) 5440 * Host Bus Data Error Status (HBDS) 5441 * Host Bus Fatal Error Status (HBFS) 5442 * Task File Error Status (TFES) 5443 */ 5444 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5445 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5446 (AHCI_INTR_STATUS_DHRS | 5447 AHCI_INTR_STATUS_PSS | 5448 AHCI_INTR_STATUS_SDBS | 5449 AHCI_INTR_STATUS_UFS | 5450 AHCI_INTR_STATUS_DPS | 5451 AHCI_INTR_STATUS_PCS | 5452 AHCI_INTR_STATUS_PRCS | 5453 AHCI_INTR_STATUS_OFS | 5454 AHCI_INTR_STATUS_INFS | 5455 AHCI_INTR_STATUS_IFS | 5456 AHCI_INTR_STATUS_HBDS | 5457 AHCI_INTR_STATUS_HBFS | 5458 AHCI_INTR_STATUS_TFES)); 5459} 5460 5461/* 5462 * Enable interrupts for all the ports. 5463 * 5464 * WARNING!!! ahcictl_mutex should be acquired before the function 5465 * is called. 5466 */ 5467static void 5468ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5469{ 5470 uint32_t ghc_control; 5471 5472 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5473 5474 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5475 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5476 5477 ghc_control |= AHCI_HBA_GHC_IE; 5478 5479 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5480 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5481} 5482 5483/* 5484 * Disable interrupts for a particular port. 5485 * 5486 * WARNING!!! ahciport_mutex should be acquired before the function 5487 * is called. 5488 */ 5489static void 5490ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5491{ 5492 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5493 "ahci_disable_port_intrs enter, port %d", port); 5494 5495 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5496 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5497} 5498 5499/* 5500 * Disable interrupts for the whole HBA. 5501 * 5502 * The global bit is cleared, then all interrupt sources from all 5503 * ports are disabled. 5504 * 5505 * WARNING!!! ahcictl_mutex should be acquired before the function 5506 * is called. 5507 */ 5508static void 5509ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5510{ 5511 uint32_t ghc_control; 5512 5513 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5514 5515 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5516 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5517 5518 ghc_control &= ~ AHCI_HBA_GHC_IE; 5519 5520 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5521 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5522} 5523 5524/* 5525 * Handle INTx and legacy interrupts. 5526 */ 5527static int 5528ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5529{ 5530 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5531 int actual, count = 0; 5532 int x, y, rc, inum = 0; 5533 5534 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5535 "ahci_add_legacy_intrs enter"); 5536 5537 /* get number of interrupts. */ 5538 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5539 if ((rc != DDI_SUCCESS) || (count == 0)) { 5540 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5541 "ddi_intr_get_nintrs() failed, " 5542 "rc %d count %d\n", rc, count); 5543 return (DDI_FAILURE); 5544 } 5545 5546 /* Allocate an array of interrupt handles. */ 5547 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5548 ahci_ctlp->ahcictl_intr_htable = 5549 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5550 5551 /* call ddi_intr_alloc(). */ 5552 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5553 DDI_INTR_TYPE_FIXED, 5554 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5555 5556 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5557 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5558 "ddi_intr_alloc() failed, rc %d\n", rc); 5559 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5560 ahci_ctlp->ahcictl_intr_size); 5561 return (DDI_FAILURE); 5562 } 5563 5564 if (actual < count) { 5565 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5566 "Requested: %d, Received: %d", count, actual); 5567 5568 for (x = 0; x < actual; x++) { 5569 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5570 } 5571 5572 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5573 ahci_ctlp->ahcictl_intr_size); 5574 return (DDI_FAILURE); 5575 } 5576 5577 ahci_ctlp->ahcictl_intr_cnt = actual; 5578 5579 /* Get intr priority. */ 5580 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5581 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5582 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5583 "ddi_intr_get_pri() failed"); 5584 5585 for (x = 0; x < actual; x++) { 5586 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5587 } 5588 5589 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5590 ahci_ctlp->ahcictl_intr_size); 5591 return (DDI_FAILURE); 5592 } 5593 5594 /* Test for high level interrupt. */ 5595 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5596 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5597 "ahci_add_legacy_intrs: Hi level intr not supported"); 5598 5599 for (x = 0; x < actual; x++) { 5600 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5601 } 5602 5603 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5604 sizeof (ddi_intr_handle_t)); 5605 5606 return (DDI_FAILURE); 5607 } 5608 5609 /* Call ddi_intr_add_handler(). */ 5610 for (x = 0; x < actual; x++) { 5611 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5612 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5613 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5614 "ddi_intr_add_handler() failed"); 5615 5616 for (y = 0; y < actual; y++) { 5617 (void) ddi_intr_free( 5618 ahci_ctlp->ahcictl_intr_htable[y]); 5619 } 5620 5621 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5622 ahci_ctlp->ahcictl_intr_size); 5623 return (DDI_FAILURE); 5624 } 5625 } 5626 5627 /* Call ddi_intr_enable() for legacy interrupts. */ 5628 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5629 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5630 } 5631 5632 return (DDI_SUCCESS); 5633} 5634 5635/* 5636 * Handle MSI interrupts. 5637 */ 5638static int 5639ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5640{ 5641 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5642 int count, avail, actual; 5643 int x, y, rc, inum = 0; 5644 5645 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5646 "ahci_add_msi_intrs enter"); 5647 5648 /* get number of interrupts. */ 5649 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5650 if ((rc != DDI_SUCCESS) || (count == 0)) { 5651 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5652 "ddi_intr_get_nintrs() failed, " 5653 "rc %d count %d\n", rc, count); 5654 return (DDI_FAILURE); 5655 } 5656 5657 /* get number of available interrupts. */ 5658 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5659 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5660 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5661 "ddi_intr_get_navail() failed, " 5662 "rc %d avail %d\n", rc, avail); 5663 return (DDI_FAILURE); 5664 } 5665 5666#if AHCI_DEBUG 5667 if (avail < count) { 5668 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5669 "ddi_intr_get_nvail returned %d, navail() returned %d", 5670 count, avail); 5671 } 5672#endif 5673 5674 /* Allocate an array of interrupt handles. */ 5675 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5676 ahci_ctlp->ahcictl_intr_htable = 5677 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5678 5679 /* call ddi_intr_alloc(). */ 5680 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5681 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5682 5683 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5684 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5685 "ddi_intr_alloc() failed, rc %d\n", rc); 5686 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5687 ahci_ctlp->ahcictl_intr_size); 5688 return (DDI_FAILURE); 5689 } 5690 5691 /* use interrupt count returned */ 5692#if AHCI_DEBUG 5693 if (actual < count) { 5694 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5695 "Requested: %d, Received: %d", count, actual); 5696 } 5697#endif 5698 5699 ahci_ctlp->ahcictl_intr_cnt = actual; 5700 5701 /* 5702 * Get priority for first msi, assume remaining are all the same. 5703 */ 5704 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5705 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5706 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5707 "ddi_intr_get_pri() failed"); 5708 5709 /* Free already allocated intr. */ 5710 for (y = 0; y < actual; y++) { 5711 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5712 } 5713 5714 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5715 ahci_ctlp->ahcictl_intr_size); 5716 return (DDI_FAILURE); 5717 } 5718 5719 /* Test for high level interrupt. */ 5720 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5721 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5722 "ahci_add_msi_intrs: Hi level intr not supported"); 5723 5724 /* Free already allocated intr. */ 5725 for (y = 0; y < actual; y++) { 5726 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5727 } 5728 5729 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5730 sizeof (ddi_intr_handle_t)); 5731 5732 return (DDI_FAILURE); 5733 } 5734 5735 /* Call ddi_intr_add_handler(). */ 5736 for (x = 0; x < actual; x++) { 5737 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5738 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5739 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5740 "ddi_intr_add_handler() failed"); 5741 5742 /* Free already allocated intr. */ 5743 for (y = 0; y < actual; y++) { 5744 (void) ddi_intr_free( 5745 ahci_ctlp->ahcictl_intr_htable[y]); 5746 } 5747 5748 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5749 ahci_ctlp->ahcictl_intr_size); 5750 return (DDI_FAILURE); 5751 } 5752 } 5753 5754 5755 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5756 &ahci_ctlp->ahcictl_intr_cap); 5757 5758 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5759 /* Call ddi_intr_block_enable() for MSI. */ 5760 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5761 ahci_ctlp->ahcictl_intr_cnt); 5762 } else { 5763 /* Call ddi_intr_enable() for MSI non block enable. */ 5764 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5765 (void) ddi_intr_enable( 5766 ahci_ctlp->ahcictl_intr_htable[x]); 5767 } 5768 } 5769 5770 return (DDI_SUCCESS); 5771} 5772 5773/* 5774 * Removes the registered interrupts irrespective of whether they 5775 * were legacy or MSI. 5776 * 5777 * WARNING!!! The controller interrupts must be disabled before calling 5778 * this routine. 5779 */ 5780static void 5781ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5782{ 5783 int x; 5784 5785 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5786 5787 /* Disable all interrupts. */ 5788 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5789 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5790 /* Call ddi_intr_block_disable(). */ 5791 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5792 ahci_ctlp->ahcictl_intr_cnt); 5793 } else { 5794 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5795 (void) ddi_intr_disable( 5796 ahci_ctlp->ahcictl_intr_htable[x]); 5797 } 5798 } 5799 5800 /* Call ddi_intr_remove_handler(). */ 5801 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5802 (void) ddi_intr_remove_handler( 5803 ahci_ctlp->ahcictl_intr_htable[x]); 5804 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5805 } 5806 5807 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5808} 5809 5810/* 5811 * This routine tries to put port into P:NotRunning state by clearing 5812 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5813 * and PxCMD.CR to '0'. 5814 * 5815 * WARNING!!! ahciport_mutex should be acquired before the function 5816 * is called. 5817 */ 5818static int 5819ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5820 ahci_port_t *ahci_portp, uint8_t port) 5821{ 5822 uint32_t port_cmd_status; 5823 int loop_count; 5824 5825 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5826 "ahci_put_port_into_notrunning_state enter: port %d", port); 5827 5828 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5829 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5830 5831 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5832 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5833 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5834 5835 /* Wait until PxCMD.CR is cleared */ 5836 loop_count = 0; 5837 do { 5838 port_cmd_status = 5839 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5840 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5841 5842 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5843 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5844 "clearing port %d CMD.CR timeout, " 5845 "port_cmd_status = 0x%x", port, 5846 port_cmd_status); 5847 /* 5848 * We are effectively timing out after 0.5 sec. 5849 * This value is specified in AHCI spec. 5850 */ 5851 break; 5852 } 5853 5854 /* Wait for 10 millisec */ 5855 delay(AHCI_10MS_TICKS); 5856 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5857 5858 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5859 5860 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5861 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5862 "ahci_put_port_into_notrunning_state: failed to clear " 5863 "PxCMD.CR to '0' after loop count: %d, and " 5864 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5865 return (AHCI_FAILURE); 5866 } else { 5867 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5868 "ahci_put_port_into_notrunning_state: succeeded to clear " 5869 "PxCMD.CR to '0' after loop count: %d, and " 5870 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5871 return (AHCI_SUCCESS); 5872 } 5873} 5874 5875/* 5876 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5877 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5878 * stable state, then set PxCMD.ST to '1' to start the port directly. 5879 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5880 * COMRESET to the device to put it in an idle state. 5881 * 5882 * The fifth argument returns whether the port reset is involved during 5883 * the process. 5884 * 5885 * The routine will be called under six scenarios: 5886 * 1. Initialize the port 5887 * 2. To abort the packet(s) 5888 * 3. To reset the port 5889 * 4. To activate the port 5890 * 5. Fatal error recovery 5891 * 6. To abort the timeout packet(s) 5892 * 5893 * WARNING!!! ahciport_mutex should be acquired before the function 5894 * is called. And ahciport_mutex will be released before the reset 5895 * event is reported to sata module by calling sata_hba_event_notify, 5896 * and then be acquired again later. 5897 * 5898 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5899 * according to the spec, the clearance of three bits will also clear 5900 * three interrupt status bits. 5901 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5902 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5903 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5904 * 5905 * Among these three interrupt events, the driver needs to take care of 5906 * PxIS.PRCS, which is the hot plug event. When the driver found out 5907 * a device was unplugged, it will call the interrupt handler. 5908 */ 5909static int 5910ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5911 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5912{ 5913 uint32_t port_sstatus; 5914 uint32_t task_file_status; 5915 sata_device_t sdevice; 5916 int rval; 5917 int dev_exists_begin = 0; 5918 int dev_exists_end = 0; 5919 5920 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5921 "ahci_restart_port_wait_till_ready: port %d enter", port); 5922 5923 if ((flag != AHCI_PORT_INIT) && 5924 (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)) 5925 dev_exists_begin = 1; 5926 5927 /* First clear PxCMD.ST */ 5928 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5929 port); 5930 if (rval != AHCI_SUCCESS) 5931 /* 5932 * If PxCMD.CR does not clear within a reasonable time, it 5933 * may assume the interface is in a hung condition and may 5934 * continue with issuing the port reset. 5935 */ 5936 goto reset; 5937 5938 /* Then clear PxSERR */ 5939 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5940 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5941 AHCI_SERROR_CLEAR_ALL); 5942 5943 /* Then get PxTFD */ 5944 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5945 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5946 5947 /* 5948 * Check whether the device is in a stable status, if yes, 5949 * then start the port directly. However for ahci_tran_dport_reset, 5950 * we may have to perform a port reset. 5951 */ 5952 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5953 !(flag & AHCI_PORT_RESET)) 5954 goto out; 5955 5956reset: 5957 /* 5958 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5959 * a COMRESET to the device 5960 */ 5961 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5962 5963 if (reset_flag != NULL) 5964 *reset_flag = 1; 5965 5966 /* Indicate to the framework that a reset has happened. */ 5967 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 5968 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 5969 /* Set the reset in progress flag */ 5970 ahci_portp->ahciport_reset_in_progress = 1; 5971 5972 bzero((void *)&sdevice, sizeof (sata_device_t)); 5973 sdevice.satadev_addr.cport = 5974 ahci_ctlp->ahcictl_port_to_cport[port]; 5975 sdevice.satadev_addr.pmport = 0; 5976 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5977 5978 sdevice.satadev_state = SATA_DSTATE_RESET | 5979 SATA_DSTATE_PWR_ACTIVE; 5980 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5981 mutex_exit(&ahci_portp->ahciport_mutex); 5982 sata_hba_event_notify( 5983 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5984 &sdevice, 5985 SATA_EVNT_DEVICE_RESET); 5986 mutex_enter(&ahci_portp->ahciport_mutex); 5987 } 5988 5989 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5990 "port %d sending event up: SATA_EVNT_RESET", port); 5991 } else { 5992 ahci_portp->ahciport_reset_in_progress = 0; 5993 } 5994 5995out: 5996 /* Start the port if not in initialization phase */ 5997 if (flag & AHCI_PORT_INIT) 5998 return (rval); 5999 6000 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6001 6002 /* SStatus tells the presence of device. */ 6003 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6004 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6005 6006 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6007 dev_exists_end = 1; 6008 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6009 } 6010 6011 /* Check whether a hot plug event happened */ 6012 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6013 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6014 "ahci_restart_port_wait_till_ready: port %d " 6015 "device is removed", port); 6016 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6017 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6018 "ahci_restart_port_wait_till_ready: port %d " 6019 "AHCI_PORT_FLAG_NODEV flag is set", port); 6020 mutex_exit(&ahci_portp->ahciport_mutex); 6021 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6022 mutex_enter(&ahci_portp->ahciport_mutex); 6023 } 6024 6025 return (rval); 6026} 6027 6028/* 6029 * This routine may be called under four scenarios: 6030 * a) do the recovery from fatal error 6031 * b) or we need to timeout some commands 6032 * c) or we need to abort some commands 6033 * d) or we need reset device/port/controller 6034 * 6035 * In all these scenarios, we need to send any pending unfinished 6036 * commands up to sata framework. 6037 * 6038 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6039 */ 6040static void 6041ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6042 ahci_port_t *ahci_portp, 6043 uint32_t slot_status, 6044 uint32_t failed_tags, 6045 uint32_t timeout_tags, 6046 uint32_t aborted_tags, 6047 uint32_t reset_tags) 6048{ 6049 uint32_t finished_tags = 0; 6050 uint32_t unfinished_tags = 0; 6051 int tmp_slot; 6052 sata_pkt_t *satapkt; 6053 int ncq_cmd_in_progress = 0; 6054 int err_retri_cmd_in_progress = 0; 6055 6056 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6057 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6058 ahci_portp->ahciport_port_num, slot_status); 6059 6060 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6061 "ahci_mop_commands: failed_tags: 0x%x, " 6062 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6063 "reset_tags: 0x%x", failed_tags, 6064 timeout_tags, aborted_tags, reset_tags); 6065 6066 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6067 finished_tags = ahci_portp->ahciport_pending_tags & 6068 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6069 6070 unfinished_tags = slot_status & 6071 AHCI_SLOT_MASK(ahci_ctlp) & 6072 ~failed_tags & 6073 ~aborted_tags & 6074 ~reset_tags & 6075 ~timeout_tags; 6076 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6077 ncq_cmd_in_progress = 1; 6078 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6079 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6080 6081 unfinished_tags = slot_status & 6082 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6083 ~failed_tags & 6084 ~aborted_tags & 6085 ~reset_tags & 6086 ~timeout_tags; 6087 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6088 6089 /* 6090 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6091 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6092 * complete successfully due to one of the following three 6093 * conditions: 6094 * 6095 * 1. Fatal error - failed_tags includes its slot 6096 * 2. Timed out - timeout_tags includes its slot 6097 * 3. Aborted when hot unplug - aborted_tags includes its 6098 * slot 6099 * 6100 * Please note that the command is always sent down in Slot 0 6101 */ 6102 err_retri_cmd_in_progress = 1; 6103 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6104 "ahci_mop_commands is called for port %d while " 6105 "REQUEST SENSE or READ LOG EXT for error retrieval " 6106 "is being executed", ahci_portp->ahciport_port_num); 6107 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6108 ASSERT(slot_status == 0x1); 6109 } 6110 6111 /* Send up finished packets with SATA_PKT_COMPLETED */ 6112 while (finished_tags) { 6113 tmp_slot = ddi_ffs(finished_tags) - 1; 6114 if (tmp_slot == -1) { 6115 break; 6116 } 6117 6118 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6119 ASSERT(satapkt != NULL); 6120 6121 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6122 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6123 (void *)satapkt); 6124 6125 /* 6126 * Cannot fetch the return register content since the port 6127 * was restarted, so the corresponding tag will be set to 6128 * aborted tags. 6129 */ 6130 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6131 CLEAR_BIT(finished_tags, tmp_slot); 6132 aborted_tags |= tmp_slot; 6133 continue; 6134 } 6135 6136 if (ncq_cmd_in_progress) 6137 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6138 tmp_slot); 6139 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6140 CLEAR_BIT(finished_tags, tmp_slot); 6141 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6142 6143 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6144 } 6145 6146 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6147 while (failed_tags) { 6148 if (err_retri_cmd_in_progress) { 6149 satapkt = ahci_portp->ahciport_err_retri_pkt; 6150 ASSERT(satapkt != NULL); 6151 ASSERT(failed_tags == 0x1); 6152 6153 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6154 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6155 (void *)satapkt); 6156 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6157 break; 6158 } 6159 6160 tmp_slot = ddi_ffs(failed_tags) - 1; 6161 if (tmp_slot == -1) { 6162 break; 6163 } 6164 6165 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6166 ASSERT(satapkt != NULL); 6167 6168 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6169 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6170 (void *)satapkt); 6171 6172 if (ncq_cmd_in_progress) 6173 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6174 tmp_slot); 6175 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6176 CLEAR_BIT(failed_tags, tmp_slot); 6177 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6178 6179 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6180 } 6181 6182 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6183 while (timeout_tags) { 6184 if (err_retri_cmd_in_progress) { 6185 satapkt = ahci_portp->ahciport_err_retri_pkt; 6186 ASSERT(satapkt != NULL); 6187 ASSERT(timeout_tags == 0x1); 6188 6189 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6190 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6191 (void *)satapkt); 6192 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6193 break; 6194 } 6195 6196 tmp_slot = ddi_ffs(timeout_tags) - 1; 6197 if (tmp_slot == -1) { 6198 break; 6199 } 6200 6201 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6202 ASSERT(satapkt != NULL); 6203 6204 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6205 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6206 (void *)satapkt); 6207 6208 if (ncq_cmd_in_progress) 6209 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6210 tmp_slot); 6211 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6212 CLEAR_BIT(timeout_tags, tmp_slot); 6213 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6214 6215 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6216 } 6217 6218 /* Send up aborted packets with SATA_PKT_ABORTED */ 6219 while (aborted_tags) { 6220 if (err_retri_cmd_in_progress) { 6221 satapkt = ahci_portp->ahciport_err_retri_pkt; 6222 ASSERT(satapkt != NULL); 6223 ASSERT(aborted_tags == 0x1); 6224 6225 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6226 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6227 (void *)satapkt); 6228 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6229 break; 6230 } 6231 6232 tmp_slot = ddi_ffs(aborted_tags) - 1; 6233 if (tmp_slot == -1) { 6234 break; 6235 } 6236 6237 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6238 ASSERT(satapkt != NULL); 6239 6240 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6241 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6242 (void *)satapkt); 6243 6244 if (ncq_cmd_in_progress) 6245 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6246 tmp_slot); 6247 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6248 CLEAR_BIT(aborted_tags, tmp_slot); 6249 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6250 6251 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6252 } 6253 6254 /* Send up reset packets with SATA_PKT_RESET. */ 6255 while (reset_tags) { 6256 tmp_slot = ddi_ffs(reset_tags) - 1; 6257 if (tmp_slot == -1) { 6258 break; 6259 } 6260 6261 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6262 ASSERT(satapkt != NULL); 6263 6264 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6265 "sending up pkt 0x%p with SATA_PKT_RESET", 6266 (void *)satapkt); 6267 6268 if (ncq_cmd_in_progress) 6269 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6270 tmp_slot); 6271 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6272 CLEAR_BIT(reset_tags, tmp_slot); 6273 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6274 6275 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6276 } 6277 6278 /* Send up unfinished packets with SATA_PKT_RESET */ 6279 while (unfinished_tags) { 6280 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6281 if (tmp_slot == -1) { 6282 break; 6283 } 6284 6285 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6286 ASSERT(satapkt != NULL); 6287 6288 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6289 "sending up pkt 0x%p with SATA_PKT_RESET", 6290 (void *)satapkt); 6291 6292 if (ncq_cmd_in_progress) 6293 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6294 tmp_slot); 6295 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6296 CLEAR_BIT(unfinished_tags, tmp_slot); 6297 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6298 6299 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6300 } 6301 6302 ahci_portp->ahciport_mop_in_progress--; 6303 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6304 6305 if (ahci_portp->ahciport_mop_in_progress == 0) 6306 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6307} 6308 6309/* 6310 * This routine is going to first request a READ LOG EXT sata pkt from sata 6311 * module, and then deliver it to the HBA to get the ncq failure context. 6312 * The return value is the exactly failed tags. 6313 */ 6314static uint32_t 6315ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6316 uint8_t port) 6317{ 6318 sata_device_t sdevice; 6319 sata_pkt_t *rdlog_spkt, *spkt; 6320 ddi_dma_handle_t buf_dma_handle; 6321 int loop_count; 6322 int rval; 6323 int failed_slot; 6324 uint32_t failed_tags = 0; 6325 struct sata_ncq_error_recovery_page *ncq_err_page; 6326 6327 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6328 "ahci_get_rdlogext_data enter: port %d", port); 6329 6330 /* Prepare the sdevice data */ 6331 bzero((void *)&sdevice, sizeof (sata_device_t)); 6332 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6333 6334 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6335 sdevice.satadev_addr.pmport = 0; 6336 6337 /* 6338 * Call the sata hba interface to get a rdlog spkt 6339 */ 6340 loop_count = 0; 6341loop: 6342 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6343 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6344 if (rdlog_spkt == NULL) { 6345 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6346 /* Sleep for a while */ 6347 delay(AHCI_10MS_TICKS); 6348 goto loop; 6349 } 6350 /* Timed out after 1s */ 6351 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6352 "failed to get rdlog spkt for port %d", port); 6353 return (failed_tags); 6354 } 6355 6356 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6357 6358 /* 6359 * This flag is used to handle the specific error recovery when the 6360 * READ LOG EXT command gets a failure (fatal error or time-out). 6361 */ 6362 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6363 6364 /* 6365 * This start is not supposed to fail because after port is restarted, 6366 * the whole command list is empty. 6367 */ 6368 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6369 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6370 ahci_portp->ahciport_err_retri_pkt = NULL; 6371 6372 /* Remove the flag after READ LOG EXT command is completed */ 6373 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6374 6375 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6376 /* Update the request log data */ 6377 buf_dma_handle = *(ddi_dma_handle_t *) 6378 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6379 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6380 DDI_DMA_SYNC_FORKERNEL); 6381 if (rval == DDI_SUCCESS) { 6382 ncq_err_page = 6383 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6384 satapkt_cmd.satacmd_bp->b_un.b_addr; 6385 6386 /* Get the failed tag */ 6387 failed_slot = ncq_err_page->ncq_tag; 6388 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6389 "ahci_get_rdlogext_data: port %d " 6390 "failed slot %d", port, failed_slot); 6391 if (failed_slot & NQ) { 6392 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6393 "the failed slot is not a valid tag"); 6394 goto out; 6395 } 6396 6397 failed_slot &= NCQ_TAG_MASK; 6398 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6399 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6400 "ahci_get_rdlogext_data: failed spkt 0x%p", 6401 (void *)spkt); 6402 if (spkt == NULL) { 6403 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6404 "the failed slot spkt is NULL") 6405 goto out; 6406 } 6407 6408 failed_tags = 0x1 << failed_slot; 6409 6410 /* Fill out the error context */ 6411 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6412 ncq_err_page); 6413 ahci_update_sata_registers(ahci_ctlp, port, 6414 &spkt->satapkt_device); 6415 } 6416 } 6417out: 6418 sata_free_error_retrieval_pkt(rdlog_spkt); 6419 6420 return (failed_tags); 6421} 6422 6423/* 6424 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6425 * module, and then deliver it to the HBA to get the sense data and copy 6426 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6427 * SENSE sata pkt later. 6428 */ 6429static void 6430ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6431 uint8_t port, sata_pkt_t *spkt) 6432{ 6433 sata_device_t sdevice; 6434 sata_pkt_t *rs_spkt; 6435 sata_cmd_t *sata_cmd; 6436 ddi_dma_handle_t buf_dma_handle; 6437 int loop_count; 6438#if AHCI_DEBUG 6439 struct scsi_extended_sense *rqsense; 6440#endif 6441 6442 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6443 "ahci_get_rqsense_data enter: port %d", port); 6444 6445 /* Prepare the sdevice data */ 6446 bzero((void *)&sdevice, sizeof (sata_device_t)); 6447 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6448 6449 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6450 sdevice.satadev_addr.pmport = 0; 6451 6452 sata_cmd = &spkt->satapkt_cmd; 6453 6454 /* 6455 * Call the sata hba interface to get a rs spkt 6456 */ 6457 loop_count = 0; 6458loop: 6459 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6460 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6461 if (rs_spkt == NULL) { 6462 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6463 /* Sleep for a while */ 6464 delay(AHCI_10MS_TICKS); 6465 goto loop; 6466 6467 } 6468 /* Timed out after 1s */ 6469 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6470 "failed to get rs spkt for port %d", port); 6471 return; 6472 } 6473 6474 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6475 6476 /* 6477 * This flag is used to handle the specific error recovery when the 6478 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6479 */ 6480 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6481 6482 /* 6483 * This start is not supposed to fail because after port is restarted, 6484 * the whole command list is empty. 6485 */ 6486 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6487 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6488 ahci_portp->ahciport_err_retri_pkt = NULL; 6489 6490 /* Remove the flag after REQUEST SENSE command is completed */ 6491 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6492 6493 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6494 /* Update the request sense data */ 6495 buf_dma_handle = *(ddi_dma_handle_t *) 6496 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6497 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6498 DDI_DMA_SYNC_FORKERNEL); 6499 /* Copy the request sense data */ 6500 bcopy(rs_spkt-> 6501 satapkt_cmd.satacmd_bp->b_un.b_addr, 6502 &sata_cmd->satacmd_rqsense, 6503 SATA_ATAPI_MIN_RQSENSE_LEN); 6504#if AHCI_DEBUG 6505 rqsense = (struct scsi_extended_sense *) 6506 sata_cmd->satacmd_rqsense; 6507 6508 /* Dump the sense data */ 6509 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6510 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6511 "Sense data for satapkt %p ATAPI cmd 0x%x", 6512 spkt, sata_cmd->satacmd_acdb[0]); 6513 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6514 " es_code 0x%x es_class 0x%x " 6515 "es_key 0x%x es_add_code 0x%x " 6516 "es_qual_code 0x%x", 6517 rqsense->es_code, rqsense->es_class, 6518 rqsense->es_key, rqsense->es_add_code, 6519 rqsense->es_qual_code); 6520#endif 6521 } 6522 6523 sata_free_error_retrieval_pkt(rs_spkt); 6524} 6525 6526/* 6527 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6528 * the port must be restarted. When the HBA detects thus error, it may try 6529 * to abort a transfer. And if the transfer was aborted, the device is 6530 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6531 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6532 * that the device is in a stable status and transfers may be restarted without 6533 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6534 * then the software will send the COMRESET to do the port reset. 6535 * 6536 * Software should perform the appropriate error recovery actions based on 6537 * whether non-queued commands were being issued or natived command queuing 6538 * commands were being issued. 6539 * 6540 * And software will complete the command that had the error with error mark 6541 * to higher level software. 6542 * 6543 * Fatal errors include the following: 6544 * PxIS.IFS - Interface Fatal Error Status 6545 * PxIS.HBDS - Host Bus Data Error Status 6546 * PxIS.HBFS - Host Bus Fatal Error Status 6547 * PxIS.TFES - Task File Error Status 6548 * 6549 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6550 */ 6551static void 6552ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6553 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6554{ 6555 uint32_t port_cmd_status; 6556 uint32_t slot_status = 0; 6557 uint32_t failed_tags = 0; 6558 int failed_slot; 6559 int reset_flag = 0; 6560 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6561 sata_cmd_t *sata_cmd = NULL; 6562 sata_pkt_t *spkt = NULL; 6563 6564 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6565 "ahci_fatal_error_recovery_handler enter: port %d", port); 6566 6567 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6568 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6569 6570 /* Read PxCI to see which commands are still outstanding */ 6571 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6572 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6573 6574 /* 6575 * Read PxCMD.CCS to determine the slot that the HBA 6576 * was processing when the error occurred. 6577 */ 6578 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6579 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6580 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6581 AHCI_CMD_STATUS_CCS_SHIFT; 6582 6583 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6584 spkt = ahci_portp->ahciport_err_retri_pkt; 6585 ASSERT(spkt != NULL); 6586 } else { 6587 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6588 if (spkt == NULL) { 6589 /* May happen when interface errors occur? */ 6590 goto next; 6591 } 6592 } 6593 6594 sata_cmd = &spkt->satapkt_cmd; 6595 6596 /* Fill out the status and error registers for PxIS.TFES */ 6597 if (intr_status & AHCI_INTR_STATUS_TFES) { 6598 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6599 ahcirf_d2h_register_fis); 6600 6601 /* Copy the error context back to the sata_cmd */ 6602 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6603 } 6604 6605 /* The failed command must be one of the outstanding commands */ 6606 failed_tags = 0x1 << failed_slot; 6607 ASSERT(failed_tags & slot_status); 6608 6609 /* Update the sata registers, especially PxSERR register */ 6610 ahci_update_sata_registers(ahci_ctlp, port, 6611 &spkt->satapkt_device); 6612 6613 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6614 /* Read PxSACT to see which commands are still outstanding */ 6615 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6616 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6617 } 6618next: 6619 6620#if AHCI_DEBUG 6621 /* 6622 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6623 * set, it means a fatal error happened after REQUEST SENSE command 6624 * or READ LOG EXT command is delivered to the HBA during the error 6625 * recovery process. At this time, the only outstanding command is 6626 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6627 */ 6628 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6629 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6630 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6631 "command or READ LOG EXT command for error data retrieval " 6632 "failed", port); 6633 ASSERT(slot_status == 0x1); 6634 ASSERT(failed_slot == 0x1); 6635 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6636 SCMD_REQUEST_SENSE || 6637 spkt->satapkt_cmd.satacmd_cmd_reg == 6638 SATAC_READ_LOG_EXT); 6639 } 6640#endif 6641 6642 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6643 ahci_portp->ahciport_mop_in_progress++; 6644 6645 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6646 port, NULL, &reset_flag); 6647 6648 /* 6649 * Won't retrieve error information: 6650 * 1. Port reset was involved to recover 6651 * 2. Device is gone 6652 * 3. IDENTIFY DEVICE command sent to ATAPI device 6653 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6654 */ 6655 if (reset_flag || 6656 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6657 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6658 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6659 goto out; 6660 6661 /* 6662 * Deliver READ LOG EXT to gather information about the error when 6663 * a COMRESET has not been performed as part of the error recovery 6664 * during NCQ command processing. 6665 */ 6666 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6667 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6668 ahci_portp, port); 6669 goto out; 6670 } 6671 6672 /* 6673 * Deliver REQUEST SENSE for ATAPI command to gather information about 6674 * the error when a COMRESET has not been performed as part of the 6675 * error recovery. 6676 */ 6677 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6678 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6679out: 6680 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6681 "ahci_fatal_error_recovery_handler: port %d interface error " 6682 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6683 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6684 port, slot_status, ahci_portp->ahciport_pending_tags, 6685 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6686 6687 ahci_mop_commands(ahci_ctlp, 6688 ahci_portp, 6689 slot_status, 6690 failed_tags, /* failed tags */ 6691 0, /* timeout tags */ 6692 0, /* aborted tags */ 6693 0); /* reset tags */ 6694} 6695 6696/* 6697 * Handle events - fatal error recovery 6698 */ 6699static void 6700ahci_events_handler(void *args) 6701{ 6702 ahci_event_arg_t *ahci_event_arg; 6703 ahci_ctl_t *ahci_ctlp; 6704 ahci_port_t *ahci_portp; 6705 uint32_t event; 6706 uint8_t port; 6707 6708 ahci_event_arg = (ahci_event_arg_t *)args; 6709 6710 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6711 ahci_portp = ahci_event_arg->ahciea_portp; 6712 event = ahci_event_arg->ahciea_event; 6713 port = ahci_portp->ahciport_port_num; 6714 6715 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6716 "ahci_events_handler enter: port %d intr_status = 0x%x", 6717 port, event); 6718 6719 mutex_enter(&ahci_portp->ahciport_mutex); 6720 6721 /* 6722 * ahci_intr_phyrdy_change() may have rendered it to 6723 * SATA_DTYPE_NONE. 6724 */ 6725 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6726 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6727 "ahci_events_handler: port %d no device attached, " 6728 "and just return without doing anything", port); 6729 goto out; 6730 } 6731 6732 if (event & (AHCI_INTR_STATUS_IFS | 6733 AHCI_INTR_STATUS_HBDS | 6734 AHCI_INTR_STATUS_HBFS | 6735 AHCI_INTR_STATUS_TFES)) 6736 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6737 port, event); 6738 6739out: 6740 mutex_exit(&ahci_portp->ahciport_mutex); 6741} 6742 6743/* 6744 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6745 * detect there are some commands which are timed out. 6746 */ 6747static void 6748ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6749 uint8_t port, uint32_t tmp_timeout_tags) 6750{ 6751 uint32_t slot_status = 0; 6752 uint32_t finished_tags = 0; 6753 uint32_t timeout_tags = 0; 6754 6755 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6756 "ahci_timeout_pkts enter: port %d", port); 6757 6758 mutex_enter(&ahci_portp->ahciport_mutex); 6759 6760 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6761 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6762 /* Read PxCI to see which commands are still outstanding */ 6763 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6764 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6765 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6766 /* Read PxSACT to see which commands are still outstanding */ 6767 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6768 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6769 } 6770 6771#if AHCI_DEBUG 6772 /* 6773 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6774 * set, it means a fatal error happened after REQUEST SENSE command 6775 * or READ LOG EXT command is delivered to the HBA during the error 6776 * recovery process. At this time, the only outstanding command is 6777 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6778 */ 6779 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6780 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6781 "ahci_timeout_pkts called while REQUEST SENSE " 6782 "command or READ LOG EXT command for error recovery " 6783 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6784 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6785 tmp_timeout_tags, slot_status, 6786 ahci_portp->ahciport_pending_tags, 6787 ahci_portp->ahciport_pending_ncq_tags); 6788 ASSERT(slot_status == 0x1); 6789 } 6790#endif 6791 6792 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6793 ahci_portp->ahciport_mop_in_progress++; 6794 6795 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6796 port, NULL, NULL); 6797 6798 /* 6799 * Re-identify timeout tags because some previously checked commands 6800 * could already complete. 6801 */ 6802 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6803 finished_tags = ahci_portp->ahciport_pending_tags & 6804 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6805 timeout_tags = tmp_timeout_tags & ~finished_tags; 6806 6807 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6808 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6809 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6810 "pending_tags = 0x%x ", 6811 port, finished_tags, timeout_tags, 6812 slot_status, ahci_portp->ahciport_pending_tags); 6813 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6814 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6815 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6816 timeout_tags = tmp_timeout_tags & ~finished_tags; 6817 6818 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6819 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6820 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6821 "pending_ncq_tags = 0x%x ", 6822 port, finished_tags, timeout_tags, 6823 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6824 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6825 timeout_tags = tmp_timeout_tags; 6826 } 6827 6828 ahci_mop_commands(ahci_ctlp, 6829 ahci_portp, 6830 slot_status, 6831 0, /* failed tags */ 6832 timeout_tags, /* timeout tags */ 6833 0, /* aborted tags */ 6834 0); /* reset tags */ 6835 6836 mutex_exit(&ahci_portp->ahciport_mutex); 6837} 6838 6839/* 6840 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6841 * for long time. 6842 */ 6843static void 6844ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6845{ 6846 ahci_port_t *ahci_portp; 6847 sata_pkt_t *spkt; 6848 uint32_t pending_tags; 6849 uint32_t timeout_tags; 6850 uint32_t port_cmd_status; 6851 uint32_t port_sactive; 6852 uint8_t port; 6853 int tmp_slot; 6854 int current_slot; 6855 uint32_t current_tags; 6856 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 6857 /* max number of cycles this packet should survive */ 6858 int max_life_cycles; 6859 6860 /* how many cycles this packet survived so far */ 6861 int watched_cycles; 6862 6863 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6864 6865 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6866 "ahci_watchdog_handler entered"); 6867 6868 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6869 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6870 continue; 6871 } 6872 6873 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6874 6875 mutex_enter(&ahci_portp->ahciport_mutex); 6876 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6877 mutex_exit(&ahci_portp->ahciport_mutex); 6878 continue; 6879 } 6880 6881 /* Skip the check for those ports in error recovery */ 6882 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6883 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6884 mutex_exit(&ahci_portp->ahciport_mutex); 6885 continue; 6886 } 6887 6888 pending_tags = 0; 6889 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6890 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6891 6892 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6893 current_slot = 0; 6894 pending_tags = 0x1; 6895 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6896 current_slot = 6897 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6898 AHCI_CMD_STATUS_CCS_SHIFT; 6899 pending_tags = ahci_portp->ahciport_pending_tags; 6900 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6901 port_sactive = ddi_get32( 6902 ahci_ctlp->ahcictl_ahci_acc_handle, 6903 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6904 current_tags = port_sactive & 6905 ~port_cmd_status & 6906 AHCI_NCQ_SLOT_MASK(ahci_portp); 6907 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6908 } 6909 6910 timeout_tags = 0; 6911 while (pending_tags) { 6912 tmp_slot = ddi_ffs(pending_tags) - 1; 6913 if (tmp_slot == -1) { 6914 break; 6915 } 6916 6917 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6918 spkt = ahci_portp->ahciport_err_retri_pkt; 6919 else 6920 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6921 6922 if ((spkt != NULL) && spkt->satapkt_time && 6923 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6924 /* 6925 * We are overloading satapkt_hba_driver_private 6926 * with watched_cycle count. 6927 * 6928 * If a packet has survived for more than it's 6929 * max life cycles, it is a candidate for time 6930 * out. 6931 */ 6932 watched_cycles = (int)(intptr_t) 6933 spkt->satapkt_hba_driver_private; 6934 watched_cycles++; 6935 max_life_cycles = (spkt->satapkt_time + 6936 ahci_watchdog_timeout - 1) / 6937 ahci_watchdog_timeout; 6938 6939 spkt->satapkt_hba_driver_private = 6940 (void *)(intptr_t)watched_cycles; 6941 6942 if (watched_cycles <= max_life_cycles) 6943 goto next; 6944 6945 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6946 "the current slot is %d", current_slot); 6947 /* 6948 * We need to check whether the HBA has 6949 * begun to execute the command, if not, 6950 * then re-set the timer of the command. 6951 */ 6952 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 6953 (tmp_slot != current_slot) || 6954 NCQ_CMD_IN_PROGRESS(ahci_portp) && 6955 ((0x1 << tmp_slot) & current_tags)) { 6956 spkt->satapkt_hba_driver_private = 6957 (void *)(intptr_t)0; 6958 } else { 6959 timeout_tags |= (0x1 << tmp_slot); 6960 cmn_err(CE_WARN, "!ahci%d: watchdog " 6961 "port %d satapkt 0x%p timed out\n", 6962 instance, port, (void *)spkt); 6963 } 6964 } 6965next: 6966 CLEAR_BIT(pending_tags, tmp_slot); 6967 } 6968 6969 if (timeout_tags) { 6970 mutex_exit(&ahci_portp->ahciport_mutex); 6971 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6972 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 6973 port, timeout_tags); 6974 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6975 mutex_enter(&ahci_portp->ahciport_mutex); 6976 } 6977 6978 mutex_exit(&ahci_portp->ahciport_mutex); 6979 } 6980 6981 /* Re-install the watchdog timeout handler */ 6982 if (ahci_ctlp->ahcictl_timeout_id != 0) { 6983 ahci_ctlp->ahcictl_timeout_id = 6984 timeout((void (*)(void *))ahci_watchdog_handler, 6985 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 6986 } 6987 6988 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6989} 6990 6991/* 6992 * Fill the error context into sata_cmd for non-queued command error. 6993 */ 6994static void 6995ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6996{ 6997 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 6998 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6999 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7000 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7001 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7002 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7003 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7004 7005 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7006 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7007 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7008 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7009 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7010 } 7011} 7012 7013/* 7014 * Fill the ncq error page into sata_cmd for queued command error. 7015 */ 7016static void 7017ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7018 struct sata_ncq_error_recovery_page *ncq_err_page) 7019{ 7020 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7021 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7022 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7023 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7024 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7025 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7026 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7027 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7028 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7029 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7030 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7031} 7032 7033/* 7034 * Put the respective register value to sata_cmd_t for satacmd_flags. 7035 */ 7036static void 7037ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7038{ 7039 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7040 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7041 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7042 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7043 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7044 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7045 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7046 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7047 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7048 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7049 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7050 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7051 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7052 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7053 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7054 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7055 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7056 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7057 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7058 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7059} 7060 7061static void 7062ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7063 uint32_t intr_status) 7064{ 7065 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7066 7067 if (intr_status & AHCI_INTR_STATUS_IFS) 7068 cmn_err(CE_WARN, "ahci%d: ahci port %d has interface fatal " 7069 "error", instance, port); 7070 7071 if (intr_status & AHCI_INTR_STATUS_HBDS) 7072 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus data error", 7073 instance, port); 7074 7075 if (intr_status & AHCI_INTR_STATUS_HBFS) 7076 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus fatal error", 7077 instance, port); 7078 7079 if (intr_status & AHCI_INTR_STATUS_TFES) 7080 cmn_err(CE_WARN, "ahci%d: ahci port %d has task file error", 7081 instance, port); 7082 7083 cmn_err(CE_WARN, "ahci%d: ahci port %d is trying to do error " 7084 "recovery", instance, port); 7085} 7086 7087/* 7088 * Dump the serror message to the log. 7089 */ 7090static void 7091ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7092 uint32_t port_serror, int debug_only) 7093{ 7094 static char err_buf[512]; 7095 static char err_msg_header[16]; 7096 char *err_msg = err_buf; 7097 7098 *err_buf = '\0'; 7099 *err_msg_header = '\0'; 7100 7101 if (port_serror & SERROR_DATA_ERR_FIXED) { 7102 err_msg = strcat(err_msg, 7103 "\tRecovered Data Integrity Error (I)\n"); 7104 } 7105 7106 if (port_serror & SERROR_COMM_ERR_FIXED) { 7107 err_msg = strcat(err_msg, 7108 "\tRecovered Communication Error (M)\n"); 7109 } 7110 7111 if (port_serror & SERROR_DATA_ERR) { 7112 err_msg = strcat(err_msg, 7113 "\tTransient Data Integrity Error (T)\n"); 7114 } 7115 7116 if (port_serror & SERROR_PERSISTENT_ERR) { 7117 err_msg = strcat(err_msg, 7118 "\tPersistent Communication or Data Integrity Error (C)\n"); 7119 } 7120 7121 if (port_serror & SERROR_PROTOCOL_ERR) { 7122 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7123 } 7124 7125 if (port_serror & SERROR_INT_ERR) { 7126 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7127 } 7128 7129 if (port_serror & SERROR_PHY_RDY_CHG) { 7130 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7131 } 7132 7133 if (port_serror & SERROR_PHY_INT_ERR) { 7134 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7135 } 7136 7137 if (port_serror & SERROR_COMM_WAKE) { 7138 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7139 } 7140 7141 if (port_serror & SERROR_10B_TO_8B_ERR) { 7142 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7143 } 7144 7145 if (port_serror & SERROR_DISPARITY_ERR) { 7146 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7147 } 7148 7149 if (port_serror & SERROR_CRC_ERR) { 7150 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7151 } 7152 7153 if (port_serror & SERROR_HANDSHAKE_ERR) { 7154 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7155 } 7156 7157 if (port_serror & SERROR_LINK_SEQ_ERR) { 7158 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7159 } 7160 7161 if (port_serror & SERROR_TRANS_ERR) { 7162 err_msg = strcat(err_msg, 7163 "\tTransport state transition error (T)\n"); 7164 } 7165 7166 if (port_serror & SERROR_FIS_TYPE) { 7167 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7168 } 7169 7170 if (port_serror & SERROR_EXCHANGED_ERR) { 7171 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7172 } 7173 7174 if (err_msg == NULL) 7175 return; 7176 7177 if (debug_only) { 7178 (void) sprintf(err_msg_header, "port %d", port); 7179 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7180 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7181 } else if (ahci_ctlp) { 7182 cmn_err(CE_WARN, "ahci%d: %s %s", 7183 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7184 err_msg_header, err_msg); 7185 } else { 7186 cmn_err(CE_WARN, "ahci: %s %s", err_msg_header, err_msg); 7187 } 7188} 7189 7190/* 7191 * This routine is to calculate the total number of ports implemented 7192 * by the HBA. 7193 */ 7194static int 7195ahci_get_num_implemented_ports(uint32_t ports_implemented) 7196{ 7197 uint8_t i; 7198 int num = 0; 7199 7200 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7201 if (((uint32_t)0x1 << i) & ports_implemented) 7202 num++; 7203 } 7204 7205 return (num); 7206} 7207 7208#if AHCI_DEBUG 7209static void 7210ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7211{ 7212 static char name[16]; 7213 va_list ap; 7214 7215 mutex_enter(&ahci_log_mutex); 7216 7217 va_start(ap, fmt); 7218 if (ahci_ctlp) { 7219 (void) sprintf(name, "ahci%d: ", 7220 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7221 } else { 7222 (void) sprintf(name, "ahci: "); 7223 } 7224 7225 (void) vsprintf(ahci_log_buf, fmt, ap); 7226 va_end(ap); 7227 7228 cmn_err(level, "%s%s", name, ahci_log_buf); 7229 7230 mutex_exit(&ahci_log_mutex); 7231} 7232#endif 7233