ahci.c revision 6272:9d192cddb541
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 * 32 * Power Management Support 33 * ------------------------ 34 * 35 * At the moment, the ahci driver only implements suspend/resume to 36 * support Suspend to RAM on X86 feature. Device power management isn't 37 * implemented, link power management is disabled, and hot plug isn't 38 * allowed during the period from suspend to resume. 39 * 40 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 41 * and DDI_RESUME entries, and don't need to take care of new requests 42 * sent down after suspend because the target driver (sd) has already 43 * handled these conditions, and blocked these requests. For the detailed 44 * information, please check with sdopen, sdclose and sdioctl routines. 45 * 46 */ 47 48#include <sys/scsi/scsi.h> 49#include <sys/pci.h> 50#include <sys/sata/sata_hba.h> 51#include <sys/sata/adapters/ahci/ahcireg.h> 52#include <sys/sata/adapters/ahci/ahcivar.h> 53 54/* 55 * Function prototypes for driver entry points 56 */ 57static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 58static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 59static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 60 61/* 62 * Function prototypes for SATA Framework interfaces 63 */ 64static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 65static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 66 67static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 68static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 69static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 70static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 71static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 72static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 73#if defined(__lock_lint) 74static int ahci_selftest(dev_info_t *, sata_device_t *); 75#endif 76 77/* 78 * Local function prototypes 79 */ 80static int ahci_alloc_ports_state(ahci_ctl_t *); 81static void ahci_dealloc_ports_state(ahci_ctl_t *); 82static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 83static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 84static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 85static void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 86static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 87static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 88static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 89static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 90 91static int ahci_initialize_controller(ahci_ctl_t *); 92static void ahci_uninitialize_controller(ahci_ctl_t *); 93static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 94static int ahci_config_space_init(ahci_ctl_t *); 95 96static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 97static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 98static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 99static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 100static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 101 uint8_t, sata_pkt_t *); 102static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 103 uint8_t, sata_pkt_t *); 104static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 105static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 106static void ahci_copy_ncq_err_page(sata_cmd_t *, 107 struct sata_ncq_error_recovery_page *); 108static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 109 110static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 111static int ahci_hba_reset(ahci_ctl_t *); 112static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 113static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 114static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 115static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 116static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 117static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 118 uint8_t); 119static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 120 uint8_t, int, int *); 121static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 122 uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 123static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 124static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 125 uint8_t, sata_pkt_t *); 126static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 127 uint8_t, uint32_t); 128static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 129 uint8_t, uint32_t); 130static void ahci_events_handler(void *); 131static void ahci_watchdog_handler(ahci_ctl_t *); 132 133static uint_t ahci_intr(caddr_t, caddr_t); 134static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 135static int ahci_add_legacy_intrs(ahci_ctl_t *); 136static int ahci_add_msi_intrs(ahci_ctl_t *); 137static void ahci_rem_intrs(ahci_ctl_t *); 138static void ahci_enable_all_intrs(ahci_ctl_t *); 139static void ahci_disable_all_intrs(ahci_ctl_t *); 140static void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 141static void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 142 143static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t, 144 uint32_t); 145static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 146static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 147static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 148 ahci_port_t *, uint8_t); 149static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 150static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 151 uint8_t, uint32_t); 152static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 153 uint8_t, uint32_t); 154static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 155 156static int ahci_get_num_implemented_ports(uint32_t); 157static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 158 uint32_t); 159static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t); 160static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 161 162 163/* 164 * DMA attributes for the data buffer 165 * 166 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 167 * does not support 64-bit addressing 168 */ 169static ddi_dma_attr_t buffer_dma_attr = { 170 DMA_ATTR_V0, /* dma_attr_version */ 171 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 172 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 173 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 174 0x2ull, /* dma_attr_align: word aligned */ 175 1, /* dma_attr_burstsizes */ 176 1, /* dma_attr_minxfer */ 177 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 178 0xffffffffull, /* dma_attr_seg */ 179 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 180 512, /* dma_attr_granular */ 181 0, /* dma_attr_flags */ 182}; 183 184/* 185 * DMA attributes for the rcvd FIS 186 * 187 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 188 * does not support 64-bit addressing 189 */ 190static ddi_dma_attr_t rcvd_fis_dma_attr = { 191 DMA_ATTR_V0, /* dma_attr_version */ 192 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 193 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 194 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 195 0x100ull, /* dma_attr_align: 256-byte aligned */ 196 1, /* dma_attr_burstsizes */ 197 1, /* dma_attr_minxfer */ 198 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 199 0xffffffffull, /* dma_attr_seg */ 200 1, /* dma_attr_sgllen */ 201 1, /* dma_attr_granular */ 202 0, /* dma_attr_flags */ 203}; 204 205/* 206 * DMA attributes for the command list 207 * 208 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 209 * does not support 64-bit addressing 210 */ 211static ddi_dma_attr_t cmd_list_dma_attr = { 212 DMA_ATTR_V0, /* dma_attr_version */ 213 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 214 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 215 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 216 0x400ull, /* dma_attr_align: 1K-byte aligned */ 217 1, /* dma_attr_burstsizes */ 218 1, /* dma_attr_minxfer */ 219 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 220 0xffffffffull, /* dma_attr_seg */ 221 1, /* dma_attr_sgllen */ 222 1, /* dma_attr_granular */ 223 0, /* dma_attr_flags */ 224}; 225 226/* 227 * DMA attributes for cmd tables 228 * 229 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 230 * does not support 64-bit addressing 231 */ 232static ddi_dma_attr_t cmd_table_dma_attr = { 233 DMA_ATTR_V0, /* dma_attr_version */ 234 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 235 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 236 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 237 0x80ull, /* dma_attr_align: 128-byte aligned */ 238 1, /* dma_attr_burstsizes */ 239 1, /* dma_attr_minxfer */ 240 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 241 0xffffffffull, /* dma_attr_seg */ 242 1, /* dma_attr_sgllen */ 243 1, /* dma_attr_granular */ 244 0, /* dma_attr_flags */ 245}; 246 247 248/* Device access attributes */ 249static ddi_device_acc_attr_t accattr = { 250 DDI_DEVICE_ATTR_V0, 251 DDI_STRUCTURE_LE_ACC, 252 DDI_STRICTORDER_ACC 253}; 254 255 256static struct dev_ops ahcictl_dev_ops = { 257 DEVO_REV, /* devo_rev */ 258 0, /* refcnt */ 259 ahci_getinfo, /* info */ 260 nulldev, /* identify */ 261 nulldev, /* probe */ 262 ahci_attach, /* attach */ 263 ahci_detach, /* detach */ 264 nodev, /* no reset */ 265 (struct cb_ops *)0, /* driver operations */ 266 NULL, /* bus operations */ 267 NULL /* power */ 268}; 269 270static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 271 SATA_TRAN_HOTPLUG_OPS_REV_1, 272 ahci_tran_hotplug_port_activate, 273 ahci_tran_hotplug_port_deactivate 274}; 275 276extern struct mod_ops mod_driverops; 277 278static struct modldrv modldrv = { 279 &mod_driverops, /* driverops */ 280 "ahci driver %I%", 281 &ahcictl_dev_ops, /* driver ops */ 282}; 283 284static struct modlinkage modlinkage = { 285 MODREV_1, 286 &modldrv, 287 NULL 288}; 289 290static int ahci_watchdog_timeout = 5; /* 5 seconds */ 291static int ahci_watchdog_tick; 292 293/* The following is needed for ahci_log() */ 294static kmutex_t ahci_log_mutex; 295static char ahci_log_buf[512]; 296 297static size_t ahci_cmd_table_size; 298 299/* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 300int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 301 302/* 303 * AHCI MSI tunable: 304 * 305 * MSI will be enabled in phase 2. 306 */ 307boolean_t ahci_msi_enabled = B_FALSE; 308 309#if AHCI_DEBUG 310uint32_t ahci_debug_flags = 0; 311#endif 312 313/* Opaque state pointer initialized by ddi_soft_state_init() */ 314static void *ahci_statep = NULL; 315 316/* 317 * ahci module initialization. 318 */ 319int 320_init(void) 321{ 322 int ret; 323 324 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 325 if (ret != 0) { 326 goto err_out; 327 } 328 329 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 330 331 if ((ret = sata_hba_init(&modlinkage)) != 0) { 332 mutex_destroy(&ahci_log_mutex); 333 ddi_soft_state_fini(&ahci_statep); 334 goto err_out; 335 } 336 337 ret = mod_install(&modlinkage); 338 if (ret != 0) { 339 sata_hba_fini(&modlinkage); 340 mutex_destroy(&ahci_log_mutex); 341 ddi_soft_state_fini(&ahci_statep); 342 goto err_out; 343 } 344 345 /* watchdog tick */ 346 ahci_watchdog_tick = drv_usectohz( 347 (clock_t)ahci_watchdog_timeout * 1000000); 348 return (ret); 349 350err_out: 351 cmn_err(CE_WARN, "!Module init failed"); 352 return (ret); 353} 354 355/* 356 * ahci module uninitialize. 357 */ 358int 359_fini(void) 360{ 361 int ret; 362 363 ret = mod_remove(&modlinkage); 364 if (ret != 0) { 365 return (ret); 366 } 367 368 /* Remove the resources allocated in _init(). */ 369 sata_hba_fini(&modlinkage); 370 mutex_destroy(&ahci_log_mutex); 371 ddi_soft_state_fini(&ahci_statep); 372 373 return (ret); 374} 375 376/* 377 * _info entry point 378 */ 379int 380_info(struct modinfo *modinfop) 381{ 382 return (mod_info(&modlinkage, modinfop)); 383} 384 385/* 386 * The attach entry point for dev_ops. 387 */ 388static int 389ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 390{ 391 ahci_ctl_t *ahci_ctlp; 392 int instance = ddi_get_instance(dip); 393 int status; 394 int attach_state; 395 uint32_t cap_status, ahci_version; 396 int intr_types; 397 int i; 398 pci_regspec_t *regs; 399 int regs_length; 400 int rnumber; 401#if AHCI_DEBUG 402 int speed; 403#endif 404 405 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 406 407 switch (cmd) { 408 case DDI_ATTACH: 409 break; 410 411 case DDI_RESUME: 412 413 /* 414 * During DDI_RESUME, the hardware state of the device 415 * (power may have been removed from the device) must be 416 * restored, allow pending requests to continue, and 417 * service new requests. 418 */ 419 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 420 mutex_enter(&ahci_ctlp->ahcictl_mutex); 421 422 /* Restart watch thread */ 423 if (ahci_ctlp->ahcictl_timeout_id == 0) 424 ahci_ctlp->ahcictl_timeout_id = timeout( 425 (void (*)(void *))ahci_watchdog_handler, 426 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 427 428 mutex_exit(&ahci_ctlp->ahcictl_mutex); 429 430 /* 431 * Re-initialize the controller and enable the interrupts and 432 * restart all the ports. 433 * 434 * Note that so far we don't support hot-plug during 435 * suspend/resume. 436 */ 437 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 438 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 439 "ahci%d: Failed to initialize the controller " 440 "during DDI_RESUME", instance); 441 return (DDI_FAILURE); 442 } 443 444 mutex_enter(&ahci_ctlp->ahcictl_mutex); 445 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 446 mutex_exit(&ahci_ctlp->ahcictl_mutex); 447 448 return (DDI_SUCCESS); 449 450 default: 451 return (DDI_FAILURE); 452 } 453 454 attach_state = AHCI_ATTACH_STATE_NONE; 455 456 /* Allocate soft state */ 457 status = ddi_soft_state_zalloc(ahci_statep, instance); 458 if (status != DDI_SUCCESS) { 459 cmn_err(CE_WARN, "!Cannot allocate soft state"); 460 goto err_out; 461 } 462 463 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 464 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 465 ahci_ctlp->ahcictl_dip = dip; 466 467 /* Initialize the cport/port mapping */ 468 for (i = 0; i < AHCI_MAX_PORTS; i++) { 469 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 470 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 471 } 472 473 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 474 475 /* 476 * Now map the AHCI base address; which includes global 477 * registers and port control registers 478 * 479 * According to the spec, the AHCI Base Address is BAR5, 480 * but BAR0-BAR4 are optional, so we need to check which 481 * rnumber is used for BAR5. 482 */ 483 484 /* 485 * search through DDI "reg" property for the AHCI register set 486 */ 487 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 488 DDI_PROP_DONTPASS, "reg", (int **)®s, 489 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 490 cmn_err(CE_WARN, "!Cannot lookup reg property"); 491 goto err_out; 492 } 493 494 /* AHCI Base Address is located at 0x24 offset */ 495 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 496 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 497 == AHCI_PCI_RNUM) 498 break; 499 } 500 501 ddi_prop_free(regs); 502 503 if (rnumber == regs_length) { 504 cmn_err(CE_WARN, "!Cannot find AHCI register set"); 505 goto err_out; 506 } 507 508 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 509 510 status = ddi_regs_map_setup(dip, 511 rnumber, 512 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 513 0, 514 0, 515 &accattr, 516 &ahci_ctlp->ahcictl_ahci_acc_handle); 517 if (status != DDI_SUCCESS) { 518 cmn_err(CE_WARN, "!Cannot map register space"); 519 goto err_out; 520 } 521 522 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 523 524 /* Get the AHCI version information */ 525 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 526 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 527 528 cmn_err(CE_NOTE, "!hba AHCI version = %x.%x", 529 (ahci_version & 0xffff0000) >> 16, 530 ((ahci_version & 0x0000ff00) >> 4 | 531 (ahci_version & 0x000000ff))); 532 533 /* We don't support controllers whose versions are lower than 1.0 */ 534 if (!(ahci_version & 0xffff0000)) { 535 cmn_err(CE_WARN, "Don't support AHCI HBA with lower than " 536 "version 1.0"); 537 goto err_out; 538 } 539 540 /* Get the HBA capabilities information */ 541 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 542 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 543 544 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 545 cap_status); 546 547#if AHCI_DEBUG 548 /* Get the interface speed supported by the HBA */ 549 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 550 if (speed == 0x01) { 551 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 552 "hba interface speed support: Gen 1 (1.5Gbps)"); 553 } else if (speed == 0x10) { 554 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 555 "hba interface speed support: Gen 2 (3 Gbps)"); 556 } else if (speed == 0x11) { 557 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 558 "hba interface speed support: Gen 3 (6 Gbps)"); 559 } 560#endif 561 562 /* Get the number of command slots supported by the HBA */ 563 ahci_ctlp->ahcictl_num_cmd_slots = 564 ((cap_status & AHCI_HBA_CAP_NCS) >> 565 AHCI_HBA_CAP_NCS_SHIFT) + 1; 566 567 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 568 ahci_ctlp->ahcictl_num_cmd_slots); 569 570 /* Get the bit map which indicates ports implemented by the HBA */ 571 ahci_ctlp->ahcictl_ports_implemented = 572 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 573 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 574 575 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 576 ahci_ctlp->ahcictl_ports_implemented); 577 578 /* 579 * According to the AHCI spec, CAP.NP should indicate the maximum 580 * number of ports supported by the HBA silicon, but we found 581 * this value of ICH8 chipset only indicates the number of ports 582 * implemented (exposed) by it. Therefore, the driver should calculate 583 * the potential maximum value by checking PI register, and use 584 * the maximum of this value and CAP.NP. 585 */ 586 ahci_ctlp->ahcictl_num_ports = max( 587 (cap_status & AHCI_HBA_CAP_NP) + 1, 588 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 589 590 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 591 ahci_ctlp->ahcictl_num_ports); 592 593 /* Get the number of implemented ports by the HBA */ 594 ahci_ctlp->ahcictl_num_implemented_ports = 595 ahci_get_num_implemented_ports( 596 ahci_ctlp->ahcictl_ports_implemented); 597 598 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 599 "hba number of implemented ports: %d", 600 ahci_ctlp->ahcictl_num_implemented_ports); 601 602 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 603 604 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 605 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 606 "hba does not support 64-bit addressing"); 607 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 608 0xffffffffull; 609 } 610 611 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 612 != DDI_SUCCESS) { 613 cmn_err(CE_WARN, "!Cannot set up pci configure space"); 614 goto err_out; 615 } 616 617 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 618 619 /* Check the pci configuration space, and set caps */ 620 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 621 cmn_err(CE_WARN, "!ahci_config_space_init failed"); 622 goto err_out; 623 } 624 625 /* 626 * Disable the whole controller interrupts before adding 627 * interrupt handlers(s). 628 */ 629 ahci_disable_all_intrs(ahci_ctlp); 630 631 /* Get supported interrupt types */ 632 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 633 cmn_err(CE_WARN, "!ddi_intr_get_supported_types failed"); 634 goto err_out; 635 } 636 637 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 638 "ddi_intr_get_supported_types() returned: 0x%x", 639 intr_types); 640 641 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 642 /* 643 * Try MSI first, but fall back to FIXED if failed 644 */ 645 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 646 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 647 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 648 "Using MSI interrupt type"); 649 goto intr_done; 650 } 651 652 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 653 "MSI registration failed, " 654 "trying FIXED interrupts"); 655 } 656 657 if (intr_types & DDI_INTR_TYPE_FIXED) { 658 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 659 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 660 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, NULL, 661 "Using FIXED interrupt type"); 662 goto intr_done; 663 } 664 665 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 666 "FIXED interrupt registration failed"); 667 } 668 669 cmn_err(CE_WARN, "!Interrupt registration failed"); 670 671 goto err_out; 672 673intr_done: 674 675 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 676 677 /* Initialize the controller mutex */ 678 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 679 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 680 681 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 682 683 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 684 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 685 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 686 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 687 } 688 689 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 690 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 691 sizeof (ahci_prdt_item_t)); 692 693 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 694 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 695 " ahci_cmd_table_size is 0x%x", 696 ahci_dma_prdt_number, ahci_cmd_table_size); 697 698 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 699 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 700 ahci_dma_prdt_number; 701 702 /* Allocate the ports structure */ 703 status = ahci_alloc_ports_state(ahci_ctlp); 704 if (status != AHCI_SUCCESS) { 705 cmn_err(CE_WARN, "!Cannot allocate ports structure"); 706 goto err_out; 707 } 708 709 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 710 711 /* 712 * A taskq is created for dealing with events 713 */ 714 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 715 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 716 cmn_err(CE_WARN, "!ddi_taskq_create failed for event handle"); 717 goto err_out; 718 } 719 720 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 721 722 /* 723 * Initialize the controller and ports. 724 */ 725 status = ahci_initialize_controller(ahci_ctlp); 726 if (status != AHCI_SUCCESS) { 727 cmn_err(CE_WARN, "!HBA initialization failed"); 728 goto err_out; 729 } 730 731 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 732 733 /* Start one thread to check packet timeouts */ 734 ahci_ctlp->ahcictl_timeout_id = timeout( 735 (void (*)(void *))ahci_watchdog_handler, 736 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 737 738 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 739 740 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 741 cmn_err(CE_WARN, "!sata hba tran registration failed"); 742 goto err_out; 743 } 744 745 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 746 747 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 748 749 return (DDI_SUCCESS); 750 751err_out: 752 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 753 mutex_enter(&ahci_ctlp->ahcictl_mutex); 754 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 755 ahci_ctlp->ahcictl_timeout_id = 0; 756 mutex_exit(&ahci_ctlp->ahcictl_mutex); 757 } 758 759 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 760 ahci_uninitialize_controller(ahci_ctlp); 761 } 762 763 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 764 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 765 } 766 767 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 768 ahci_dealloc_ports_state(ahci_ctlp); 769 } 770 771 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 772 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 773 } 774 775 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 776 ahci_rem_intrs(ahci_ctlp); 777 } 778 779 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 780 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 781 } 782 783 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 784 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 785 } 786 787 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 788 ddi_soft_state_free(ahci_statep, instance); 789 } 790 791 return (DDI_FAILURE); 792} 793 794/* 795 * The detach entry point for dev_ops. 796 */ 797static int 798ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 799{ 800 ahci_ctl_t *ahci_ctlp; 801 int instance; 802 int ret; 803 804 instance = ddi_get_instance(dip); 805 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 806 807 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 808 809 switch (cmd) { 810 case DDI_DETACH: 811 812 /* disable the interrupts for an uninterrupted detach */ 813 mutex_enter(&ahci_ctlp->ahcictl_mutex); 814 ahci_disable_all_intrs(ahci_ctlp); 815 mutex_exit(&ahci_ctlp->ahcictl_mutex); 816 817 /* unregister from the sata framework. */ 818 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 819 if (ret != AHCI_SUCCESS) { 820 mutex_enter(&ahci_ctlp->ahcictl_mutex); 821 ahci_enable_all_intrs(ahci_ctlp); 822 mutex_exit(&ahci_ctlp->ahcictl_mutex); 823 return (DDI_FAILURE); 824 } 825 826 mutex_enter(&ahci_ctlp->ahcictl_mutex); 827 828 /* stop the watchdog handler */ 829 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 830 ahci_ctlp->ahcictl_timeout_id = 0; 831 832 mutex_exit(&ahci_ctlp->ahcictl_mutex); 833 834 /* uninitialize the controller */ 835 ahci_uninitialize_controller(ahci_ctlp); 836 837 /* remove the interrupts */ 838 ahci_rem_intrs(ahci_ctlp); 839 840 /* destroy the taskq */ 841 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 842 843 /* deallocate the ports structures */ 844 ahci_dealloc_ports_state(ahci_ctlp); 845 846 /* destroy mutex */ 847 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 848 849 /* teardown the pci config */ 850 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 851 852 /* remove the reg maps. */ 853 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 854 855 /* free the soft state. */ 856 ddi_soft_state_free(ahci_statep, instance); 857 858 return (DDI_SUCCESS); 859 860 case DDI_SUSPEND: 861 862 /* 863 * The steps associated with suspension must include putting 864 * the underlying device into a quiescent state so that it 865 * will not generate interrupts or modify or access memory. 866 */ 867 mutex_enter(&ahci_ctlp->ahcictl_mutex); 868 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 869 mutex_exit(&ahci_ctlp->ahcictl_mutex); 870 return (DDI_SUCCESS); 871 } 872 873 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 874 875 /* stop the watchdog handler */ 876 if (ahci_ctlp->ahcictl_timeout_id) { 877 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 878 ahci_ctlp->ahcictl_timeout_id = 0; 879 } 880 881 mutex_exit(&ahci_ctlp->ahcictl_mutex); 882 883 /* 884 * drain the taskq 885 */ 886 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 887 888 /* 889 * Disable the interrupts and stop all the ports. 890 */ 891 ahci_uninitialize_controller(ahci_ctlp); 892 893 return (DDI_SUCCESS); 894 895 default: 896 return (DDI_FAILURE); 897 } 898} 899 900/* 901 * The info entry point for dev_ops. 902 * 903 */ 904static int 905ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 906 void *arg, void **result) 907{ 908#ifndef __lock_lint 909 _NOTE(ARGUNUSED(dip)) 910#endif /* __lock_lint */ 911 912 ahci_ctl_t *ahci_ctlp; 913 int instance; 914 dev_t dev; 915 916 dev = (dev_t)arg; 917 instance = getminor(dev); 918 919 switch (infocmd) { 920 case DDI_INFO_DEVT2DEVINFO: 921 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 922 if (ahci_ctlp != NULL) { 923 *result = ahci_ctlp->ahcictl_dip; 924 return (DDI_SUCCESS); 925 } else { 926 *result = NULL; 927 return (DDI_FAILURE); 928 } 929 case DDI_INFO_DEVT2INSTANCE: 930 *(int *)result = instance; 931 break; 932 default: 933 break; 934 } 935 936 return (DDI_SUCCESS); 937} 938 939/* 940 * Registers the ahci with sata framework. 941 */ 942static int 943ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 944{ 945 struct sata_hba_tran *sata_hba_tran; 946 947 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 948 "ahci_register_sata_hba_tran enter"); 949 950 mutex_enter(&ahci_ctlp->ahcictl_mutex); 951 952 /* Allocate memory for the sata_hba_tran */ 953 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 954 955 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 956 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 957 sata_hba_tran->sata_tran_hba_dma_attr = 958 &ahci_ctlp->ahcictl_buffer_dma_attr; 959 960 /* Report the number of implemented ports */ 961 sata_hba_tran->sata_tran_hba_num_cports = 962 ahci_ctlp->ahcictl_num_implemented_ports; 963 964 /* Support ATAPI device */ 965 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 966 967 /* Get the data transfer capability for PIO command by the HBA */ 968 if (cap_status & AHCI_HBA_CAP_PMD) { 969 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 970 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 971 "DRQ block data transfer for PIO command protocol"); 972 } else { 973 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 974 "DRQ block data transfer for PIO command protocol"); 975 } 976 977 /* 978 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 979 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 980 * QUEUED (EXT), and SERVICE commands). Queued operations are 981 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 982 * QUEUED commands when the HBA and device support native command 983 * queuing(NCQ). 984 * 985 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 986 * CAP register of the HBA indicates NCQ is supported. 987 * 988 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 989 * set because the previous register content of PxCI can be re-written 990 * in the register write. 991 */ 992 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 993 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 994 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 995 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 996 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 997 "Command Queuing"); 998 } 999 1000 /* Report the number of command slots */ 1001 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1002 1003 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1004 sata_hba_tran->sata_tran_start = ahci_tran_start; 1005 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1006 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1007 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1008#ifdef __lock_lint 1009 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1010#endif 1011 /* 1012 * When SATA framework adds support for pwrmgt the 1013 * pwrmgt_ops needs to be updated 1014 */ 1015 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1016 sata_hba_tran->sata_tran_ioctl = NULL; 1017 1018 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1019 1020 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1021 1022 /* Attach it to SATA framework */ 1023 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1024 != DDI_SUCCESS) { 1025 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1026 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1027 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1028 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1029 return (AHCI_FAILURE); 1030 } 1031 1032 return (AHCI_SUCCESS); 1033} 1034 1035/* 1036 * Unregisters the ahci with sata framework. 1037 */ 1038static int 1039ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1040{ 1041 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1042 "ahci_unregister_sata_hba_tran enter"); 1043 1044 /* Detach from the SATA framework. */ 1045 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1046 DDI_SUCCESS) { 1047 return (AHCI_FAILURE); 1048 } 1049 1050 /* Deallocate sata_hba_tran. */ 1051 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1052 sizeof (sata_hba_tran_t)); 1053 1054 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1055 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1056 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1057 1058 return (AHCI_SUCCESS); 1059} 1060 1061/* 1062 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1063 * port status registers and an attached device type via sata_device 1064 * structure. 1065 * 1066 * We return the cached information from a previous hardware probe. The 1067 * actual hardware probing itself was done either from within 1068 * ahci_initialize_controller() during the driver attach or from a phy 1069 * ready change interrupt handler. 1070 */ 1071static int 1072ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1073{ 1074 ahci_ctl_t *ahci_ctlp; 1075 ahci_port_t *ahci_portp; 1076 uint8_t cport = sd->satadev_addr.cport; 1077 uint8_t pmport = sd->satadev_addr.pmport; 1078 uint8_t qual = sd->satadev_addr.qual; 1079 uint8_t device_type; 1080 uint32_t port_state; 1081 uint8_t port; 1082 1083 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1084 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1085 1086 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1087 "ahci_tran_probe_port enter: cport: %d, " 1088 "pmport: %d, qual: %d", cport, pmport, qual); 1089 1090 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1091 1092 mutex_enter(&ahci_portp->ahciport_mutex); 1093 1094 port_state = ahci_portp->ahciport_port_state; 1095 switch (port_state) { 1096 1097 case SATA_PSTATE_FAILED: 1098 sd->satadev_state = SATA_PSTATE_FAILED; 1099 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1100 "ahci_tran_probe_port: port %d PORT FAILED", port); 1101 goto out; 1102 1103 case SATA_PSTATE_SHUTDOWN: 1104 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1105 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1106 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1107 goto out; 1108 1109 case SATA_PSTATE_PWROFF: 1110 sd->satadev_state = SATA_PSTATE_PWROFF; 1111 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1112 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1113 goto out; 1114 1115 case SATA_PSTATE_PWRON: 1116 sd->satadev_state = SATA_PSTATE_PWRON; 1117 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1118 "ahci_tran_probe_port: port %d PORT PWRON", port); 1119 break; 1120 1121 default: 1122 sd->satadev_state = port_state; 1123 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1124 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1125 port, port_state); 1126 break; 1127 } 1128 1129 device_type = ahci_portp->ahciport_device_type; 1130 1131 switch (device_type) { 1132 1133 case SATA_DTYPE_ATADISK: 1134 sd->satadev_type = SATA_DTYPE_ATADISK; 1135 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1136 "ahci_tran_probe_port: port %d DISK found", port); 1137 break; 1138 1139 case SATA_DTYPE_ATAPICD: 1140 sd->satadev_type = SATA_DTYPE_ATAPICD; 1141 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1142 "ahci_tran_probe_port: port %d ATAPI found", port); 1143 break; 1144 1145 case SATA_DTYPE_PMULT: 1146 sd->satadev_type = SATA_DTYPE_PMULT; 1147 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1148 "ahci_tran_probe_port: port %d Port Multiplier found", 1149 port); 1150 break; 1151 1152 case SATA_DTYPE_UNKNOWN: 1153 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1154 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1155 "ahci_tran_probe_port: port %d Unknown device found", port); 1156 break; 1157 1158 default: 1159 /* we don't support any other device types */ 1160 sd->satadev_type = SATA_DTYPE_NONE; 1161 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1162 "ahci_tran_probe_port: port %d No device found", port); 1163 break; 1164 } 1165 1166out: 1167 ahci_update_sata_registers(ahci_ctlp, port, sd); 1168 mutex_exit(&ahci_portp->ahciport_mutex); 1169 1170 return (SATA_SUCCESS); 1171} 1172 1173/* 1174 * There are four operation modes in sata framework: 1175 * SATA_OPMODE_INTERRUPTS 1176 * SATA_OPMODE_POLLING 1177 * SATA_OPMODE_ASYNCH 1178 * SATA_OPMODE_SYNCH 1179 * 1180 * Their combined meanings as following: 1181 * 1182 * SATA_OPMODE_SYNCH 1183 * The command has to be completed before sata_tran_start functions returns. 1184 * Either interrupts or polling could be used - it's up to the driver. 1185 * Mode used currently for internal, sata-module initiated operations. 1186 * 1187 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1188 * It is the same as the one above. 1189 * 1190 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1191 * The command has to be completed before sata_tran_start function returns. 1192 * No interrupt used, polling only. This should be the mode used for scsi 1193 * packets with FLAG_NOINTR. 1194 * 1195 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1196 * The command may be queued (callback function specified). Interrupts could 1197 * be used. It's normal operation mode. 1198 */ 1199/* 1200 * Called by sata framework to transport a sata packet down stream. 1201 */ 1202static int 1203ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1204{ 1205 ahci_ctl_t *ahci_ctlp; 1206 ahci_port_t *ahci_portp; 1207 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1208 uint8_t port; 1209 1210 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1211 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1212 1213 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1214 "ahci_tran_start enter: cport %d satapkt 0x%p", 1215 cport, (void *)spkt); 1216 1217 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1218 1219 mutex_enter(&ahci_portp->ahciport_mutex); 1220 1221 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1222 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1223 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1224 /* 1225 * In case the targer driver would send the packet before 1226 * sata framework can have the opportunity to process those 1227 * event reports. 1228 */ 1229 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1230 spkt->satapkt_device.satadev_state = 1231 ahci_portp->ahciport_port_state; 1232 ahci_update_sata_registers(ahci_ctlp, port, 1233 &spkt->satapkt_device); 1234 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1235 "ahci_tran_start returning PORT_ERROR while " 1236 "port in FAILED/SHUTDOWN/PWROFF state: " 1237 "port: %d", port); 1238 mutex_exit(&ahci_portp->ahciport_mutex); 1239 return (SATA_TRAN_PORT_ERROR); 1240 } 1241 1242 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1243 /* 1244 * ahci_intr_phyrdy_change() may have rendered it to 1245 * SATA_DTYPE_NONE. 1246 */ 1247 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1248 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1249 spkt->satapkt_device.satadev_state = 1250 ahci_portp->ahciport_port_state; 1251 ahci_update_sata_registers(ahci_ctlp, port, 1252 &spkt->satapkt_device); 1253 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1254 "ahci_tran_start returning PORT_ERROR while " 1255 "no device attached: port: %d", port); 1256 mutex_exit(&ahci_portp->ahciport_mutex); 1257 return (SATA_TRAN_PORT_ERROR); 1258 } 1259 1260 /* 1261 * SATA HBA driver should remember that a device was reset and it 1262 * is supposed to reject any packets which do not specify either 1263 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1264 * 1265 * This is to prevent a race condition when a device was arbitrarily 1266 * reset by the HBA driver (and lost it's setting) and a target 1267 * driver sending some commands to a device before the sata framework 1268 * has a chance to restore the device setting (such as cache enable/ 1269 * disable or other resettable stuff). 1270 */ 1271 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1272 ahci_portp->ahciport_reset_in_progress = 0; 1273 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1274 "ahci_tran_start clearing the " 1275 "reset_in_progress for port: %d", port); 1276 } 1277 1278 if (ahci_portp->ahciport_reset_in_progress && 1279 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1280 ! ddi_in_panic()) { 1281 spkt->satapkt_reason = SATA_PKT_BUSY; 1282 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1283 "ahci_tran_start returning BUSY while " 1284 "reset in progress: port: %d", port); 1285 mutex_exit(&ahci_portp->ahciport_mutex); 1286 return (SATA_TRAN_BUSY); 1287 } 1288 1289 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1290 spkt->satapkt_reason = SATA_PKT_BUSY; 1291 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1292 "ahci_tran_start returning BUSY while " 1293 "mopping in progress: port: %d", port); 1294 mutex_exit(&ahci_portp->ahciport_mutex); 1295 return (SATA_TRAN_BUSY); 1296 } 1297 1298 if (spkt->satapkt_op_mode & 1299 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1300 /* We need to do the sync start now */ 1301 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1302 spkt) == AHCI_FAILURE) { 1303 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1304 "return QUEUE_FULL: port %d", port); 1305 mutex_exit(&ahci_portp->ahciport_mutex); 1306 return (SATA_TRAN_QUEUE_FULL); 1307 } 1308 } else { 1309 /* Async start, using interrupt */ 1310 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1311 == AHCI_FAILURE) { 1312 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1313 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1314 "returning QUEUE_FULL: port %d", port); 1315 mutex_exit(&ahci_portp->ahciport_mutex); 1316 return (SATA_TRAN_QUEUE_FULL); 1317 } 1318 } 1319 1320 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1321 "sata tran accepted: port %d", port); 1322 1323 mutex_exit(&ahci_portp->ahciport_mutex); 1324 return (SATA_TRAN_ACCEPTED); 1325} 1326 1327/* 1328 * SATA_OPMODE_SYNCH flag is set 1329 * 1330 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1331 * without interrupt, otherwise we can still use the interrupt. 1332 * 1333 * WARNING!!! ahciport_mutex should be acquired before the function 1334 * is called. 1335 */ 1336static int 1337ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1338 uint8_t port, sata_pkt_t *spkt) 1339{ 1340 int pkt_timeout_ticks; 1341 uint32_t timeout_tags; 1342 int rval; 1343 1344 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1345 "port %d spkt 0x%p", port, spkt); 1346 1347 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1348 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1349 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1350 port, spkt)) == AHCI_FAILURE) { 1351 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1352 return (rval); 1353 } 1354 1355 pkt_timeout_ticks = 1356 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1357 1358 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1359 mutex_exit(&ahci_portp->ahciport_mutex); 1360 1361 /* Simulate the interrupt */ 1362 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1363 1364 drv_usecwait(AHCI_1MS_USECS); 1365 1366 mutex_enter(&ahci_portp->ahciport_mutex); 1367 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1368 if (pkt_timeout_ticks < 0) { 1369 cmn_err(CE_NOTE, "!ahci_do_sync_start: " 1370 "port %d satapkt 0x%p timed out\n", 1371 port, (void *)spkt); 1372 timeout_tags = (0x1 << rval); 1373 mutex_exit(&ahci_portp->ahciport_mutex); 1374 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1375 port, timeout_tags); 1376 mutex_enter(&ahci_portp->ahciport_mutex); 1377 } 1378 } 1379 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1380 return (AHCI_SUCCESS); 1381 1382 } else { 1383 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1384 port, spkt)) == AHCI_FAILURE) 1385 return (rval); 1386 1387#if AHCI_DEBUG 1388 /* 1389 * Note that the driver always uses the slot 0 to deliver 1390 * REQUEST SENSE or READ LOG EXT command 1391 */ 1392 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1393 ASSERT(rval == 0); 1394#endif 1395 1396 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1397 cv_wait(&ahci_portp->ahciport_cv, 1398 &ahci_portp->ahciport_mutex); 1399 1400 return (AHCI_SUCCESS); 1401 } 1402} 1403 1404#define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1405 if (satapkt) { \ 1406 satapkt->satapkt_reason = reason; \ 1407 /* \ 1408 * We set the satapkt_reason in both sync and \ 1409 * non-sync cases. \ 1410 */ \ 1411 } \ 1412 if (satapkt && \ 1413 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1414 satapkt->satapkt_comp) { \ 1415 mutex_exit(&ahci_portp->ahciport_mutex); \ 1416 (*satapkt->satapkt_comp)(satapkt); \ 1417 mutex_enter(&ahci_portp->ahciport_mutex); \ 1418 } else { \ 1419 if (satapkt && \ 1420 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1421 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1422 cv_signal(&ahci_portp->ahciport_cv); \ 1423 } 1424 1425/* 1426 * Searches for and claims a free command slot. 1427 * 1428 * Returns: 1429 * 1430 * AHCI_FAILURE if failed 1431 * 1. if no empty slot left 1432 * 2. non-queued command requested while queued command(s) is outstanding 1433 * 3. queued command requested whild non-queued command(s) is outstanding 1434 * 4. HBA doesn't support multiple-use of command list while already a 1435 * non-queued command is oustanding 1436 * 1437 * claimed slot number if succeeded 1438 * 1439 * NOTE: it will always return slot 0 during error recovery process for 1440 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1441 * 1442 * WARNING!!! ahciport_mutex should be acquired before the function 1443 * is called. 1444 */ 1445/*ARGSUSED*/ 1446static int 1447ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1448 ahci_port_t *ahci_portp, int command_type) 1449{ 1450 uint32_t free_slots; 1451 int slot; 1452 1453 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1454 "ahciport_pending_tags = 0x%x " 1455 "ahciport_pending_ncq_tags = 0x%x", 1456 ahci_portp->ahciport_pending_tags, 1457 ahci_portp->ahciport_pending_ncq_tags); 1458 1459 /* 1460 * According to the AHCI spec, system software is responsible to 1461 * ensure that queued and non-queued commands are not mixed in 1462 * the command list. 1463 */ 1464 if (command_type == AHCI_NON_NCQ_CMD) { 1465 /* Non-NCQ command request */ 1466 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1467 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1468 "ahci_claim_free_slot: there is still pending " 1469 "queued command(s) in the command list, " 1470 "so no available slot for the non-queued " 1471 "command"); 1472 return (AHCI_FAILURE); 1473 } 1474 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1475 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1476 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1477 "ahci_claim_free_slot: HBA cannot support multiple-" 1478 "use of the command list for non-queued commands"); 1479 return (AHCI_FAILURE); 1480 } 1481 free_slots = (~ahci_portp->ahciport_pending_tags) & 1482 AHCI_SLOT_MASK(ahci_ctlp); 1483 } else if (command_type == AHCI_NCQ_CMD) { 1484 /* NCQ command request */ 1485 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1486 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1487 "ahci_claim_free_slot: there is still pending " 1488 "non-queued command(s) in the command list, " 1489 "so no available slot for the queued command"); 1490 return (AHCI_FAILURE); 1491 } 1492 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1493 AHCI_NCQ_SLOT_MASK(ahci_portp); 1494 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1495 /* Error retrieval command request */ 1496 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1497 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1498 "SENSE or READ LOG EXT command"); 1499 slot = 0; 1500 goto out; 1501 } 1502 1503 slot = ddi_ffs(free_slots) - 1; 1504 if (slot == -1) { 1505 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1506 "ahci_claim_free_slot: no empty slots"); 1507 return (AHCI_FAILURE); 1508 } 1509 1510 /* 1511 * According to the AHCI spec, to allow a simple mechanism for the 1512 * HBA to map command list slots to queue entries, software must 1513 * match the tag number it uses to the slot it is placing the command 1514 * in. For example, if a queued command is placed in slot 5, the tag 1515 * for that command must be 5. 1516 */ 1517 if (command_type == AHCI_NCQ_CMD) { 1518 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1519 } 1520 1521 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1522 1523out: 1524 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1525 "ahci_claim_free_slot: found slot: 0x%x", slot); 1526 1527 return (slot); 1528} 1529 1530/* 1531 * Builds the Command Table for the sata packet and delivers it to controller. 1532 * 1533 * Returns: 1534 * slot number if we can obtain a slot successfully 1535 * otherwise, return AHCI_FAILURE 1536 * 1537 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1538 */ 1539static int 1540ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1541 uint8_t port, sata_pkt_t *spkt) 1542{ 1543 int cmd_slot; 1544 sata_cmd_t *scmd; 1545 ahci_fis_h2d_register_t *h2d_register_fisp; 1546 ahci_cmd_table_t *cmd_table; 1547 ahci_cmd_header_t *cmd_header; 1548 int ncookies; 1549 int i; 1550 int command_type = AHCI_NON_NCQ_CMD; 1551 int ncq_qdepth; 1552#if AHCI_DEBUG 1553 uint32_t *ptr; 1554 uint8_t *ptr2; 1555#endif 1556 1557 spkt->satapkt_reason = SATA_PKT_BUSY; 1558 1559 scmd = &spkt->satapkt_cmd; 1560 1561 /* Check if the command is a NCQ command */ 1562 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1563 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1564 command_type = AHCI_NCQ_CMD; 1565 1566 /* 1567 * When NCQ is support, system software must determine the 1568 * maximum tag allowed by the device and the HBA, and it 1569 * must use a value not beyond of the lower bound of the two. 1570 * 1571 * Sata module is going to calculate the qdepth and send 1572 * down to HBA driver via sata_cmd. 1573 */ 1574 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1575 1576 /* 1577 * At the moment, the driver doesn't support the dynamic 1578 * setting of the maximum ncq depth, and the value can be 1579 * set either during the attach or after hot-plug insertion. 1580 */ 1581 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1582 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1583 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1584 "ahci_deliver_satapkt: port %d the max tags for " 1585 "NCQ command is %d", port, ncq_qdepth); 1586 } else { 1587 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1588 cmn_err(CE_WARN, "ahci_deliver_satapkt: port " 1589 "%d the max tag for NCQ command is " 1590 "requested to change from %d to %d, at the" 1591 " moment the driver doesn't support the " 1592 "dynamic change so it's going to " 1593 "still use the previous tag value", port, 1594 ahci_portp->ahciport_max_ncq_tags, 1595 ncq_qdepth); 1596 } 1597 } 1598 } 1599 1600 /* Check if the command is an error retrieval command */ 1601 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1602 command_type = AHCI_ERR_RETRI_CMD; 1603 1604 /* Check if there is an empty command slot */ 1605 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1606 if (cmd_slot == AHCI_FAILURE) { 1607 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1608 return (AHCI_FAILURE); 1609 } 1610 1611 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1612 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1613 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1614 cmd_slot, port, (void *)spkt); 1615 1616 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1617 bzero((void *)cmd_table, ahci_cmd_table_size); 1618 1619 /* For data transfer operations, it is the H2D Register FIS */ 1620 h2d_register_fisp = 1621 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1622 1623 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1624 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1625 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1626 SET_FIS_PMP(h2d_register_fisp, 1627 spkt->satapkt_device.satadev_addr.pmport); 1628 } 1629 1630 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1631 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1632 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1633 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1634 1635 switch (scmd->satacmd_addr_type) { 1636 1637 case 0: 1638 /* 1639 * satacmd_addr_type will be 0 for the commands below: 1640 * ATAPI command 1641 * SATAC_IDLE_IM 1642 * SATAC_STANDBY_IM 1643 * SATAC_DOWNLOAD_MICROCODE 1644 * SATAC_FLUSH_CACHE 1645 * SATAC_SET_FEATURES 1646 * SATAC_SMART 1647 * SATAC_ID_PACKET_DEVICE 1648 * SATAC_ID_DEVICE 1649 */ 1650 /* fallthrough */ 1651 1652 case ATA_ADDR_LBA: 1653 /* fallthrough */ 1654 1655 case ATA_ADDR_LBA28: 1656 /* LBA[7:0] */ 1657 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1658 1659 /* LBA[15:8] */ 1660 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1661 1662 /* LBA[23:16] */ 1663 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1664 1665 /* LBA [27:24] (also called dev_head) */ 1666 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1667 1668 break; 1669 1670 case ATA_ADDR_LBA48: 1671 /* LBA[7:0] */ 1672 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1673 1674 /* LBA[15:8] */ 1675 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1676 1677 /* LBA[23:16] */ 1678 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1679 1680 /* LBA [31:24] */ 1681 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1682 scmd->satacmd_lba_low_msb); 1683 1684 /* LBA [39:32] */ 1685 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1686 scmd->satacmd_lba_mid_msb); 1687 1688 /* LBA [47:40] */ 1689 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1690 scmd->satacmd_lba_high_msb); 1691 1692 /* Set dev_head */ 1693 SET_FIS_DEV_HEAD(h2d_register_fisp, 1694 scmd->satacmd_device_reg); 1695 1696 /* Set the extended sector count and features */ 1697 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1698 scmd->satacmd_sec_count_msb); 1699 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1700 scmd->satacmd_features_reg_ext); 1701 break; 1702 } 1703 1704 /* 1705 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1706 * filled into features field, and sector count 8:15 is filled into 1707 * features (exp) field. TAG is filled into sector field. 1708 */ 1709 if (command_type == AHCI_NCQ_CMD) { 1710 SET_FIS_FEATURES(h2d_register_fisp, 1711 scmd->satacmd_sec_count_lsb); 1712 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1713 scmd->satacmd_sec_count_msb); 1714 1715 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1716 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1717 } 1718 1719 ncookies = scmd->satacmd_num_dma_cookies; 1720 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1721 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1722 ncookies, ahci_dma_prdt_number); 1723 1724 ASSERT(ncookies <= ahci_dma_prdt_number); 1725 1726 /* *** now fill the scatter gather list ******* */ 1727 for (i = 0; i < ncookies; i++) { 1728 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1729 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1730 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1731 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1732 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1733 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1734 } 1735 1736 /* The ACMD field is filled in for ATAPI command */ 1737 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1738 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1739 SATA_ATAPI_MAX_CDB_LEN); 1740 } 1741 1742 /* Set Command Header in Command List */ 1743 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1744 BZERO_DESCR_INFO(cmd_header); 1745 BZERO_PRD_BYTE_COUNT(cmd_header); 1746 1747 /* Set the number of entries in the PRD table */ 1748 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1749 1750 /* Set the length of the command in the CFIS area */ 1751 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1752 1753 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1754 "sata_data_direction = 0x%x", 1755 scmd->satacmd_flags.sata_data_direction); 1756 1757 /* Set A bit if it is an ATAPI command */ 1758 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1759 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1760 1761 /* Set W bit if data is going to the device */ 1762 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1763 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1764 1765 /* 1766 * Set the prefetchable bit - this bit is only valid if the PRDTL 1767 * field is non-zero or the ATAPI 'A' bit is set in the command 1768 * header. This bit cannot be set when using native command 1769 * queuing commands or when using FIS-based switching with a Port 1770 * multiplier. 1771 */ 1772 if (command_type != AHCI_NCQ_CMD) 1773 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1774 1775 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1776 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1777 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1778 1779 /* 1780 * We are overloading satapkt_hba_driver_private with 1781 * watched_cycle count. 1782 */ 1783 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1784 1785#if AHCI_DEBUG 1786 /* Dump the command header and table */ 1787 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1788 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1789 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1790 spkt, scmd->satacmd_cmd_reg, port); 1791 ptr = (uint32_t *)cmd_header; 1792 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1793 " Command Header:%8x %8x %8x %8x", 1794 ptr[0], ptr[1], ptr[2], ptr[3]); 1795 1796 /* Dump the H2D register FIS */ 1797 ptr = (uint32_t *)h2d_register_fisp; 1798 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1799 " Command FIS: %8x %8x %8x %8x", 1800 ptr[0], ptr[1], ptr[2], ptr[3]); 1801 1802 /* Dump the ACMD register FIS */ 1803 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1804 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1805 if (ahci_debug_flags & AHCIDBG_COMMAND) 1806 ahci_log(ahci_ctlp, CE_WARN, 1807 " ATAPI command: %2x %2x %2x %2x " 1808 "%2x %2x %2x %2x", 1809 ptr2[8 * i], ptr2[8 * i + 1], 1810 ptr2[8 * i + 2], ptr2[8 * i + 3], 1811 ptr2[8 * i + 4], ptr2[8 * i + 5], 1812 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1813 1814 /* Dump the PRDT */ 1815 for (i = 0; i < ncookies; i++) { 1816 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1817 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1818 " Cookie %d: %8x %8x %8x %8x", 1819 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1820 } 1821#endif 1822 1823 (void) ddi_dma_sync( 1824 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1825 0, 1826 ahci_cmd_table_size, 1827 DDI_DMA_SYNC_FORDEV); 1828 1829 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1830 cmd_slot * sizeof (ahci_cmd_header_t), 1831 sizeof (ahci_cmd_header_t), 1832 DDI_DMA_SYNC_FORDEV); 1833 1834 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1835 if (command_type == AHCI_NCQ_CMD) { 1836 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1837 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1838 (0x1 << cmd_slot)); 1839 } 1840 1841 /* Indicate to the HBA that a command is active. */ 1842 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1843 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1844 (0x1 << cmd_slot)); 1845 1846 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1847 "exit: port %d", port); 1848 1849 return (cmd_slot); 1850} 1851 1852/* 1853 * Called by the sata framework to abort the previously sent packet(s). 1854 * 1855 * Reset device to abort commands. 1856 */ 1857static int 1858ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1859{ 1860 ahci_ctl_t *ahci_ctlp; 1861 ahci_port_t *ahci_portp; 1862 uint32_t slot_status = 0; 1863 uint32_t aborted_tags = 0; 1864 uint32_t finished_tags = 0; 1865 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1866 uint8_t port; 1867 int tmp_slot; 1868 1869 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1870 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1871 1872 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1873 "ahci_tran_abort enter: port %d", port); 1874 1875 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1876 mutex_enter(&ahci_portp->ahciport_mutex); 1877 1878 /* 1879 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1880 * commands are being mopped, therefore there is nothing else to do 1881 */ 1882 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1883 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1884 "ahci_tran_abort: port %d is in " 1885 "mopping process, so just return directly ", port); 1886 mutex_exit(&ahci_portp->ahciport_mutex); 1887 return (SATA_SUCCESS); 1888 } 1889 1890 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1891 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1892 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1893 /* 1894 * In case the targer driver would send the request before 1895 * sata framework can have the opportunity to process those 1896 * event reports. 1897 */ 1898 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1899 spkt->satapkt_device.satadev_state = 1900 ahci_portp->ahciport_port_state; 1901 ahci_update_sata_registers(ahci_ctlp, port, 1902 &spkt->satapkt_device); 1903 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1904 "ahci_tran_abort returning SATA_FAILURE while " 1905 "port in FAILED/SHUTDOWN/PWROFF state: " 1906 "port: %d", port); 1907 mutex_exit(&ahci_portp->ahciport_mutex); 1908 return (SATA_FAILURE); 1909 } 1910 1911 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1912 /* 1913 * ahci_intr_phyrdy_change() may have rendered it to 1914 * AHCI_PORT_TYPE_NODEV. 1915 */ 1916 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1917 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1918 spkt->satapkt_device.satadev_state = 1919 ahci_portp->ahciport_port_state; 1920 ahci_update_sata_registers(ahci_ctlp, port, 1921 &spkt->satapkt_device); 1922 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1923 "ahci_tran_abort returning SATA_FAILURE while " 1924 "no device attached: port: %d", port); 1925 mutex_exit(&ahci_portp->ahciport_mutex); 1926 return (SATA_FAILURE); 1927 } 1928 1929 if (flag == SATA_ABORT_ALL_PACKETS) { 1930 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1931 aborted_tags = ahci_portp->ahciport_pending_tags; 1932 1933 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1934 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1935 1936 cmn_err(CE_NOTE, "!ahci port %d abort all packets", port); 1937 } else { 1938 aborted_tags = 0xffffffff; 1939 /* 1940 * Aborting one specific packet, first search the 1941 * ahciport_slot_pkts[] list for matching spkt. 1942 */ 1943 for (tmp_slot = 0; 1944 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1945 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1946 aborted_tags = (0x1 << tmp_slot); 1947 break; 1948 } 1949 } 1950 1951 if (aborted_tags == 0xffffffff) { 1952 /* request packet is not on the pending list */ 1953 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1954 "Cannot find the aborting pkt 0x%p on the " 1955 "pending list", (void *)spkt); 1956 ahci_update_sata_registers(ahci_ctlp, port, 1957 &spkt->satapkt_device); 1958 mutex_exit(&ahci_portp->ahciport_mutex); 1959 return (SATA_FAILURE); 1960 } 1961 cmn_err(CE_NOTE, "!ahci port %d abort satapkt 0x%p", 1962 port, (void *)spkt); 1963 } 1964 1965 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1966 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1967 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1968 1969 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1970 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1971 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 1972 1973 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1974 ahci_portp->ahciport_mop_in_progress++; 1975 1976 /* 1977 * To abort the packet(s), first we are trying to clear PxCMD.ST 1978 * to stop the port, and if the port can be stopped 1979 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 1980 * then we just send back the aborted packet(s) with ABORTED flag 1981 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 1982 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 1983 * perform a COMRESET. 1984 */ 1985 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1986 ahci_portp, port, NULL, NULL); 1987 1988 /* 1989 * Compute which have finished and which need to be retried. 1990 * 1991 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 1992 * minus the slot_status. The aborted_tags has to be deducted by 1993 * finished_tags since we can't possibly abort a tag which had finished 1994 * already. 1995 */ 1996 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1997 finished_tags = ahci_portp->ahciport_pending_tags & 1998 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1999 2000 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2001 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2002 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2003 2004 aborted_tags &= ~finished_tags; 2005 2006 ahci_mop_commands(ahci_ctlp, 2007 ahci_portp, 2008 port, 2009 slot_status, 2010 0, /* failed tags */ 2011 0, /* timeout tags */ 2012 aborted_tags, 2013 0); /* reset tags */ 2014 2015 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2016 mutex_exit(&ahci_portp->ahciport_mutex); 2017 2018 return (SATA_SUCCESS); 2019} 2020 2021/* 2022 * Used to do device reset and reject all the pending packets on a device 2023 * during the reset operation. 2024 * 2025 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2026 */ 2027static int 2028ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2029 ahci_port_t *ahci_portp, uint8_t port) 2030{ 2031 uint32_t slot_status = 0; 2032 uint32_t reset_tags = 0; 2033 uint32_t finished_tags = 0; 2034 sata_device_t sdevice; 2035 int ret; 2036 2037 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2038 "ahci_reset_device_reject_pkts on port: %d", port); 2039 2040 /* 2041 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2042 * commands are being mopped, therefore there is nothing else to do 2043 */ 2044 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2045 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2046 "ahci_reset_device_reject_pkts: port %d is in " 2047 "mopping process, so return directly ", port); 2048 return (SATA_SUCCESS); 2049 } 2050 2051 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2052 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2053 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2054 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2055 } 2056 2057 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2058 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2059 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2060 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2061 } 2062 2063 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2064 != AHCI_SUCCESS) { 2065 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2066 "Try to do a port reset after software " 2067 "reset failed", port); 2068 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2069 if (ret != AHCI_SUCCESS) { 2070 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2071 "ahci_reset_device_reject_pkts: port %d " 2072 "failed", port); 2073 return (SATA_FAILURE); 2074 } 2075 } 2076 /* Set the reset in progress flag */ 2077 ahci_portp->ahciport_reset_in_progress = 1; 2078 2079 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2080 ahci_portp->ahciport_mop_in_progress++; 2081 2082 /* Indicate to the framework that a reset has happened */ 2083 bzero((void *)&sdevice, sizeof (sata_device_t)); 2084 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2085 sdevice.satadev_addr.pmport = 0; 2086 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2087 2088 sdevice.satadev_state = SATA_DSTATE_RESET | 2089 SATA_DSTATE_PWR_ACTIVE; 2090 mutex_exit(&ahci_portp->ahciport_mutex); 2091 sata_hba_event_notify( 2092 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2093 &sdevice, 2094 SATA_EVNT_DEVICE_RESET); 2095 mutex_enter(&ahci_portp->ahciport_mutex); 2096 2097 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2098 "port %d sending event up: SATA_EVNT_RESET", port); 2099 2100 /* Next try to mop the pending commands */ 2101 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2102 finished_tags = ahci_portp->ahciport_pending_tags & 2103 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2104 2105 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2106 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2107 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2108 2109 reset_tags &= ~finished_tags; 2110 2111 ahci_mop_commands(ahci_ctlp, 2112 ahci_portp, 2113 port, 2114 slot_status, 2115 0, /* failed tags */ 2116 0, /* timeout tags */ 2117 0, /* aborted tags */ 2118 reset_tags); /* reset tags */ 2119 2120 return (SATA_SUCCESS); 2121} 2122 2123/* 2124 * Used to do port reset and reject all the pending packets on a port during 2125 * the reset operation. 2126 * 2127 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2128 */ 2129static int 2130ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2131 ahci_port_t *ahci_portp, uint8_t port) 2132{ 2133 uint32_t slot_status = 0; 2134 uint32_t reset_tags = 0; 2135 uint32_t finished_tags = 0; 2136 2137 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2138 "ahci_reset_port_reject_pkts on port: %d", port); 2139 2140 /* 2141 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2142 * commands are being mopped, therefore there is nothing else to do 2143 */ 2144 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2145 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2146 "ahci_reset_port_reject_pkts: port %d is in " 2147 "mopping process, so return directly ", port); 2148 return (SATA_SUCCESS); 2149 } 2150 2151 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2152 ahci_portp->ahciport_mop_in_progress++; 2153 2154 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2155 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2156 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2157 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2158 } 2159 2160 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2161 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2162 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2163 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2164 } 2165 2166 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2167 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2168 NULL) != AHCI_SUCCESS) 2169 return (SATA_FAILURE); 2170 2171 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2172 finished_tags = ahci_portp->ahciport_pending_tags & 2173 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2174 2175 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2176 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2177 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2178 2179 reset_tags &= ~finished_tags; 2180 2181 ahci_mop_commands(ahci_ctlp, 2182 ahci_portp, 2183 port, 2184 slot_status, 2185 0, /* failed tags */ 2186 0, /* timeout tags */ 2187 0, /* aborted tags */ 2188 reset_tags); /* reset tags */ 2189 2190 return (SATA_SUCCESS); 2191} 2192 2193/* 2194 * Used to do hba reset and reject all the pending packets on all ports 2195 * during the reset operation. 2196 */ 2197static int 2198ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2199{ 2200 ahci_port_t *ahci_portp; 2201 uint32_t slot_status[AHCI_MAX_PORTS]; 2202 uint32_t reset_tags[AHCI_MAX_PORTS]; 2203 uint32_t finished_tags[AHCI_MAX_PORTS]; 2204 uint8_t port; 2205 int ret = SATA_SUCCESS; 2206 2207 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2208 "ahci_reset_hba_reject_pkts enter"); 2209 2210 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2211 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2212 continue; 2213 } 2214 2215 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2216 2217 mutex_enter(&ahci_portp->ahciport_mutex); 2218 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2219 slot_status[port] = ddi_get32( 2220 ahci_ctlp->ahcictl_ahci_acc_handle, 2221 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2222 reset_tags[port] = slot_status[port] & 2223 AHCI_SLOT_MASK(ahci_ctlp); 2224 } 2225 2226 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2227 slot_status[port] = ddi_get32( 2228 ahci_ctlp->ahcictl_ahci_acc_handle, 2229 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2230 reset_tags[port] = slot_status[port] & 2231 AHCI_NCQ_SLOT_MASK(ahci_portp); 2232 } 2233 mutex_exit(&ahci_portp->ahciport_mutex); 2234 } 2235 2236 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2237 ret = SATA_FAILURE; 2238 goto out; 2239 } 2240 2241 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2242 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2243 continue; 2244 } 2245 2246 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2247 2248 mutex_enter(&ahci_portp->ahciport_mutex); 2249 /* 2250 * To prevent recursive enter to ahci_mop_commands, we need 2251 * check AHCI_PORT_FLAG_MOPPING flag. 2252 */ 2253 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2254 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2255 "ahci_reset_hba_reject_pkts: port %d is in " 2256 "mopping process, so return directly ", port); 2257 mutex_exit(&ahci_portp->ahciport_mutex); 2258 continue; 2259 } 2260 2261 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2262 ahci_portp->ahciport_mop_in_progress++; 2263 2264 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2265 finished_tags[port] = 2266 ahci_portp->ahciport_pending_tags & 2267 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2268 2269 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2270 finished_tags[port] = 2271 ahci_portp->ahciport_pending_ncq_tags & 2272 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2273 2274 reset_tags[port] &= ~finished_tags[port]; 2275 2276 ahci_mop_commands(ahci_ctlp, 2277 ahci_portp, 2278 port, 2279 slot_status[port], 2280 0, /* failed tags */ 2281 0, /* timeout tags */ 2282 0, /* aborted tags */ 2283 reset_tags[port]); /* reset tags */ 2284 mutex_exit(&ahci_portp->ahciport_mutex); 2285 } 2286out: 2287 return (ret); 2288} 2289 2290/* 2291 * Called by sata framework to reset a port(s) or device. 2292 */ 2293static int 2294ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2295{ 2296 ahci_ctl_t *ahci_ctlp; 2297 ahci_port_t *ahci_portp; 2298 uint8_t cport = sd->satadev_addr.cport; 2299 uint8_t port; 2300 int ret = SATA_SUCCESS; 2301 2302 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2303 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2304 2305 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2306 "ahci_tran_reset_port enter: cport: %d", cport); 2307 2308 switch (sd->satadev_addr.qual) { 2309 case SATA_ADDR_CPORT: 2310 /* Port reset */ 2311 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2312 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2313 "reset port", port); 2314 2315 mutex_enter(&ahci_portp->ahciport_mutex); 2316 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2317 mutex_exit(&ahci_portp->ahciport_mutex); 2318 2319 break; 2320 2321 case SATA_ADDR_DCPORT: 2322 /* Device reset */ 2323 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2324 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2325 "reset device", port); 2326 2327 mutex_enter(&ahci_portp->ahciport_mutex); 2328 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2329 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2330 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2331 /* 2332 * In case the targer driver would send the request 2333 * before sata framework can have the opportunity to 2334 * process those event reports. 2335 */ 2336 sd->satadev_state = ahci_portp->ahciport_port_state; 2337 ahci_update_sata_registers(ahci_ctlp, port, sd); 2338 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2339 "ahci_tran_reset_dport returning SATA_FAILURE " 2340 "while port in FAILED/SHUTDOWN/PWROFF state: " 2341 "port: %d", port); 2342 mutex_exit(&ahci_portp->ahciport_mutex); 2343 ret = SATA_FAILURE; 2344 break; 2345 } 2346 2347 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2348 /* 2349 * ahci_intr_phyrdy_change() may have rendered it to 2350 * AHCI_PORT_TYPE_NODEV. 2351 */ 2352 sd->satadev_type = SATA_DTYPE_NONE; 2353 sd->satadev_state = ahci_portp->ahciport_port_state; 2354 ahci_update_sata_registers(ahci_ctlp, port, sd); 2355 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2356 "ahci_tran_reset_dport returning SATA_FAILURE " 2357 "while no device attached: port: %d", port); 2358 mutex_exit(&ahci_portp->ahciport_mutex); 2359 ret = SATA_FAILURE; 2360 break; 2361 } 2362 2363 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2364 ahci_portp, port); 2365 mutex_exit(&ahci_portp->ahciport_mutex); 2366 break; 2367 2368 case SATA_ADDR_CNTRL: 2369 /* Reset the whole controller */ 2370 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2371 "reset the whole hba", port); 2372 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2373 break; 2374 2375 case SATA_ADDR_PMPORT: 2376 case SATA_ADDR_DPMPORT: 2377 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2378 "ahci_tran_reset_dport: port multiplier will be " 2379 "supported later"); 2380 /* FALLSTHROUGH */ 2381 default: 2382 ret = SATA_FAILURE; 2383 } 2384 2385 return (ret); 2386} 2387 2388/* 2389 * Called by sata framework to activate a port as part of hotplug. 2390 * (cfgadm -c connect satax/y) 2391 * Note: Not port-mult aware. 2392 */ 2393static int 2394ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2395{ 2396 ahci_ctl_t *ahci_ctlp; 2397 ahci_port_t *ahci_portp; 2398 uint8_t cport = satadev->satadev_addr.cport; 2399 uint8_t port; 2400 2401 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2402 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2403 2404 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2405 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2406 2407 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2408 2409 mutex_enter(&ahci_portp->ahciport_mutex); 2410 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2411 cmn_err(CE_NOTE, "!ahci port %d is activated", port); 2412 2413 /* 2414 * Reset the port so that the PHY communication would be re-established. 2415 * But this reset is an internal operation and the sata module doesn't 2416 * need to know about it. Moreover, the port with a device attached will 2417 * be started too. 2418 */ 2419 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2420 ahci_portp, port, 2421 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2422 NULL); 2423 2424 /* 2425 * Need to check the link status and device status of the port 2426 * and consider raising power if the port was in D3 state 2427 */ 2428 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2429 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2430 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2431 2432 satadev->satadev_state = ahci_portp->ahciport_port_state; 2433 2434 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2435 2436 mutex_exit(&ahci_portp->ahciport_mutex); 2437 return (SATA_SUCCESS); 2438} 2439 2440/* 2441 * Called by sata framework to deactivate a port as part of hotplug. 2442 * (cfgadm -c disconnect satax/y) 2443 * Note: Not port-mult aware. 2444 */ 2445static int 2446ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2447{ 2448 ahci_ctl_t *ahci_ctlp; 2449 ahci_port_t *ahci_portp; 2450 uint8_t cport = satadev->satadev_addr.cport; 2451 uint8_t port; 2452 uint32_t port_scontrol; 2453 2454 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2455 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2456 2457 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2458 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2459 2460 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2461 2462 mutex_enter(&ahci_portp->ahciport_mutex); 2463 cmn_err(CE_NOTE, "!ahci port %d is deactivated", port); 2464 2465 /* Disable the interrupts on the port */ 2466 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2467 2468 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2469 goto phy_offline; 2470 } 2471 2472 /* First to abort all the pending commands */ 2473 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2474 2475 /* Then stop the port */ 2476 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2477 ahci_portp, port); 2478 2479 /* Next put the PHY offline */ 2480 2481phy_offline: 2482 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2483 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2484 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2485 2486 /* Update ahciport_port_state */ 2487 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2488 satadev->satadev_state = ahci_portp->ahciport_port_state; 2489 2490 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2491 2492 mutex_exit(&ahci_portp->ahciport_mutex); 2493 return (SATA_SUCCESS); 2494} 2495 2496/* 2497 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2498 * when a device is unplugged or a port is deactivated. 2499 * 2500 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2501 */ 2502static void 2503ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2504 ahci_port_t *ahci_portp, uint8_t port) 2505{ 2506 uint32_t slot_status = 0; 2507 uint32_t abort_tags = 0; 2508 2509 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2510 "ahci_reject_all_abort_pkts on port: %d", port); 2511 2512 /* 2513 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2514 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2515 * to get the error data, if yes when the device is removed, the 2516 * command needs to be aborted too. 2517 */ 2518 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2519 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2520 slot_status = 0x1; 2521 abort_tags = 0x1; 2522 goto out; 2523 } else { 2524 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2525 "ahci_reject_all_abort_pkts return directly " 2526 "port %d no needs to reject any outstanding " 2527 "commands", port); 2528 return; 2529 } 2530 } 2531 2532 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2533 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2534 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2535 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2536 } 2537 2538 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2539 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2540 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2541 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2542 } 2543 2544out: 2545 /* No need to do mop when there is no outstanding commands */ 2546 if (slot_status != 0) { 2547 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2548 ahci_portp->ahciport_mop_in_progress++; 2549 2550 ahci_mop_commands(ahci_ctlp, 2551 ahci_portp, 2552 port, 2553 slot_status, 2554 0, /* failed tags */ 2555 0, /* timeout tags */ 2556 abort_tags, /* aborting tags */ 2557 0); /* reset tags */ 2558 } 2559} 2560 2561#if defined(__lock_lint) 2562static int 2563ahci_selftest(dev_info_t *dip, sata_device_t *device) 2564{ 2565 return (SATA_SUCCESS); 2566} 2567#endif 2568 2569/* 2570 * Allocate the ports structure, only called by ahci_attach 2571 */ 2572static int 2573ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2574{ 2575 int port, cport = 0; 2576 2577 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2578 "ahci_alloc_ports_state enter"); 2579 2580 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2581 2582 /* Allocate structures only for the implemented ports */ 2583 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2584 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2585 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2586 "hba port %d not implemented", port); 2587 continue; 2588 } 2589 2590#ifndef __lock_lint 2591 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2592 ahci_ctlp->ahcictl_port_to_cport[port] = 2593 (uint8_t)cport++; 2594#endif /* __lock_lint */ 2595 2596 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2597 goto err_out; 2598 } 2599 } 2600 2601 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2602 return (AHCI_SUCCESS); 2603 2604err_out: 2605 for (port--; port >= 0; port--) { 2606 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2607 ahci_dealloc_port_state(ahci_ctlp, port); 2608 } 2609 } 2610 2611 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2612 return (AHCI_FAILURE); 2613} 2614 2615/* 2616 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2617 */ 2618static void 2619ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2620{ 2621 int port; 2622 2623 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2624 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2625 /* if this port is implemented by the HBA */ 2626 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2627 ahci_dealloc_port_state(ahci_ctlp, port); 2628 } 2629 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2630} 2631 2632/* 2633 * Initialize the controller and all ports. And then try to start the ports 2634 * if there are devices attached. 2635 * 2636 * This routine can be called from three seperate cases: DDI_ATTACH, 2637 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2638 * other two cases; device signature probing are attempted only during 2639 * DDI_ATTACH case. 2640 * 2641 * WARNING!!! Disable the whole controller's interrupts before calling and 2642 * the interrupts will be enabled upon successfully return. 2643 */ 2644static int 2645ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2646{ 2647 ahci_port_t *ahci_portp; 2648 uint32_t ghc_control; 2649 int port; 2650 2651 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2652 "ahci_initialize_controller enter"); 2653 2654 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2655 2656 /* 2657 * Indicate that system software is AHCI aware by setting 2658 * GHC.AE to 1 2659 */ 2660 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2661 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2662 2663 ghc_control |= AHCI_HBA_GHC_AE; 2664 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2665 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2666 ghc_control); 2667 2668 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2669 2670 /* Initialize the implemented ports and structures */ 2671 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2672 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2673 continue; 2674 } 2675 2676 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2677 mutex_enter(&ahci_portp->ahciport_mutex); 2678 2679 /* 2680 * Ensure that the controller is not in the running state 2681 * by checking every implemented port's PxCMD register 2682 */ 2683 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2684 != AHCI_SUCCESS) { 2685 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2686 "ahci_initialize_controller: failed to " 2687 "initialize port %d", port); 2688 /* 2689 * Set the port state to SATA_PSTATE_FAILED if 2690 * failed to initialize it. 2691 */ 2692 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2693 } 2694 2695 mutex_exit(&ahci_portp->ahciport_mutex); 2696 } 2697 2698 /* Enable the whole controller interrupts */ 2699 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2700 ahci_enable_all_intrs(ahci_ctlp); 2701 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2702 2703 return (AHCI_SUCCESS); 2704} 2705 2706/* 2707 * Reverse of ahci_initialize_controller() 2708 * 2709 * We only need to stop the ports and disable the interrupt. 2710 */ 2711static void 2712ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2713{ 2714 ahci_port_t *ahci_portp; 2715 int port; 2716 2717 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2718 "ahci_uninitialize_controller enter"); 2719 2720 /* disable all the interrupts. */ 2721 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2722 ahci_disable_all_intrs(ahci_ctlp); 2723 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2724 2725 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2726 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2727 continue; 2728 } 2729 2730 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2731 2732 /* Stop the port by clearing PxCMD.ST */ 2733 mutex_enter(&ahci_portp->ahciport_mutex); 2734 2735 /* 2736 * Here we must disable the port interrupt because 2737 * ahci_disable_all_intrs only clear GHC.IE, and IS 2738 * register will be still set if PxIE is enabled. 2739 * When ahci shares one IRQ with other drivers, the 2740 * intr handler may claim the intr mistakenly. 2741 */ 2742 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2743 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2744 ahci_portp, port); 2745 mutex_exit(&ahci_portp->ahciport_mutex); 2746 } 2747} 2748 2749/* 2750 * The routine is to initialize the port. First put the port in NOTRunning 2751 * state, then enable port interrupt and clear Serror register. And under 2752 * AHCI_ATTACH case, find device signature and then try to start the port. 2753 * 2754 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2755 */ 2756static int 2757ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2758 ahci_port_t *ahci_portp, uint8_t port) 2759{ 2760 uint32_t port_cmd_status; 2761 2762 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2763 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2764 2765 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2766 "ahci_initialize_port: port %d " 2767 "port_cmd_status = 0x%x", port, port_cmd_status); 2768 /* 2769 * Check whether the port is in NotRunning state, if not, 2770 * put the port in NotRunning state 2771 */ 2772 if (!(port_cmd_status & 2773 (AHCI_CMD_STATUS_ST | 2774 AHCI_CMD_STATUS_CR | 2775 AHCI_CMD_STATUS_FRE | 2776 AHCI_CMD_STATUS_FR))) { 2777 2778 goto next; 2779 } 2780 2781 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2782 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2783 return (AHCI_FAILURE); 2784 2785next: 2786 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2787 "port %d is in NotRunning state now", port); 2788 2789 /* 2790 * At the time being, only probe ports/devices and get the types of 2791 * attached devices during DDI_ATTACH. In fact, the device can be 2792 * changed during power state changes, but at the time being, we 2793 * don't support the situation. 2794 */ 2795 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2796 /* Try to get the device signature */ 2797 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2798 } else { 2799 2800 /* 2801 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2802 * and PxFBU registers in case these registers were cleared 2803 * during the suspend. 2804 */ 2805 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2806 "ahci_initialize_port: port %d " 2807 "reset the port during resume", port); 2808 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2809 2810 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2811 "ahci_initialize_port: port %d " 2812 "set PxCLB, PxCLBU, PxFB and PxFBU " 2813 "during resume", port); 2814 2815 /* Config Port Received FIS Base Address */ 2816 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2817 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2818 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2819 2820 /* Config Port Command List Base Address */ 2821 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2822 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2823 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2824 } 2825 2826 /* Disable the interface power management */ 2827 ahci_disable_interface_pm(ahci_ctlp, port); 2828 2829 /* Return directly if no device connected */ 2830 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2831 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2832 "No device connected to port %d", port); 2833 goto out; 2834 } 2835 2836 /* Try to start the port */ 2837 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2838 != AHCI_SUCCESS) { 2839 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2840 "failed to start port %d", port); 2841 return (AHCI_FAILURE); 2842 } 2843out: 2844 /* Enable port interrupts */ 2845 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2846 2847 return (AHCI_SUCCESS); 2848} 2849 2850/* 2851 * Figure out which chip and set flag for VT8251; Also check 2852 * the power management capability. 2853 */ 2854static int 2855ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2856{ 2857 ushort_t venid, caps_ptr, cap_count, cap, pmcap, pmcsr; 2858 uint8_t revision; 2859 2860 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2861 PCI_CONF_VENID); 2862 2863 /* 2864 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2865 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2866 * which is a bug and was fixed after 0x00 revision id controllers. 2867 * 2868 * Moreover, VT8251 cannot use multiple command slots in the command 2869 * list for non-queued commands because the previous register content 2870 * of PxCI can be re-written in the register write, so a flag will be 2871 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2872 */ 2873 if (venid == VIA_VENID) { 2874 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2875 PCI_CONF_REVID); 2876 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2877 "revision id = 0x%x", revision); 2878 if (revision == 0x00) { 2879 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2880 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2881 "change ddi_attr_align to 0x4"); 2882 } 2883 2884 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2885 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2886 "VT8251 cannot use multiple command lists for " 2887 "non-queued commands"); 2888 } 2889 2890 /* 2891 * Check if capabilities list is supported and if so, 2892 * get initial capabilities pointer and clear bits 0,1. 2893 */ 2894 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2895 PCI_CONF_STAT) & PCI_STAT_CAP) { 2896 caps_ptr = P2ALIGN(pci_config_get8( 2897 ahci_ctlp->ahcictl_pci_conf_handle, 2898 PCI_CONF_CAP_PTR), 4); 2899 } else { 2900 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2901 } 2902 2903 /* 2904 * Walk capabilities if supported. 2905 */ 2906 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2907 2908 /* 2909 * Check that we haven't exceeded the maximum number of 2910 * capabilities and that the pointer is in a valid range. 2911 */ 2912 if (++cap_count > PCI_CAP_MAX_PTR) { 2913 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2914 "too many device capabilities"); 2915 return (AHCI_FAILURE); 2916 } 2917 if (caps_ptr < PCI_CAP_PTR_OFF) { 2918 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2919 "capabilities pointer 0x%x out of range", 2920 caps_ptr); 2921 return (AHCI_FAILURE); 2922 } 2923 2924 /* 2925 * Get next capability and check that it is valid. 2926 * For now, we only support power management. 2927 */ 2928 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2929 caps_ptr); 2930 switch (cap) { 2931 case PCI_CAP_ID_PM: 2932 2933 /* power management supported */ 2934 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 2935 2936 /* Save PMCSR offset */ 2937 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 2938 2939 pmcap = pci_config_get16( 2940 ahci_ctlp->ahcictl_pci_conf_handle, 2941 caps_ptr + PCI_PMCAP); 2942 pmcsr = pci_config_get16( 2943 ahci_ctlp->ahcictl_pci_conf_handle, 2944 ahci_ctlp->ahcictl_pmcsr_offset); 2945 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 2946 "Power Management capability found PCI_PMCAP " 2947 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 2948#if AHCI_DEBUG 2949 if ((pmcap & 0x3) == 0x3) 2950 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2951 "PCI Power Management Interface " 2952 "spec 1.2 compliant"); 2953#endif 2954 break; 2955 2956 case PCI_CAP_ID_MSI: 2957 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 2958 break; 2959 2960 case PCI_CAP_ID_PCIX: 2961 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2962 "PCI-X capability found"); 2963 break; 2964 2965 case PCI_CAP_ID_PCI_E: 2966 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2967 "PCI Express capability found"); 2968 break; 2969 2970 case PCI_CAP_ID_MSI_X: 2971 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2972 "MSI-X capability found"); 2973 break; 2974 2975 case PCI_CAP_ID_SATA: 2976 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2977 "SATA capability found"); 2978 break; 2979 2980 default: 2981 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2982 "unrecognized capability 0x%x", cap); 2983 break; 2984 } 2985 2986 /* 2987 * Get next capabilities pointer and clear bits 0,1. 2988 */ 2989 caps_ptr = P2ALIGN(pci_config_get8( 2990 ahci_ctlp->ahcictl_pci_conf_handle, 2991 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 2992 } 2993 2994 return (AHCI_SUCCESS); 2995} 2996 2997/* 2998 * AHCI device reset ...; a single device on one of the ports is reset, 2999 * but the HBA and physical communication remain intact. This is the 3000 * least intrusive. 3001 * 3002 * When issuing a software reset sequence, there should not be other 3003 * commands in the command list, so we will first clear and then re-set 3004 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3005 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3006 * cleared. 3007 * 3008 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3009 * set before the function is called. 3010 */ 3011static int 3012ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3013 uint8_t port) 3014{ 3015 ahci_fis_h2d_register_t *h2d_register_fisp; 3016 ahci_cmd_table_t *cmd_table; 3017 ahci_cmd_header_t *cmd_header; 3018 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3019 int slot, loop_count; 3020 3021 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3022 "Port %d device resetting", port); 3023 3024 /* First to clear PxCMD.ST */ 3025 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3026 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3027 3028 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 3029 3030 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3031 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3032 port_cmd_status|AHCI_CMD_STATUS_ST); 3033 3034 /* And then to re-set PxCMD.ST */ 3035 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3036 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3037 3038 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3039 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3040 port_cmd_status|AHCI_CMD_STATUS_ST); 3041 3042 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3043 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3044 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3045 3046 if (port_task_file & AHCI_TFD_STS_BSY || 3047 port_task_file & AHCI_TFD_STS_DRQ) { 3048 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3049 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3050 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3051 "but PxCMD.CLO isn't supported, so a port " 3052 "reset is needed."); 3053 return (AHCI_FAILURE); 3054 } 3055 } 3056 3057 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3058 if (slot == AHCI_FAILURE) { 3059 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3060 "ahci_software_reset: no free slot"); 3061 return (AHCI_FAILURE); 3062 } 3063 3064 /* Now send the first R2H FIS with SRST set to 1 */ 3065 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3066 bzero((void *)cmd_table, ahci_cmd_table_size); 3067 3068 h2d_register_fisp = 3069 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3070 3071 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3072 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3073 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3074 3075 /* Set Command Header in Command List */ 3076 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3077 BZERO_DESCR_INFO(cmd_header); 3078 BZERO_PRD_BYTE_COUNT(cmd_header); 3079 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3080 3081 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3082 SET_RESET(cmd_header, 1); 3083 SET_WRITE(cmd_header, 1); 3084 3085 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3086 0, 3087 ahci_cmd_table_size, 3088 DDI_DMA_SYNC_FORDEV); 3089 3090 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3091 slot * sizeof (ahci_cmd_header_t), 3092 sizeof (ahci_cmd_header_t), 3093 DDI_DMA_SYNC_FORDEV); 3094 3095 /* Indicate to the HBA that a command is active. */ 3096 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3097 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3098 (0x1 << slot)); 3099 3100 loop_count = 0; 3101 3102 /* Loop till the first command is finished */ 3103 do { 3104 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3105 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3106 3107 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3108 /* We are effectively timing out after 0.1 sec. */ 3109 break; 3110 } 3111 /* Wait for 10 millisec */ 3112#ifndef __lock_lint 3113 delay(AHCI_10MS_TICKS); 3114#endif /* __lock_lint */ 3115 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3116 3117 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3118 "ahci_software_reset: 1st loop count: %d, " 3119 "port_cmd_issue = 0x%x, slot = 0x%x", 3120 loop_count, port_cmd_issue, slot); 3121 3122 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3123 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3124 3125 /* Now send the second R2H FIS with SRST cleard to zero */ 3126 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3127 bzero((void *)cmd_table, ahci_cmd_table_size); 3128 3129 h2d_register_fisp = 3130 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3131 3132 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3133 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3134 3135 /* Set Command Header in Command List */ 3136 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3137 BZERO_DESCR_INFO(cmd_header); 3138 BZERO_PRD_BYTE_COUNT(cmd_header); 3139 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3140 3141 SET_WRITE(cmd_header, 1); 3142 3143 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3144 0, 3145 ahci_cmd_table_size, 3146 DDI_DMA_SYNC_FORDEV); 3147 3148 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3149 slot * sizeof (ahci_cmd_header_t), 3150 sizeof (ahci_cmd_header_t), 3151 DDI_DMA_SYNC_FORDEV); 3152 3153 /* Indicate to the HBA that a command is active. */ 3154 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3155 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3156 (0x1 << slot)); 3157 3158 loop_count = 0; 3159 3160 /* Loop till the second command is finished */ 3161 do { 3162 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3163 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3164 3165 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3166 /* We are effectively timing out after 0.1 sec. */ 3167 break; 3168 } 3169 /* Wait for 10 millisec */ 3170#ifndef __lock_lint 3171 delay(AHCI_10MS_TICKS); 3172#endif /* __lock_lint */ 3173 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3174 3175 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3176 "ahci_software_reset: 2nd loop count: %d, " 3177 "port_cmd_issue = 0x%x, slot = 0x%x", 3178 loop_count, port_cmd_issue, slot); 3179 3180 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3181 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3182 3183 return (AHCI_SUCCESS); 3184} 3185 3186/* 3187 * AHCI port reset ...; the physical communication between the HBA and device 3188 * on a port are disabled. This is more intrusive. 3189 * 3190 * When an HBA or port reset occurs, Phy communication is going to 3191 * be re-established with the device through a COMRESET followed by the 3192 * normal out-of-band communication sequence defined in Serial ATA. AT 3193 * the end of reset, the device, if working properly, will send a D2H 3194 * Register FIS, which contains the device signature. When the HBA receives 3195 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3196 * the PxSIG register with the signature. 3197 * 3198 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3199 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3200 * AHCI 1.0 spec. 3201 */ 3202/* 3203 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3204 * cleared before the function is called. 3205 */ 3206static int 3207ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3208{ 3209 uint32_t cap_status, port_cmd_status; 3210 uint32_t port_scontrol, port_sstatus; 3211 uint32_t port_signature, port_intr_status, port_task_file; 3212 int loop_count; 3213 int rval = AHCI_SUCCESS; 3214 3215 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3216 "Port %d port resetting...", port); 3217 ahci_portp->ahciport_port_state = 0; 3218 3219 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3220 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3221 3222 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3223 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3224 3225 if (cap_status & AHCI_HBA_CAP_SSS) { 3226 /* 3227 * HBA support staggered spin-up, if the port has 3228 * not spin up yet, then force it to do spin-up 3229 */ 3230 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3231 if (!(ahci_portp->ahciport_flags 3232 & AHCI_PORT_FLAG_SPINUP)) { 3233 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3234 "Port %d PxCMD.SUD is zero, force " 3235 "it to do spin-up", port); 3236 ahci_portp->ahciport_flags |= 3237 AHCI_PORT_FLAG_SPINUP; 3238 } 3239 } 3240 } else { 3241 /* 3242 * HBA doesn't support stagger spin-up, force it 3243 * to do normal COMRESET 3244 */ 3245 if (ahci_portp->ahciport_flags & 3246 AHCI_PORT_FLAG_SPINUP) { 3247 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3248 "HBA does not support staggered spin-up " 3249 "force it to do normal COMRESET"); 3250 ahci_portp->ahciport_flags &= 3251 ~AHCI_PORT_FLAG_SPINUP; 3252 } 3253 } 3254 3255 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3256 /* Do normal COMRESET */ 3257 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3258 "ahci_port_reset: do normal COMRESET", port); 3259 3260 /* 3261 * According to the spec, SUD bit should be set here, 3262 * but JMicron JMB363 doesn't follow it, so remove 3263 * the assertion, and just print a debug message. 3264 */ 3265#if AHCI_DEBUG 3266 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3267 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3268 "port %d SUD bit not set", port) 3269#endif 3270 3271 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3272 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3273 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3274 3275 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3276 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3277 port_scontrol); 3278 3279 /* Enable PxCMD.FRE to read device */ 3280 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3281 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3282 port_cmd_status|AHCI_CMD_STATUS_FRE); 3283 3284 /* 3285 * Give time for COMRESET to percolate, according to the AHCI 3286 * spec, software shall wait at least 1 millisecond before 3287 * clearing PxSCTL.DET 3288 */ 3289#ifndef __lock_lint 3290 delay(AHCI_1MS_TICKS*2); 3291#endif /* __lock_lint */ 3292 3293 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3294 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3295 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3296 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3297 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3298 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3299 port_scontrol); 3300 } else { 3301 /* Do staggered spin-up */ 3302 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3303 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3304 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3305 3306 /* PxSCTL.DET must be 0 */ 3307 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3308 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3309 port_scontrol); 3310 3311 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3312 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3313 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3314 port_cmd_status); 3315 3316 /* 0 -> 1 edge */ 3317#ifndef __lock_lint 3318 delay(AHCI_1MS_TICKS*2); 3319#endif /* __lock_lint */ 3320 3321 /* Set PxCMD.SUD to 1 */ 3322 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3323 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3324 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3325 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3326 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3327 port_cmd_status); 3328 3329 /* Enable PxCMD.FRE to read device */ 3330 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3331 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3332 port_cmd_status|AHCI_CMD_STATUS_FRE); 3333 } 3334 3335 /* 3336 * The port enters P:StartComm state, and HBA tells link layer to 3337 * start communication, which involves sending COMRESET to device. 3338 * And the HBA resets PxTFD.STS to 7Fh. 3339 * 3340 * When a COMINIT is received from the device, then the port enters 3341 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3342 * PxSSTS.DET to 1h to indicate a device is detected but communication 3343 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3344 * a COMINIT has been received. 3345 */ 3346 /* 3347 * The DET field is valid only if IPM field indicates 3348 * that the interface is in active state. 3349 */ 3350 loop_count = 0; 3351 do { 3352 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3353 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3354 3355 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3356 /* 3357 * If the interface is not active, the DET field 3358 * is considered not accurate. So we want to 3359 * continue looping. 3360 */ 3361 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3362 } 3363 3364 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3365 /* 3366 * We are effectively timing out after 0.1 sec. 3367 */ 3368 break; 3369 } 3370 3371 /* Wait for 10 millisec */ 3372#ifndef __lock_lint 3373 delay(AHCI_10MS_TICKS); 3374#endif /* __lock_lint */ 3375 3376 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3377 3378 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3379 "ahci_port_reset: 1st loop count: %d, " 3380 "port_sstatus = 0x%x port %d", 3381 loop_count, port_sstatus, port); 3382 3383 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3384 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3385 /* 3386 * Either the port is not active or there 3387 * is no device present. 3388 */ 3389 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3390 goto out; 3391 } 3392 3393 /* Now we can make sure there is a device connected to the port */ 3394 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3395 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3396 3397 /* a COMINIT signal is supposed to be received */ 3398 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3399 cmn_err(CE_WARN, "ahci_port_reset: port %d COMINIT signal " 3400 "from the device not received", port); 3401 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3402 rval = AHCI_FAILURE; 3403 goto out; 3404 } 3405 3406 /* 3407 * According to the spec, when PxSCTL.DET is set to 0h, upon 3408 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3409 * shall be set to '1' by the HBA. 3410 * 3411 * However, we found JMicron JMB363 doesn't follow this, so 3412 * remove this check, and just print a debug message. 3413 */ 3414#if AHCI_DEBUG 3415 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3416 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3417 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3418 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3419 "port %d BSY bit is not set after COMINIT signal " 3420 "is received", port); 3421 } 3422#endif 3423 3424 /* 3425 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3426 * the D2H FIS received by HBA. 3427 */ 3428 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3429 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3430 SERROR_EXCHANGED_ERR); 3431 3432 /* 3433 * Next check whether COMRESET is completed successfully 3434 */ 3435 loop_count = 0; 3436 do { 3437 port_task_file = 3438 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3439 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3440 3441 /* 3442 * The Error bit '1' means COMRESET is finished successfully 3443 * The device hardware has been initialized and the power-up 3444 * diagnostics successfully completed. 3445 */ 3446 if (((port_task_file & AHCI_TFD_ERR_MASK) 3447 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3448 3449 port_signature = ddi_get32( 3450 ahci_ctlp->ahcictl_ahci_acc_handle, 3451 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3452 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3453 "COMRESET success, D2H register FIS " 3454 "post to received FIS structure " 3455 "port %d signature = 0x%x", 3456 port, port_signature); 3457 goto out_check; 3458 } 3459 3460 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3461 /* 3462 * We are effectively timing out after 11 sec. 3463 */ 3464 break; 3465 } 3466 3467 /* Wait for 10 millisec */ 3468#ifndef __lock_lint 3469 delay(AHCI_10MS_TICKS); 3470#endif /* __lock_lint */ 3471 3472 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3473 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3474 3475 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3476 "count: %d, port_task_file = 0x%x port %d", 3477 loop_count, port_task_file, port); 3478 3479 cmn_err(CE_WARN, "ahci_port_reset: port %d the device hardware " 3480 "has been initialized and the power-up diagnostics failed", 3481 port); 3482 3483 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3484 rval = AHCI_FAILURE; 3485 3486out: 3487 /* Clear port serror register for the port */ 3488 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3489 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3490 AHCI_SERROR_CLEAR_ALL); 3491 3492 return (rval); 3493 3494out_check: 3495 /* 3496 * Check device status, if keep busy or COMRESET error 3497 * do device reset to patch some SATA disks' issue 3498 * 3499 * For VT8251, sometimes need to do the device reset 3500 */ 3501 if ((port_task_file & AHCI_TFD_STS_BSY) || 3502 (port_task_file & AHCI_TFD_STS_DRQ)) { 3503 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3504 "need to do device reset", port); 3505 3506 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3507 3508 port_task_file = 3509 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3510 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3511 3512 if (port_task_file & AHCI_TFD_STS_BSY || 3513 port_task_file & AHCI_TFD_STS_DRQ) { 3514 cmn_err(CE_WARN, "ahci_port_reset: port %d " 3515 "BSY/DRQ still set after device reset " 3516 "port_task_file = 0x%x", 3517 port, port_task_file); 3518 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3519 rval = AHCI_FAILURE; 3520 } 3521 } 3522 3523 goto out; 3524} 3525 3526/* 3527 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3528 * This is the most intrusive. 3529 * 3530 * When an HBA reset occurs, Phy communication will be re-established with 3531 * the device through a COMRESET followed by the normal out-of-band 3532 * communication sequence defined in Serial ATA. AT the end of reset, the 3533 * device, if working properly, will send a D2H Register FIS, which contains 3534 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3535 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3536 * signature. 3537 * 3538 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3539 */ 3540static int 3541ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3542{ 3543 ahci_port_t *ahci_portp; 3544 uint32_t ghc_control; 3545 uint8_t port; 3546 int loop_count; 3547 int rval = AHCI_SUCCESS; 3548 3549 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3550 3551 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3552 3553 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3554 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3555 3556 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3557 ghc_control |= AHCI_HBA_GHC_HR; 3558 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3559 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3560 3561 /* 3562 * Wait until HBA Reset complete or timeout 3563 */ 3564 loop_count = 0; 3565 do { 3566 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3567 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3568 3569 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3570 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3571 "ahci hba reset is timing out, " 3572 "ghc_control = 0x%x", ghc_control); 3573 /* We are effectively timing out after 1 sec. */ 3574 break; 3575 } 3576 3577 /* Wait for 10 millisec */ 3578#ifndef __lock_lint 3579 delay(AHCI_10MS_TICKS); 3580#endif /* __lock_lint */ 3581 3582 } while (ghc_control & AHCI_HBA_GHC_HR); 3583 3584 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3585 "ahci_hba_reset: 1st loop count: %d, " 3586 "ghc_control = 0x%x", loop_count, ghc_control); 3587 3588 if (ghc_control & AHCI_HBA_GHC_HR) { 3589 /* The hba is not reset for some reasons */ 3590 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3591 "hba reset failed: HBA in a hung or locked state"); 3592 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3593 return (AHCI_FAILURE); 3594 } 3595 3596 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3597 /* Only check implemented ports */ 3598 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3599 continue; 3600 } 3601 3602 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3603 mutex_enter(&ahci_portp->ahciport_mutex); 3604 3605 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3606 != AHCI_SUCCESS) { 3607 rval = AHCI_FAILURE; 3608 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3609 "ahci_hba_reset: port %d failed", port); 3610 } 3611 3612 mutex_exit(&ahci_portp->ahciport_mutex); 3613 } 3614 3615 /* 3616 * Indicate that system software is AHCI aware by setting 3617 * GHC.AE to 1 3618 */ 3619 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3620 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3621 3622 ghc_control |= AHCI_HBA_GHC_AE; 3623 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3624 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3625 3626 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3627 3628 return (rval); 3629} 3630 3631/* 3632 * This routine is only called from AHCI_ATTACH or phyrdy change 3633 * case. It first calls port reset to initialize port, probe port and probe 3634 * device, then try to read PxSIG register to find the type of device 3635 * attached to the port. 3636 * 3637 * WARNING!!! ahciport_mutex should be acquired before the function 3638 * is called. And the port interrupt is disabled. 3639 */ 3640static void 3641ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3642 ahci_port_t *ahci_portp, uint8_t port) 3643{ 3644 uint32_t signature; 3645 3646 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3647 "ahci_find_dev_signature enter: port %d", port); 3648 3649 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3650 3651 /* Call port reset to check link status and get device signature */ 3652 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3653 3654 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3655 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3656 "ahci_find_dev_signature: No device is found " 3657 "at port %d", port); 3658 return; 3659 } 3660 3661 /* Check the port state */ 3662 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3663 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3664 "ahci_find_dev_signature: port %d state 0x%x", 3665 port, ahci_portp->ahciport_port_state); 3666 return; 3667 } 3668 3669 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3670 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3671 3672 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3673 "ahci_find_dev_signature: port %d signature = 0x%x", 3674 port, signature); 3675 3676 switch (signature) { 3677 3678 case AHCI_SIGNATURE_DISK: 3679 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3680 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3681 "Disk is found at port: %d", port); 3682 break; 3683 3684 case AHCI_SIGNATURE_ATAPI: 3685 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3686 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3687 "ATAPI device is found at port: %d", port); 3688 break; 3689 3690 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3691 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3692 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3693 "Port Multiplier is found at port: %d", port); 3694 break; 3695 3696 default: 3697 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3698 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3699 "Unknown device is found at port: %d", port); 3700 } 3701} 3702 3703/* 3704 * According to the spec, to reliably detect hot plug removals, software 3705 * must disable interface power management. Software should perform the 3706 * following initialization on a port after a device is attached: 3707 * Set PxSCTL.IPM to 3h to disable interface state transitions 3708 * Set PxCMD.ALPE to '0' to disable aggressive power management 3709 * Disable device initiated interface power management by SET FEATURE 3710 * 3711 * We can ignore the last item because by default the feature is disabled 3712 */ 3713static void 3714ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3715{ 3716 uint32_t port_scontrol, port_cmd_status; 3717 3718 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3719 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3720 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3721 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3722 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3723 3724 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3725 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3726 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3727 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3728 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3729} 3730 3731/* 3732 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3733 * to 1, then set it firstly. 3734 * 3735 * Each port contains two major DMA engines. One DMA engine walks through 3736 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3737 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3738 * 3739 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3740 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3741 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3742 * 3743 * Software shall not set PxCMD.ST to '1' unless a functional device is 3744 * present on the port(as determined by PxTFD.STS.BSY = '0', 3745 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3746 * 3747 * WARNING!!! ahciport_mutex should be acquired before the function 3748 * is called. 3749 */ 3750static int 3751ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3752{ 3753 uint32_t port_cmd_status; 3754 3755 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3756 3757 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3758 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3759 "the state for port %d is 0x%x", 3760 port, ahci_portp->ahciport_port_state); 3761 return (AHCI_FAILURE); 3762 } 3763 3764 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3765 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3766 "no device is attached at port %d", port); 3767 return (AHCI_FAILURE); 3768 } 3769 3770 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3771 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3772 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3773 3774 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3775 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3776 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3777 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3778 port_cmd_status); 3779 } 3780 3781 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3782 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3783 3784 port_cmd_status |= AHCI_CMD_STATUS_ST; 3785 3786 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3787 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3788 port_cmd_status); 3789 3790 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3791 3792 return (AHCI_SUCCESS); 3793} 3794 3795/* 3796 * Allocate the ahci_port_t including Received FIS and Command List. 3797 * The argument - port is the physical port number, and not logical 3798 * port number seen by the SATA framework. 3799 * 3800 * WARNING!!! ahcictl_mutex should be acquired before the function 3801 * is called. 3802 */ 3803static int 3804ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3805{ 3806 ahci_port_t *ahci_portp; 3807 3808 ahci_portp = 3809 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3810 3811#ifndef __lock_lint 3812 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3813#endif /* __lock_lint */ 3814 3815 ahci_portp->ahciport_port_num = port; 3816 3817 /* Intialize the port condition variable */ 3818 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3819 3820 /* Initialize the port mutex */ 3821 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3822 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3823 3824 mutex_enter(&ahci_portp->ahciport_mutex); 3825 3826 /* 3827 * Allocate memory for received FIS structure and 3828 * command list for this port 3829 */ 3830 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3831 goto err_case1; 3832 } 3833 3834 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3835 goto err_case2; 3836 } 3837 3838 ahci_portp->ahciport_event_args = 3839 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3840 3841 if (ahci_portp->ahciport_event_args == NULL) 3842 goto err_case3; 3843 3844 mutex_exit(&ahci_portp->ahciport_mutex); 3845 3846 return (AHCI_SUCCESS); 3847 3848err_case3: 3849 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3850 3851err_case2: 3852 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3853 3854err_case1: 3855 mutex_exit(&ahci_portp->ahciport_mutex); 3856 mutex_destroy(&ahci_portp->ahciport_mutex); 3857 cv_destroy(&ahci_portp->ahciport_cv); 3858 3859 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3860 3861 return (AHCI_FAILURE); 3862} 3863 3864/* 3865 * Reverse of ahci_dealloc_port_state(). 3866 * 3867 * WARNING!!! ahcictl_mutex should be acquired before the function 3868 * is called. 3869 */ 3870static void 3871ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3872{ 3873 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3874 3875 ASSERT(ahci_portp != NULL); 3876 3877 mutex_enter(&ahci_portp->ahciport_mutex); 3878 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3879 ahci_portp->ahciport_event_args = NULL; 3880 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3881 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3882 mutex_exit(&ahci_portp->ahciport_mutex); 3883 3884 mutex_destroy(&ahci_portp->ahciport_mutex); 3885 cv_destroy(&ahci_portp->ahciport_cv); 3886 3887 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3888 3889#ifndef __lock_lint 3890 ahci_ctlp->ahcictl_ports[port] = NULL; 3891#endif /* __lock_lint */ 3892} 3893 3894/* 3895 * Allocates memory for the Received FIS Structure 3896 * 3897 * WARNING!!! ahciport_mutex should be acquired before the function 3898 * is called. 3899 */ 3900static int 3901ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3902 uint8_t port) 3903{ 3904 size_t rcvd_fis_size; 3905 size_t ret_len; 3906 uint_t cookie_count; 3907 uint32_t cap_status; 3908 3909 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3910 3911 /* Check whether the HBA can access 64-bit data structures */ 3912 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3913 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3914 3915 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 3916 3917 /* 3918 * If 64-bit addressing is not supported, 3919 * change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr 3920 */ 3921 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3922 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3923 "hba does not support 64-bit addressing"); 3924 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 3925 0xffffffffull; 3926 } 3927 3928 /* allocate rcvd FIS dma handle. */ 3929 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3930 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3931 DDI_DMA_SLEEP, 3932 NULL, 3933 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3934 DDI_SUCCESS) { 3935 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3936 "rcvd FIS dma handle alloc failed"); 3937 3938 return (AHCI_FAILURE); 3939 } 3940 3941 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3942 rcvd_fis_size, 3943 &accattr, 3944 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3945 DDI_DMA_SLEEP, 3946 NULL, 3947 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3948 &ret_len, 3949 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3950 3951 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3952 "rcvd FIS dma mem alloc fail"); 3953 /* error.. free the dma handle. */ 3954 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3955 return (AHCI_FAILURE); 3956 } 3957 3958 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3959 NULL, 3960 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3961 rcvd_fis_size, 3962 DDI_DMA_CONSISTENT, 3963 DDI_DMA_SLEEP, 3964 NULL, 3965 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 3966 &cookie_count) != DDI_DMA_MAPPED) { 3967 3968 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3969 "rcvd FIS dma handle bind fail"); 3970 /* error.. free the dma handle & free the memory. */ 3971 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3972 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3973 return (AHCI_FAILURE); 3974 } 3975 3976 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3977 3978 /* Config Port Received FIS Base Address */ 3979 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3980 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3981 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3982 3983 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3984 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3985 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3986 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 3987 3988 return (AHCI_SUCCESS); 3989} 3990 3991/* 3992 * Deallocates the Received FIS Structure 3993 * 3994 * WARNING!!! ahciport_mutex should be acquired before the function 3995 * is called. 3996 */ 3997static void 3998ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3999{ 4000 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4001 "ahci_dealloc_rcvd_fis: port %d enter", 4002 ahci_portp->ahciport_port_num); 4003 4004 /* Unbind the cmd list dma handle first. */ 4005 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4006 4007 /* Then free the underlying memory. */ 4008 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4009 4010 /* Now free the handle itself. */ 4011 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4012} 4013 4014/* 4015 * Allocates memory for the Command List, which contains up to 32 entries. 4016 * Each entry contains a command header, which is a 32-byte structure that 4017 * includes the pointer to the command table. 4018 * 4019 * WARNING!!! ahciport_mutex should be acquired before the function 4020 * is called. 4021 */ 4022static int 4023ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4024 uint8_t port) 4025{ 4026 size_t cmd_list_size; 4027 size_t ret_len; 4028 uint_t cookie_count; 4029 uint32_t cap_status; 4030 4031 cmd_list_size = 4032 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4033 4034 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4035 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4036 4037 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 4038 4039 /* 4040 * If 64-bit addressing is not supported, 4041 * change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr 4042 */ 4043 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 4044 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4045 "hba does not support 64-bit addressing"); 4046 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 4047 0xffffffffull; 4048 } 4049 4050 /* allocate cmd list dma handle. */ 4051 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4052 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4053 DDI_DMA_SLEEP, 4054 NULL, 4055 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4056 4057 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4058 "cmd list dma handle alloc failed"); 4059 return (AHCI_FAILURE); 4060 } 4061 4062 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4063 cmd_list_size, 4064 &accattr, 4065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4066 DDI_DMA_SLEEP, 4067 NULL, 4068 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4069 &ret_len, 4070 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4071 4072 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4073 "cmd list dma mem alloc fail"); 4074 /* error.. free the dma handle. */ 4075 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4076 return (AHCI_FAILURE); 4077 } 4078 4079 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4080 NULL, 4081 (caddr_t)ahci_portp->ahciport_cmd_list, 4082 cmd_list_size, 4083 DDI_DMA_CONSISTENT, 4084 DDI_DMA_SLEEP, 4085 NULL, 4086 &ahci_portp->ahciport_cmd_list_dma_cookie, 4087 &cookie_count) != DDI_DMA_MAPPED) { 4088 4089 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4090 "cmd list dma handle bind fail"); 4091 /* error.. free the dma handle & free the memory. */ 4092 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4093 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4094 return (AHCI_FAILURE); 4095 } 4096 4097 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4098 4099 /* Config Port Command List Base Address */ 4100 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4101 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4102 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4103 4104 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4105 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4106 4107 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4108 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4109 4110 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4111 goto err_out; 4112 } 4113 4114 return (AHCI_SUCCESS); 4115 4116err_out: 4117 /* Unbind the cmd list dma handle first. */ 4118 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4119 4120 /* Then free the underlying memory. */ 4121 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4122 4123 /* Now free the handle itself. */ 4124 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4125 4126 return (AHCI_FAILURE); 4127} 4128 4129/* 4130 * Deallocates the Command List 4131 * 4132 * WARNING!!! ahciport_mutex should be acquired before the function 4133 * is called. 4134 */ 4135static void 4136ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4137{ 4138 /* First dealloc command table */ 4139 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4140 4141 /* Unbind the cmd list dma handle first. */ 4142 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4143 4144 /* Then free the underlying memory. */ 4145 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4146 4147 /* Now free the handle itself. */ 4148 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4149} 4150 4151/* 4152 * Allocates memory for all Command Tables, which contains Command FIS, 4153 * ATAPI Command and Physical Region Descriptor Table. 4154 * 4155 * WARNING!!! ahciport_mutex should be acquired before the function 4156 * is called. 4157 */ 4158static int 4159ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4160{ 4161 size_t ret_len; 4162 ddi_dma_cookie_t cmd_table_dma_cookie; 4163 uint_t cookie_count; 4164 uint32_t cap_status; 4165 int slot; 4166 4167 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4168 "ahci_alloc_cmd_tables: port %d enter", 4169 ahci_portp->ahciport_port_num); 4170 4171 /* Check whether the HBA can access 64-bit data structures */ 4172 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4173 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4174 4175 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 4176 4177 /* 4178 * If 64-bit addressing is not supported, 4179 * change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr 4180 */ 4181 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 4182 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4183 "hba does not support 64-bit addressing"); 4184 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 4185 0xffffffffull; 4186 } 4187 4188 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4189 /* Allocate cmd table dma handle. */ 4190 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4191 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4192 DDI_DMA_SLEEP, 4193 NULL, 4194 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4195 DDI_SUCCESS) { 4196 4197 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4198 "cmd table dma handle alloc failed"); 4199 4200 goto err_out; 4201 } 4202 4203 if (ddi_dma_mem_alloc( 4204 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4205 ahci_cmd_table_size, 4206 &accattr, 4207 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4208 DDI_DMA_SLEEP, 4209 NULL, 4210 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4211 &ret_len, 4212 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4213 NULL) { 4214 4215 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4216 "cmd table dma mem alloc fail"); 4217 4218 /* error.. free the dma handle. */ 4219 ddi_dma_free_handle( 4220 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4221 goto err_out; 4222 } 4223 4224 if (ddi_dma_addr_bind_handle( 4225 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4226 NULL, 4227 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4228 ahci_cmd_table_size, 4229 DDI_DMA_CONSISTENT, 4230 DDI_DMA_SLEEP, 4231 NULL, 4232 &cmd_table_dma_cookie, 4233 &cookie_count) != DDI_DMA_MAPPED) { 4234 4235 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4236 "cmd table dma handle bind fail"); 4237 /* error.. free the dma handle & free the memory. */ 4238 ddi_dma_mem_free( 4239 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4240 ddi_dma_free_handle( 4241 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4242 goto err_out; 4243 } 4244 4245 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4246 ahci_cmd_table_size); 4247 4248 /* Config Port Command Table Base Address */ 4249 SET_COMMAND_TABLE_BASE_ADDR( 4250 (&ahci_portp->ahciport_cmd_list[slot]), 4251 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4252 4253#ifndef __lock_lint 4254 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4255 (&ahci_portp->ahciport_cmd_list[slot]), 4256 cmd_table_dma_cookie.dmac_laddress >> 32); 4257#endif /* __lock_lint */ 4258 } 4259 4260 return (AHCI_SUCCESS); 4261err_out: 4262 4263 for (slot--; slot >= 0; slot--) { 4264 /* Unbind the cmd table dma handle first */ 4265 (void) ddi_dma_unbind_handle( 4266 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4267 4268 /* Then free the underlying memory */ 4269 ddi_dma_mem_free( 4270 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4271 4272 /* Now free the handle itself */ 4273 ddi_dma_free_handle( 4274 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4275 } 4276 4277 return (AHCI_FAILURE); 4278} 4279 4280/* 4281 * Deallocates memory for all Command Tables. 4282 * 4283 * WARNING!!! ahciport_mutex should be acquired before the function 4284 * is called. 4285 */ 4286static void 4287ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4288{ 4289 int slot; 4290 4291 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4292 "ahci_dealloc_cmd_tables: %d enter", 4293 ahci_portp->ahciport_port_num); 4294 4295 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4296 /* Unbind the cmd table dma handle first. */ 4297 (void) ddi_dma_unbind_handle( 4298 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4299 4300 /* Then free the underlying memory. */ 4301 ddi_dma_mem_free( 4302 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4303 4304 /* Now free the handle itself. */ 4305 ddi_dma_free_handle( 4306 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4307 } 4308} 4309 4310/* 4311 * WARNING!!! ahciport_mutex should be acquired before the function 4312 * is called. 4313 */ 4314static void 4315ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4316 sata_device_t *sd) 4317{ 4318 sd->satadev_scr.sstatus = 4319 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4320 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4321 sd->satadev_scr.serror = 4322 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4323 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4324 sd->satadev_scr.scontrol = 4325 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4326 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4327 sd->satadev_scr.sactive = 4328 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4329 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4330} 4331 4332/* 4333 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4334 */ 4335static void 4336ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4337{ 4338 uint32_t port_intr_status; 4339 uint32_t port_intr_enable; 4340 4341 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4342 "ahci_port_intr enter: port %d", port); 4343 4344 mutex_enter(&ahci_portp->ahciport_mutex); 4345 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4346 /* For SATA_OPMODE_POLLING commands */ 4347 port_intr_enable = 4348 (AHCI_INTR_STATUS_DHRS | 4349 AHCI_INTR_STATUS_PSS | 4350 AHCI_INTR_STATUS_SDBS | 4351 AHCI_INTR_STATUS_UFS | 4352 AHCI_INTR_STATUS_PCS | 4353 AHCI_INTR_STATUS_PRCS | 4354 AHCI_INTR_STATUS_OFS | 4355 AHCI_INTR_STATUS_INFS | 4356 AHCI_INTR_STATUS_IFS | 4357 AHCI_INTR_STATUS_HBDS | 4358 AHCI_INTR_STATUS_HBFS | 4359 AHCI_INTR_STATUS_TFES); 4360 mutex_exit(&ahci_portp->ahciport_mutex); 4361 goto next; 4362 } 4363 mutex_exit(&ahci_portp->ahciport_mutex); 4364 4365 /* 4366 * port_intr_enable indicates that the corresponding interrrupt 4367 * reporting is enabled. 4368 */ 4369 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4370 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4371next: 4372 /* 4373 * port_intr_stats indicates that the corresponding interrupt 4374 * condition is active. 4375 */ 4376 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4377 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4378 4379 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4380 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4381 "port_intr_enable = 0x%x", 4382 port, port_intr_status, port_intr_enable); 4383 4384 port_intr_status &= port_intr_enable; 4385 4386 /* First clear the port interrupts status */ 4387 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4388 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4389 port_intr_status); 4390 4391 /* Check the completed non-queued commands */ 4392 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4393 AHCI_INTR_STATUS_PSS)) { 4394 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4395 ahci_portp, port, port_intr_status); 4396 } 4397 4398 /* Check the completed queued commands */ 4399 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4400 (void) ahci_intr_set_device_bits(ahci_ctlp, 4401 ahci_portp, port); 4402 } 4403 4404 /* Check the port connect change status interrupt bit */ 4405 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4406 (void) ahci_intr_port_connect_change(ahci_ctlp, 4407 ahci_portp, port); 4408 } 4409 4410 /* Check the device mechanical presence status interrupt bit */ 4411 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4412 (void) ahci_intr_device_mechanical_presence_status( 4413 ahci_ctlp, ahci_portp, port); 4414 } 4415 4416 /* Check the PhyRdy change status interrupt bit */ 4417 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4418 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4419 port); 4420 } 4421 4422 /* 4423 * Check the non-fatal error interrupt bits, there are three 4424 * kinds of non-fatal errors at the time being: 4425 * 4426 * PxIS.UFS - Unknown FIS Error 4427 * PxIS.OFS - Overflow Error 4428 * PxIS.INFS - Interface Non-Fatal Error 4429 * 4430 * For these non-fatal errors, the HBA can continue to operate, 4431 * so the driver just log the error messages. 4432 */ 4433 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4434 AHCI_INTR_STATUS_OFS | 4435 AHCI_INTR_STATUS_INFS)) { 4436 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4437 port, port_intr_status); 4438 } 4439 4440 /* 4441 * Check the fatal error interrupt bits, there are four kinds 4442 * of fatal errors for AHCI controllers: 4443 * 4444 * PxIS.HBFS - Host Bus Fatal Error 4445 * PxIS.HBDS - Host Bus Data Error 4446 * PxIS.IFS - Interface Fatal Error 4447 * PxIS.TFES - Task File Error 4448 * 4449 * The fatal error means the HBA can not recover from it by 4450 * itself, and it will try to abort the transfer, and the software 4451 * must intervene to restart the port. 4452 */ 4453 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4454 AHCI_INTR_STATUS_HBDS | 4455 AHCI_INTR_STATUS_HBFS | 4456 AHCI_INTR_STATUS_TFES)) 4457 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4458 port, port_intr_status); 4459 4460 /* Check the cold port detect interrupt bit */ 4461 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4462 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4463 } 4464 4465 /* Second clear the corresponding bit in IS.IPS */ 4466 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4467 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4468} 4469 4470/* 4471 * Interrupt service handler 4472 */ 4473/* ARGSUSED1 */ 4474static uint_t 4475ahci_intr(caddr_t arg1, caddr_t arg2) 4476{ 4477 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4478 ahci_port_t *ahci_portp; 4479 int32_t global_intr_status; 4480 uint8_t port; 4481 4482 /* 4483 * global_intr_status indicates that the corresponding port has 4484 * an interrupt pending. 4485 */ 4486 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4487 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4488 4489 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4490 /* The interrupt is not ours */ 4491 return (DDI_INTR_UNCLAIMED); 4492 } 4493 4494 /* Loop for all the ports */ 4495 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4496 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4497 continue; 4498 } 4499 if (!((0x1 << port) & global_intr_status)) { 4500 continue; 4501 } 4502 4503 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4504 4505 /* Call ahci_port_intr */ 4506 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4507 } 4508 4509 return (DDI_INTR_CLAIMED); 4510} 4511 4512/* 4513 * For non-queued commands, when the corresponding bit in the PxCI register 4514 * is cleared, it means the command is completed successfully. And according 4515 * to the HBA state machine, there are three conditions which possibly will 4516 * try to clear the PxCI register bit. 4517 * 1. Receive one D2H Register FIS which is with 'I' bit set 4518 * 2. Update PIO Setup FIS 4519 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4520 * 4521 * Process completed non-queued commands when the interrupt status bit - 4522 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4523 * 4524 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4525 * with the 'I' bit set. And the following commands will send thus 4526 * FIS with 'I' bit set upon the successful completion: 4527 * 1. Non-data commands 4528 * 2. DMA data-in command 4529 * 3. DMA data-out command 4530 * 4. PIO data-out command 4531 * 5. PACKET non-data commands 4532 * 6. PACKET PIO data-in command 4533 * 7. PACKET PIO data-out command 4534 * 8. PACKET DMA data-in command 4535 * 9. PACKET DMA data-out command 4536 * 4537 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4538 * with the 'I' bit set. And the following commands will send this 4539 * FIS upon the successful completion: 4540 * 1. PIO data-in command 4541 */ 4542static int 4543ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4544 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4545{ 4546 uint32_t port_cmd_issue = 0; 4547 uint32_t finished_tags; 4548 int finished_slot; 4549 sata_pkt_t *satapkt; 4550 ahci_fis_d2h_register_t *rcvd_fisp; 4551 4552 if (intr_status & AHCI_INTR_STATUS_DHRS) 4553 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4554 "ahci_intr_cmd_cmplt enter: port %d " 4555 "a d2h register fis is received", port); 4556 4557 if (intr_status & AHCI_INTR_STATUS_PSS) 4558 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4559 "ahci_intr_cmd_cmplt enter: port %d " 4560 "a pio setup fis is received", port); 4561 4562 mutex_enter(&ahci_portp->ahciport_mutex); 4563 4564 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4565 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4566 /* 4567 * Spurious interrupt. Nothing to be done. 4568 */ 4569 mutex_exit(&ahci_portp->ahciport_mutex); 4570 return (AHCI_SUCCESS); 4571 } 4572 4573 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4574 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4575 4576 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4577 /* Slot 0 is always used during error recovery */ 4578 finished_tags = 0x1 & ~port_cmd_issue; 4579 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4580 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4581 "retrieval is finished, and finished_tags = 0x%x", 4582 port, finished_tags); 4583 } else { 4584 finished_tags = ahci_portp->ahciport_pending_tags & 4585 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4586 } 4587 4588 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4589 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4590 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4591 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4592 finished_tags); 4593 4594 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4595 (finished_tags == 0x1)) { 4596 satapkt = ahci_portp->ahciport_err_retri_pkt; 4597 ASSERT(satapkt != NULL); 4598 4599 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4600 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4601 "with SATA_PKT_COMPLETED", (void *)satapkt); 4602 4603 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4604 goto out; 4605 } 4606 4607 while (finished_tags) { 4608 finished_slot = ddi_ffs(finished_tags) - 1; 4609 if (finished_slot == -1) { 4610 goto out; 4611 } 4612 4613 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4614 ASSERT(satapkt != NULL); 4615 4616 /* 4617 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4618 * feature, sata_special_regs flag will be set, and the 4619 * driver should copy the status and the other corresponding 4620 * register values in the D2H Register FIS received (It's 4621 * working on Non-data protocol) from the device back to 4622 * the sata_cmd. 4623 * 4624 * For every AHCI port, there is only one Received FIS 4625 * structure, which contains the FISes received from the 4626 * device, So we're trying to copy the content of D2H 4627 * Register FIS in the Received FIS structure back to 4628 * the sata_cmd. 4629 */ 4630 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4631 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4632 ahcirf_d2h_register_fis); 4633 satapkt->satapkt_cmd.satacmd_status_reg = 4634 GET_RFIS_STATUS(rcvd_fisp); 4635 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4636 } 4637 4638 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4639 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4640 "with SATA_PKT_COMPLETED", (void *)satapkt); 4641 4642 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4643 CLEAR_BIT(finished_tags, finished_slot); 4644 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4645 4646 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4647 } 4648out: 4649 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4650 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4651 ahci_portp->ahciport_pending_tags); 4652 4653 mutex_exit(&ahci_portp->ahciport_mutex); 4654 4655 return (AHCI_SUCCESS); 4656} 4657 4658/* 4659 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4660 * with the 'I' bit set and has been copied into system memory. It will 4661 * be sent under the following situations: 4662 * 4663 * 1. NCQ command is completed 4664 * 2. Asynchronous notification 4665 * 4666 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4667 * via the Set Device Bits FIS. When such event is generated, the software 4668 * needs to read PxSACT register and compares the current value to the 4669 * list of commands previously issue by software. ahciport_pending_ncq_tags 4670 * keeps the tags of previously issued commands. 4671 * 4672 * Asynchronous Notification is a feature in SATA II, which allows an 4673 * ATAPI device to send a signal to the host when media is inserted or 4674 * removed and avoids polling the device for media changes. The signal 4675 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4676 * set to '1'. At the moment, it's not supported yet. 4677 */ 4678static int 4679ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4680 ahci_port_t *ahci_portp, uint8_t port) 4681{ 4682 uint32_t port_sactive; 4683 uint32_t port_cmd_issue; 4684 uint32_t issued_tags; 4685 int issued_slot; 4686 uint32_t finished_tags; 4687 int finished_slot; 4688 sata_pkt_t *satapkt; 4689 4690 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4691 "ahci_intr_set_device_bits enter: port %d", port); 4692 4693 mutex_enter(&ahci_portp->ahciport_mutex); 4694 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4695 mutex_exit(&ahci_portp->ahciport_mutex); 4696 return (AHCI_SUCCESS); 4697 } 4698 4699 /* 4700 * First the handler got which commands are finished by checking 4701 * PxSACT register 4702 */ 4703 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4704 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4705 4706 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4707 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4708 4709 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4710 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4711 "port_sactive = 0x%x", port, 4712 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4713 4714 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4715 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4716 4717 /* 4718 * For NCQ commands, the software can determine which command has 4719 * already been transmitted to the device by checking PxCI register. 4720 */ 4721 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4722 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4723 4724 issued_tags = ahci_portp->ahciport_pending_tags & 4725 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4726 4727 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4728 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4729 "port_cmd_issue = 0x%x", port, 4730 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4731 4732 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4733 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4734 4735 /* 4736 * Clear ahciport_pending_tags bit when the corresponding command 4737 * is already sent down to the device. 4738 */ 4739 while (issued_tags) { 4740 issued_slot = ddi_ffs(issued_tags) - 1; 4741 if (issued_slot == -1) { 4742 goto next; 4743 } 4744 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4745 CLEAR_BIT(issued_tags, issued_slot); 4746 } 4747 4748next: 4749 while (finished_tags) { 4750 finished_slot = ddi_ffs(finished_tags) - 1; 4751 if (finished_slot == -1) { 4752 goto out; 4753 } 4754 4755 /* The command is certainly transmitted to the device */ 4756 ASSERT(!(ahci_portp->ahciport_pending_tags & 4757 (0x1 << finished_slot))); 4758 4759 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4760 ASSERT(satapkt != NULL); 4761 4762 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4763 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4764 "with SATA_PKT_COMPLETED", (void *)satapkt); 4765 4766 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4767 CLEAR_BIT(finished_tags, finished_slot); 4768 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4769 4770 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4771 } 4772out: 4773 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4774 "ahci_intr_set_device_bits: port %d " 4775 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4776 port, ahci_portp->ahciport_pending_ncq_tags, 4777 ahci_portp->ahciport_pending_tags); 4778 4779 mutex_exit(&ahci_portp->ahciport_mutex); 4780 4781 return (AHCI_SUCCESS); 4782} 4783 4784/* 4785 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4786 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4787 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4788 * indicates a COMINIT signal was received. 4789 * 4790 * Hot plug insertion is detected by reception of a COMINIT signal from the 4791 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4792 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4793 * begin the normal communication negotiation sequence as outlined in the 4794 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4795 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4796 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4797 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4798 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4799 * to handle hot plug insertion. In this interrupt handler, just do nothing 4800 * but print some log message and clear the bit. 4801 */ 4802static int 4803ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4804 ahci_port_t *ahci_portp, uint8_t port) 4805{ 4806 uint32_t port_serror; 4807 4808 mutex_enter(&ahci_portp->ahciport_mutex); 4809 4810 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4811 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4812 4813 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4814 "ahci_intr_port_connect_change: port %d, " 4815 "port_serror = 0x%x", port, port_serror); 4816 4817 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4818 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4819 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4820 SERROR_EXCHANGED_ERR); 4821 4822 mutex_exit(&ahci_portp->ahciport_mutex); 4823 4824 return (AHCI_SUCCESS); 4825} 4826 4827/* 4828 * Hot Plug Operation for platforms that support Mechanical Presence 4829 * Switches. 4830 * 4831 * When set, it indicates that a mechanical presence switch attached to this 4832 * port has been opened or closed, which may lead to a change in the connection 4833 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4834 * are set to '1'. 4835 * 4836 * At the moment, this interrupt is not needed and disabled and we just log 4837 * the debug message. 4838 */ 4839/* ARGSUSED */ 4840static int 4841ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4842 ahci_port_t *ahci_portp, uint8_t port) 4843{ 4844 uint32_t cap_status, port_cmd_status; 4845 4846 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4847 "ahci_intr_device_mechanical_presence_status enter, " 4848 "port %d", port); 4849 4850 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4851 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4852 4853 mutex_enter(&ahci_portp->ahciport_mutex); 4854 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4855 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4856 4857 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4858 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4859 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4860 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4861 "the interrupt: cap_status = 0x%x, " 4862 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4863 mutex_exit(&ahci_portp->ahciport_mutex); 4864 4865 return (AHCI_SUCCESS); 4866 } 4867 4868 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4869 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4870 "The mechanical presence switch is open: " 4871 "port %d, port_cmd_status = 0x%x", 4872 port, port_cmd_status); 4873 } else { 4874 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4875 "The mechanical presence switch is close: " 4876 "port %d, port_cmd_status = 0x%x", 4877 port, port_cmd_status); 4878 } 4879 4880 mutex_exit(&ahci_portp->ahciport_mutex); 4881 4882 return (AHCI_SUCCESS); 4883} 4884 4885/* 4886 * Native Hot Plug Support. 4887 * 4888 * When set, it indicates that the internal PHYRDY signal changed state. 4889 * This bit reflects the state of PxSERR.DIAG.N. 4890 * 4891 * There are three kinds of conditions to generate this interrupt event: 4892 * 1. a device is inserted 4893 * 2. a device is disconnected 4894 * 3. when the link enters/exits a Partial or Slumber interface power 4895 * management state 4896 * 4897 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4898 * bit may be set due to the link entering the Partial or Slumber power 4899 * management state, rather than due to a hot plug insertion or removal 4900 * event. So far, the interface power management is disabled, so the 4901 * driver can reliably get removal detection notification via the 4902 * PxSERR.DIAG.N bit. 4903 */ 4904static int 4905ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4906 ahci_port_t *ahci_portp, uint8_t port) 4907{ 4908 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4909 sata_device_t sdevice; 4910 int dev_exists_now = 0; 4911 int dev_existed_previously = 0; 4912 4913 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4914 "ahci_intr_phyrdy_change enter, port %d", port); 4915 4916 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4917 mutex_enter(&ahci_portp->ahciport_mutex); 4918 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4919 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4920 SERROR_PHY_RDY_CHG); 4921 mutex_exit(&ahci_portp->ahciport_mutex); 4922 4923 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4924 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4925 (ahci_portp == NULL)) { 4926 /* The whole controller setup is not yet done. */ 4927 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4928 return (AHCI_SUCCESS); 4929 } 4930 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4931 4932 mutex_enter(&ahci_portp->ahciport_mutex); 4933 4934 /* SStatus tells the presence of device. */ 4935 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4936 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4937 4938 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4939 dev_exists_now = 1; 4940 } 4941 4942 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4943 dev_existed_previously = 1; 4944 } 4945 4946 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4947 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4948 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4949 "ahci_intr_phyrdy_change: port %d " 4950 "AHCI_PORT_FLAG_NODEV is cleared", port); 4951 if (dev_exists_now == 0) 4952 dev_existed_previously = 1; 4953 } 4954 4955 bzero((void *)&sdevice, sizeof (sata_device_t)); 4956 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4957 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4958 sdevice.satadev_addr.pmport = 0; 4959 sdevice.satadev_state = SATA_PSTATE_PWRON; 4960 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4961 4962 if (dev_exists_now) { 4963 if (dev_existed_previously) { 4964 /* Things are fine now. The loss was temporary. */ 4965 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4966 "ahci_intr_phyrdy_change port %d " 4967 "device link lost/established", port); 4968 4969 mutex_exit(&ahci_portp->ahciport_mutex); 4970 sata_hba_event_notify( 4971 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4972 &sdevice, 4973 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4974 mutex_enter(&ahci_portp->ahciport_mutex); 4975 4976 } else { 4977 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4978 "ahci_intr_phyrdy_change: port %d " 4979 "device link established", port); 4980 4981 /* A new device has been detected. */ 4982 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4983 4984 /* Try to start the port */ 4985 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4986 != AHCI_SUCCESS) { 4987 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4988 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4989 "ahci_intr_phyrdy_change: port %d failed " 4990 "at start port", port); 4991 } 4992 4993 /* Clear the max queue depth for inserted device */ 4994 ahci_portp->ahciport_max_ncq_tags = 0; 4995 4996 mutex_exit(&ahci_portp->ahciport_mutex); 4997 sata_hba_event_notify( 4998 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4999 &sdevice, 5000 SATA_EVNT_LINK_ESTABLISHED); 5001 mutex_enter(&ahci_portp->ahciport_mutex); 5002 5003 } 5004 } else { /* No device exists now */ 5005 5006 if (dev_existed_previously) { 5007 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5008 "ahci_intr_phyrdy_change: port %d " 5009 "device link lost", port); 5010 5011 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 5012 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 5013 ahci_portp, port); 5014 5015 /* An existing device is lost. */ 5016 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 5017 5018 mutex_exit(&ahci_portp->ahciport_mutex); 5019 sata_hba_event_notify( 5020 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5021 &sdevice, 5022 SATA_EVNT_LINK_LOST); 5023 mutex_enter(&ahci_portp->ahciport_mutex); 5024 5025 } else { 5026 5027 /* Spurious interrupt */ 5028 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 5029 "ahci_intr_phyrdy_change: " 5030 "spurious phy ready interrupt"); 5031 } 5032 } 5033 5034 mutex_exit(&ahci_portp->ahciport_mutex); 5035 5036 return (AHCI_SUCCESS); 5037} 5038 5039/* 5040 * PxIS.UFS - Unknown FIS Error 5041 * 5042 * This interrupt event means an unknown FIS was received and has been 5043 * copied into system memory. An unknown FIS is not considered an illegal 5044 * FIS, unless the length received is more than 64 bytes. If an unknown 5045 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5046 * normal operation. If the unknown FIS is more than 64 bytes, then it 5047 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5048 * a fatal error. 5049 * 5050 * PxIS.OFS - Overflow Error 5051 * 5052 * Command list overflow is defined as software building a command table 5053 * that has fewer total bytes than the transaction given to the device. 5054 * On device writes, the HBA will run out of data, and on reads, there 5055 * will be no room to put the data. 5056 * 5057 * For an overflow on data read, either PIO or DMA, the HBA will set 5058 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5059 * non-fatal error when the HBA can continues. Sometimes, it will cause 5060 * a fatal error and need the software to do something. 5061 * 5062 * For an overflow on data write, setting PxIS.OFS is optional for both 5063 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5064 * software to clean up from this serious error. 5065 * 5066 * PxIS.INFS - Interface Non-Fatal Error 5067 * 5068 * This interrupt event indicates that the HBA encountered an error on 5069 * the Serial ATA interface but was able to continue operation. The kind 5070 * of error usually occurred during a non-Data FIS, and under this condition 5071 * the FIS will be re-transmitted by HBA automatically. 5072 * 5073 * When the FMA is implemented, there should be a stat structure to 5074 * record how many every kind of error happens. 5075 */ 5076static int 5077ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5078 uint8_t port, uint32_t intr_status) 5079{ 5080 uint32_t port_serror; 5081#if AHCI_DEBUG 5082 uint32_t port_cmd_status; 5083 uint32_t port_cmd_issue; 5084 uint32_t port_sactive; 5085 int current_slot; 5086 uint32_t current_tags; 5087 sata_pkt_t *satapkt; 5088#endif 5089 5090 mutex_enter(&ahci_portp->ahciport_mutex); 5091 5092 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5093 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5094 5095 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5096 "ahci_intr_non_fatal_error: port %d, " 5097 "port_serror = 0x%x", port, port_serror); 5098 5099 ahci_log_serror_message(ahci_ctlp, port, port_serror); 5100 5101 if (intr_status & AHCI_INTR_STATUS_UFS) { 5102 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5103 "ahci port %d has unknown FIS error", port); 5104 5105 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5106 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5107 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5108 SERROR_FIS_TYPE); 5109 } 5110 5111#if AHCI_DEBUG 5112 if (intr_status & AHCI_INTR_STATUS_OFS) { 5113 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5114 "ahci port %d has overflow error", port); 5115 } 5116 5117 if (intr_status & AHCI_INTR_STATUS_INFS) { 5118 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5119 "ahci port %d has interface non fatal error", port); 5120 } 5121 5122 /* 5123 * Record the error occurred command's slot. 5124 */ 5125 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5126 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5127 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5128 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5129 5130 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5131 AHCI_CMD_STATUS_CCS_SHIFT; 5132 5133 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5134 satapkt = ahci_portp->ahciport_err_retri_pkt; 5135 ASSERT(satapkt != NULL); 5136 ASSERT(current_slot == 0); 5137 } else { 5138 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5139 } 5140 5141 if (satapkt != NULL) { 5142 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5143 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5144 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5145 satapkt->satapkt_cmd.satacmd_cmd_reg); 5146 5147 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5148 "ahci_intr_non_fatal_error: port %d, " 5149 "satapkt 0x%p is being processed when error occurs", 5150 port, (void *)satapkt); 5151 } 5152 } 5153 5154 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5155 /* 5156 * For queued command, list those command which have already 5157 * been transmitted to the device and still not completed. 5158 */ 5159 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5160 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5161 5162 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5163 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5164 5165 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5166 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5167 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5168 ahci_portp->ahciport_pending_ncq_tags, 5169 port_sactive, port_cmd_issue); 5170 5171 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5172 port_sactive & ~port_cmd_issue & 5173 AHCI_NCQ_SLOT_MASK(ahci_portp); 5174 5175 while (current_tags) { 5176 current_slot = ddi_ffs(current_tags) - 1; 5177 if (current_slot == -1) { 5178 goto out; 5179 } 5180 5181 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5182 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5183 ahci_ctlp, "ahci_intr_non_fatal_error: " 5184 "port %d, satapkt 0x%p is outstanding when " 5185 "error occurs", port, (void *)satapkt); 5186 } 5187 } 5188out: 5189#endif 5190 mutex_exit(&ahci_portp->ahciport_mutex); 5191 5192 return (AHCI_SUCCESS); 5193} 5194 5195/* 5196 * According to the AHCI spec, the error types include system memory 5197 * errors, interface errors, port multiplier errors, device errors, 5198 * command list overflow, command list underflow, native command 5199 * queuing tag errors and pio data transfer errors. 5200 * 5201 * System memory errors such as target abort, master abort, and parity 5202 * may cause the host to stop, and they are serious errors and needed 5203 * to be recovered with software intervention. When system software 5204 * has given a pointer to the HBA that doesn't exist in physical memory, 5205 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5206 * data error such as CRC or parity occurs, the HBA aborts the transfer 5207 * (if necessary) and PxIS.HBDS will be set. 5208 * 5209 * Interface errors are errors that occur due to electrical issues on 5210 * the interface, or protocol miscommunication between the device and 5211 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5212 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5213 * causes PxIS.IFS/PxIS.INFS to be set are 5214 * 1. in PxSERR.ERR, P bit is set to '1' 5215 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5216 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5217 * If the error occurred during a non-data FIS, the FIS must be 5218 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5219 * the error occurred during a data FIS, the transfer will stop, so 5220 * the error is fatal and PxIS.IFS is set. 5221 * 5222 * When a FIS arrives that updates the taskfile, the HBA checks to see 5223 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5224 * stops processing any more commands. 5225 * 5226 * Command list overflow is defined as software building a command table 5227 * that has fewer total bytes than the transaction given to the device. 5228 * On device writes, the HBA will run out of data, and on reads, there 5229 * will be no room to put the data. For an overflow on data read, either 5230 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5231 * For an overflow on data write, setting PxIS.OFS is optional for both 5232 * DMA and PIO, and a COMRESET is required by software to clean up from 5233 * this serious error. 5234 * 5235 * Command list underflow is defined as software building a command 5236 * table that has more total bytes than the transaction given to the 5237 * device. For data writes, both PIO and DMA, the device will detect 5238 * an error and end the transfer. And these errors are most likely going 5239 * to be fatal errors that will cause the port to be restarted. For 5240 * data reads, the HBA updates its PRD byte count, and may be 5241 * able to continue normally, but is not required to. And The HBA is 5242 * not required to detect underflow conditions for native command 5243 * queuing command. 5244 * 5245 * The HBA does not actively check incoming DMA Setup FISes to ensure 5246 * that the PxSACT register bit for that slot is set. Existing error 5247 * mechanisms, such as host bus failure, or bad protocol, are used to 5248 * recover from this case. 5249 * 5250 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5251 * DATA FIS must be an integral number of Dwords. If the HBA receives 5252 * a request which is not an integral number of Dwords, the HBA 5253 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5254 * software restarts the port. And the HBA ensures that the size 5255 * of the DATA FIS received during a PIO command matches the size in 5256 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5257 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5258 * stop running until software restarts the port. 5259 */ 5260/* 5261 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5262 * 5263 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5264 * interface which caused the transfer to stop. 5265 * 5266 * PxIS.HBDS indicates that the hba encountered a data error 5267 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5268 * 5269 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5270 * cannot recover from, such as a bad software pointer. 5271 * 5272 * PxIS.TFES is set whenever the status register is updated by the device 5273 * and the error bit (bit 0) is set. 5274 */ 5275static int 5276ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5277 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5278{ 5279 uint32_t port_cmd_status; 5280 uint32_t port_serror; 5281 uint32_t task_file_status; 5282 int failed_slot; 5283 sata_pkt_t *spkt = NULL; 5284 uint8_t err_byte; 5285 ahci_event_arg_t *args; 5286 5287 mutex_enter(&ahci_portp->ahciport_mutex); 5288 5289 /* 5290 * ahci_intr_phyrdy_change() may have rendered it to 5291 * SATA_DTYPE_NONE. 5292 */ 5293 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5294 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5295 "ahci_intr_fatal_error: port %d no device attached, " 5296 "and just return without doing anything", port); 5297 goto out0; 5298 } 5299 5300 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5301 /* 5302 * Read PxCMD.CCS to determine the slot that the HBA 5303 * was processing when the error occurred. 5304 */ 5305 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5306 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5307 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5308 AHCI_CMD_STATUS_CCS_SHIFT; 5309 5310 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5311 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5312 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5313 "fatal error occurred for port %d", spkt, port); 5314 5315 if (intr_status & AHCI_INTR_STATUS_TFES) { 5316 task_file_status = ddi_get32( 5317 ahci_ctlp->ahcictl_ahci_acc_handle, 5318 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5319 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5320 "ahci_intr_fatal_error: port %d " 5321 "task_file_status = 0x%x", port, task_file_status); 5322 5323 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5324 >> AHCI_TFD_ERR_SHIFT; 5325 5326 /* 5327 * Won't emit the error message if it is an IDENTIFY 5328 * DEVICE command sent to an ATAPI device. 5329 */ 5330 if ((spkt != NULL) && 5331 (spkt->satapkt_cmd.satacmd_cmd_reg == 5332 SATAC_ID_DEVICE) && 5333 (err_byte == SATA_ERROR_ABORT)) 5334 goto out1; 5335 5336 /* 5337 * Won't emit the error message if it is an ATAPI PACKET 5338 * command 5339 */ 5340 if ((spkt != NULL) && 5341 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5342 goto out1; 5343 } 5344 } 5345 5346 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5347 5348out1: 5349 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5350 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5351 ahci_log_serror_message(ahci_ctlp, port, port_serror); 5352 5353 /* Prepare the argument for the taskq */ 5354 args = ahci_portp->ahciport_event_args; 5355 args->ahciea_ctlp = (void *)ahci_ctlp; 5356 args->ahciea_portp = (void *)ahci_portp; 5357 args->ahciea_event = intr_status; 5358 5359 /* Start the taskq to handle error recovery */ 5360 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5361 ahci_events_handler, 5362 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5363 cmn_err(CE_WARN, "ahci start taskq for event handler failed"); 5364 } 5365out0: 5366 mutex_exit(&ahci_portp->ahciport_mutex); 5367 5368 return (AHCI_SUCCESS); 5369} 5370 5371/* 5372 * Hot Plug Operation for platforms that support Cold Presence Detect. 5373 * 5374 * When set, a device status has changed as detected by the cold presence 5375 * detect logic. This bit can either be set due to a non-connected port 5376 * receiving a device, or a connected port having its device removed. 5377 * This bit is only valid if the port supports cold presence detect as 5378 * indicated by PxCMD.CPD set to '1'. 5379 * 5380 * At the moment, this interrupt is not needed and disabled and we just 5381 * log the debug message. 5382 */ 5383/* ARGSUSED */ 5384static int 5385ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5386 ahci_port_t *ahci_portp, uint8_t port) 5387{ 5388 uint32_t port_cmd_status; 5389 sata_device_t sdevice; 5390 5391 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5392 "ahci_intr_cold_port_detect enter, port %d", port); 5393 5394 mutex_enter(&ahci_portp->ahciport_mutex); 5395 5396 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5397 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5398 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5399 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5400 "port %d does not support cold presence detect, so " 5401 "we just ignore this interrupt", port); 5402 mutex_exit(&ahci_portp->ahciport_mutex); 5403 return (AHCI_SUCCESS); 5404 } 5405 5406 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5407 "port %d device status has changed", port); 5408 5409 bzero((void *)&sdevice, sizeof (sata_device_t)); 5410 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5411 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5412 sdevice.satadev_addr.pmport = 0; 5413 sdevice.satadev_state = SATA_PSTATE_PWRON; 5414 5415 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5416 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5417 "port %d: a device is hot plugged", port); 5418 mutex_exit(&ahci_portp->ahciport_mutex); 5419 sata_hba_event_notify( 5420 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5421 &sdevice, 5422 SATA_EVNT_DEVICE_ATTACHED); 5423 mutex_enter(&ahci_portp->ahciport_mutex); 5424 5425 } else { 5426 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5427 "port %d: a device is hot unplugged", port); 5428 mutex_exit(&ahci_portp->ahciport_mutex); 5429 sata_hba_event_notify( 5430 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5431 &sdevice, 5432 SATA_EVNT_DEVICE_DETACHED); 5433 mutex_enter(&ahci_portp->ahciport_mutex); 5434 } 5435 5436 mutex_exit(&ahci_portp->ahciport_mutex); 5437 5438 return (AHCI_SUCCESS); 5439} 5440 5441/* 5442 * Enable the interrupts for a particular port. 5443 * 5444 * WARNING!!! ahciport_mutex should be acquired before the function 5445 * is called. 5446 */ 5447/* ARGSUSED */ 5448static void 5449ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 5450 ahci_port_t *ahci_portp, uint8_t port) 5451{ 5452 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5453 "ahci_enable_port_intrs enter, port %d", port); 5454 5455 /* 5456 * Clear port interrupt status before enabling interrupt 5457 */ 5458 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5459 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5460 AHCI_PORT_INTR_MASK); 5461 5462 /* 5463 * Clear the pending bit from IS.IPS 5464 */ 5465 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5466 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5467 5468 /* 5469 * Enable the following interrupts: 5470 * Device to Host Register FIS Interrupt (DHRS) 5471 * PIO Setup FIS Interrupt (PSS) 5472 * Set Device Bits Interrupt (SDBS) 5473 * Unknown FIS Interrupt (UFS) 5474 * Port Connect Change Status (PCS) 5475 * PhyRdy Change Status (PRCS) 5476 * Overflow Status (OFS) 5477 * Interface Non-fatal Error Status (INFS) 5478 * Interface Fatal Error Status (IFS) 5479 * Host Bus Data Error Status (HBDS) 5480 * Host Bus Fatal Error Status (HBFS) 5481 * Task File Error Status (TFES) 5482 */ 5483 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5484 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5485 (AHCI_INTR_STATUS_DHRS | 5486 AHCI_INTR_STATUS_PSS | 5487 AHCI_INTR_STATUS_SDBS | 5488 AHCI_INTR_STATUS_UFS | 5489 AHCI_INTR_STATUS_DPS | 5490 AHCI_INTR_STATUS_PCS | 5491 AHCI_INTR_STATUS_PRCS | 5492 AHCI_INTR_STATUS_OFS | 5493 AHCI_INTR_STATUS_INFS | 5494 AHCI_INTR_STATUS_IFS | 5495 AHCI_INTR_STATUS_HBDS | 5496 AHCI_INTR_STATUS_HBFS | 5497 AHCI_INTR_STATUS_TFES)); 5498} 5499 5500/* 5501 * Enable interrupts for all the ports. 5502 * 5503 * WARNING!!! ahcictl_mutex should be acquired before the function 5504 * is called. 5505 */ 5506static void 5507ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5508{ 5509 uint32_t ghc_control; 5510 5511 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5512 5513 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5514 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5515 5516 ghc_control |= AHCI_HBA_GHC_IE; 5517 5518 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5519 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5520} 5521 5522/* 5523 * Disable interrupts for a particular port. 5524 * 5525 * WARNING!!! ahciport_mutex should be acquired before the function 5526 * is called. 5527 */ 5528/* ARGSUSED */ 5529static void 5530ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 5531 ahci_port_t *ahci_portp, uint8_t port) 5532{ 5533 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5534 "ahci_disable_port_intrs enter, port %d", port); 5535 5536 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5537 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5538} 5539 5540/* 5541 * Disable interrupts for the whole HBA. 5542 * 5543 * The global bit is cleared, then all interrupt sources from all 5544 * ports are disabled. 5545 * 5546 * WARNING!!! ahcictl_mutex should be acquired before the function 5547 * is called. 5548 */ 5549static void 5550ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5551{ 5552 uint32_t ghc_control; 5553 5554 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5555 5556 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5557 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5558 5559 ghc_control &= ~ AHCI_HBA_GHC_IE; 5560 5561 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5562 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5563} 5564 5565/* 5566 * Handle INTx and legacy interrupts. 5567 */ 5568static int 5569ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5570{ 5571 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5572 int actual, count = 0; 5573 int x, y, rc, inum = 0; 5574 5575 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5576 "ahci_add_legacy_intrs enter"); 5577 5578 /* get number of interrupts. */ 5579 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5580 if ((rc != DDI_SUCCESS) || (count == 0)) { 5581 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5582 "ddi_intr_get_nintrs() failed, " 5583 "rc %d count %d\n", rc, count); 5584 return (DDI_FAILURE); 5585 } 5586 5587 /* Allocate an array of interrupt handles. */ 5588 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5589 ahci_ctlp->ahcictl_intr_htable = 5590 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5591 5592 /* call ddi_intr_alloc(). */ 5593 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5594 DDI_INTR_TYPE_FIXED, 5595 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5596 5597 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5598 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5599 "ddi_intr_alloc() failed, rc %d\n", rc); 5600 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5601 ahci_ctlp->ahcictl_intr_size); 5602 return (DDI_FAILURE); 5603 } 5604 5605 if (actual < count) { 5606 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5607 "Requested: %d, Received: %d", count, actual); 5608 5609 for (x = 0; x < actual; x++) { 5610 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5611 } 5612 5613 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5614 ahci_ctlp->ahcictl_intr_size); 5615 return (DDI_FAILURE); 5616 } 5617 5618 ahci_ctlp->ahcictl_intr_cnt = actual; 5619 5620 /* Get intr priority. */ 5621 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5622 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5623 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5624 "ddi_intr_get_pri() failed"); 5625 5626 for (x = 0; x < actual; x++) { 5627 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5628 } 5629 5630 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5631 ahci_ctlp->ahcictl_intr_size); 5632 return (DDI_FAILURE); 5633 } 5634 5635 /* Test for high level interrupt. */ 5636 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5637 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5638 "ahci_add_legacy_intrs: Hi level intr not supported"); 5639 5640 for (x = 0; x < actual; x++) { 5641 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5642 } 5643 5644 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5645 sizeof (ddi_intr_handle_t)); 5646 5647 return (DDI_FAILURE); 5648 } 5649 5650 /* Call ddi_intr_add_handler(). */ 5651 for (x = 0; x < actual; x++) { 5652 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5653 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5654 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5655 "ddi_intr_add_handler() failed"); 5656 5657 for (y = 0; y < actual; y++) { 5658 (void) ddi_intr_free( 5659 ahci_ctlp->ahcictl_intr_htable[y]); 5660 } 5661 5662 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5663 ahci_ctlp->ahcictl_intr_size); 5664 return (DDI_FAILURE); 5665 } 5666 } 5667 5668 /* Call ddi_intr_enable() for legacy interrupts. */ 5669 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5670 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5671 } 5672 5673 return (DDI_SUCCESS); 5674} 5675 5676/* 5677 * Handle MSI interrupts. 5678 */ 5679static int 5680ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5681{ 5682 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5683 int count, avail, actual; 5684 int x, y, rc, inum = 0; 5685 5686 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5687 "ahci_add_msi_intrs enter"); 5688 5689 /* get number of interrupts. */ 5690 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5691 if ((rc != DDI_SUCCESS) || (count == 0)) { 5692 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5693 "ddi_intr_get_nintrs() failed, " 5694 "rc %d count %d\n", rc, count); 5695 return (DDI_FAILURE); 5696 } 5697 5698 /* get number of available interrupts. */ 5699 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5700 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5701 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5702 "ddi_intr_get_navail() failed, " 5703 "rc %d avail %d\n", rc, avail); 5704 return (DDI_FAILURE); 5705 } 5706 5707 if (avail < count) { 5708 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5709 "ddi_intr_get_nvail returned %d, navail() returned %d", 5710 count, avail); 5711 } 5712 5713 /* Allocate an array of interrupt handles. */ 5714 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5715 ahci_ctlp->ahcictl_intr_htable = 5716 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5717 5718 /* call ddi_intr_alloc(). */ 5719 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5720 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5721 5722 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5723 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5724 "ddi_intr_alloc() failed, rc %d\n", rc); 5725 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5726 ahci_ctlp->ahcictl_intr_size); 5727 return (DDI_FAILURE); 5728 } 5729 5730 /* use interrupt count returned */ 5731 if (actual < count) { 5732 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5733 "Requested: %d, Received: %d", count, actual); 5734 } 5735 5736 ahci_ctlp->ahcictl_intr_cnt = actual; 5737 5738 /* 5739 * Get priority for first msi, assume remaining are all the same. 5740 */ 5741 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5742 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5743 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5744 "ddi_intr_get_pri() failed"); 5745 5746 /* Free already allocated intr. */ 5747 for (y = 0; y < actual; y++) { 5748 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5749 } 5750 5751 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5752 ahci_ctlp->ahcictl_intr_size); 5753 return (DDI_FAILURE); 5754 } 5755 5756 /* Test for high level interrupt. */ 5757 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5758 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5759 "ahci_add_msi_intrs: Hi level intr not supported"); 5760 5761 /* Free already allocated intr. */ 5762 for (y = 0; y < actual; y++) { 5763 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5764 } 5765 5766 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5767 sizeof (ddi_intr_handle_t)); 5768 5769 return (DDI_FAILURE); 5770 } 5771 5772 /* Call ddi_intr_add_handler(). */ 5773 for (x = 0; x < actual; x++) { 5774 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5775 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5776 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5777 "ddi_intr_add_handler() failed"); 5778 5779 /* Free already allocated intr. */ 5780 for (y = 0; y < actual; y++) { 5781 (void) ddi_intr_free( 5782 ahci_ctlp->ahcictl_intr_htable[y]); 5783 } 5784 5785 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5786 ahci_ctlp->ahcictl_intr_size); 5787 return (DDI_FAILURE); 5788 } 5789 } 5790 5791 5792 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5793 &ahci_ctlp->ahcictl_intr_cap); 5794 5795 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5796 /* Call ddi_intr_block_enable() for MSI. */ 5797 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5798 ahci_ctlp->ahcictl_intr_cnt); 5799 } else { 5800 /* Call ddi_intr_enable() for MSI non block enable. */ 5801 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5802 (void) ddi_intr_enable( 5803 ahci_ctlp->ahcictl_intr_htable[x]); 5804 } 5805 } 5806 5807 return (DDI_SUCCESS); 5808} 5809 5810/* 5811 * Removes the registered interrupts irrespective of whether they 5812 * were legacy or MSI. 5813 * 5814 * WARNING!!! The controller interrupts must be disabled before calling 5815 * this routine. 5816 */ 5817static void 5818ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5819{ 5820 int x; 5821 5822 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5823 5824 /* Disable all interrupts. */ 5825 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5826 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5827 /* Call ddi_intr_block_disable(). */ 5828 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5829 ahci_ctlp->ahcictl_intr_cnt); 5830 } else { 5831 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5832 (void) ddi_intr_disable( 5833 ahci_ctlp->ahcictl_intr_htable[x]); 5834 } 5835 } 5836 5837 /* Call ddi_intr_remove_handler(). */ 5838 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5839 (void) ddi_intr_remove_handler( 5840 ahci_ctlp->ahcictl_intr_htable[x]); 5841 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5842 } 5843 5844 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5845} 5846 5847/* 5848 * This routine tries to put port into P:NotRunning state by clearing 5849 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5850 * and PxCMD.CR to '0'. 5851 * 5852 * WARNING!!! ahciport_mutex should be acquired before the function 5853 * is called. 5854 */ 5855/* ARGSUSED */ 5856static int 5857ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5858 ahci_port_t *ahci_portp, uint8_t port) 5859{ 5860 uint32_t port_cmd_status; 5861 int loop_count; 5862 5863 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5864 "ahci_put_port_into_notrunning_state enter: port %d", port); 5865 5866 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5867 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5868 5869 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5870 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5871 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5872 5873 /* Wait until PxCMD.CR is cleared */ 5874 loop_count = 0; 5875 do { 5876 port_cmd_status = 5877 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5878 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5879 5880 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5881 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5882 "clearing port %d CMD.CR timeout, " 5883 "port_cmd_status = 0x%x", port, 5884 port_cmd_status); 5885 /* 5886 * We are effectively timing out after 0.5 sec. 5887 * This value is specified in AHCI spec. 5888 */ 5889 break; 5890 } 5891 5892 /* Wait for 10 millisec */ 5893#ifndef __lock_lint 5894 delay(AHCI_10MS_TICKS); 5895#endif /* __lock_lint */ 5896 5897 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5898 5899 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5900 5901 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5902 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5903 "ahci_put_port_into_notrunning_state: failed to clear " 5904 "PxCMD.CR to '0' after loop count: %d, and " 5905 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5906 return (AHCI_FAILURE); 5907 } else { 5908 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5909 "ahci_put_port_into_notrunning_state: succeeded to clear " 5910 "PxCMD.CR to '0' after loop count: %d, and " 5911 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5912 return (AHCI_SUCCESS); 5913 } 5914} 5915 5916/* 5917 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5918 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5919 * stable state, then set PxCMD.ST to '1' to start the port directly. 5920 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5921 * COMRESET to the device to put it in an idle state. 5922 * 5923 * The fifth argument returns whether the port reset is involved during 5924 * the process. 5925 * 5926 * The routine will be called under six scenarios: 5927 * 1. Initialize the port 5928 * 2. To abort the packet(s) 5929 * 3. To reset the port 5930 * 4. To activate the port 5931 * 5. Fatal error recovery 5932 * 6. To abort the timeout packet(s) 5933 * 5934 * WARNING!!! ahciport_mutex should be acquired before the function 5935 * is called. And ahciport_mutex will be released before the reset 5936 * event is reported to sata module by calling sata_hba_event_notify, 5937 * and then be acquired again later. 5938 * 5939 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5940 * according to the spec, the clearance of three bits will also clear 5941 * three interrupt status bits. 5942 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5943 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5944 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5945 * 5946 * Among these three interrupt events, the driver needs to take care of 5947 * PxIS.PRCS, which is the hot plug event. When the driver found out 5948 * a device was unplugged, it will call the interrupt handler. 5949 */ 5950static int 5951ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5952 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5953{ 5954 uint32_t port_sstatus; 5955 uint32_t task_file_status; 5956 sata_device_t sdevice; 5957 int rval; 5958 int dev_exists_begin = 0; 5959 int dev_exists_end = 0; 5960 5961 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5962 "ahci_restart_port_wait_till_ready: port %d enter", port); 5963 5964 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 5965 dev_exists_begin = 1; 5966 5967 /* First clear PxCMD.ST */ 5968 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5969 port); 5970 if (rval != AHCI_SUCCESS) 5971 /* 5972 * If PxCMD.CR does not clear within a reasonable time, it 5973 * may assume the interface is in a hung condition and may 5974 * continue with issuing the port reset. 5975 */ 5976 goto reset; 5977 5978 /* Then clear PxSERR */ 5979 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5980 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5981 AHCI_SERROR_CLEAR_ALL); 5982 5983 /* Then get PxTFD */ 5984 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5985 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5986 5987 /* 5988 * Check whether the device is in a stable status, if yes, 5989 * then start the port directly. However for ahci_tran_dport_reset, 5990 * we may have to perform a port reset. 5991 */ 5992 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5993 !(flag & AHCI_PORT_RESET)) 5994 goto out; 5995 5996reset: 5997 /* 5998 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5999 * a COMRESET to the device 6000 */ 6001 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 6002 if (rval != AHCI_SUCCESS) 6003 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6004 "ahci_restart_port_wait_till_ready: port %d failed", 6005 port); 6006 6007 if (reset_flag != NULL) 6008 *reset_flag = 1; 6009 6010 /* Indicate to the framework that a reset has happened. */ 6011 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 6012 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 6013 /* Set the reset in progress flag */ 6014 ahci_portp->ahciport_reset_in_progress = 1; 6015 6016 bzero((void *)&sdevice, sizeof (sata_device_t)); 6017 sdevice.satadev_addr.cport = 6018 ahci_ctlp->ahcictl_port_to_cport[port]; 6019 sdevice.satadev_addr.pmport = 0; 6020 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6021 6022 sdevice.satadev_state = SATA_DSTATE_RESET | 6023 SATA_DSTATE_PWR_ACTIVE; 6024 if (ahci_ctlp->ahcictl_sata_hba_tran) { 6025 mutex_exit(&ahci_portp->ahciport_mutex); 6026 sata_hba_event_notify( 6027 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6028 &sdevice, 6029 SATA_EVNT_DEVICE_RESET); 6030 mutex_enter(&ahci_portp->ahciport_mutex); 6031 } 6032 6033 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 6034 "port %d sending event up: SATA_EVNT_RESET", port); 6035 } else { 6036 ahci_portp->ahciport_reset_in_progress = 0; 6037 } 6038 6039out: 6040 /* Start the port */ 6041 if (!(flag & AHCI_PORT_INIT)) { 6042 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6043 } 6044 6045 /* SStatus tells the presence of device. */ 6046 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6047 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6048 6049 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6050 dev_exists_end = 1; 6051 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6052 } 6053 6054 /* Check whether a hot plug event happened */ 6055 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6056 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6057 "ahci_restart_port_wait_till_ready: port %d " 6058 "device is removed", port); 6059 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6060 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6061 "ahci_restart_port_wait_till_ready: port %d " 6062 "AHCI_PORT_FLAG_NODEV flag is set", port); 6063 mutex_exit(&ahci_portp->ahciport_mutex); 6064 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6065 mutex_enter(&ahci_portp->ahciport_mutex); 6066 } 6067 6068 return (rval); 6069} 6070 6071/* 6072 * This routine may be called under four scenarios: 6073 * a) do the recovery from fatal error 6074 * b) or we need to timeout some commands 6075 * c) or we need to abort some commands 6076 * d) or we need reset device/port/controller 6077 * 6078 * In all these scenarios, we need to send any pending unfinished 6079 * commands up to sata framework. 6080 * 6081 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6082 */ 6083static void 6084ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6085 ahci_port_t *ahci_portp, 6086 uint8_t port, 6087 uint32_t slot_status, 6088 uint32_t failed_tags, 6089 uint32_t timeout_tags, 6090 uint32_t aborted_tags, 6091 uint32_t reset_tags) 6092{ 6093 uint32_t finished_tags = 0; 6094 uint32_t unfinished_tags = 0; 6095 int tmp_slot; 6096 sata_pkt_t *satapkt; 6097 int ncq_cmd_in_progress = 0; 6098 int err_retri_cmd_in_progress = 0; 6099 6100 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6101 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6102 port, slot_status); 6103 6104 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6105 "ahci_mop_commands: failed_tags: 0x%x, " 6106 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6107 "reset_tags: 0x%x", failed_tags, 6108 timeout_tags, aborted_tags, reset_tags); 6109 6110 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6111 finished_tags = ahci_portp->ahciport_pending_tags & 6112 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6113 6114 unfinished_tags = slot_status & 6115 AHCI_SLOT_MASK(ahci_ctlp) & 6116 ~failed_tags & 6117 ~aborted_tags & 6118 ~reset_tags & 6119 ~timeout_tags; 6120 } 6121 6122 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6123 ncq_cmd_in_progress = 1; 6124 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6125 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6126 6127 unfinished_tags = slot_status & 6128 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6129 ~failed_tags & 6130 ~aborted_tags & 6131 ~reset_tags & 6132 ~timeout_tags; 6133 } 6134 6135 /* 6136 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is set, 6137 * it means REQUEST SENSE or READ LOG EXT command doesn't complete 6138 * successfully due to one of the following three conditions: 6139 * 6140 * 1. Fatal error - failed_tags includes its slot 6141 * 2. Timed out - timeout_tags includes its slot 6142 * 3. Aborted when hot unplug - aborted_tags includes its slot 6143 * 6144 * Please note that the command is always sent down in Slot 0 6145 */ 6146 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6147 err_retri_cmd_in_progress = 1; 6148 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6149 "ahci_mop_commands is called for port %d while " 6150 "REQUEST SENSE or READ LOG EXT for error retrieval " 6151 "is being executed", port); 6152 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6153 ASSERT(slot_status == 0x1); 6154 } 6155 6156 /* Send up finished packets with SATA_PKT_COMPLETED */ 6157 while (finished_tags) { 6158 tmp_slot = ddi_ffs(finished_tags) - 1; 6159 if (tmp_slot == -1) { 6160 break; 6161 } 6162 6163 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6164 ASSERT(satapkt != NULL); 6165 6166 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6167 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6168 (void *)satapkt); 6169 6170 /* 6171 * Cannot fetch the return register content since the port 6172 * was restarted, so the corresponding tag will be set to 6173 * aborted tags. 6174 */ 6175 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6176 CLEAR_BIT(finished_tags, tmp_slot); 6177 aborted_tags |= tmp_slot; 6178 continue; 6179 } 6180 6181 if (ncq_cmd_in_progress) 6182 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6183 tmp_slot); 6184 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6185 CLEAR_BIT(finished_tags, tmp_slot); 6186 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6187 6188 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6189 } 6190 6191 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6192 while (failed_tags) { 6193 if (err_retri_cmd_in_progress) { 6194 satapkt = ahci_portp->ahciport_err_retri_pkt; 6195 ASSERT(satapkt != NULL); 6196 ASSERT(failed_tags == 0x1); 6197 6198 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6199 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6200 (void *)satapkt); 6201 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6202 break; 6203 } 6204 6205 tmp_slot = ddi_ffs(failed_tags) - 1; 6206 if (tmp_slot == -1) { 6207 break; 6208 } 6209 6210 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6211 ASSERT(satapkt != NULL); 6212 6213 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6214 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6215 (void *)satapkt); 6216 6217 if (ncq_cmd_in_progress) 6218 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6219 tmp_slot); 6220 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6221 CLEAR_BIT(failed_tags, tmp_slot); 6222 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6223 6224 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6225 } 6226 6227 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6228 while (timeout_tags) { 6229 if (err_retri_cmd_in_progress) { 6230 satapkt = ahci_portp->ahciport_err_retri_pkt; 6231 ASSERT(satapkt != NULL); 6232 ASSERT(timeout_tags == 0x1); 6233 6234 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6235 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6236 (void *)satapkt); 6237 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6238 break; 6239 } 6240 6241 tmp_slot = ddi_ffs(timeout_tags) - 1; 6242 if (tmp_slot == -1) { 6243 break; 6244 } 6245 6246 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6247 ASSERT(satapkt != NULL); 6248 6249 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6250 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6251 (void *)satapkt); 6252 6253 if (ncq_cmd_in_progress) 6254 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6255 tmp_slot); 6256 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6257 CLEAR_BIT(timeout_tags, tmp_slot); 6258 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6259 6260 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6261 } 6262 6263 /* Send up aborted packets with SATA_PKT_ABORTED */ 6264 while (aborted_tags) { 6265 if (err_retri_cmd_in_progress) { 6266 satapkt = ahci_portp->ahciport_err_retri_pkt; 6267 ASSERT(satapkt != NULL); 6268 ASSERT(aborted_tags == 0x1); 6269 6270 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6271 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6272 (void *)satapkt); 6273 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6274 break; 6275 } 6276 6277 tmp_slot = ddi_ffs(aborted_tags) - 1; 6278 if (tmp_slot == -1) { 6279 break; 6280 } 6281 6282 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6283 ASSERT(satapkt != NULL); 6284 6285 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6286 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6287 (void *)satapkt); 6288 6289 if (ncq_cmd_in_progress) 6290 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6291 tmp_slot); 6292 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6293 CLEAR_BIT(aborted_tags, tmp_slot); 6294 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6295 6296 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6297 } 6298 6299 /* Send up reset packets with SATA_PKT_RESET. */ 6300 while (reset_tags) { 6301 tmp_slot = ddi_ffs(reset_tags) - 1; 6302 if (tmp_slot == -1) { 6303 break; 6304 } 6305 6306 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6307 ASSERT(satapkt != NULL); 6308 6309 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6310 "sending up pkt 0x%p with SATA_PKT_RESET", 6311 (void *)satapkt); 6312 6313 if (ncq_cmd_in_progress) 6314 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6315 tmp_slot); 6316 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6317 CLEAR_BIT(reset_tags, tmp_slot); 6318 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6319 6320 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6321 } 6322 6323 /* Send up unfinished packets with SATA_PKT_RESET */ 6324 while (unfinished_tags) { 6325 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6326 if (tmp_slot == -1) { 6327 break; 6328 } 6329 6330 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6331 ASSERT(satapkt != NULL); 6332 6333 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6334 "sending up pkt 0x%p with SATA_PKT_RESET", 6335 (void *)satapkt); 6336 6337 if (ncq_cmd_in_progress) 6338 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6339 tmp_slot); 6340 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6341 CLEAR_BIT(unfinished_tags, tmp_slot); 6342 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6343 6344 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6345 } 6346 6347 ahci_portp->ahciport_mop_in_progress--; 6348 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6349 6350 if (ahci_portp->ahciport_mop_in_progress == 0) 6351 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6352} 6353 6354/* 6355 * This routine is going to first request a READ LOG EXT sata pkt from sata 6356 * module, and then deliver it to the HBA to get the ncq failure context. 6357 * The return value is the exactly failed tags. 6358 */ 6359static uint32_t 6360ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6361 uint8_t port) 6362{ 6363 sata_device_t sdevice; 6364 sata_pkt_t *rdlog_spkt, *spkt; 6365 ddi_dma_handle_t buf_dma_handle; 6366 int loop_count; 6367 int rval; 6368 int failed_slot; 6369 uint32_t failed_tags = 0; 6370 struct sata_ncq_error_recovery_page *ncq_err_page; 6371 6372 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6373 "ahci_get_rdlogext_data enter: port %d", port); 6374 6375 /* Prepare the sdevice data */ 6376 bzero((void *)&sdevice, sizeof (sata_device_t)); 6377 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6378 6379 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6380 sdevice.satadev_addr.pmport = 0; 6381 6382 /* 6383 * Call the sata hba interface to get a rdlog spkt 6384 */ 6385 loop_count = 0; 6386loop: 6387 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6388 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6389 if (rdlog_spkt == NULL) { 6390 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6391 /* Sleep for a while */ 6392 delay(AHCI_10MS_TICKS); 6393 goto loop; 6394 } 6395 /* Timed out after 1s */ 6396 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6397 "failed to get rdlog spkt for port %d", port); 6398 return (failed_tags); 6399 } 6400 6401 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6402 6403 /* 6404 * This flag is used to handle the specific error recovery when the 6405 * READ LOG EXT command gets a failure (fatal error or time-out). 6406 */ 6407 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6408 6409 /* 6410 * This start is not supposed to fail because after port is restarted, 6411 * the whole command list is empty. 6412 */ 6413 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6414 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6415 ahci_portp->ahciport_err_retri_pkt = NULL; 6416 6417 /* Remove the flag after READ LOG EXT command is completed */ 6418 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6419 6420 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6421 /* Update the request log data */ 6422 buf_dma_handle = *(ddi_dma_handle_t *) 6423 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6424 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6425 DDI_DMA_SYNC_FORKERNEL); 6426 if (rval == DDI_SUCCESS) { 6427 ncq_err_page = 6428 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6429 satapkt_cmd.satacmd_bp->b_un.b_addr; 6430 6431 /* Get the failed tag */ 6432 failed_slot = ncq_err_page->ncq_tag; 6433 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6434 "ahci_get_rdlogext_data: port %d " 6435 "failed slot %d", port, failed_slot); 6436 if (failed_slot & NQ) { 6437 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6438 "the failed slot is not a valid tag"); 6439 goto out; 6440 } 6441 6442 failed_slot &= NCQ_TAG_MASK; 6443 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6444 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6445 "ahci_get_rdlogext_data: failed spkt 0x%p", 6446 (void *)spkt); 6447 if (spkt == NULL) { 6448 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6449 "the failed slot spkt is NULL") 6450 goto out; 6451 } 6452 6453 failed_tags = 0x1 << failed_slot; 6454 6455 /* Fill out the error context */ 6456 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6457 ncq_err_page); 6458 ahci_update_sata_registers(ahci_ctlp, port, 6459 &spkt->satapkt_device); 6460 } 6461 } else { 6462 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6463 "ahci_get_rdlogext_data: port %d READ LOG EXT command " 6464 "did not successfully complete", port); 6465 } 6466out: 6467 sata_free_error_retrieval_pkt(rdlog_spkt); 6468 6469 return (failed_tags); 6470} 6471 6472/* 6473 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6474 * module, and then deliver it to the HBA to get the sense data and copy 6475 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6476 * SENSE sata pkt later. 6477 */ 6478static void 6479ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6480 uint8_t port, sata_pkt_t *spkt) 6481{ 6482 sata_device_t sdevice; 6483 sata_pkt_t *rs_spkt; 6484 sata_cmd_t *sata_cmd; 6485 ddi_dma_handle_t buf_dma_handle; 6486 int loop_count; 6487#if AHCI_DEBUG 6488 struct scsi_extended_sense *rqsense; 6489#endif 6490 6491 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6492 "ahci_get_rqsense_data enter: port %d", port); 6493 6494 /* Prepare the sdevice data */ 6495 bzero((void *)&sdevice, sizeof (sata_device_t)); 6496 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6497 6498 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6499 sdevice.satadev_addr.pmport = 0; 6500 6501 sata_cmd = &spkt->satapkt_cmd; 6502 6503 /* 6504 * Call the sata hba interface to get a rs spkt 6505 */ 6506 loop_count = 0; 6507loop: 6508 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6509 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6510 if (rs_spkt == NULL) { 6511 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6512 /* Sleep for a while */ 6513 delay(AHCI_10MS_TICKS); 6514 goto loop; 6515 6516 } 6517 /* Timed out after 1s */ 6518 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6519 "failed to get rs spkt for port %d", port); 6520 return; 6521 } 6522 6523 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6524 6525 /* 6526 * This flag is used to handle the specific error recovery when the 6527 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6528 */ 6529 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6530 6531 /* 6532 * This start is not supposed to fail because after port is restarted, 6533 * the whole command list is empty. 6534 */ 6535 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6536 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6537 ahci_portp->ahciport_err_retri_pkt = NULL; 6538 6539 /* Remove the flag after REQUEST SENSE command is completed */ 6540 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6541 6542 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6543 /* Update the request sense data */ 6544 buf_dma_handle = *(ddi_dma_handle_t *) 6545 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6546 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6547 DDI_DMA_SYNC_FORKERNEL); 6548 /* Copy the request sense data */ 6549 bcopy(rs_spkt-> 6550 satapkt_cmd.satacmd_bp->b_un.b_addr, 6551 &sata_cmd->satacmd_rqsense, 6552 SATA_ATAPI_MIN_RQSENSE_LEN); 6553#if AHCI_DEBUG 6554 rqsense = (struct scsi_extended_sense *) 6555 sata_cmd->satacmd_rqsense; 6556 6557 /* Dump the sense data */ 6558 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6559 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6560 "Sense data for satapkt %p ATAPI cmd 0x%x", 6561 spkt, sata_cmd->satacmd_acdb[0]); 6562 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6563 " es_code 0x%x es_class 0x%x " 6564 "es_key 0x%x es_add_code 0x%x " 6565 "es_qual_code 0x%x", 6566 rqsense->es_code, rqsense->es_class, 6567 rqsense->es_key, rqsense->es_add_code, 6568 rqsense->es_qual_code); 6569#endif 6570 } else { 6571 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6572 "ahci_get_rqsense_data: port %d REQUEST SENSE command " 6573 "did not successfully complete", port); 6574 } 6575 6576 sata_free_error_retrieval_pkt(rs_spkt); 6577} 6578 6579/* 6580 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6581 * the port must be restarted. When the HBA detects thus error, it may try 6582 * to abort a transfer. And if the transfer was aborted, the device is 6583 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6584 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6585 * that the device is in a stable status and transfers may be restarted without 6586 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6587 * then the software will send the COMRESET to do the port reset. 6588 * 6589 * Software should perform the appropriate error recovery actions based on 6590 * whether non-queued commands were being issued or natived command queuing 6591 * commands were being issued. 6592 * 6593 * And software will complete the command that had the error with error mark 6594 * to higher level software. 6595 * 6596 * Fatal errors include the following: 6597 * PxIS.IFS - Interface Fatal Error Status 6598 * PxIS.HBDS - Host Bus Data Error Status 6599 * PxIS.HBFS - Host Bus Fatal Error Status 6600 * PxIS.TFES - Task File Error Status 6601 * 6602 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6603 */ 6604static void 6605ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6606 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6607{ 6608 uint32_t port_cmd_status; 6609 uint32_t slot_status = 0; 6610 uint32_t failed_tags = 0; 6611 int failed_slot; 6612 int reset_flag = 0; 6613 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6614 sata_cmd_t *sata_cmd = NULL; 6615 sata_pkt_t *spkt = NULL; 6616 6617 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6618 "ahci_fatal_error_recovery_handler enter: port %d", port); 6619 6620 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6621 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6622 6623 /* Read PxCI to see which commands are still outstanding */ 6624 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6625 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6626 6627 /* 6628 * Read PxCMD.CCS to determine the slot that the HBA 6629 * was processing when the error occurred. 6630 */ 6631 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6632 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6633 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6634 AHCI_CMD_STATUS_CCS_SHIFT; 6635 6636 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6637 spkt = ahci_portp->ahciport_err_retri_pkt; 6638 ASSERT(spkt != NULL); 6639 } else { 6640 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6641 if (spkt == NULL) { 6642 /* May happen when interface errors occur? */ 6643 goto next; 6644 } 6645 } 6646 6647 sata_cmd = &spkt->satapkt_cmd; 6648 6649 /* Fill out the status and error registers for PxIS.TFES */ 6650 if (intr_status & AHCI_INTR_STATUS_TFES) { 6651 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6652 ahcirf_d2h_register_fis); 6653 6654 /* Copy the error context back to the sata_cmd */ 6655 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6656 } 6657 6658 /* The failed command must be one of the outstanding commands */ 6659 failed_tags = 0x1 << failed_slot; 6660 ASSERT(failed_tags & slot_status); 6661 6662 /* Update the sata registers, especially PxSERR register */ 6663 ahci_update_sata_registers(ahci_ctlp, port, 6664 &spkt->satapkt_device); 6665 6666 } 6667 6668 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6669 /* Read PxSACT to see which commands are still outstanding */ 6670 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6671 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6672 } 6673next: 6674 6675#if AHCI_DEBUG 6676 /* 6677 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6678 * set, it means a fatal error happened after REQUEST SENSE command 6679 * or READ LOG EXT command is delivered to the HBA during the error 6680 * recovery process. At this time, the only outstanding command is 6681 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6682 */ 6683 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6684 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6685 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6686 "command or READ LOG EXT command for error data retrieval " 6687 "failed", port); 6688 ASSERT(slot_status == 0x1); 6689 ASSERT(failed_slot == 0x1); 6690 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6691 SCMD_REQUEST_SENSE || 6692 spkt->satapkt_cmd.satacmd_cmd_reg == 6693 SATAC_READ_LOG_EXT); 6694 } 6695#endif 6696 6697 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6698 ahci_portp->ahciport_mop_in_progress++; 6699 6700 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6701 port, NULL, &reset_flag); 6702 6703 /* 6704 * Won't retrieve error information: 6705 * 1. Port reset was involved to recover 6706 * 2. Device is gone 6707 * 3. IDENTIFY DEVICE command sent to ATAPI device 6708 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6709 */ 6710 if (reset_flag || 6711 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6712 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6713 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6714 goto out; 6715 6716 /* 6717 * Deliver READ LOG EXT to gather information about the error when 6718 * a COMRESET has not been performed as part of the error recovery 6719 * during NCQ command processing. 6720 */ 6721 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6722 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6723 ahci_portp, port); 6724 goto out; 6725 } 6726 6727 /* 6728 * Deliver REQUEST SENSE for ATAPI command to gather information about 6729 * the error when a COMRESET has not been performed as part of the 6730 * error recovery. 6731 */ 6732 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6733 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6734out: 6735 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6736 "ahci_fatal_error_recovery_handler: port %d interface error " 6737 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6738 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6739 port, slot_status, ahci_portp->ahciport_pending_tags, 6740 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6741 6742 ahci_mop_commands(ahci_ctlp, 6743 ahci_portp, 6744 port, 6745 slot_status, 6746 failed_tags, /* failed tags */ 6747 0, /* timeout tags */ 6748 0, /* aborted tags */ 6749 0); /* reset tags */ 6750} 6751 6752/* 6753 * Handle events - fatal error recovery 6754 */ 6755static void 6756ahci_events_handler(void *args) 6757{ 6758 ahci_event_arg_t *ahci_event_arg; 6759 ahci_ctl_t *ahci_ctlp; 6760 ahci_port_t *ahci_portp; 6761 uint32_t event; 6762 uint8_t port; 6763 6764 ahci_event_arg = (ahci_event_arg_t *)args; 6765 6766 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6767 ahci_portp = ahci_event_arg->ahciea_portp; 6768 event = ahci_event_arg->ahciea_event; 6769 port = ahci_portp->ahciport_port_num; 6770 6771 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6772 "ahci_events_handler enter: port %d intr_status = 0x%x", 6773 port, event); 6774 6775 mutex_enter(&ahci_portp->ahciport_mutex); 6776 6777 /* 6778 * ahci_intr_phyrdy_change() may have rendered it to 6779 * SATA_DTYPE_NONE. 6780 */ 6781 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6782 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6783 "ahci_events_handler: port %d no device attached, " 6784 "and just return without doing anything", port); 6785 goto out; 6786 } 6787 6788 if (event & (AHCI_INTR_STATUS_IFS | 6789 AHCI_INTR_STATUS_HBDS | 6790 AHCI_INTR_STATUS_HBFS | 6791 AHCI_INTR_STATUS_TFES)) 6792 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6793 port, event); 6794 6795out: 6796 mutex_exit(&ahci_portp->ahciport_mutex); 6797} 6798 6799/* 6800 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6801 * detect there are some commands which are timed out. 6802 */ 6803static void 6804ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6805 uint8_t port, uint32_t tmp_timeout_tags) 6806{ 6807 uint32_t slot_status = 0; 6808 uint32_t finished_tags = 0; 6809 uint32_t timeout_tags = 0; 6810 6811 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6812 "ahci_timeout_pkts enter: port %d", port); 6813 6814 mutex_enter(&ahci_portp->ahciport_mutex); 6815 6816 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6817 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6818 /* Read PxCI to see which commands are still outstanding */ 6819 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6820 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6821 } 6822 6823 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6824 /* Read PxSACT to see which commands are still outstanding */ 6825 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6826 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6827 } 6828 6829#if AHCI_DEBUG 6830 /* 6831 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6832 * set, it means a fatal error happened after REQUEST SENSE command 6833 * or READ LOG EXT command is delivered to the HBA during the error 6834 * recovery process. At this time, the only outstanding command is 6835 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6836 */ 6837 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6838 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6839 "ahci_timeout_pkts called while REQUEST SENSE " 6840 "command or READ LOG EXT command for error recovery " 6841 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6842 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6843 tmp_timeout_tags, slot_status, 6844 ahci_portp->ahciport_pending_tags, 6845 ahci_portp->ahciport_pending_ncq_tags); 6846 ASSERT(slot_status == 0x1); 6847 } 6848#endif 6849 6850 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6851 ahci_portp->ahciport_mop_in_progress++; 6852 6853 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6854 port, NULL, NULL); 6855 6856 /* 6857 * Re-identify timeout tags because some previously checked commands 6858 * could already complete. 6859 */ 6860 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6861 finished_tags = ahci_portp->ahciport_pending_tags & 6862 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6863 timeout_tags = tmp_timeout_tags & ~finished_tags; 6864 6865 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6866 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6867 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6868 "pending_tags = 0x%x ", 6869 port, finished_tags, timeout_tags, 6870 slot_status, ahci_portp->ahciport_pending_tags); 6871 } 6872 6873 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6874 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6875 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6876 timeout_tags = tmp_timeout_tags & ~finished_tags; 6877 6878 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6879 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6880 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6881 "pending_ncq_tags = 0x%x ", 6882 port, finished_tags, timeout_tags, 6883 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6884 } 6885 6886 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6887 timeout_tags = tmp_timeout_tags; 6888 } 6889 6890 ahci_mop_commands(ahci_ctlp, 6891 ahci_portp, 6892 port, 6893 slot_status, 6894 0, /* failed tags */ 6895 timeout_tags, /* timeout tags */ 6896 0, /* aborted tags */ 6897 0); /* reset tags */ 6898 6899 mutex_exit(&ahci_portp->ahciport_mutex); 6900} 6901 6902/* 6903 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6904 * for long time. 6905 */ 6906static void 6907ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6908{ 6909 ahci_port_t *ahci_portp; 6910 sata_pkt_t *spkt; 6911 uint32_t pending_tags; 6912 uint32_t timeout_tags; 6913 uint32_t port_cmd_status; 6914 uint32_t port_sactive; 6915 uint8_t port; 6916 int tmp_slot; 6917 int current_slot; 6918 uint32_t current_tags; 6919 /* max number of cycles this packet should survive */ 6920 int max_life_cycles; 6921 6922 /* how many cycles this packet survived so far */ 6923 int watched_cycles; 6924 6925 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6926 6927 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6928 "ahci_watchdog_handler entered"); 6929 6930 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6931 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6932 continue; 6933 } 6934 6935 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6936 6937 mutex_enter(&ahci_portp->ahciport_mutex); 6938 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6939 mutex_exit(&ahci_portp->ahciport_mutex); 6940 continue; 6941 } 6942 6943 /* Skip the check for those ports in error recovery */ 6944 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6945 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6946 mutex_exit(&ahci_portp->ahciport_mutex); 6947 continue; 6948 } 6949 6950 pending_tags = 0; 6951 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6952 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6953 6954 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6955 current_slot = 0; 6956 pending_tags = 0x1; 6957 } 6958 6959 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6960 current_slot = 6961 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6962 AHCI_CMD_STATUS_CCS_SHIFT; 6963 pending_tags = ahci_portp->ahciport_pending_tags; 6964 } 6965 6966 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6967 port_sactive = ddi_get32( 6968 ahci_ctlp->ahcictl_ahci_acc_handle, 6969 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6970 current_tags = port_sactive & 6971 ~port_cmd_status & 6972 AHCI_NCQ_SLOT_MASK(ahci_portp); 6973 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6974 } 6975 6976 timeout_tags = 0; 6977 while (pending_tags) { 6978 tmp_slot = ddi_ffs(pending_tags) - 1; 6979 if (tmp_slot == -1) { 6980 break; 6981 } 6982 6983 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6984 spkt = ahci_portp->ahciport_err_retri_pkt; 6985 else 6986 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6987 6988 if ((spkt != NULL) && spkt->satapkt_time && 6989 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6990 /* 6991 * We are overloading satapkt_hba_driver_private 6992 * with watched_cycle count. 6993 * 6994 * If a packet has survived for more than it's 6995 * max life cycles, it is a candidate for time 6996 * out. 6997 */ 6998 watched_cycles = (int)(intptr_t) 6999 spkt->satapkt_hba_driver_private; 7000 watched_cycles++; 7001 max_life_cycles = (spkt->satapkt_time + 7002 ahci_watchdog_timeout - 1) / 7003 ahci_watchdog_timeout; 7004 7005 spkt->satapkt_hba_driver_private = 7006 (void *)(intptr_t)watched_cycles; 7007 7008 if (watched_cycles <= max_life_cycles) 7009 goto next; 7010 7011 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 7012 "the current slot is %d", current_slot); 7013 /* 7014 * We need to check whether the HBA has 7015 * begun to execute the command, if not, 7016 * then re-set the timer of the command. 7017 */ 7018 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 7019 (tmp_slot != current_slot) || 7020 NCQ_CMD_IN_PROGRESS(ahci_portp) && 7021 ((0x1 << tmp_slot) & current_tags)) { 7022 spkt->satapkt_hba_driver_private = 7023 (void *)(intptr_t)0; 7024 } else { 7025 timeout_tags |= (0x1 << tmp_slot); 7026 cmn_err(CE_NOTE, "!ahci watchdog: " 7027 "port %d satapkt 0x%p timed out\n", 7028 port, (void *)spkt); 7029 } 7030 } 7031next: 7032 CLEAR_BIT(pending_tags, tmp_slot); 7033 } 7034 7035 if (timeout_tags) { 7036 mutex_exit(&ahci_portp->ahciport_mutex); 7037 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7038 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 7039 port, timeout_tags); 7040 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7041 mutex_enter(&ahci_portp->ahciport_mutex); 7042 } 7043 7044 mutex_exit(&ahci_portp->ahciport_mutex); 7045 } 7046 7047 /* Re-install the watchdog timeout handler */ 7048 if (ahci_ctlp->ahcictl_timeout_id != 0) { 7049 ahci_ctlp->ahcictl_timeout_id = 7050 timeout((void (*)(void *))ahci_watchdog_handler, 7051 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 7052 } 7053 7054 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7055} 7056 7057/* 7058 * Fill the error context into sata_cmd for non-queued command error. 7059 */ 7060static void 7061ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7062{ 7063 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7064 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7065 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7066 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7067 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7068 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7069 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7070 7071 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7072 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7073 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7074 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7075 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7076 } 7077} 7078 7079/* 7080 * Fill the ncq error page into sata_cmd for queued command error. 7081 */ 7082static void 7083ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7084 struct sata_ncq_error_recovery_page *ncq_err_page) 7085{ 7086 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7087 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7088 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7089 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7090 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7091 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7092 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7093 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7094 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7095 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7096 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7097} 7098 7099/* 7100 * Put the respective register value to sata_cmd_t for satacmd_flags. 7101 */ 7102static void 7103ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7104{ 7105 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7106 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7107 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7108 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7109 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7110 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7111 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7112 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7113 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7114 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7115 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7116 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7117 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7118 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7119 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7120 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7121 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7122 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7123 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7124 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7125} 7126 7127static void 7128ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7129 uint32_t intr_status) 7130{ 7131#ifndef __lock_lint 7132 _NOTE(ARGUNUSED(ahci_ctlp)) 7133#endif 7134 7135 if (intr_status & AHCI_INTR_STATUS_IFS) 7136 cmn_err(CE_NOTE, "!ahci port %d has interface fatal " 7137 "error", port); 7138 7139 if (intr_status & AHCI_INTR_STATUS_HBDS) 7140 cmn_err(CE_NOTE, "!ahci port %d has bus data error", port); 7141 7142 if (intr_status & AHCI_INTR_STATUS_HBFS) 7143 cmn_err(CE_NOTE, "!ahci port %d has bus fatal error", port); 7144 7145 if (intr_status & AHCI_INTR_STATUS_TFES) 7146 cmn_err(CE_NOTE, "!ahci port %d has task file error", port); 7147 7148 cmn_err(CE_NOTE, "!ahci port %d is trying to do error " 7149 "recovery", port); 7150} 7151 7152/* 7153 * Dump the serror message to the log. 7154 */ 7155static void 7156ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7157 uint32_t port_serror) 7158{ 7159#ifndef __lock_lint 7160 _NOTE(ARGUNUSED(ahci_ctlp)) 7161#endif 7162 char *err_str; 7163 7164 if (port_serror & SERROR_DATA_ERR_FIXED) { 7165 err_str = "Recovered Data Integrity Error (I)"; 7166 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7167 "command error: port: %d, error: %s", 7168 port, err_str); 7169 } 7170 7171 if (port_serror & SERROR_COMM_ERR_FIXED) { 7172 err_str = "Recovered Communication Error (M)"; 7173 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7174 "command error: port: %d, error: %s", 7175 port, err_str); 7176 } 7177 7178 if (port_serror & SERROR_DATA_ERR) { 7179 err_str = "Transient Data Integrity Error (T)"; 7180 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7181 "command error: port: %d, error: %s", 7182 port, err_str); 7183 } 7184 7185 if (port_serror & SERROR_PERSISTENT_ERR) { 7186 err_str = 7187 "Persistent Communication or Data Integrity Error (C)"; 7188 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7189 "command error: port: %d, error: %s", 7190 port, err_str); 7191 } 7192 7193 if (port_serror & SERROR_PROTOCOL_ERR) { 7194 err_str = "Protocol Error (P)"; 7195 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7196 "command error: port: %d, error: %s", 7197 port, err_str); 7198 } 7199 7200 if (port_serror & SERROR_INT_ERR) { 7201 err_str = "Internal Error (E)"; 7202 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7203 "command error: port: %d, error: %s", 7204 port, err_str); 7205 } 7206 7207 if (port_serror & SERROR_PHY_RDY_CHG) { 7208 err_str = "PhyRdy Change (N)"; 7209 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7210 "command error: port: %d, error: %s", 7211 port, err_str); 7212 } 7213 7214 if (port_serror & SERROR_PHY_INT_ERR) { 7215 err_str = "Phy Internal Error (I)"; 7216 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7217 "command error: port: %d, error: %s", 7218 port, err_str); 7219 } 7220 7221 if (port_serror & SERROR_COMM_WAKE) { 7222 err_str = "Comm Wake (W)"; 7223 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7224 "command error: port: %d, error: %s", 7225 port, err_str); 7226 } 7227 7228 if (port_serror & SERROR_10B_TO_8B_ERR) { 7229 err_str = "10B to 8B Decode Error (B)"; 7230 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7231 "command error: port: %d, error: %s", 7232 port, err_str); 7233 } 7234 7235 if (port_serror & SERROR_DISPARITY_ERR) { 7236 err_str = "Disparity Error (D)"; 7237 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7238 "command error: port: %d, error: %s", 7239 port, err_str); 7240 } 7241 7242 if (port_serror & SERROR_CRC_ERR) { 7243 err_str = "CRC Error (C)"; 7244 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7245 "command error: port: %d, error: %s", 7246 port, err_str); 7247 } 7248 7249 if (port_serror & SERROR_HANDSHAKE_ERR) { 7250 err_str = "Handshake Error (H)"; 7251 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7252 "command error: port: %d, error: %s", 7253 port, err_str); 7254 } 7255 7256 if (port_serror & SERROR_LINK_SEQ_ERR) { 7257 err_str = "Link Sequence Error (S)"; 7258 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7259 "command error: port: %d, error: %s", 7260 port, err_str); 7261 } 7262 7263 if (port_serror & SERROR_TRANS_ERR) { 7264 err_str = "Transport state transition error (T)"; 7265 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7266 "command error: port: %d, error: %s", 7267 port, err_str); 7268 } 7269 7270 if (port_serror & SERROR_FIS_TYPE) { 7271 err_str = "Unknown FIS Type (F)"; 7272 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7273 "command error: port: %d, error: %s", 7274 port, err_str); 7275 } 7276 7277 if (port_serror & SERROR_EXCHANGED_ERR) { 7278 err_str = "Exchanged (X)"; 7279 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7280 "command error: port: %d, error: %s", 7281 port, err_str); 7282 } 7283} 7284 7285/* 7286 * This routine is to calculate the total number of ports implemented 7287 * by the HBA. 7288 */ 7289static int 7290ahci_get_num_implemented_ports(uint32_t ports_implemented) 7291{ 7292 uint8_t i; 7293 int num = 0; 7294 7295 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7296 if (((uint32_t)0x1 << i) & ports_implemented) 7297 num++; 7298 } 7299 7300 return (num); 7301} 7302 7303static void 7304ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7305{ 7306 va_list ap; 7307 7308 mutex_enter(&ahci_log_mutex); 7309 7310 va_start(ap, fmt); 7311 if (ahci_ctlp) { 7312 (void) sprintf(ahci_log_buf, "%s-[%d]:", 7313 ddi_get_name(ahci_ctlp->ahcictl_dip), 7314 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7315 } else { 7316 (void) sprintf(ahci_log_buf, "ahci:"); 7317 } 7318 7319 (void) vsprintf(ahci_log_buf, fmt, ap); 7320 va_end(ap); 7321 7322 cmn_err(level, "%s", ahci_log_buf); 7323 7324 mutex_exit(&ahci_log_mutex); 7325} 7326