ahci.c revision 4879:ced5e1e3b491
1246149Ssjg/* 2246149Ssjg * CDDL HEADER START 3246149Ssjg * 4246149Ssjg * The contents of this file are subject to the terms of the 5246149Ssjg * Common Development and Distribution License (the "License"). 6246149Ssjg * You may not use this file except in compliance with the License. 7246149Ssjg * 8246149Ssjg * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9246149Ssjg * or http://www.opensolaris.org/os/licensing. 10246149Ssjg * See the License for the specific language governing permissions 11246149Ssjg * and limitations under the License. 12246149Ssjg * 13246149Ssjg * When distributing Covered Code, include this CDDL HEADER in each 14246149Ssjg * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15246149Ssjg * If applicable, add the following below this CDDL HEADER, with the 16246149Ssjg * fields enclosed by brackets "[]" replaced with your own identifying 17246149Ssjg * information: Portions Copyright [yyyy] [name of copyright owner] 18246149Ssjg * 19246149Ssjg * CDDL HEADER END 20246149Ssjg */ 21246149Ssjg 22246149Ssjg/* 23246149Ssjg * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24246149Ssjg * Use is subject to license terms. 25246149Ssjg */ 26246149Ssjg 27246149Ssjg#pragma ident "%Z%%M% %I% %E% SMI" 28246149Ssjg 29246149Ssjg/* 30246149Ssjg * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31246149Ssjg */ 32246149Ssjg 33246149Ssjg#include <sys/scsi/scsi.h> 34246149Ssjg#include <sys/pci.h> 35246149Ssjg#include <sys/sata/sata_hba.h> 36246149Ssjg#include <sys/sata/adapters/ahci/ahcireg.h> 37246149Ssjg#include <sys/sata/adapters/ahci/ahcivar.h> 38246149Ssjg 39246149Ssjg/* 40246149Ssjg * Function prototypes for driver entry points 41246149Ssjg */ 42246149Ssjgstatic int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 43246149Ssjgstatic int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 44246149Ssjgstatic int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 45246149Ssjg 46246149Ssjg/* 47246149Ssjg * Function prototypes for SATA Framework interfaces 48246149Ssjg */ 49246149Ssjgstatic int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 50246149Ssjgstatic int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 51246149Ssjg 52246149Ssjgstatic int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 53246149Ssjgstatic int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 54246149Ssjgstatic int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 55246149Ssjgstatic int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 56246149Ssjgstatic int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 57246149Ssjgstatic int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 58246149Ssjg#if defined(__lock_lint) 59246149Ssjgstatic int ahci_selftest(dev_info_t *, sata_device_t *); 60246149Ssjg#endif 61246149Ssjg 62246149Ssjg/* 63246149Ssjg * Local function prototypes 64246149Ssjg */ 65246149Ssjgstatic int ahci_alloc_ports_state(ahci_ctl_t *); 66246149Ssjgstatic void ahci_dealloc_ports_state(ahci_ctl_t *); 67246149Ssjgstatic int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 68246149Ssjgstatic void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 69246149Ssjgstatic int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 70246149Ssjgstatic void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 71246149Ssjgstatic int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 72246149Ssjgstatic void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 73246149Ssjgstatic int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 74246149Ssjgstatic void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 75246149Ssjg 76246149Ssjgstatic int ahci_initialize_controller(ahci_ctl_t *); 77246149Ssjgstatic void ahci_uninitialize_controller(ahci_ctl_t *); 78246149Ssjgstatic int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 79246149Ssjg 80246149Ssjgstatic int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 81246149Ssjgstatic void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 82246149Ssjgstatic void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 83246149Ssjgstatic int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 84246149Ssjg uint8_t, sata_pkt_t *); 85246149Ssjgstatic int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 86246149Ssjg uint8_t, sata_pkt_t *); 87246149Ssjgstatic int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *); 88246149Ssjgstatic void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 89246149Ssjgstatic void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 90246149Ssjg 91246149Ssjgstatic int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 92246149Ssjgstatic int ahci_hba_reset(ahci_ctl_t *); 93246149Ssjgstatic int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 94246149Ssjgstatic void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 95246149Ssjgstatic int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 96246149Ssjgstatic int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 97246149Ssjgstatic int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 98246149Ssjgstatic int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 99246149Ssjg uint8_t); 100246149Ssjgstatic int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 101246149Ssjg uint8_t, int, int *); 102246149Ssjgstatic void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 103246149Ssjg uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 104246149Ssjgstatic void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 105246149Ssjg uint8_t, sata_pkt_t *); 106246149Ssjgstatic void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 107246149Ssjg uint8_t, uint32_t, uint32_t); 108246149Ssjgstatic void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 109246149Ssjg uint8_t, uint32_t, uint32_t); 110246149Ssjgstatic void ahci_events_handler(void *); 111246149Ssjgstatic void ahci_watchdog_handler(ahci_ctl_t *); 112246149Ssjg 113246149Ssjgstatic uint_t ahci_intr(caddr_t, caddr_t); 114246149Ssjgstatic void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t, uint32_t); 115246149Ssjgstatic int ahci_add_legacy_intrs(ahci_ctl_t *); 116246149Ssjgstatic int ahci_add_msi_intrs(ahci_ctl_t *); 117246149Ssjgstatic void ahci_rem_intrs(ahci_ctl_t *); 118246149Ssjgstatic void ahci_enable_all_intrs(ahci_ctl_t *); 119246149Ssjgstatic void ahci_disable_all_intrs(ahci_ctl_t *); 120246149Ssjgstatic void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 121246149Ssjgstatic void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 122246149Ssjg 123246149Ssjgstatic int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t, 124246149Ssjg uint32_t, uint32_t); 125246149Ssjgstatic int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 126246149Ssjgstatic int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 127246149Ssjgstatic int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 128246149Ssjg ahci_port_t *, uint8_t); 129246149Ssjgstatic int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 130246149Ssjgstatic int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 131246149Ssjg uint8_t, uint32_t); 132246149Ssjgstatic int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 133246149Ssjg uint8_t, uint32_t, uint32_t); 134246149Ssjgstatic int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 135246149Ssjg 136246149Ssjgstatic int ahci_get_num_implemented_ports(uint32_t); 137246149Ssjgstatic void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 138246149Ssjg uint32_t); 139246149Ssjgstatic void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t); 140246149Ssjgstatic void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 141246149Ssjg 142246149Ssjg 143246149Ssjg/* 144246149Ssjg * DMA attributes for the data buffer 145246149Ssjg * 146246149Ssjg * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 147246149Ssjg * does not support 64-bit addressing 148246149Ssjg */ 149246149Ssjgstatic ddi_dma_attr_t buffer_dma_attr = { 150246149Ssjg DMA_ATTR_V0, /* dma_attr_version */ 151246149Ssjg 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 152246149Ssjg 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 153246149Ssjg 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 154246149Ssjg 0x2ull, /* dma_attr_align: word aligned */ 155246149Ssjg 1, /* dma_attr_burstsizes */ 156246149Ssjg 1, /* dma_attr_minxfer */ 157246149Ssjg 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 158246149Ssjg 0xffffffffull, /* dma_attr_seg */ 159246149Ssjg AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 160246149Ssjg 512, /* dma_attr_granular */ 161246149Ssjg 0, /* dma_attr_flags */ 162246149Ssjg}; 163246149Ssjg 164246149Ssjg/* 165246149Ssjg * DMA attributes for the rcvd FIS 166246149Ssjg * 167246149Ssjg * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 168246149Ssjg * does not support 64-bit addressing 169246149Ssjg */ 170246149Ssjgstatic ddi_dma_attr_t rcvd_fis_dma_attr = { 171246149Ssjg DMA_ATTR_V0, /* dma_attr_version */ 172246149Ssjg 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 173246149Ssjg 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 174246149Ssjg 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 175246149Ssjg 0x100ull, /* dma_attr_align: 256-byte aligned */ 176246149Ssjg 1, /* dma_attr_burstsizes */ 177246149Ssjg 1, /* dma_attr_minxfer */ 178246149Ssjg 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 179246149Ssjg 0xffffffffull, /* dma_attr_seg */ 180246149Ssjg 1, /* dma_attr_sgllen */ 181246149Ssjg 1, /* dma_attr_granular */ 182246149Ssjg 0, /* dma_attr_flags */ 183246149Ssjg}; 184246149Ssjg 185246149Ssjg/* 186246149Ssjg * DMA attributes for the command list 187246149Ssjg * 188246149Ssjg * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 189246149Ssjg * does not support 64-bit addressing 190246149Ssjg */ 191246149Ssjgstatic ddi_dma_attr_t cmd_list_dma_attr = { 192246149Ssjg DMA_ATTR_V0, /* dma_attr_version */ 193246149Ssjg 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 194246149Ssjg 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 195246149Ssjg 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 196246149Ssjg 0x400ull, /* dma_attr_align: 1K-byte aligned */ 197246149Ssjg 1, /* dma_attr_burstsizes */ 198246149Ssjg 1, /* dma_attr_minxfer */ 199246149Ssjg 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 200246149Ssjg 0xffffffffull, /* dma_attr_seg */ 201246149Ssjg 1, /* dma_attr_sgllen */ 202246149Ssjg 1, /* dma_attr_granular */ 203246149Ssjg 0, /* dma_attr_flags */ 204246149Ssjg}; 205246149Ssjg 206246149Ssjg/* 207246149Ssjg * DMA attributes for cmd tables 208246149Ssjg * 209246149Ssjg * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 210246149Ssjg * does not support 64-bit addressing 211246149Ssjg */ 212246149Ssjgstatic ddi_dma_attr_t cmd_table_dma_attr = { 213246149Ssjg DMA_ATTR_V0, /* dma_attr_version */ 214246149Ssjg 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 215246149Ssjg 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 216246149Ssjg 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 217246149Ssjg 0x80ull, /* dma_attr_align: 128-byte aligned */ 218246149Ssjg 1, /* dma_attr_burstsizes */ 219246149Ssjg 1, /* dma_attr_minxfer */ 220246149Ssjg 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 221246149Ssjg 0xffffffffull, /* dma_attr_seg */ 222246149Ssjg 1, /* dma_attr_sgllen */ 223246149Ssjg 1, /* dma_attr_granular */ 224246149Ssjg 0, /* dma_attr_flags */ 225246149Ssjg}; 226246149Ssjg 227246149Ssjg 228246149Ssjg/* Device access attributes */ 229246149Ssjgstatic ddi_device_acc_attr_t accattr = { 230246149Ssjg DDI_DEVICE_ATTR_V0, 231246149Ssjg DDI_STRUCTURE_LE_ACC, 232246149Ssjg DDI_STRICTORDER_ACC 233246149Ssjg}; 234246149Ssjg 235246149Ssjg 236246149Ssjgstatic struct dev_ops ahcictl_dev_ops = { 237246149Ssjg DEVO_REV, /* devo_rev */ 238246149Ssjg 0, /* refcnt */ 239246149Ssjg ahci_getinfo, /* info */ 240246149Ssjg nulldev, /* identify */ 241246149Ssjg nulldev, /* probe */ 242246149Ssjg ahci_attach, /* attach */ 243246149Ssjg ahci_detach, /* detach */ 244246149Ssjg nodev, /* no reset */ 245246149Ssjg (struct cb_ops *)0, /* driver operations */ 246246149Ssjg NULL, /* bus operations */ 247246149Ssjg NULL /* power */ 248246149Ssjg}; 249246149Ssjg 250246149Ssjgstatic sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 251246149Ssjg SATA_TRAN_HOTPLUG_OPS_REV_1, 252246149Ssjg ahci_tran_hotplug_port_activate, 253246149Ssjg ahci_tran_hotplug_port_deactivate 254246149Ssjg}; 255 256extern struct mod_ops mod_driverops; 257 258static struct modldrv modldrv = { 259 &mod_driverops, /* driverops */ 260 "ahci driver %I%", 261 &ahcictl_dev_ops, /* driver ops */ 262}; 263 264static struct modlinkage modlinkage = { 265 MODREV_1, 266 &modldrv, 267 NULL 268}; 269 270static int ahci_watchdog_timeout = 5; /* 5 seconds */ 271static int ahci_watchdog_tick; 272 273/* The following is needed for ahci_log() */ 274static kmutex_t ahci_log_mutex; 275static char ahci_log_buf[512]; 276 277static size_t ahci_cmd_table_size; 278 279/* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 280int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 281 282/* 283 * AHCI MSI tunable: 284 * 285 * MSI will be enabled in phase 2. 286 */ 287boolean_t ahci_msi_enabled = B_FALSE; 288 289#if AHCI_DEBUG 290uint32_t ahci_debug_flags = 0; 291#endif 292 293/* Opaque state pointer initialized by ddi_soft_state_init() */ 294static void *ahci_statep = NULL; 295 296/* 297 * ahci module initialization. 298 */ 299int 300_init(void) 301{ 302 int ret; 303 304 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 305 if (ret != 0) { 306 goto err_out; 307 } 308 309 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 310 311 if ((ret = sata_hba_init(&modlinkage)) != 0) { 312 mutex_destroy(&ahci_log_mutex); 313 ddi_soft_state_fini(&ahci_statep); 314 goto err_out; 315 } 316 317 ret = mod_install(&modlinkage); 318 if (ret != 0) { 319 sata_hba_fini(&modlinkage); 320 mutex_destroy(&ahci_log_mutex); 321 ddi_soft_state_fini(&ahci_statep); 322 goto err_out; 323 } 324 325 /* watchdog tick */ 326 ahci_watchdog_tick = drv_usectohz( 327 (clock_t)ahci_watchdog_timeout * 1000000); 328 return (ret); 329 330err_out: 331 cmn_err(CE_WARN, "!Module init failed"); 332 return (ret); 333} 334 335/* 336 * ahci module uninitialize. 337 */ 338int 339_fini(void) 340{ 341 int ret; 342 343 ret = mod_remove(&modlinkage); 344 if (ret != 0) { 345 return (ret); 346 } 347 348 /* Remove the resources allocated in _init(). */ 349 sata_hba_fini(&modlinkage); 350 mutex_destroy(&ahci_log_mutex); 351 ddi_soft_state_fini(&ahci_statep); 352 353 return (ret); 354} 355 356/* 357 * _info entry point 358 */ 359int 360_info(struct modinfo *modinfop) 361{ 362 return (mod_info(&modlinkage, modinfop)); 363} 364 365/* 366 * The attach entry point for dev_ops. 367 */ 368static int 369ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 370{ 371 ahci_ctl_t *ahci_ctlp; 372 int instance = ddi_get_instance(dip); 373 int status; 374 int attach_state; 375 uint32_t cap_status, ahci_version; 376 int intr_types; 377 ushort_t venid; 378 uint8_t revision; 379 int i; 380#if AHCI_DEBUG 381 int speed; 382#endif 383 384 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 385 386 switch (cmd) { 387 case DDI_ATTACH: 388 break; 389 390 case DDI_RESUME: 391 /* It will be implemented in Phase 2 */ 392 return (DDI_FAILURE); 393 394 default: 395 return (DDI_FAILURE); 396 } 397 398 attach_state = AHCI_ATTACH_STATE_NONE; 399 400 /* Allocate soft state */ 401 status = ddi_soft_state_zalloc(ahci_statep, instance); 402 if (status != DDI_SUCCESS) { 403 cmn_err(CE_WARN, "!Cannot allocate soft state"); 404 goto err_out; 405 } 406 407 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 408 ahci_ctlp->ahcictl_dip = dip; 409 410 /* Initialize the cport/port mapping */ 411 for (i = 0; i < AHCI_MAX_PORTS; i++) { 412 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 413 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 414 } 415 416 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 417 418 /* 419 * Now map the AHCI base address; which includes global 420 * registers and port control registers 421 */ 422 status = ddi_regs_map_setup(dip, 423 AHCI_BASE_REG, 424 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 425 0, 426 0, 427 &accattr, 428 &ahci_ctlp->ahcictl_ahci_acc_handle); 429 if (status != DDI_SUCCESS) { 430 cmn_err(CE_WARN, "!Cannot map register space"); 431 goto err_out; 432 } 433 434 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 435 436 /* Get the AHCI version information */ 437 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 438 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 439 440 cmn_err(CE_NOTE, "!hba AHCI version = %x.%x", 441 (ahci_version & 0xffff0000) >> 16, 442 ((ahci_version & 0x0000ff00) >> 4 | 443 (ahci_version & 0x000000ff))); 444 445 /* We don't support controllers whose versions are lower than 1.0 */ 446 if (!(ahci_version & 0xffff0000)) { 447 cmn_err(CE_WARN, "Don't support AHCI HBA with lower than " 448 "version 1.0"); 449 goto err_out; 450 } 451 452 /* Get the HBA capabilities information */ 453 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 454 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 455 456 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 457 cap_status); 458 459#if AHCI_DEBUG 460 /* Get the interface speed supported by the HBA */ 461 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 462 if (speed == 0x01) { 463 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 464 "hba interface speed support: Gen 1 (1.5Gbps)"); 465 } else if (speed == 0x10) { 466 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 467 "hba interface speed support: Gen 2 (3 Gbps)"); 468 } else if (speed == 0x11) { 469 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 470 "hba interface speed support: Gen 3 (6 Gbps)"); 471 } 472#endif 473 474 /* Get the number of command slots supported by the HBA */ 475 ahci_ctlp->ahcictl_num_cmd_slots = 476 ((cap_status & AHCI_HBA_CAP_NCS) >> 477 AHCI_HBA_CAP_NCS_SHIFT) + 1; 478 479 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 480 ahci_ctlp->ahcictl_num_cmd_slots); 481 482 /* Get the bit map which indicates ports implemented by the HBA */ 483 ahci_ctlp->ahcictl_ports_implemented = 484 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 485 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 486 487 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 488 ahci_ctlp->ahcictl_ports_implemented); 489 490 /* 491 * According to the AHCI spec, CAP.NP should indicate the maximum 492 * number of ports supported by the HBA silicon, but we found 493 * this value of ICH8 chipset only indicates the number of ports 494 * implemented (exposed) by it. Therefore, the driver should calculate 495 * the potential maximum value by checking PI register, and use 496 * the maximum of this value and CAP.NP. 497 */ 498 ahci_ctlp->ahcictl_num_ports = max( 499 (cap_status & AHCI_HBA_CAP_NP) + 1, 500 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 501 502 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 503 ahci_ctlp->ahcictl_num_ports); 504 505 /* Get the number of implemented ports by the HBA */ 506 ahci_ctlp->ahcictl_num_implemented_ports = 507 ahci_get_num_implemented_ports( 508 ahci_ctlp->ahcictl_ports_implemented); 509 510 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 511 "hba number of implemented ports: %d", 512 ahci_ctlp->ahcictl_num_implemented_ports); 513 514 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 515 516 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 517 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 518 "hba does not support 64-bit addressing"); 519 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 520 0xffffffffull; 521 } 522 523 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 524 != DDI_SUCCESS) { 525 cmn_err(CE_WARN, "!Cannot set up pci configure space"); 526 goto err_out; 527 } 528 529 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 530 531 /* 532 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 533 * controllers with 0x00 revision id work on 4-byte aligned buffer, 534 * which is a bug and was fixed after 0x00 revision id controllers. 535 * 536 * And VT8251 cannot use multiple command lists for non-queued commands 537 * because the Command Issue register bit can be cleared by software 538 * set. 539 */ 540 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 541 PCI_CONF_VENID); 542 543 if (venid == VIA_VENID) { 544 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 545 PCI_CONF_REVID); 546 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 547 "revision id = 0x%x", revision); 548 if (revision == 0x00) { 549 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 550 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 551 "change ddi_attr_align to 0x4"); 552 } 553 554 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 555 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 556 "VT8251 cannot use multiple command lists for " 557 "non-queued commands"); 558 } 559 560 /* 561 * Disable the whole controller interrupts before adding 562 * interrupt handlers(s). 563 */ 564 ahci_disable_all_intrs(ahci_ctlp); 565 566 /* Get supported interrupt types */ 567 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 568 cmn_err(CE_WARN, "!ddi_intr_get_supported_types failed"); 569 goto err_out; 570 } 571 572 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 573 "ddi_intr_get_supported_types() returned: 0x%x", 574 intr_types); 575 576 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 577 /* 578 * Try MSI first, but fall back to FIXED if failed 579 */ 580 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 581 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 582 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 583 "Using MSI interrupt type"); 584 goto intr_done; 585 } 586 587 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 588 "MSI registration failed, " 589 "trying FIXED interrupts"); 590 } 591 592 if (intr_types & DDI_INTR_TYPE_FIXED) { 593 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 594 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 595 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, NULL, 596 "Using FIXED interrupt type"); 597 goto intr_done; 598 } 599 600 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 601 "FIXED interrupt registration failed"); 602 } 603 604 cmn_err(CE_WARN, "!Interrupt registration failed"); 605 606 goto err_out; 607 608intr_done: 609 610 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 611 612 /* Initialize the controller mutex */ 613 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 614 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 615 616 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 617 618 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 619 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 620 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 621 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 622 } 623 624 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 625 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 626 sizeof (ahci_prdt_item_t)); 627 628 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 629 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 630 " ahci_cmd_table_size is 0x%x", 631 ahci_dma_prdt_number, ahci_cmd_table_size); 632 633 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 634 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 635 ahci_dma_prdt_number; 636 637 /* Allocate the ports structure */ 638 status = ahci_alloc_ports_state(ahci_ctlp); 639 if (status != AHCI_SUCCESS) { 640 cmn_err(CE_WARN, "!Cannot allocate ports structure"); 641 goto err_out; 642 } 643 644 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 645 646 /* 647 * A taskq is created for dealing with events 648 */ 649 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 650 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 651 cmn_err(CE_WARN, "!ddi_taskq_create failed for event handle"); 652 goto err_out; 653 } 654 655 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 656 657 /* 658 * Initialize the controller and ports. 659 */ 660 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 661 status = ahci_initialize_controller(ahci_ctlp); 662 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 663 if (status != AHCI_SUCCESS) { 664 cmn_err(CE_WARN, "!HBA initialization failed"); 665 goto err_out; 666 } 667 668 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 669 670 /* Start one thread to check packet timeouts */ 671 ahci_ctlp->ahcictl_timeout_id = timeout( 672 (void (*)(void *))ahci_watchdog_handler, 673 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 674 675 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 676 677 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 678 cmn_err(CE_WARN, "!sata hba tran registration failed"); 679 goto err_out; 680 } 681 682 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 683 684 return (DDI_SUCCESS); 685 686err_out: 687 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 688 mutex_enter(&ahci_ctlp->ahcictl_mutex); 689 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 690 ahci_ctlp->ahcictl_timeout_id = 0; 691 mutex_exit(&ahci_ctlp->ahcictl_mutex); 692 } 693 694 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 695 mutex_enter(&ahci_ctlp->ahcictl_mutex); 696 ahci_uninitialize_controller(ahci_ctlp); 697 mutex_exit(&ahci_ctlp->ahcictl_mutex); 698 } 699 700 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 701 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 702 } 703 704 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 705 ahci_dealloc_ports_state(ahci_ctlp); 706 } 707 708 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 709 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 710 } 711 712 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 713 ahci_rem_intrs(ahci_ctlp); 714 } 715 716 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 717 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 718 } 719 720 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 721 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 722 } 723 724 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 725 ddi_soft_state_free(ahci_statep, instance); 726 } 727 728 return (DDI_FAILURE); 729} 730 731/* 732 * The detach entry point for dev_ops. 733 */ 734static int 735ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 736{ 737 ahci_ctl_t *ahci_ctlp; 738 int instance; 739 int ret; 740 741 instance = ddi_get_instance(dip); 742 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 743 744 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 745 746 switch (cmd) { 747 case DDI_DETACH: 748 /* disable the interrupts for an uninterrupted detach */ 749 mutex_enter(&ahci_ctlp->ahcictl_mutex); 750 ahci_disable_all_intrs(ahci_ctlp); 751 mutex_exit(&ahci_ctlp->ahcictl_mutex); 752 753 /* unregister from the sata framework. */ 754 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 755 if (ret != AHCI_SUCCESS) { 756 mutex_enter(&ahci_ctlp->ahcictl_mutex); 757 ahci_enable_all_intrs(ahci_ctlp); 758 mutex_exit(&ahci_ctlp->ahcictl_mutex); 759 return (DDI_FAILURE); 760 } 761 762 mutex_enter(&ahci_ctlp->ahcictl_mutex); 763 764 /* stop the watchdog handler */ 765 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 766 ahci_ctlp->ahcictl_timeout_id = 0; 767 768 mutex_exit(&ahci_ctlp->ahcictl_mutex); 769 770 /* uninitialize the controller */ 771 ahci_ctlp->ahcictl_flags |= AHCI_DETACH; 772 ahci_uninitialize_controller(ahci_ctlp); 773 ahci_ctlp->ahcictl_flags &= ~AHCI_DETACH; 774 775 /* remove the interrupts */ 776 ahci_rem_intrs(ahci_ctlp); 777 778 /* destroy the taskq */ 779 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 780 781 /* deallocate the ports structures */ 782 ahci_dealloc_ports_state(ahci_ctlp); 783 784 /* destroy mutex */ 785 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 786 787 /* teardown the pci config */ 788 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 789 790 /* remove the reg maps. */ 791 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 792 793 /* free the soft state. */ 794 ddi_soft_state_free(ahci_statep, instance); 795 796 return (DDI_SUCCESS); 797 798 case DDI_SUSPEND: 799 /* It will be implemented in Phase 2 */ 800 return (DDI_FAILURE); 801 802 default: 803 return (DDI_FAILURE); 804 } 805} 806 807/* 808 * The info entry point for dev_ops. 809 * 810 */ 811static int 812ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 813 void *arg, void **result) 814{ 815#ifndef __lock_lint 816 _NOTE(ARGUNUSED(dip)) 817#endif /* __lock_lint */ 818 819 ahci_ctl_t *ahci_ctlp; 820 int instance; 821 dev_t dev; 822 823 dev = (dev_t)arg; 824 instance = getminor(dev); 825 826 switch (infocmd) { 827 case DDI_INFO_DEVT2DEVINFO: 828 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 829 if (ahci_ctlp != NULL) { 830 *result = ahci_ctlp->ahcictl_dip; 831 return (DDI_SUCCESS); 832 } else { 833 *result = NULL; 834 return (DDI_FAILURE); 835 } 836 case DDI_INFO_DEVT2INSTANCE: 837 *(int *)result = instance; 838 break; 839 default: 840 break; 841 } 842 843 return (DDI_SUCCESS); 844} 845 846/* 847 * Registers the ahci with sata framework. 848 */ 849static int 850ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 851{ 852 struct sata_hba_tran *sata_hba_tran; 853 854 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 855 "ahci_register_sata_hba_tran enter"); 856 857 mutex_enter(&ahci_ctlp->ahcictl_mutex); 858 859 /* Allocate memory for the sata_hba_tran */ 860 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 861 862 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 863 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 864 sata_hba_tran->sata_tran_hba_dma_attr = 865 &ahci_ctlp->ahcictl_buffer_dma_attr; 866 867 /* Report the number of implemented ports */ 868 sata_hba_tran->sata_tran_hba_num_cports = 869 ahci_ctlp->ahcictl_num_implemented_ports; 870 871 /* Support ATAPI device */ 872 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 873 874 /* Get the data transfer capability for PIO command by the HBA */ 875 if (cap_status & AHCI_HBA_CAP_PMD) { 876 ahci_ctlp->ahcictl_flags |= AHCI_CAP_PIO_MDRQ; 877 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 878 "DRQ block data transfer for PIO command protocol"); 879 } else { 880 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 881 "DRQ block data transfer for PIO command protocol"); 882 } 883 884 /* Report the number of command slots */ 885 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 886 887 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 888 sata_hba_tran->sata_tran_start = ahci_tran_start; 889 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 890 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 891 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 892#ifdef __lock_lint 893 sata_hba_tran->sata_tran_selftest = ahci_selftest; 894#endif 895 /* 896 * When SATA framework adds support for pwrmgt the 897 * pwrmgt_ops needs to be updated 898 */ 899 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 900 sata_hba_tran->sata_tran_ioctl = NULL; 901 902 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 903 904 mutex_exit(&ahci_ctlp->ahcictl_mutex); 905 906 /* Attach it to SATA framework */ 907 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 908 != DDI_SUCCESS) { 909 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 910 mutex_enter(&ahci_ctlp->ahcictl_mutex); 911 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 912 mutex_exit(&ahci_ctlp->ahcictl_mutex); 913 return (AHCI_FAILURE); 914 } 915 916 return (AHCI_SUCCESS); 917} 918 919/* 920 * Unregisters the ahci with sata framework. 921 */ 922static int 923ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 924{ 925 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 926 "ahci_unregister_sata_hba_tran enter"); 927 928 /* Detach from the SATA framework. */ 929 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 930 DDI_SUCCESS) { 931 return (AHCI_FAILURE); 932 } 933 934 /* Deallocate sata_hba_tran. */ 935 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 936 sizeof (sata_hba_tran_t)); 937 938 mutex_enter(&ahci_ctlp->ahcictl_mutex); 939 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 940 mutex_exit(&ahci_ctlp->ahcictl_mutex); 941 942 return (AHCI_SUCCESS); 943} 944 945/* 946 * ahci_tran_probe_port is called by SATA framework. It returns port state, 947 * port status registers and an attached device type via sata_device 948 * structure. 949 * 950 * We return the cached information from a previous hardware probe. The 951 * actual hardware probing itself was done either from within 952 * ahci_initialize_controller() during the driver attach or from a phy 953 * ready change interrupt handler. 954 */ 955static int 956ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 957{ 958 ahci_ctl_t *ahci_ctlp; 959 ahci_port_t *ahci_portp; 960 uint8_t cport = sd->satadev_addr.cport; 961 uint8_t pmport = sd->satadev_addr.pmport; 962 uint8_t qual = sd->satadev_addr.qual; 963 uint8_t device_type; 964 uint32_t port_state; 965 uint8_t port; 966 967 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 968 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 969 970 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 971 "ahci_tran_probe_port enter: cport: %d, " 972 "pmport: %d, qual: %d", cport, pmport, qual); 973 974 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 975 976 mutex_enter(&ahci_portp->ahciport_mutex); 977 978 port_state = ahci_portp->ahciport_port_state; 979 switch (port_state) { 980 981 case SATA_PSTATE_FAILED: 982 sd->satadev_state = SATA_PSTATE_FAILED; 983 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 984 "ahci_tran_probe_port: port %d PORT FAILED", port); 985 goto out; 986 987 case SATA_PSTATE_SHUTDOWN: 988 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 989 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 990 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 991 goto out; 992 993 case SATA_PSTATE_PWROFF: 994 sd->satadev_state = SATA_PSTATE_PWROFF; 995 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 996 "ahci_tran_probe_port: port %d PORT PWROFF", port); 997 goto out; 998 999 case SATA_PSTATE_PWRON: 1000 sd->satadev_state = SATA_PSTATE_PWRON; 1001 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1002 "ahci_tran_probe_port: port %d PORT PWRON", port); 1003 break; 1004 1005 default: 1006 sd->satadev_state = port_state; 1007 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1008 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1009 port, port_state); 1010 break; 1011 } 1012 1013 device_type = ahci_portp->ahciport_device_type; 1014 1015 switch (device_type) { 1016 1017 case SATA_DTYPE_ATADISK: 1018 sd->satadev_type = SATA_DTYPE_ATADISK; 1019 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1020 "ahci_tran_probe_port: port %d DISK found", port); 1021 break; 1022 1023 case SATA_DTYPE_ATAPICD: 1024 sd->satadev_type = SATA_DTYPE_ATAPICD; 1025 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1026 "ahci_tran_probe_port: port %d ATAPI found", port); 1027 break; 1028 1029 case SATA_DTYPE_PMULT: 1030 sd->satadev_type = SATA_DTYPE_PMULT; 1031 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1032 "ahci_tran_probe_port: port %d Port Multiplier found", 1033 port); 1034 break; 1035 1036 case SATA_DTYPE_UNKNOWN: 1037 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1038 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1039 "ahci_tran_probe_port: port %d Unknown device found", port); 1040 break; 1041 1042 default: 1043 /* we don't support any other device types */ 1044 sd->satadev_type = SATA_DTYPE_NONE; 1045 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1046 "ahci_tran_probe_port: port %d No device found", port); 1047 break; 1048 } 1049 1050out: 1051 ahci_update_sata_registers(ahci_ctlp, port, sd); 1052 mutex_exit(&ahci_portp->ahciport_mutex); 1053 1054 return (SATA_SUCCESS); 1055} 1056 1057/* 1058 * There are four operation modes in sata framework: 1059 * SATA_OPMODE_INTERRUPTS 1060 * SATA_OPMODE_POLLING 1061 * SATA_OPMODE_ASYNCH 1062 * SATA_OPMODE_SYNCH 1063 * 1064 * Their combined meanings as following: 1065 * 1066 * SATA_OPMODE_SYNCH 1067 * The command has to be completed before sata_tran_start functions returns. 1068 * Either interrupts or polling could be used - it's up to the driver. 1069 * Mode used currently for internal, sata-module initiated operations. 1070 * 1071 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1072 * It is the same as the one above. 1073 * 1074 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1075 * The command has to be completed before sata_tran_start function returns. 1076 * No interrupt used, polling only. This should be the mode used for scsi 1077 * packets with FLAG_NOINTR. 1078 * 1079 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1080 * The command may be queued (callback function specified). Interrupts could 1081 * be used. It's normal operation mode. 1082 */ 1083/* 1084 * Called by sata framework to transport a sata packet down stream. 1085 */ 1086static int 1087ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1088{ 1089 ahci_ctl_t *ahci_ctlp; 1090 ahci_port_t *ahci_portp; 1091 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1092 uint8_t port; 1093 1094 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1095 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1096 1097 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1098 "ahci_tran_start enter: cport %d satapkt 0x%p", 1099 cport, (void *)spkt); 1100 1101 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1102 1103 mutex_enter(&ahci_portp->ahciport_mutex); 1104 1105 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1106 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1107 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1108 /* 1109 * In case the targer driver would send the packet before 1110 * sata framework can have the opportunity to process those 1111 * event reports. 1112 */ 1113 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1114 spkt->satapkt_device.satadev_state = 1115 ahci_portp->ahciport_port_state; 1116 ahci_update_sata_registers(ahci_ctlp, port, 1117 &spkt->satapkt_device); 1118 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1119 "ahci_tran_start returning PORT_ERROR while " 1120 "port in FAILED/SHUTDOWN/PWROFF state: " 1121 "port: %d", port); 1122 mutex_exit(&ahci_portp->ahciport_mutex); 1123 return (SATA_TRAN_PORT_ERROR); 1124 } 1125 1126 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1127 /* 1128 * ahci_intr_phyrdy_change() may have rendered it to 1129 * SATA_DTYPE_NONE. 1130 */ 1131 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1132 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1133 spkt->satapkt_device.satadev_state = 1134 ahci_portp->ahciport_port_state; 1135 ahci_update_sata_registers(ahci_ctlp, port, 1136 &spkt->satapkt_device); 1137 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1138 "ahci_tran_start returning PORT_ERROR while " 1139 "no device attached: port: %d", port); 1140 mutex_exit(&ahci_portp->ahciport_mutex); 1141 return (SATA_TRAN_PORT_ERROR); 1142 } 1143 1144 /* 1145 * SATA HBA driver should remember that a device was reset and it 1146 * is supposed to reject any packets which do not specify either 1147 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1148 * 1149 * This is to prevent a race condition when a device was arbitrarily 1150 * reset by the HBA driver (and lost it's setting) and a target 1151 * driver sending some commands to a device before the sata framework 1152 * has a chance to restore the device setting (such as cache enable/ 1153 * disable or other resettable stuff). 1154 */ 1155 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1156 ahci_portp->ahciport_reset_in_progress = 0; 1157 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1158 "ahci_tran_start clearing the " 1159 "reset_in_progress for port: %d", port); 1160 } 1161 1162 if (ahci_portp->ahciport_reset_in_progress && 1163 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1164 ! ddi_in_panic()) { 1165 spkt->satapkt_reason = SATA_PKT_BUSY; 1166 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1167 "ahci_tran_start returning BUSY while " 1168 "reset in progress: port: %d", port); 1169 mutex_exit(&ahci_portp->ahciport_mutex); 1170 return (SATA_TRAN_BUSY); 1171 } 1172 1173 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1174 spkt->satapkt_reason = SATA_PKT_BUSY; 1175 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1176 "ahci_tran_start returning BUSY while " 1177 "mopping in progress: port: %d", port); 1178 mutex_exit(&ahci_portp->ahciport_mutex); 1179 return (SATA_TRAN_BUSY); 1180 } 1181 1182 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1183 (ahci_portp->ahciport_pending_tags != 0)) { 1184 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1185 "return QUEUE_FULL: port %d because HBA cannot " 1186 "use multiple command lists for non-queued commands", 1187 port); 1188 mutex_exit(&ahci_portp->ahciport_mutex); 1189 return (SATA_TRAN_QUEUE_FULL); 1190 } 1191 1192 if (spkt->satapkt_op_mode & 1193 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1194 /* We need to do the sync start now */ 1195 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1196 spkt) == AHCI_FAILURE) { 1197 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1198 "return QUEUE_FULL: port %d", port); 1199 mutex_exit(&ahci_portp->ahciport_mutex); 1200 return (SATA_TRAN_QUEUE_FULL); 1201 } 1202 } else { 1203 /* Async start, using interrupt */ 1204 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1205 == AHCI_FAILURE) { 1206 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1207 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1208 "returning QUEUE_FULL: port %d", port); 1209 mutex_exit(&ahci_portp->ahciport_mutex); 1210 return (SATA_TRAN_QUEUE_FULL); 1211 } 1212 } 1213 1214 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1215 "sata tran accepted: port %d", port); 1216 1217 mutex_exit(&ahci_portp->ahciport_mutex); 1218 return (SATA_TRAN_ACCEPTED); 1219} 1220 1221/* 1222 * SATA_OPMODE_SYNCH flag is set 1223 * 1224 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1225 * without interrupt, otherwise we can still use the interrupt. 1226 * 1227 * WARNING!!! ahciport_mutex should be acquired before the function 1228 * is called. 1229 */ 1230static int 1231ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1232 uint8_t port, sata_pkt_t *spkt) 1233{ 1234 int pkt_timeout_ticks; 1235 uint32_t timeout_tags; 1236 uint32_t retrieve_errinfo_slot_status = 0; 1237 int rval; 1238 1239 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1240 "port %d spkt 0x%p", port, spkt); 1241 1242 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1243 /* Disable the port interrupt */ 1244 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 1245 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1246 1247 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1248 port, spkt)) == AHCI_FAILURE) { 1249 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1250 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 1251 return (rval); 1252 } 1253 1254 pkt_timeout_ticks = 1255 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1256 1257 /* 1258 * AHCI_PORT_FLAG_RQSENSE means the command is the REQUEST 1259 * SENSE which is sent down to retrieve sense data during 1260 * error recovery, so we need to keep the slot number of it 1261 * in order to handle it's completion. 1262 */ 1263 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RQSENSE) { 1264 /* rval is the allocated command slot */ 1265 retrieve_errinfo_slot_status = 0x1 << rval; 1266 } 1267 1268 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1269 mutex_exit(&ahci_portp->ahciport_mutex); 1270 1271 /* Simulate the interrupt */ 1272 ahci_port_intr(ahci_ctlp, ahci_portp, port, 1273 retrieve_errinfo_slot_status); 1274 1275 drv_usecwait(AHCI_1MS_USECS); 1276 1277 mutex_enter(&ahci_portp->ahciport_mutex); 1278 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1279 if (pkt_timeout_ticks < 0) { 1280 cmn_err(CE_NOTE, "!ahci_do_sync_start: " 1281 "port %d satapkt 0x%p timed out\n", 1282 port, (void *)spkt); 1283 timeout_tags = (0x1 << rval); 1284 mutex_exit(&ahci_portp->ahciport_mutex); 1285 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1286 port, timeout_tags, 1287 retrieve_errinfo_slot_status); 1288 mutex_enter(&ahci_portp->ahciport_mutex); 1289 } 1290 } 1291 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1292 /* Enable the port interrupt */ 1293 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 1294 return (AHCI_SUCCESS); 1295 1296 } else { 1297 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1298 port, spkt)) == AHCI_FAILURE) 1299 return (rval); 1300 1301 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1302 cv_wait(&ahci_portp->ahciport_cv, 1303 &ahci_portp->ahciport_mutex); 1304 1305 return (AHCI_SUCCESS); 1306 } 1307} 1308 1309#define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1310 if (satapkt) { \ 1311 satapkt->satapkt_reason = reason; \ 1312 /* \ 1313 * We set the satapkt_reason in both sync and \ 1314 * non-sync cases. \ 1315 */ \ 1316 } \ 1317 if (satapkt && \ 1318 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1319 satapkt->satapkt_comp) { \ 1320 mutex_exit(&ahci_portp->ahciport_mutex); \ 1321 (*satapkt->satapkt_comp)(satapkt); \ 1322 mutex_enter(&ahci_portp->ahciport_mutex); \ 1323 } else { \ 1324 if (satapkt && \ 1325 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1326 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1327 cv_signal(&ahci_portp->ahciport_cv); \ 1328 } 1329 1330/* 1331 * Searches for and claims a free slot. 1332 * 1333 * Returns: AHCI_FAILURE if no slots found 1334 * claimed slot number if successful 1335 * 1336 * WARNING!!! ahciport_mutex should be acquired before the function 1337 * is called. 1338 */ 1339/*ARGSUSED*/ 1340static int 1341ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 1342{ 1343 uint32_t free_slots; 1344 int slot; 1345 1346 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1347 "ahciport_pending_tags = 0x%x", 1348 ahci_portp->ahciport_pending_tags); 1349 1350 free_slots = (~ahci_portp->ahciport_pending_tags) 1351 & AHCI_SLOT_MASK(ahci_ctlp); 1352 1353 slot = ddi_ffs(free_slots) - 1; 1354 if (slot == -1) { 1355 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1356 "ahci_claim_free_slot: no empty slots"); 1357 return (AHCI_FAILURE); 1358 } 1359 1360 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1361 1362 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1363 "ahci_claim_free_slot: found slot: 0x%x", slot); 1364 1365 return (slot); 1366} 1367 1368/* 1369 * Builds the Command Table for the sata packet and delivers it to controller. 1370 * 1371 * Returns: 1372 * slot number if we can obtain a slot successfully 1373 * otherwise, return AHCI_FAILURE 1374 * 1375 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1376 */ 1377static int 1378ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1379 uint8_t port, sata_pkt_t *spkt) 1380{ 1381 int cmd_slot; 1382 sata_cmd_t *scmd; 1383 ahci_fis_h2d_register_t *h2d_register_fisp; 1384 ahci_cmd_table_t *cmd_table; 1385 ahci_cmd_header_t *cmd_header; 1386 int ncookies; 1387 int i; 1388#if AHCI_DEBUG 1389 uint32_t *ptr; 1390 uint8_t *ptr2; 1391#endif 1392 1393 spkt->satapkt_reason = SATA_PKT_BUSY; 1394 1395 scmd = &spkt->satapkt_cmd; 1396 1397 /* check if there is an empty command slot */ 1398 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp); 1399 if (cmd_slot == AHCI_FAILURE) { 1400 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free slot"); 1401 return (AHCI_FAILURE); 1402 } 1403 1404 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1405 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1406 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1407 cmd_slot, port, (void *)spkt); 1408 1409 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1410 bzero((void *)cmd_table, ahci_cmd_table_size); 1411 1412 /* for data transfer operations, this is the h2d register fis */ 1413 h2d_register_fisp = 1414 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1415 1416 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1417 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1418 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1419 SET_FIS_PMP(h2d_register_fisp, 1420 spkt->satapkt_device.satadev_addr.pmport); 1421 } 1422 1423 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1424 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1425 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1426 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1427 1428 switch (scmd->satacmd_addr_type) { 1429 1430 case ATA_ADDR_LBA: 1431 /* fallthrough */ 1432 1433 case ATA_ADDR_LBA28: 1434 /* LBA[7:0] */ 1435 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1436 1437 /* LBA[15:8] */ 1438 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1439 1440 /* LBA[23:16] */ 1441 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1442 1443 /* LBA [27:24] (also called dev_head) */ 1444 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1445 1446 break; 1447 1448 case ATA_ADDR_LBA48: 1449 /* LBA[7:0] */ 1450 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1451 1452 /* LBA[15:8] */ 1453 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1454 1455 /* LBA[23:16] */ 1456 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1457 1458 /* LBA [31:24] */ 1459 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1460 scmd->satacmd_lba_low_msb); 1461 1462 /* LBA [39:32] */ 1463 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1464 scmd->satacmd_lba_mid_msb); 1465 1466 /* LBA [47:40] */ 1467 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1468 scmd->satacmd_lba_high_msb); 1469 1470 /* Set dev_head */ 1471 SET_FIS_DEV_HEAD(h2d_register_fisp, 1472 scmd->satacmd_device_reg); 1473 1474 /* Set the extended sector count and features */ 1475 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1476 scmd->satacmd_sec_count_msb); 1477 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1478 scmd->satacmd_features_reg_ext); 1479 break; 1480 } 1481 1482 ncookies = scmd->satacmd_num_dma_cookies; 1483 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1484 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1485 ncookies, ahci_dma_prdt_number); 1486 1487 ASSERT(ncookies <= ahci_dma_prdt_number); 1488 1489 /* *** now fill the scatter gather list ******* */ 1490 for (i = 0; i < ncookies; i++) { 1491 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1492 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1493 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1494 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1495 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1496 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1497 } 1498 1499 /* The ACMD field is filled in for ATAPI command */ 1500 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1501 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1502 SATA_ATAPI_MAX_CDB_LEN); 1503 /* 1504 * For ATAPI command, scmd->satacmd_addr_type is 0 1505 */ 1506 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1507 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1508 } 1509 1510 /* Set Command Header in Command List */ 1511 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1512 BZERO_DESCR_INFO(cmd_header); 1513 BZERO_PRD_BYTE_COUNT(cmd_header); 1514 1515 /* Set the number of entries in the PRD table */ 1516 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1517 1518 /* Set the length of the command in the CFIS area */ 1519 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1520 1521 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1522 "sata_data_direction = 0x%x", 1523 scmd->satacmd_flags.sata_data_direction); 1524 1525 /* Set A bit if it is an ATAPI command */ 1526 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1527 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1528 1529 /* Set W bit if data is going to the device */ 1530 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1531 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1532 1533 /* 1534 * Set the prefetchable bit - this bit is only valid if the PRDTL 1535 * field is non-zero or the ATAPI 'A' bit is set in the command 1536 * header. This bit cannot be set when using native command 1537 * queuing commands or when using FIS-based switching with a Port 1538 * Multiplier. At the moment, the driver doesn't support these two 1539 * functions, so it's always setting the 'P' bit. 1540 */ 1541 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1542 1543 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1544 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1545 1546 /* 1547 * We are overloading satapkt_hba_driver_private with 1548 * watched_cycle count. 1549 */ 1550 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1551 1552#if AHCI_DEBUG 1553 /* Dump the command header and table */ 1554 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1555 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1556 "Command header&table for spkt 0x%p cmd_reg 0x%x port%d", 1557 spkt, scmd->satacmd_cmd_reg, port); 1558 ptr = (uint32_t *)cmd_header; 1559 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1560 " Command Header:%8x %8x %8x %8x", 1561 ptr[0], ptr[1], ptr[2], ptr[3]); 1562 1563 /* Dump the H2D register FIS */ 1564 ptr = (uint32_t *)h2d_register_fisp; 1565 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1566 " Command FIS: %8x %8x %8x %8x", 1567 ptr[0], ptr[1], ptr[2], ptr[3]); 1568 1569 /* Dump the ACMD register FIS */ 1570 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1571 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1572 if (ahci_debug_flags & AHCIDBG_COMMAND) 1573 ahci_log(ahci_ctlp, CE_WARN, 1574 " ATAPI command: %2x %2x %2x %2x " 1575 "%2x %2x %2x %2x", 1576 ptr2[8 * i], ptr2[8 * i + 1], 1577 ptr2[8 * i + 2], ptr2[8 * i + 3], 1578 ptr2[8 * i + 4], ptr2[8 * i + 5], 1579 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1580 1581 /* Dump the PRDT */ 1582 for (i = 0; i < ncookies; i++) { 1583 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1584 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1585 " Cookie %d: %8x %8x %8x %8x", 1586 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1587 } 1588#endif 1589 1590 (void) ddi_dma_sync( 1591 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1592 0, 1593 ahci_cmd_table_size, 1594 DDI_DMA_SYNC_FORDEV); 1595 1596 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1597 cmd_slot * sizeof (ahci_cmd_header_t), 1598 sizeof (ahci_cmd_header_t), 1599 DDI_DMA_SYNC_FORDEV); 1600 1601 /* Indicate to the HBA that a command is active. */ 1602 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1603 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1604 (0x1 << cmd_slot)); 1605 1606 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1607 "exit: port %d", port); 1608 1609 return (cmd_slot); 1610} 1611 1612/* 1613 * Called by the sata framework to abort the previously sent packet(s). 1614 * 1615 * Reset device to abort commands. 1616 */ 1617static int 1618ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1619{ 1620 ahci_ctl_t *ahci_ctlp; 1621 ahci_port_t *ahci_portp; 1622 uint32_t slot_status; 1623 uint32_t aborted_tags, finished_tags; 1624 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1625 uint8_t port; 1626 int tmp_slot; 1627 1628 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1629 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1630 1631 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1632 "ahci_tran_abort enter: port %d", port); 1633 1634 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1635 mutex_enter(&ahci_portp->ahciport_mutex); 1636 1637 /* 1638 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1639 * commands are being mopped, therefore there is nothing else to do 1640 */ 1641 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1642 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1643 "ahci_tran_abort: port %d is in " 1644 "mopping process, so just return directly ", port); 1645 mutex_exit(&ahci_portp->ahciport_mutex); 1646 return (SATA_SUCCESS); 1647 } 1648 1649 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1650 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1651 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1652 /* 1653 * In case the targer driver would send the request before 1654 * sata framework can have the opportunity to process those 1655 * event reports. 1656 */ 1657 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1658 spkt->satapkt_device.satadev_state = 1659 ahci_portp->ahciport_port_state; 1660 ahci_update_sata_registers(ahci_ctlp, port, 1661 &spkt->satapkt_device); 1662 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1663 "ahci_tran_abort returning SATA_FAILURE while " 1664 "port in FAILED/SHUTDOWN/PWROFF state: " 1665 "port: %d", port); 1666 mutex_exit(&ahci_portp->ahciport_mutex); 1667 return (SATA_FAILURE); 1668 } 1669 1670 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1671 /* 1672 * ahci_intr_phyrdy_change() may have rendered it to 1673 * AHCI_PORT_TYPE_NODEV. 1674 */ 1675 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1676 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1677 spkt->satapkt_device.satadev_state = 1678 ahci_portp->ahciport_port_state; 1679 ahci_update_sata_registers(ahci_ctlp, port, 1680 &spkt->satapkt_device); 1681 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1682 "ahci_tran_abort returning SATA_FAILURE while " 1683 "no device attached: port: %d", port); 1684 mutex_exit(&ahci_portp->ahciport_mutex); 1685 return (SATA_FAILURE); 1686 } 1687 1688 if (flag == SATA_ABORT_ALL_PACKETS) { 1689 aborted_tags = ahci_portp->ahciport_pending_tags; 1690 cmn_err(CE_NOTE, "!ahci port %d abort all packets", port); 1691 } else { 1692 aborted_tags = 0xffffffff; 1693 /* 1694 * Aborting one specific packet, first search our 1695 * ahciport_slot_pkts[] list for matching spkt. 1696 */ 1697 for (tmp_slot = 0; 1698 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1699 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1700 aborted_tags = (0x1 << tmp_slot); 1701 break; 1702 } 1703 } 1704 1705 if (aborted_tags == 0xffffffff) { 1706 /* request packet is not on the pending list */ 1707 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1708 "Cannot find the aborting pkt 0x%p on the " 1709 "pending list", (void *)spkt); 1710 ahci_update_sata_registers(ahci_ctlp, port, 1711 &spkt->satapkt_device); 1712 mutex_exit(&ahci_portp->ahciport_mutex); 1713 return (SATA_FAILURE); 1714 } 1715 cmn_err(CE_NOTE, "!ahci port %d abort satapkt 0x%p", 1716 port, (void *)spkt); 1717 } 1718 1719 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1720 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1721 1722 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1723 ahci_portp->ahciport_mop_in_progress++; 1724 1725 /* 1726 * To abort the packet(s), first we are trying to clear PxCMD.ST 1727 * to stop the port, and if the port can be stopped 1728 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 1729 * then we just send back the aborted packet(s) with ABORTED flag 1730 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 1731 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 1732 * perform a COMRESET. 1733 */ 1734 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1735 ahci_portp, port, NULL, NULL); 1736 1737 /* 1738 * Compute which have finished and which need to be retried. 1739 * 1740 * The finished tags are ahciport_pending_tags minus the slot_status. 1741 * The aborted_tags have to be reduced by finished_tags since we 1742 * can't possibly abort a tag which had finished already. 1743 */ 1744 finished_tags = ahci_portp->ahciport_pending_tags & 1745 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1746 1747 aborted_tags &= ~finished_tags; 1748 1749 ahci_mop_commands(ahci_ctlp, 1750 ahci_portp, 1751 port, 1752 slot_status, 1753 0, /* failed tags */ 1754 0, /* timeout tags */ 1755 aborted_tags, 1756 0); /* reset tags */ 1757 1758 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 1759 mutex_exit(&ahci_portp->ahciport_mutex); 1760 1761 return (SATA_SUCCESS); 1762} 1763 1764/* 1765 * Used to do device reset and reject all the pending packets on a device 1766 * during the reset operation. 1767 * 1768 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1769 */ 1770static int 1771ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 1772 ahci_port_t *ahci_portp, uint8_t port) 1773{ 1774 uint32_t slot_status; 1775 uint32_t reset_tags, finished_tags; 1776 sata_device_t sdevice; 1777 int ret; 1778 1779 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1780 "ahci_reset_device_reject_pkts on port: %d", port); 1781 1782 /* 1783 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1784 * commands are being mopped, therefore there is nothing else to do 1785 */ 1786 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1787 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1788 "ahci_reset_device_reject_pkts: port %d is in " 1789 "mopping process, so return directly ", port); 1790 return (SATA_SUCCESS); 1791 } 1792 1793 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1794 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1795 1796 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1797 1798 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 1799 != AHCI_SUCCESS) { 1800 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1801 "Try to do a port reset after software " 1802 "reset failed", port); 1803 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 1804 if (ret != AHCI_SUCCESS) { 1805 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1806 "ahci_reset_device_reject_pkts: port %d " 1807 "failed", port); 1808 return (SATA_FAILURE); 1809 } 1810 } 1811 /* Set the reset in progress flag */ 1812 ahci_portp->ahciport_reset_in_progress = 1; 1813 1814 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1815 ahci_portp->ahciport_mop_in_progress++; 1816 1817 /* Indicate to the framework that a reset has happened */ 1818 bzero((void *)&sdevice, sizeof (sata_device_t)); 1819 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 1820 sdevice.satadev_addr.pmport = 0; 1821 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 1822 1823 sdevice.satadev_state = SATA_DSTATE_RESET | 1824 SATA_DSTATE_PWR_ACTIVE; 1825 mutex_exit(&ahci_portp->ahciport_mutex); 1826 sata_hba_event_notify( 1827 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 1828 &sdevice, 1829 SATA_EVNT_DEVICE_RESET); 1830 mutex_enter(&ahci_portp->ahciport_mutex); 1831 1832 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 1833 "port %d sending event up: SATA_EVNT_RESET", port); 1834 1835 /* Next try to mop the pending commands */ 1836 finished_tags = ahci_portp->ahciport_pending_tags & 1837 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1838 1839 reset_tags &= ~finished_tags; 1840 1841 ahci_mop_commands(ahci_ctlp, 1842 ahci_portp, 1843 port, 1844 slot_status, 1845 0, /* failed tags */ 1846 0, /* timeout tags */ 1847 0, /* aborted tags */ 1848 reset_tags); /* reset tags */ 1849 1850 return (SATA_SUCCESS); 1851} 1852 1853/* 1854 * Used to do port reset and reject all the pending packets on a port during 1855 * the reset operation. 1856 * 1857 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1858 */ 1859static int 1860ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 1861 ahci_port_t *ahci_portp, uint8_t port) 1862{ 1863 uint32_t slot_status; 1864 uint32_t reset_tags, finished_tags; 1865 1866 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1867 "ahci_reset_port_reject_pkts on port: %d", port); 1868 1869 /* 1870 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1871 * commands are being mopped, therefore there is nothing else to do 1872 */ 1873 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1874 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1875 "ahci_reset_port_reject_pkts: port %d is in " 1876 "mopping process, so return directly ", port); 1877 return (SATA_SUCCESS); 1878 } 1879 1880 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1881 ahci_portp->ahciport_mop_in_progress++; 1882 1883 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1884 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1885 1886 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1887 1888 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 1889 ahci_portp, port, AHCI_PORT_RESET, NULL) != AHCI_SUCCESS) 1890 return (SATA_FAILURE); 1891 1892 finished_tags = ahci_portp->ahciport_pending_tags & 1893 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1894 1895 reset_tags &= ~finished_tags; 1896 1897 ahci_mop_commands(ahci_ctlp, 1898 ahci_portp, 1899 port, 1900 slot_status, 1901 0, /* failed tags */ 1902 0, /* timeout tags */ 1903 0, /* aborted tags */ 1904 reset_tags); /* reset tags */ 1905 1906 return (SATA_SUCCESS); 1907} 1908 1909/* 1910 * Used to do hba reset and reject all the pending packets on all ports 1911 * during the reset operation. 1912 */ 1913static int 1914ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 1915{ 1916 ahci_port_t *ahci_portp; 1917 uint32_t slot_status[AHCI_MAX_PORTS]; 1918 uint32_t reset_tags[AHCI_MAX_PORTS]; 1919 uint32_t finished_tags[AHCI_MAX_PORTS]; 1920 sata_device_t sdevice[AHCI_MAX_PORTS]; 1921 uint8_t port; 1922 int ret = SATA_SUCCESS; 1923 1924 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1925 "ahci_reset_hba_reject_pkts enter"); 1926 1927 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 1928 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 1929 continue; 1930 } 1931 1932 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1933 1934 mutex_enter(&ahci_portp->ahciport_mutex); 1935 slot_status[port] = ddi_get32( 1936 ahci_ctlp->ahcictl_ahci_acc_handle, 1937 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1938 reset_tags[port] = slot_status[port] 1939 & AHCI_SLOT_MASK(ahci_ctlp); 1940 mutex_exit(&ahci_portp->ahciport_mutex); 1941 } 1942 1943 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 1944 ret = SATA_FAILURE; 1945 goto out; 1946 } 1947 1948 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 1949 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 1950 continue; 1951 } 1952 1953 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1954 1955 mutex_enter(&ahci_portp->ahciport_mutex); 1956 /* 1957 * To prevent recursive enter to ahci_mop_commands, we need 1958 * check AHCI_PORT_FLAG_MOPPING flag. 1959 */ 1960 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1961 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1962 "ahci_reset_hba_reject_pkts: port %d is in " 1963 "mopping process, so return directly ", port); 1964 mutex_exit(&ahci_portp->ahciport_mutex); 1965 continue; 1966 } 1967 1968 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1969 ahci_portp->ahciport_mop_in_progress++; 1970 1971 /* Indicate to the framework that a reset has happened */ 1972 bzero((void *)&sdevice[port], sizeof (sata_device_t)); 1973 sdevice[port].satadev_addr.cport = 1974 ahci_ctlp->ahcictl_port_to_cport[port]; 1975 sdevice[port].satadev_addr.pmport = 0; 1976 sdevice[port].satadev_addr.qual = SATA_ADDR_DCPORT; 1977 1978 sdevice[port].satadev_state = SATA_DSTATE_RESET | 1979 SATA_DSTATE_PWR_ACTIVE; 1980 mutex_exit(&ahci_portp->ahciport_mutex); 1981 sata_hba_event_notify( 1982 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 1983 &sdevice[port], 1984 SATA_EVNT_DEVICE_RESET); 1985 mutex_enter(&ahci_portp->ahciport_mutex); 1986 1987 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 1988 "port %d sending event up: SATA_EVNT_RESET", 1989 port); 1990 1991 finished_tags[port] = ahci_portp->ahciport_pending_tags & 1992 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 1993 1994 reset_tags[port] &= ~finished_tags[port]; 1995 1996 ahci_mop_commands(ahci_ctlp, 1997 ahci_portp, 1998 port, 1999 slot_status[port], 2000 0, /* failed tags */ 2001 0, /* timeout tags */ 2002 0, /* aborted tags */ 2003 reset_tags[port]); /* reset tags */ 2004 mutex_exit(&ahci_portp->ahciport_mutex); 2005 } 2006out: 2007 return (ret); 2008} 2009 2010/* 2011 * Called by sata framework to reset a port(s) or device. 2012 */ 2013static int 2014ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2015{ 2016 ahci_ctl_t *ahci_ctlp; 2017 ahci_port_t *ahci_portp; 2018 uint8_t cport = sd->satadev_addr.cport; 2019 uint8_t port; 2020 int ret = SATA_SUCCESS; 2021 2022 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2023 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2024 2025 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2026 "ahci_tran_reset_port enter: cport: %d", cport); 2027 2028 switch (sd->satadev_addr.qual) { 2029 case SATA_ADDR_CPORT: 2030 /* Port reset */ 2031 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2032 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2033 "reset port", port); 2034 2035 mutex_enter(&ahci_portp->ahciport_mutex); 2036 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2037 mutex_exit(&ahci_portp->ahciport_mutex); 2038 2039 break; 2040 2041 case SATA_ADDR_DCPORT: 2042 /* Device reset */ 2043 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2044 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2045 "reset device", port); 2046 2047 mutex_enter(&ahci_portp->ahciport_mutex); 2048 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2049 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2050 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2051 /* 2052 * In case the targer driver would send the request 2053 * before sata framework can have the opportunity to 2054 * process those event reports. 2055 */ 2056 sd->satadev_state = ahci_portp->ahciport_port_state; 2057 ahci_update_sata_registers(ahci_ctlp, port, sd); 2058 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2059 "ahci_tran_reset_dport returning SATA_FAILURE " 2060 "while port in FAILED/SHUTDOWN/PWROFF state: " 2061 "port: %d", port); 2062 mutex_exit(&ahci_portp->ahciport_mutex); 2063 ret = SATA_FAILURE; 2064 break; 2065 } 2066 2067 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2068 /* 2069 * ahci_intr_phyrdy_change() may have rendered it to 2070 * AHCI_PORT_TYPE_NODEV. 2071 */ 2072 sd->satadev_type = SATA_DTYPE_NONE; 2073 sd->satadev_state = ahci_portp->ahciport_port_state; 2074 ahci_update_sata_registers(ahci_ctlp, port, sd); 2075 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2076 "ahci_tran_reset_dport returning SATA_FAILURE " 2077 "while no device attached: port: %d", port); 2078 mutex_exit(&ahci_portp->ahciport_mutex); 2079 ret = SATA_FAILURE; 2080 break; 2081 } 2082 2083 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2084 ahci_portp, port); 2085 mutex_exit(&ahci_portp->ahciport_mutex); 2086 break; 2087 2088 case SATA_ADDR_CNTRL: 2089 /* Reset the whole controller */ 2090 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2091 "reset the whole hba", port); 2092 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2093 break; 2094 2095 case SATA_ADDR_PMPORT: 2096 case SATA_ADDR_DPMPORT: 2097 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2098 "ahci_tran_reset_dport: port multiplier will be " 2099 "supported later"); 2100 /* FALLSTHROUGH */ 2101 default: 2102 ret = SATA_FAILURE; 2103 } 2104 2105 return (ret); 2106} 2107 2108/* 2109 * Called by sata framework to activate a port as part of hotplug. 2110 * (cfgadm -c connect satax/y) 2111 * Note: Not port-mult aware. 2112 */ 2113static int 2114ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2115{ 2116 ahci_ctl_t *ahci_ctlp; 2117 ahci_port_t *ahci_portp; 2118 uint8_t cport = satadev->satadev_addr.cport; 2119 uint8_t port; 2120 2121 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2122 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2123 2124 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2125 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2126 2127 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2128 2129 mutex_enter(&ahci_portp->ahciport_mutex); 2130 cmn_err(CE_NOTE, "!ahci port %d is activated", port); 2131 2132 /* 2133 * Reset the port so that the PHY communication would be re-established. 2134 * But this reset is an internal operation and the sata module doesn't 2135 * need to know about it. Moreover, the port with a device attached will 2136 * be started too. 2137 */ 2138 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2139 ahci_portp, port, 2140 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2141 NULL); 2142 2143 /* 2144 * Need to check the link status and device status of the port 2145 * and consider raising power if the port was in D3 state 2146 */ 2147 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2148 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2149 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2150 2151 satadev->satadev_state = ahci_portp->ahciport_port_state; 2152 2153 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2154 2155 mutex_exit(&ahci_portp->ahciport_mutex); 2156 return (SATA_SUCCESS); 2157} 2158 2159/* 2160 * Called by sata framework to deactivate a port as part of hotplug. 2161 * (cfgadm -c disconnect satax/y) 2162 * Note: Not port-mult aware. 2163 */ 2164static int 2165ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2166{ 2167 ahci_ctl_t *ahci_ctlp; 2168 ahci_port_t *ahci_portp; 2169 uint8_t cport = satadev->satadev_addr.cport; 2170 uint8_t port; 2171 uint32_t port_scontrol; 2172 2173 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2174 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2175 2176 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2177 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2178 2179 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2180 2181 mutex_enter(&ahci_portp->ahciport_mutex); 2182 cmn_err(CE_NOTE, "!ahci port %d is deactivated", port); 2183 2184 /* Disable the interrupts on the port */ 2185 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2186 2187 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2188 goto phy_offline; 2189 } 2190 2191 /* First to abort all the pending commands */ 2192 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2193 2194 /* Then stop the port */ 2195 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2196 ahci_portp, port); 2197 2198 /* Next put the PHY offline */ 2199 2200phy_offline: 2201 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2202 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2203 AHCI_SCONTROL_SET_DET(port_scontrol, AHCI_SCONTROL_DET_PHYOFFLINE); 2204 2205 /* Update ahciport_port_state */ 2206 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2207 satadev->satadev_state = ahci_portp->ahciport_port_state; 2208 2209 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2210 2211 mutex_exit(&ahci_portp->ahciport_mutex); 2212 return (SATA_SUCCESS); 2213} 2214 2215/* 2216 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2217 * when a device is unplugged or a port is deactivated. 2218 * 2219 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2220 */ 2221static void 2222ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2223 ahci_port_t *ahci_portp, uint8_t port) 2224{ 2225 uint32_t slot_status; 2226 uint32_t abort_tags; 2227 2228 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2229 "ahci_reject_all_abort_pkts on port: %d", port); 2230 2231 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2232 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2233 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2234 2235 /* No need to do mop when there is no outstanding commands */ 2236 if (slot_status != 0) { 2237 /* 2238 * We need to do the mop even AHCI_PORT_FLAG_MOPPING is 2239 * already set because during error recovery process, the 2240 * REQUEST SENSE command can be delivered to HBA to get 2241 * sense data, so when the device is removed, the command 2242 * need to be aborted too. And for this kind of condition, 2243 * we can make sure the abort_tags is just the REQUEST 2244 * SENSE slot number. 2245 */ 2246 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2247 ahci_portp->ahciport_mop_in_progress++; 2248 2249 ahci_mop_commands(ahci_ctlp, 2250 ahci_portp, 2251 port, 2252 slot_status, 2253 0, /* failed tags */ 2254 0, /* timeout tags */ 2255 abort_tags, /* aborting tags */ 2256 0); /* reset tags */ 2257 } 2258} 2259 2260#if defined(__lock_lint) 2261static int 2262ahci_selftest(dev_info_t *dip, sata_device_t *device) 2263{ 2264 return (SATA_SUCCESS); 2265} 2266#endif 2267 2268/* 2269 * Allocate the ports structure, only called by ahci_attach 2270 */ 2271static int 2272ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2273{ 2274 int port, cport = 0; 2275 2276 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2277 "ahci_alloc_ports_state enter"); 2278 2279 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2280 2281 /* Allocate structures only for the implemented ports */ 2282 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2283 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2284 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2285 "hba port %d not implemented", port); 2286 continue; 2287 } 2288 2289#ifndef __lock_lint 2290 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2291 ahci_ctlp->ahcictl_port_to_cport[port] = 2292 (uint8_t)cport++; 2293#endif /* __lock_lint */ 2294 2295 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2296 goto err_out; 2297 } 2298 } 2299 2300 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2301 return (AHCI_SUCCESS); 2302 2303err_out: 2304 for (port--; port >= 0; port--) { 2305 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2306 ahci_dealloc_port_state(ahci_ctlp, port); 2307 } 2308 } 2309 2310 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2311 return (AHCI_FAILURE); 2312} 2313 2314/* 2315 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2316 */ 2317static void 2318ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2319{ 2320 int port; 2321 2322 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2323 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2324 /* if this port is implemented by the HBA */ 2325 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2326 ahci_dealloc_port_state(ahci_ctlp, port); 2327 } 2328 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2329} 2330 2331/* 2332 * Initialize the controller. 2333 * 2334 * This routine can be called from three seperate cases: DDI_ATTACH, 2335 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2336 * other two cases; device signature probing are attempted only during 2337 * DDI_ATTACH case. 2338 * 2339 * WARNING!!! Disable the whole controller's interrupts before calling and 2340 * the interrupts will be enabled upon successfully return. 2341 */ 2342static int 2343ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2344{ 2345 ahci_port_t *ahci_portp; 2346 uint32_t ghc_control; 2347 int port; 2348 2349 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2350 "ahci_initialize_controller enter"); 2351 2352 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2353 2354 /* 2355 * Indicate that system software is AHCI aware by setting 2356 * GHC.AE to 1 2357 */ 2358 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2359 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2360 2361 ghc_control |= AHCI_HBA_GHC_AE; 2362 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2363 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2364 ghc_control); 2365 2366 /* Initialize the implemented ports and structures */ 2367 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2368 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2369 continue; 2370 } 2371 2372 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2373 mutex_enter(&ahci_portp->ahciport_mutex); 2374 2375 /* 2376 * Ensure that the controller is not in the running state 2377 * by checking every implemented port's PxCMD register 2378 */ 2379 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2380 != AHCI_SUCCESS) { 2381 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2382 "ahci_initialize_controller: failed to " 2383 "initialize port %d", port); 2384 /* 2385 * Set the port state to SATA_PSTATE_FAILED if 2386 * failed to initialize it. 2387 */ 2388 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2389 } 2390 2391 mutex_exit(&ahci_portp->ahciport_mutex); 2392 } 2393 2394 /* Enable the whole controller interrupts */ 2395 ahci_enable_all_intrs(ahci_ctlp); 2396 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2397 2398 return (AHCI_SUCCESS); 2399} 2400 2401/* 2402 * Reverse of ahci_initialize_controller() 2403 * 2404 * WARNING!!! ahcictl_mutex should be acquired before the function is called. 2405 */ 2406static void 2407ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2408{ 2409 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2410 "ahci_uninitialize_controller enter"); 2411 2412 /* disable all the interrupts. */ 2413 ahci_disable_all_intrs(ahci_ctlp); 2414} 2415 2416/* 2417 * The routine is to initialize the port. First put the port in NOTRunning 2418 * state, then enable port interrupt and clear Serror register. And under 2419 * AHCI_ATTACH case, find device signature and then try to start the port. 2420 * 2421 * WARNING!!! ahcictl_mutex and ahciport_mutex should be acquired before 2422 * the function is called. 2423 */ 2424static int 2425ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2426 ahci_port_t *ahci_portp, uint8_t port) 2427{ 2428 uint32_t port_cmd_status; 2429 2430 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2431 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2432 2433 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2434 "ahci_initialize_port: port %d " 2435 "port_cmd_status = 0x%x", port, port_cmd_status); 2436 /* 2437 * Check whether the port is in NotRunning state, if not, 2438 * put the port in NotRunning state 2439 */ 2440 if (!(port_cmd_status & 2441 (AHCI_CMD_STATUS_ST | 2442 AHCI_CMD_STATUS_CR | 2443 AHCI_CMD_STATUS_FRE | 2444 AHCI_CMD_STATUS_FR))) { 2445 2446 goto next; 2447 } 2448 2449 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2450 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2451 return (AHCI_FAILURE); 2452 2453next: 2454 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2455 "port %d is in NotRunning state now", port); 2456 2457 /* 2458 * At the time being, only probe ports/devices and get the types of 2459 * attached devices during attach. In fact, the device can be changed 2460 * during power state changes, but I would like to postpone this part 2461 * when the power management is supported. 2462 */ 2463 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2464 /* Try to get the device signature */ 2465 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2466 2467 /* Return directly if no device connected */ 2468 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2469 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2470 "No device connected to port %d", port); 2471 goto out; 2472 } 2473 2474 /* Try to start the port */ 2475 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2476 != AHCI_SUCCESS) { 2477 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2478 "failed to start port %d", port); 2479 return (AHCI_FAILURE); 2480 } 2481 } 2482out: 2483 /* Enable port interrupts */ 2484 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2485 2486 return (AHCI_SUCCESS); 2487} 2488 2489/* 2490 * AHCI device reset ...; a single device on one of the ports is reset, 2491 * but the HBA and physical communication remain intact. This is the 2492 * least intrusive. 2493 * 2494 * When issuing a software reset sequence, there should not be other 2495 * commands in the command list, so we will first clear and then re-set 2496 * PxCMD.ST to clear PxCI. And before issuing the software reset, 2497 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 2498 * cleared. 2499 * 2500 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 2501 * set before the function is called. 2502 */ 2503static int 2504ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 2505 uint8_t port) 2506{ 2507 ahci_fis_h2d_register_t *h2d_register_fisp; 2508 ahci_cmd_table_t *cmd_table; 2509 ahci_cmd_header_t *cmd_header; 2510 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 2511 int slot, loop_count; 2512 2513 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2514 "Port %d device resetting", port); 2515 2516 /* First to clear PxCMD.ST */ 2517 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2518 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2519 2520 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 2521 2522 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2523 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2524 port_cmd_status|AHCI_CMD_STATUS_ST); 2525 2526 /* And then to re-set PxCMD.ST */ 2527 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2528 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2529 2530 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2531 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2532 port_cmd_status|AHCI_CMD_STATUS_ST); 2533 2534 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 2535 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2536 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2537 2538 if (port_task_file & AHCI_TFD_STS_BSY || 2539 port_task_file & AHCI_TFD_STS_DRQ) { 2540 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 2541 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2542 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 2543 "but PxCMD.CLO isn't supported, so a port " 2544 "reset is needed."); 2545 return (AHCI_FAILURE); 2546 } 2547 } 2548 2549 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp); 2550 if (slot == AHCI_FAILURE) { 2551 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2552 "ahci_software_reset: no free slot"); 2553 return (AHCI_FAILURE); 2554 } 2555 2556 /* Now send the first R2H FIS with SRST set to 1 */ 2557 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2558 bzero((void *)cmd_table, ahci_cmd_table_size); 2559 2560 h2d_register_fisp = 2561 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2562 2563 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2564 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2565 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 2566 2567 /* Set Command Header in Command List */ 2568 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2569 BZERO_DESCR_INFO(cmd_header); 2570 BZERO_PRD_BYTE_COUNT(cmd_header); 2571 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2572 2573 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 2574 SET_RESET(cmd_header, 1); 2575 SET_WRITE(cmd_header, 1); 2576 2577 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2578 0, 2579 ahci_cmd_table_size, 2580 DDI_DMA_SYNC_FORDEV); 2581 2582 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2583 slot * sizeof (ahci_cmd_header_t), 2584 sizeof (ahci_cmd_header_t), 2585 DDI_DMA_SYNC_FORDEV); 2586 2587 /* Indicate to the HBA that a command is active. */ 2588 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2589 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2590 (0x1 << slot)); 2591 2592 loop_count = 0; 2593 2594 /* Loop till the first command is finished */ 2595 do { 2596 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2597 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2598 2599 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2600 /* We are effectively timing out after 0.1 sec. */ 2601 break; 2602 } 2603 /* Wait for 10 millisec */ 2604#ifndef __lock_lint 2605 delay(AHCI_10MS_TICKS); 2606#endif /* __lock_lint */ 2607 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2608 2609 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2610 "ahci_software_reset: 1st loop count: %d, " 2611 "port_cmd_issue = 0x%x, slot = 0x%x", 2612 loop_count, port_cmd_issue, slot); 2613 2614 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2615 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2616 2617 /* Now send the second R2H FIS with SRST cleard to zero */ 2618 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2619 bzero((void *)cmd_table, ahci_cmd_table_size); 2620 2621 h2d_register_fisp = 2622 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2623 2624 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2625 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2626 2627 /* Set Command Header in Command List */ 2628 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2629 BZERO_DESCR_INFO(cmd_header); 2630 BZERO_PRD_BYTE_COUNT(cmd_header); 2631 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2632 2633 SET_WRITE(cmd_header, 1); 2634 2635 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2636 0, 2637 ahci_cmd_table_size, 2638 DDI_DMA_SYNC_FORDEV); 2639 2640 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2641 slot * sizeof (ahci_cmd_header_t), 2642 sizeof (ahci_cmd_header_t), 2643 DDI_DMA_SYNC_FORDEV); 2644 2645 /* Indicate to the HBA that a command is active. */ 2646 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2647 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2648 (0x1 << slot)); 2649 2650 loop_count = 0; 2651 2652 /* Loop till the second command is finished */ 2653 do { 2654 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2655 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2656 2657 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2658 /* We are effectively timing out after 0.1 sec. */ 2659 break; 2660 } 2661 /* Wait for 10 millisec */ 2662#ifndef __lock_lint 2663 delay(AHCI_10MS_TICKS); 2664#endif /* __lock_lint */ 2665 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2666 2667 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2668 "ahci_software_reset: 2nd loop count: %d, " 2669 "port_cmd_issue = 0x%x, slot = 0x%x", 2670 loop_count, port_cmd_issue, slot); 2671 2672 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2673 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2674 2675 return (AHCI_SUCCESS); 2676} 2677 2678/* 2679 * AHCI port reset ...; the physical communication between the HBA and device 2680 * on a port are disabled. This is more intrusive. 2681 * 2682 * When an HBA or port reset occurs, Phy communication is going to 2683 * be re-established with the device through a COMRESET followed by the 2684 * normal out-of-band communication sequence defined in Serial ATA. AT 2685 * the end of reset, the device, if working properly, will send a D2H 2686 * Register FIS, which contains the device signature. When the HBA receives 2687 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 2688 * the PxSIG register with the signature. 2689 * 2690 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 2691 * to individually spin-up attached devices. Please refer to chapter 10.9 of 2692 * AHCI 1.0 spec. 2693 */ 2694/* 2695 * WARNING!!! ahciport_mutex should be acquired, intr should be disabled, 2696 * and PxCMD.ST and PxCMD.FRE should be also cleared before the function 2697 * is called. 2698 */ 2699static int 2700ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 2701{ 2702 uint32_t cap_status, port_cmd_status; 2703 uint32_t port_scontrol, port_sstatus; 2704 uint32_t port_signature, port_intr_status, port_task_file; 2705 int loop_count; 2706 int rval = AHCI_SUCCESS; 2707 2708 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2709 "Port %d port resetting...", port); 2710 ahci_portp->ahciport_port_state = 0; 2711 2712 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2713 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 2714 2715 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2716 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2717 2718 if (cap_status & AHCI_HBA_CAP_SSS) { 2719 /* 2720 * HBA support staggered spin-up, if the port has 2721 * not spin up yet, then force it to do spin-up 2722 */ 2723 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 2724 if (!(ahci_portp->ahciport_flags 2725 & AHCI_PORT_FLAG_SPINUP)) { 2726 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2727 "Port %d PxCMD.SUD is zero, force " 2728 "it to do spin-up", port); 2729 ahci_portp->ahciport_flags |= 2730 AHCI_PORT_FLAG_SPINUP; 2731 } 2732 } 2733 } else { 2734 /* 2735 * HBA doesn't support stagger spin-up, force it 2736 * to do normal COMRESET 2737 */ 2738 ASSERT(port_cmd_status & AHCI_CMD_STATUS_SUD); 2739 if (ahci_portp->ahciport_flags & 2740 AHCI_PORT_FLAG_SPINUP) { 2741 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2742 "HBA does not support staggered spin-up " 2743 "force it to do normal COMRESET"); 2744 ahci_portp->ahciport_flags &= 2745 ~AHCI_PORT_FLAG_SPINUP; 2746 } 2747 } 2748 2749 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 2750 /* Do normal COMRESET */ 2751 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2752 "ahci_port_reset: do normal COMRESET", port); 2753 2754 ASSERT(port_cmd_status & AHCI_CMD_STATUS_SUD); 2755 2756 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2757 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2758 AHCI_SCONTROL_SET_DET(port_scontrol, 2759 AHCI_SCONTROL_DET_COMRESET); 2760 2761 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2762 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2763 port_scontrol); 2764 2765 /* Enable PxCMD.FRE to read device */ 2766 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2767 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2768 port_cmd_status|AHCI_CMD_STATUS_FRE); 2769 2770 /* 2771 * Give time for COMRESET to percolate, according to the AHCI 2772 * spec, software shall wait at least 1 millisecond before 2773 * clearing PxSCTL.DET 2774 */ 2775#ifndef __lock_lint 2776 delay(AHCI_1MS_TICKS*2); 2777#endif /* __lock_lint */ 2778 2779 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 2780 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2781 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2782 AHCI_SCONTROL_SET_DET(port_scontrol, 2783 AHCI_SCONTROL_DET_NOACTION); 2784 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2785 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2786 port_scontrol); 2787 } else { 2788 /* Do staggered spin-up */ 2789 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2790 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2791 AHCI_SCONTROL_SET_DET(port_scontrol, 2792 AHCI_SCONTROL_DET_NOACTION); 2793 2794 /* PxSCTL.DET must be 0 */ 2795 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2796 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2797 port_scontrol); 2798 2799 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 2800 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2801 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2802 port_cmd_status); 2803 2804 /* 0 -> 1 edge */ 2805#ifndef __lock_lint 2806 delay(AHCI_1MS_TICKS*2); 2807#endif /* __lock_lint */ 2808 2809 /* Set PxCMD.SUD to 1 */ 2810 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2811 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2812 port_cmd_status |= AHCI_CMD_STATUS_SUD; 2813 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2814 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2815 port_cmd_status); 2816 2817 /* Enable PxCMD.FRE to read device */ 2818 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2819 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2820 port_cmd_status|AHCI_CMD_STATUS_FRE); 2821 } 2822 2823 /* 2824 * The port enters P:StartComm state, and HBA tells link layer to 2825 * start communication, which involves sending COMRESET to device. 2826 * And the HBA resets PxTFD.STS to 7Fh. 2827 * 2828 * When a COMINIT is received from the device, then the port enters 2829 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 2830 * PxSSTS.DET to 1h to indicate a device is detected but communication 2831 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 2832 * a COMINIT has been received. 2833 */ 2834 /* 2835 * The DET field is valid only if IPM field indicates 2836 * that the interface is in active state. 2837 */ 2838 loop_count = 0; 2839 do { 2840 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2841 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 2842 2843 if (AHCI_SSTATUS_GET_IPM(port_sstatus) != 2844 AHCI_SSTATUS_IPM_INTERFACE_ACTIVE) { 2845 /* 2846 * If the interface is not active, the DET field 2847 * is considered not accurate. So we want to 2848 * continue looping. 2849 */ 2850 AHCI_SSTATUS_SET_DET(port_sstatus, 2851 AHCI_SSTATUS_DET_NODEV_NOPHY); 2852 } 2853 2854 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 2855 /* 2856 * We are effectively timing out after 0.1 sec. 2857 */ 2858 break; 2859 } 2860 2861 /* Wait for 10 millisec */ 2862#ifndef __lock_lint 2863 delay(AHCI_10MS_TICKS); 2864#endif /* __lock_lint */ 2865 2866 } while (AHCI_SSTATUS_GET_DET(port_sstatus) != 2867 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE); 2868 2869 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 2870 "ahci_port_reset: 1st loop count: %d, " 2871 "port_sstatus = 0x%x port %d", 2872 loop_count, port_sstatus, port); 2873 2874 if ((AHCI_SSTATUS_GET_IPM(port_sstatus) != 2875 AHCI_SSTATUS_IPM_INTERFACE_ACTIVE) || 2876 (AHCI_SSTATUS_GET_DET(port_sstatus) != 2877 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2878 /* 2879 * Either the port is not active or there 2880 * is no device present. 2881 */ 2882 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 2883 goto out; 2884 } 2885 2886 /* Now we can make sure there is a device connected to the port */ 2887 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2888 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 2889 2890 /* a COMINIT signal is supposed to be received */ 2891 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 2892 cmn_err(CE_WARN, "ahci_port_reset: port %d COMINIT signal " 2893 "from the device not received", port); 2894 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 2895 rval = AHCI_FAILURE; 2896 goto out; 2897 } 2898 2899 /* PxTFD.STS.BSY is supposed to be set */ 2900 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2901 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2902 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 2903 cmn_err(CE_WARN, "ahci_port_reset: port %d BSY bit " 2904 "is not set after COMINIT signal is received", port); 2905 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 2906 rval = AHCI_FAILURE; 2907 goto out; 2908 } 2909 2910 /* 2911 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 2912 * the D2H FIS received by HBA. 2913 */ 2914 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2915 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 2916 AHCI_SERROR_DIAG_X); 2917 2918 /* 2919 * Next check whether COMRESET is completed successfully 2920 */ 2921 loop_count = 0; 2922 do { 2923 port_task_file = 2924 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2925 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2926 2927 /* 2928 * The Error bit '1' means COMRESET is finished successfully 2929 * The device hardware has been initialized and the power-up 2930 * diagnostics successfully completed. 2931 */ 2932 if (((port_task_file & AHCI_TFD_ERR_MASK) 2933 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 2934 2935 port_signature = ddi_get32( 2936 ahci_ctlp->ahcictl_ahci_acc_handle, 2937 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 2938 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 2939 "COMRESET success, D2H register FIS " 2940 "post to received FIS structure " 2941 "port %d signature = 0x%x", 2942 port, port_signature); 2943 goto out_check; 2944 } 2945 2946 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 2947 /* 2948 * We are effectively timing out after 11 sec. 2949 */ 2950 break; 2951 } 2952 2953 /* Wait for 10 millisec */ 2954#ifndef __lock_lint 2955 delay(AHCI_10MS_TICKS); 2956#endif /* __lock_lint */ 2957 2958 } while (((port_task_file & AHCI_TFD_ERR_MASK) 2959 >> AHCI_TFD_ERR_SHIFT) != 0x1); 2960 2961 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 2962 "count: %d, port_task_file = 0x%x port %d", 2963 loop_count, port_task_file, port); 2964 2965 cmn_err(CE_WARN, "ahci_port_reset: port %d the device hardware " 2966 "has been initialized and the power-up diagnostics failed", 2967 port); 2968 2969 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 2970 rval = AHCI_FAILURE; 2971 2972out: 2973 /* Clear port serror register for the port */ 2974 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2975 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 2976 AHCI_SERROR_CLEAR_ALL); 2977 2978 return (rval); 2979 2980out_check: 2981 /* 2982 * Check device status, if keep busy or COMRESET error 2983 * do device reset to patch some SATA disks' issue 2984 * 2985 * For VT8251, sometimes need to do the device reset 2986 */ 2987 if ((port_task_file & AHCI_TFD_STS_BSY) || 2988 (port_task_file & AHCI_TFD_STS_DRQ)) { 2989 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 2990 "need to do device reset", port); 2991 2992 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 2993 2994 port_task_file = 2995 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2996 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2997 2998 if (port_task_file & AHCI_TFD_STS_BSY || 2999 port_task_file & AHCI_TFD_STS_DRQ) { 3000 cmn_err(CE_WARN, "ahci_port_reset: port %d " 3001 "BSY/DRQ still set after device reset " 3002 "port_task_file = 0x%x", 3003 port, port_task_file); 3004 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3005 rval = AHCI_FAILURE; 3006 } 3007 } 3008 3009 goto out; 3010} 3011 3012/* 3013 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3014 * This is the most intrusive. 3015 * 3016 * When an HBA reset occurs, Phy communication will be re-established with 3017 * the device through a COMRESET followed by the normal out-of-band 3018 * communication sequence defined in Serial ATA. AT the end of reset, the 3019 * device, if working properly, will send a D2H Register FIS, which contains 3020 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3021 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3022 * signature. 3023 * 3024 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3025 */ 3026static int 3027ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3028{ 3029 ahci_port_t *ahci_portp; 3030 uint32_t ghc_control; 3031 uint8_t port; 3032 int loop_count; 3033 int rval = AHCI_SUCCESS; 3034 3035 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3036 3037 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3038 3039 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3040 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3041 3042 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3043 ghc_control |= AHCI_HBA_GHC_HR; 3044 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3045 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3046 3047 /* 3048 * Wait until HBA Reset complete or timeout 3049 */ 3050 loop_count = 0; 3051 do { 3052 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3053 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3054 3055 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3056 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3057 "ahci hba reset is timing out, " 3058 "ghc_control = 0x%x", ghc_control); 3059 /* We are effectively timing out after 1 sec. */ 3060 break; 3061 } 3062 3063 /* Wait for 10 millisec */ 3064#ifndef __lock_lint 3065 delay(AHCI_10MS_TICKS); 3066#endif /* __lock_lint */ 3067 3068 } while (ghc_control & AHCI_HBA_GHC_HR); 3069 3070 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3071 "ahci_hba_reset: 1st loop count: %d, " 3072 "ghc_control = 0x%x", loop_count, ghc_control); 3073 3074 if (ghc_control & AHCI_HBA_GHC_HR) { 3075 /* The hba is not reset for some reasons */ 3076 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3077 "hba reset failed: HBA in a hung or locked state"); 3078 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3079 return (AHCI_FAILURE); 3080 } 3081 3082 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3083 /* Only check implemented ports */ 3084 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3085 continue; 3086 } 3087 3088 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3089 mutex_enter(&ahci_portp->ahciport_mutex); 3090 3091 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3092 != AHCI_SUCCESS) { 3093 rval = AHCI_FAILURE; 3094 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3095 "ahci_hba_reset: port %d failed", port); 3096 } 3097 3098 mutex_exit(&ahci_portp->ahciport_mutex); 3099 } 3100 3101 /* 3102 * Indicate that system software is AHCI aware by setting 3103 * GHC.AE to 1 3104 */ 3105 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3106 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3107 3108 ghc_control |= AHCI_HBA_GHC_AE; 3109 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3110 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3111 3112 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3113 3114 return (rval); 3115} 3116 3117/* 3118 * This routine is only called from AHCI_ATTACH or phyrdy change 3119 * case. It first calls port reset to initialize port, probe port and probe 3120 * device, then try to read PxSIG register to find the type of device 3121 * attached to the port. 3122 * 3123 * WARNING!!! ahciport_mutex should be acquired before the function 3124 * is called. And the port interrupt is disabled. 3125 */ 3126static void 3127ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3128 ahci_port_t *ahci_portp, uint8_t port) 3129{ 3130 uint32_t signature; 3131 3132 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3133 "ahci_find_dev_signature enter: port %d", port); 3134 3135 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3136 3137 /* Call port reset to check link status and get device signature */ 3138 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3139 3140 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3141 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3142 "ahci_find_dev_signature: No device is found " 3143 "at port %d", port); 3144 return; 3145 } 3146 3147 /* Check the port state */ 3148 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3149 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3150 "ahci_find_dev_signature: port %d state 0x%x", 3151 port, ahci_portp->ahciport_port_state); 3152 return; 3153 } 3154 3155 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3156 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3157 3158 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3159 "ahci_find_dev_signature: port %d signature = 0x%x", 3160 port, signature); 3161 3162 switch (signature) { 3163 3164 case AHCI_SIGNATURE_DISK: 3165 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3166 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3167 "Disk is found at port: %d", port); 3168 break; 3169 3170 case AHCI_SIGNATURE_ATAPI: 3171 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3172 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3173 "ATAPI device is found at port: %d", port); 3174 break; 3175 3176 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3177 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3178 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3179 "Port Multiplier is found at port: %d", port); 3180 break; 3181 3182 default: 3183 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3184 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3185 "Unknown device is found at port: %d", port); 3186 } 3187} 3188 3189/* 3190 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3191 * to 1, then set it firstly. 3192 * 3193 * Each port contains two major DMA engines. One DMA engine walks through 3194 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3195 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3196 * 3197 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3198 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3199 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3200 * 3201 * Software shall not set PxCMD.ST to '1' unless a functional device is 3202 * present on the port(as determined by PxTFD.STS.BSY = '0', 3203 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3204 * 3205 * WARNING!!! ahciport_mutex should be acquired before the function 3206 * is called. 3207 */ 3208static int 3209ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3210{ 3211 uint32_t port_cmd_status; 3212 3213 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3214 3215 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3216 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3217 "the state for port %d is 0x%x", 3218 port, ahci_portp->ahciport_port_state); 3219 return (AHCI_FAILURE); 3220 } 3221 3222 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3223 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3224 "no device is attached at port %d", port); 3225 return (AHCI_FAILURE); 3226 } 3227 3228 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3229 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3230 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3231 3232 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3233 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3234 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3235 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3236 port_cmd_status); 3237 } 3238 3239 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3240 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3241 3242 port_cmd_status |= AHCI_CMD_STATUS_ST; 3243 3244 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3245 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3246 port_cmd_status); 3247 3248 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3249 3250 return (AHCI_SUCCESS); 3251} 3252 3253/* 3254 * Allocate the ahci_port_t including Received FIS and Command List. 3255 * The argument - port is the physical port number, and not logical 3256 * port number seen by the SATA framework. 3257 * 3258 * WARNING!!! ahcictl_mutex should be acquired before the function 3259 * is called. 3260 */ 3261static int 3262ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3263{ 3264 ahci_port_t *ahci_portp; 3265 3266 ahci_portp = 3267 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3268 3269#ifndef __lock_lint 3270 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3271#endif /* __lock_lint */ 3272 3273 ahci_portp->ahciport_port_num = port; 3274 3275 /* Intialize the port condition variable */ 3276 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3277 3278 /* Initialize the port mutex */ 3279 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3280 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3281 3282 mutex_enter(&ahci_portp->ahciport_mutex); 3283 3284 /* 3285 * Allocate memory for received FIS structure and 3286 * command list for this port 3287 */ 3288 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3289 goto err_case1; 3290 } 3291 3292 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3293 goto err_case2; 3294 } 3295 3296 ahci_portp->ahciport_event_args = 3297 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3298 3299 if (ahci_portp->ahciport_event_args == NULL) 3300 goto err_case3; 3301 3302 mutex_exit(&ahci_portp->ahciport_mutex); 3303 3304 return (AHCI_SUCCESS); 3305 3306err_case3: 3307 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3308 3309err_case2: 3310 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3311 3312err_case1: 3313 mutex_exit(&ahci_portp->ahciport_mutex); 3314 mutex_destroy(&ahci_portp->ahciport_mutex); 3315 cv_destroy(&ahci_portp->ahciport_cv); 3316 3317 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3318 3319 return (AHCI_FAILURE); 3320} 3321 3322/* 3323 * Reverse of ahci_dealloc_port_state(). 3324 * 3325 * WARNING!!! ahcictl_mutex should be acquired before the function 3326 * is called. 3327 */ 3328static void 3329ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3330{ 3331 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3332 3333 ASSERT(ahci_portp != NULL); 3334 3335 mutex_enter(&ahci_portp->ahciport_mutex); 3336 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3337 ahci_portp->ahciport_event_args = NULL; 3338 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3339 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3340 mutex_exit(&ahci_portp->ahciport_mutex); 3341 3342 mutex_destroy(&ahci_portp->ahciport_mutex); 3343 cv_destroy(&ahci_portp->ahciport_cv); 3344 3345 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3346 3347#ifndef __lock_lint 3348 ahci_ctlp->ahcictl_ports[port] = NULL; 3349#endif /* __lock_lint */ 3350} 3351 3352/* 3353 * Allocates memory for the Received FIS Structure 3354 * 3355 * WARNING!!! ahciport_mutex should be acquired before the function 3356 * is called. 3357 */ 3358static int 3359ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3360 uint8_t port) 3361{ 3362 size_t rcvd_fis_size; 3363 size_t ret_len; 3364 ddi_dma_cookie_t rcvd_fis_dma_cookie; 3365 uint_t cookie_count; 3366 uint32_t cap_status; 3367 3368 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3369 3370 /* Check whether the HBA can access 64-bit data structures */ 3371 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3372 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3373 3374 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 3375 3376 /* 3377 * If 64-bit addressing is not supported, 3378 * change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr 3379 */ 3380 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3381 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3382 "hba does not support 64-bit addressing"); 3383 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 3384 0xffffffffull; 3385 } 3386 3387 /* allocate rcvd FIS dma handle. */ 3388 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3389 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3390 DDI_DMA_SLEEP, 3391 NULL, 3392 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3393 DDI_SUCCESS) { 3394 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3395 "rcvd FIS dma handle alloc failed"); 3396 3397 return (AHCI_FAILURE); 3398 } 3399 3400 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3401 rcvd_fis_size, 3402 &accattr, 3403 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3404 DDI_DMA_SLEEP, 3405 NULL, 3406 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3407 &ret_len, 3408 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3409 3410 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3411 "rcvd FIS dma mem alloc fail"); 3412 /* error.. free the dma handle. */ 3413 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3414 return (AHCI_FAILURE); 3415 } 3416 3417 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3418 NULL, 3419 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3420 rcvd_fis_size, 3421 DDI_DMA_CONSISTENT, 3422 DDI_DMA_SLEEP, 3423 NULL, 3424 &rcvd_fis_dma_cookie, 3425 &cookie_count) != DDI_DMA_MAPPED) { 3426 3427 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3428 "rcvd FIS dma handle bind fail"); 3429 /* error.. free the dma handle & free the memory. */ 3430 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3431 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3432 return (AHCI_FAILURE); 3433 } 3434 3435 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3436 3437 /* Config Port Received FIS Base Address */ 3438 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3439 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3440 rcvd_fis_dma_cookie.dmac_laddress); 3441 3442 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3443 rcvd_fis_dma_cookie.dmac_laddress); 3444 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3445 rcvd_fis_dma_cookie.dmac_address); 3446 3447 return (AHCI_SUCCESS); 3448} 3449 3450/* 3451 * Deallocates the Received FIS Structure 3452 * 3453 * WARNING!!! ahciport_mutex should be acquired before the function 3454 * is called. 3455 */ 3456static void 3457ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3458{ 3459 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3460 "ahci_dealloc_rcvd_fis: port %d enter", 3461 ahci_portp->ahciport_port_num); 3462 3463 /* Unbind the cmd list dma handle first. */ 3464 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 3465 3466 /* Then free the underlying memory. */ 3467 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3468 3469 /* Now free the handle itself. */ 3470 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3471} 3472 3473/* 3474 * Allocates memory for the Command List, which contains up to 32 entries. 3475 * Each entry contains a command header, which is a 32-byte structure that 3476 * includes the pointer to the command table. 3477 * 3478 * WARNING!!! ahciport_mutex should be acquired before the function 3479 * is called. 3480 */ 3481static int 3482ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3483 uint8_t port) 3484{ 3485 size_t cmd_list_size; 3486 size_t ret_len; 3487 ddi_dma_cookie_t cmd_list_dma_cookie; 3488 uint_t cookie_count; 3489 uint32_t cap_status; 3490 3491 cmd_list_size = 3492 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 3493 3494 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3495 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3496 3497 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 3498 3499 /* 3500 * If 64-bit addressing is not supported, 3501 * change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr 3502 */ 3503 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3504 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3505 "hba does not support 64-bit addressing"); 3506 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 3507 0xffffffffull; 3508 } 3509 3510 /* allocate cmd list dma handle. */ 3511 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3512 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 3513 DDI_DMA_SLEEP, 3514 NULL, 3515 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 3516 3517 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3518 "cmd list dma handle alloc failed"); 3519 return (AHCI_FAILURE); 3520 } 3521 3522 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 3523 cmd_list_size, 3524 &accattr, 3525 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3526 DDI_DMA_SLEEP, 3527 NULL, 3528 (caddr_t *)&ahci_portp->ahciport_cmd_list, 3529 &ret_len, 3530 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 3531 3532 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3533 "cmd list dma mem alloc fail"); 3534 /* error.. free the dma handle. */ 3535 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3536 return (AHCI_FAILURE); 3537 } 3538 3539 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 3540 NULL, 3541 (caddr_t)ahci_portp->ahciport_cmd_list, 3542 cmd_list_size, 3543 DDI_DMA_CONSISTENT, 3544 DDI_DMA_SLEEP, 3545 NULL, 3546 &cmd_list_dma_cookie, 3547 &cookie_count) != DDI_DMA_MAPPED) { 3548 3549 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3550 "cmd list dma handle bind fail"); 3551 /* error.. free the dma handle & free the memory. */ 3552 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3553 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3554 return (AHCI_FAILURE); 3555 } 3556 3557 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 3558 3559 /* Config Port Command List Base Address */ 3560 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3561 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 3562 cmd_list_dma_cookie.dmac_laddress); 3563 3564 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3565 cmd_list_dma_cookie.dmac_laddress); 3566 3567 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3568 cmd_list_dma_cookie.dmac_address); 3569 3570 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 3571 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3572 return (AHCI_FAILURE); 3573 } 3574 3575 return (AHCI_SUCCESS); 3576} 3577 3578/* 3579 * Deallocates the Command List 3580 * 3581 * WARNING!!! ahciport_mutex should be acquired before the function 3582 * is called. 3583 */ 3584static void 3585ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3586{ 3587 /* First dealloc command table */ 3588 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 3589 3590 /* Unbind the cmd list dma handle first. */ 3591 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 3592 3593 /* Then free the underlying memory. */ 3594 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3595 3596 /* Now free the handle itself. */ 3597 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3598} 3599 3600/* 3601 * Allocates memory for all Command Tables, which contains Command FIS, 3602 * ATAPI Command and Physical Region Descriptor Table. 3603 * 3604 * WARNING!!! ahciport_mutex should be acquired before the function 3605 * is called. 3606 */ 3607static int 3608ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3609{ 3610 size_t ret_len; 3611 ddi_dma_cookie_t cmd_table_dma_cookie; 3612 uint_t cookie_count; 3613 uint32_t cap_status; 3614 int slot; 3615 3616 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3617 "ahci_alloc_cmd_tables: port %d enter", 3618 ahci_portp->ahciport_port_num); 3619 3620 /* Check whether the HBA can access 64-bit data structures */ 3621 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3622 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3623 3624 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 3625 3626 /* 3627 * If 64-bit addressing is not supported, 3628 * change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr 3629 */ 3630 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3631 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3632 "hba does not support 64-bit addressing"); 3633 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 3634 0xffffffffull; 3635 } 3636 3637 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3638 /* Allocate cmd table dma handle. */ 3639 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3640 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 3641 DDI_DMA_SLEEP, 3642 NULL, 3643 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 3644 DDI_SUCCESS) { 3645 3646 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3647 "cmd table dma handle alloc failed"); 3648 3649 goto err_out; 3650 } 3651 3652 if (ddi_dma_mem_alloc( 3653 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3654 ahci_cmd_table_size, 3655 &accattr, 3656 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3657 DDI_DMA_SLEEP, 3658 NULL, 3659 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 3660 &ret_len, 3661 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 3662 NULL) { 3663 3664 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3665 "cmd table dma mem alloc fail"); 3666 3667 /* error.. free the dma handle. */ 3668 ddi_dma_free_handle( 3669 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3670 goto err_out; 3671 } 3672 3673 if (ddi_dma_addr_bind_handle( 3674 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3675 NULL, 3676 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 3677 ahci_cmd_table_size, 3678 DDI_DMA_CONSISTENT, 3679 DDI_DMA_SLEEP, 3680 NULL, 3681 &cmd_table_dma_cookie, 3682 &cookie_count) != DDI_DMA_MAPPED) { 3683 3684 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3685 "cmd table dma handle bind fail"); 3686 /* error.. free the dma handle & free the memory. */ 3687 ddi_dma_mem_free( 3688 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3689 ddi_dma_free_handle( 3690 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3691 goto err_out; 3692 } 3693 3694 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 3695 ahci_cmd_table_size); 3696 3697 /* Config Port Command Table Base Address */ 3698 SET_COMMAND_TABLE_BASE_ADDR( 3699 (&ahci_portp->ahciport_cmd_list[slot]), 3700 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 3701 3702#ifndef __lock_lint 3703 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 3704 (&ahci_portp->ahciport_cmd_list[slot]), 3705 cmd_table_dma_cookie.dmac_laddress >> 32); 3706#endif /* __lock_lint */ 3707 } 3708 3709 return (AHCI_SUCCESS); 3710err_out: 3711 3712 for (slot--; slot >= 0; slot--) { 3713 /* Unbind the cmd table dma handle first */ 3714 (void) ddi_dma_unbind_handle( 3715 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3716 3717 /* Then free the underlying memory */ 3718 ddi_dma_mem_free( 3719 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3720 3721 /* Now free the handle itself */ 3722 ddi_dma_free_handle( 3723 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3724 } 3725 3726 return (AHCI_FAILURE); 3727} 3728 3729/* 3730 * Deallocates memory for all Command Tables. 3731 * 3732 * WARNING!!! ahciport_mutex should be acquired before the function 3733 * is called. 3734 */ 3735static void 3736ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3737{ 3738 int slot; 3739 3740 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3741 "ahci_dealloc_cmd_tables: %d enter", 3742 ahci_portp->ahciport_port_num); 3743 3744 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3745 /* Unbind the cmd table dma handle first. */ 3746 (void) ddi_dma_unbind_handle( 3747 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3748 3749 /* Then free the underlying memory. */ 3750 ddi_dma_mem_free( 3751 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3752 3753 /* Now free the handle itself. */ 3754 ddi_dma_free_handle( 3755 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3756 } 3757} 3758 3759/* 3760 * WARNING!!! ahciport_mutex should be acquired before the function 3761 * is called. 3762 */ 3763static void 3764ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 3765 sata_device_t *sd) 3766{ 3767 sd->satadev_scr.sstatus = 3768 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3769 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 3770 sd->satadev_scr.serror = 3771 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3772 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 3773 sd->satadev_scr.scontrol = 3774 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3775 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 3776 sd->satadev_scr.sactive = 3777 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3778 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 3779} 3780 3781/* 3782 * For poll mode, ahci_port_intr will be called to emulate the interrupt 3783 * 3784 * retrieve_errinfo_slot_status keeps the slot number of REQUEST SENSE command 3785 * which is sent down to get sense data for a failed PACKET command. 3786 */ 3787static void 3788ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3789 uint8_t port, uint32_t retrieve_errinfo_slot_status) 3790{ 3791 uint32_t port_intr_status; 3792 uint32_t port_intr_enable; 3793 3794 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3795 "ahci_port_intr enter: port %d", port); 3796 3797 mutex_enter(&ahci_portp->ahciport_mutex); 3798 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 3799 /* For SATA_OPMODE_POLLING commands */ 3800 port_intr_enable = 3801 (AHCI_INTR_STATUS_DHRS | 3802 AHCI_INTR_STATUS_PSS | 3803 AHCI_INTR_STATUS_SDBS | 3804 AHCI_INTR_STATUS_UFS | 3805 AHCI_INTR_STATUS_PCS | 3806 AHCI_INTR_STATUS_PRCS | 3807 AHCI_INTR_STATUS_OFS | 3808 AHCI_INTR_STATUS_INFS | 3809 AHCI_INTR_STATUS_IFS | 3810 AHCI_INTR_STATUS_HBDS | 3811 AHCI_INTR_STATUS_HBFS | 3812 AHCI_INTR_STATUS_TFES); 3813 mutex_exit(&ahci_portp->ahciport_mutex); 3814 goto next; 3815 } 3816 mutex_exit(&ahci_portp->ahciport_mutex); 3817 3818 /* 3819 * port_intr_enable indicates that the corresponding interrrupt 3820 * reporting is enabled. 3821 */ 3822 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3823 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 3824next: 3825 /* 3826 * port_intr_stats indicates that the corresponding interrupt 3827 * condition is active. 3828 */ 3829 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3830 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3831 3832 AHCIDBG4(AHCIDBG_INTR, ahci_ctlp, 3833 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 3834 "port_intr_enable = 0x%x, retrieve_errinfo_slot_status = 0x%x", 3835 port, port_intr_status, port_intr_enable, 3836 retrieve_errinfo_slot_status); 3837 3838 port_intr_status &= port_intr_enable; 3839 3840 /* First clear the port interrupts status */ 3841 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3842 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 3843 port_intr_status); 3844 3845 /* Check the completed commands */ 3846 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 3847 AHCI_INTR_STATUS_PSS)) { 3848 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 3849 ahci_portp, port, port_intr_status, 3850 retrieve_errinfo_slot_status); 3851 } 3852 3853 /* Check the asynchronous notification */ 3854 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 3855 (void) ahci_intr_set_device_bits(ahci_ctlp, 3856 ahci_portp, port); 3857 } 3858 3859 /* Check the port connect change status interrupt bit */ 3860 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 3861 (void) ahci_intr_port_connect_change(ahci_ctlp, 3862 ahci_portp, port); 3863 } 3864 3865 /* Check the device mechanical presence status interrupt bit */ 3866 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 3867 (void) ahci_intr_device_mechanical_presence_status( 3868 ahci_ctlp, ahci_portp, port); 3869 } 3870 3871 /* Check the PhyRdy change status interrupt bit */ 3872 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 3873 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 3874 port); 3875 } 3876 3877 /* 3878 * Check the non-fatal error interrupt bits, there are three 3879 * kinds of non-fatal errors at the time being: 3880 * 3881 * PxIS.UFS - Unknown FIS Error 3882 * PxIS.OFS - Overflow Error 3883 * PxIS.INFS - Interface Non-Fatal Error 3884 * 3885 * For these non-fatal errors, the HBA can continue to operate, 3886 * so the driver just log the error messages. 3887 */ 3888 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 3889 AHCI_INTR_STATUS_OFS | 3890 AHCI_INTR_STATUS_INFS)) { 3891 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 3892 port, port_intr_status); 3893 } 3894 3895 /* 3896 * Check the fatal error interrupt bits, there are four kinds 3897 * of fatal errors for AHCI controllers: 3898 * 3899 * PxIS.HBFS - Host Bus Fatal Error 3900 * PxIS.HBDS - Host Bus Data Error 3901 * PxIS.IFS - Interface Fatal Error 3902 * PxIS.TFES - Task File Error 3903 * 3904 * The fatal error means the HBA can not recover from it by 3905 * itself, and it will try to abort the transfer, and the software 3906 * must intervene to restart the port. 3907 */ 3908 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 3909 AHCI_INTR_STATUS_HBDS | 3910 AHCI_INTR_STATUS_HBFS | 3911 AHCI_INTR_STATUS_TFES)) 3912 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 3913 port, port_intr_status, retrieve_errinfo_slot_status); 3914 3915 /* Check the cold port detect interrupt bit */ 3916 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 3917 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 3918 } 3919 3920 /* Second clear the corresponding bit in IS.IPS */ 3921 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3922 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 3923} 3924 3925/* 3926 * Interrupt service handler 3927 */ 3928/* ARGSUSED1 */ 3929static uint_t 3930ahci_intr(caddr_t arg1, caddr_t arg2) 3931{ 3932 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 3933 ahci_port_t *ahci_portp; 3934 int32_t global_intr_status; 3935 uint8_t port; 3936 3937 /* 3938 * global_intr_status indicates that the corresponding port has 3939 * an interrupt pending. 3940 */ 3941 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3942 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 3943 3944 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 3945 /* The interrupt is not ours */ 3946 return (DDI_INTR_UNCLAIMED); 3947 } 3948 3949 /* Loop for all the ports */ 3950 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3951 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3952 continue; 3953 } 3954 if (!((0x1 << port) & global_intr_status)) { 3955 continue; 3956 } 3957 3958 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3959 3960 /* Call ahci_port_intr */ 3961 ahci_port_intr(ahci_ctlp, ahci_portp, port, 0); 3962 } 3963 3964 return (DDI_INTR_CLAIMED); 3965} 3966 3967/* 3968 * For non-queued commands, when the corresponding bit in the PxCI register 3969 * is cleared, it means the command is completed successfully. And according 3970 * to the HBA state machine, there are three conditions which possibly will 3971 * try to clear the PxCI register bit. 3972 * 1. Receive one D2H Register FIS which is with 'I' bit set 3973 * 2. Update PIO Setup FIS 3974 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 3975 * 3976 * Process completed commands including non-queued commands when the 3977 * interrupt status bit - AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS 3978 * is set, and queued commands when the interrupt bit - 3979 * AHCI_INTR_STATUS_SDBS is set. Currently, the driver doesn't support 3980 * queued commands yet. 3981 * 3982 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 3983 * with the 'I' bit set. And the following commands will send thus 3984 * FIS with 'I' bit set upon the successful completion: 3985 * 1. Non-data commands 3986 * 2. DMA data-in command 3987 * 3. DMA data-out command 3988 * 4. PIO data-out command 3989 * 5. PACKET non-data commands 3990 * 6. PACKET PIO data-in command 3991 * 7. PACKET PIO data-out command 3992 * 8. PACKET DMA data-in command 3993 * 9. PACKET DMA data-out command 3994 * 3995 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 3996 * with the 'I' bit set. And the following commands will send this 3997 * FIS upon the successful completion: 3998 * 1. PIO data-in command 3999 */ 4000static int 4001ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4002 uint8_t port, uint32_t intr_status, uint32_t retrieve_errinfo_slot_status) 4003{ 4004 uint32_t port_cmd_issue = 0; 4005 uint32_t finished_tags; 4006 int finished_slot; 4007 sata_pkt_t *satapkt; 4008 ahci_fis_d2h_register_t *rcvd_fisp; 4009 4010 if (intr_status & AHCI_INTR_STATUS_DHRS) 4011 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4012 "ahci_intr_cmd_cmplt enter: port %d " 4013 "a d2h register fis is received", port); 4014 4015 if (intr_status & AHCI_INTR_STATUS_PSS) 4016 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4017 "ahci_intr_cmd_cmplt enter: port %d " 4018 "a pio setup fis is received", port); 4019 4020 mutex_enter(&ahci_portp->ahciport_mutex); 4021 if (!ahci_portp->ahciport_pending_tags) { 4022 /* 4023 * Spurious interrupt. Nothing to be done. 4024 */ 4025 mutex_exit(&ahci_portp->ahciport_mutex); 4026 return (AHCI_SUCCESS); 4027 } 4028 4029 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4030 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4031 4032 /* 4033 * When AHCI_PORT_FLAG_RQSENSE is set, the port is doing error recovery, 4034 * and REQUEST SENSE for sense data retrieval is sent down to get the 4035 * sense data. At this time, the only pending command is REQUESR SENSE, 4036 * and retrieve_errinfo_slot_status contains the slot number of it. 4037 */ 4038 if (retrieve_errinfo_slot_status != 0) { 4039 ASSERT(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RQSENSE); 4040 finished_tags = ahci_portp->ahciport_pending_tags & 4041 retrieve_errinfo_slot_status & 4042 ~port_cmd_issue & 4043 AHCI_SLOT_MASK(ahci_ctlp); 4044 } else { 4045 finished_tags = ahci_portp->ahciport_pending_tags & 4046 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4047 } 4048 4049 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4050 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, port_cmd_issue = 0x%x " 4051 "retrieve_errinfo_slot_status = 0x%x", 4052 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4053 retrieve_errinfo_slot_status); 4054 4055 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4056 "ahci_intr_cmd_cmplt: finished_tags = 0x%x", finished_tags); 4057 4058 while (finished_tags) { 4059 finished_slot = ddi_ffs(finished_tags) - 1; 4060 if (finished_slot == -1) { 4061 goto out; 4062 } 4063 4064 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4065 ASSERT(satapkt != NULL); 4066 4067 /* 4068 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4069 * feature, sata_special_regs flag will be set, and the 4070 * driver should copy the status and the other corresponding 4071 * register values in the D2H Register FIS received (It's 4072 * working on Non-data protocol) from the device back to 4073 * the sata_cmd. 4074 * 4075 * For every AHCI port, there is only one Received FIS 4076 * structure, which contains the FISes received from the 4077 * device, So we're trying to copy the content of D2H 4078 * Register FIS in the Received FIS structure back to 4079 * the sata_cmd. 4080 */ 4081 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4082 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4083 ahcirf_d2h_register_fis); 4084 satapkt->satapkt_cmd.satacmd_status_reg = 4085 GET_RFIS_STATUS(rcvd_fisp); 4086 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4087 } 4088 4089 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4090 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4091 "with SATA_PKT_COMPLETED", (void *)satapkt); 4092 4093 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4094 CLEAR_BIT(finished_tags, finished_slot); 4095 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4096 4097 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4098 } 4099out: 4100 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4101 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4102 ahci_portp->ahciport_pending_tags); 4103 4104 mutex_exit(&ahci_portp->ahciport_mutex); 4105 4106 return (AHCI_SUCCESS); 4107} 4108 4109/* 4110 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4111 * with the 'I' bit set and has been copied into system memory. 4112 * 4113 * Asynchronous Notification is a feature in SATA II, which allows an 4114 * ATAPI device to send a signal to the host when media is inserted or 4115 * removed and avoids polling the device for media changes. The signal 4116 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4117 * set to '1'. 4118 */ 4119static int 4120ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4121 ahci_port_t *ahci_portp, uint8_t port) 4122{ 4123 ahci_fis_set_device_bits_t *rcvd_fisp; 4124 4125 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4126 "ahci_intr_set_device_bits enter: port %d", port); 4127 4128 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4129 ahcirf_set_device_bits_fis); 4130 4131 if (GET_N_BIT_OF_SET_DEV_BITS(rcvd_fisp)) { 4132 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4133 "ahci_intr_set_device_bits N bit is set for " 4134 "port %d", port); 4135 } 4136 4137 return (AHCI_SUCCESS); 4138} 4139 4140/* 4141 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4142 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4143 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4144 * indicates a COMINIT signal was received. 4145 * 4146 * Hot plug insertion is detected by reception of a COMINIT signal from the 4147 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4148 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4149 * begin the normal communication negotiation sequence as outlined in the 4150 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4151 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4152 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4153 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4154 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4155 * to handle hot plug insertion. In this interrupt handler, just do nothing 4156 * but print some log message and clear the bit. 4157 */ 4158static int 4159ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4160 ahci_port_t *ahci_portp, uint8_t port) 4161{ 4162 uint32_t port_serror; 4163 4164 mutex_enter(&ahci_portp->ahciport_mutex); 4165 4166 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4167 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4168 4169 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4170 "ahci_intr_port_connect_change: port %d, " 4171 "port_serror = 0x%x", port, port_serror); 4172 4173 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4174 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4175 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4176 AHCI_SERROR_DIAG_X); 4177 4178 mutex_exit(&ahci_portp->ahciport_mutex); 4179 4180 return (AHCI_SUCCESS); 4181} 4182 4183/* 4184 * Hot Plug Operation for platforms that support Mechanical Presence 4185 * Switches. 4186 * 4187 * When set, it indicates that a mechanical presence switch attached to this 4188 * port has been opened or closed, which may lead to a change in the connection 4189 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4190 * are set to '1'. 4191 * 4192 * At the moment, this interrupt is not needed and disabled and we just log 4193 * the debug message. 4194 */ 4195/* ARGSUSED */ 4196static int 4197ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4198 ahci_port_t *ahci_portp, uint8_t port) 4199{ 4200 uint32_t cap_status, port_cmd_status; 4201 4202 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4203 "ahci_intr_device_mechanical_presence_status enter, " 4204 "port %d", port); 4205 4206 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4207 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4208 4209 mutex_enter(&ahci_portp->ahciport_mutex); 4210 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4211 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4212 4213 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4214 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4215 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4216 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4217 "the interrupt: cap_status = 0x%x, " 4218 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4219 mutex_exit(&ahci_portp->ahciport_mutex); 4220 4221 return (AHCI_SUCCESS); 4222 } 4223 4224 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4225 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4226 "The mechanical presence switch is open: " 4227 "port %d, port_cmd_status = 0x%x", 4228 port, port_cmd_status); 4229 } else { 4230 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4231 "The mechanical presence switch is close: " 4232 "port %d, port_cmd_status = 0x%x", 4233 port, port_cmd_status); 4234 } 4235 4236 mutex_exit(&ahci_portp->ahciport_mutex); 4237 4238 return (AHCI_SUCCESS); 4239} 4240 4241/* 4242 * Native Hot Plug Support. 4243 * 4244 * When set, it indicates that the internal PHYRDY signal changed state. 4245 * This bit reflects the state of PxSERR.DIAG.N. 4246 * 4247 * There are three kinds of conditions to generate this interrupt event: 4248 * 1. a device is inserted 4249 * 2. a device is disconnected 4250 * 3. when the link enters/exits a Partial or Slumber interface power 4251 * management state 4252 * 4253 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4254 * bit may be set due to the link entering the Partial or Slumber power 4255 * management state, rather than due to a hot plug insertion or removal 4256 * event. So far, the power management is disabled, so the driver can 4257 * reliably get removal detection notification via the PxSERR.DIAG.N bit. 4258 */ 4259static int 4260ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4261 ahci_port_t *ahci_portp, uint8_t port) 4262{ 4263 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4264 sata_device_t sdevice; 4265 int dev_exists_now = 0; 4266 int dev_existed_previously = 0; 4267 4268 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4269 "ahci_intr_phyrdy_change enter, port %d", port); 4270 4271 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4272 mutex_enter(&ahci_portp->ahciport_mutex); 4273 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4274 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4275 AHCI_SERROR_DIAG_N); 4276 mutex_exit(&ahci_portp->ahciport_mutex); 4277 4278 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4279 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4280 (ahci_portp == NULL)) { 4281 /* The whole controller setup is not yet done. */ 4282 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4283 return (AHCI_SUCCESS); 4284 } 4285 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4286 4287 mutex_enter(&ahci_portp->ahciport_mutex); 4288 4289 /* SStatus tells the presence of device. */ 4290 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4291 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4292 4293 if (AHCI_SSTATUS_GET_DET(port_sstatus) == 4294 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE) { 4295 dev_exists_now = 1; 4296 } 4297 4298 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4299 dev_existed_previously = 1; 4300 } 4301 4302 bzero((void *)&sdevice, sizeof (sata_device_t)); 4303 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4304 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4305 sdevice.satadev_addr.pmport = 0; 4306 sdevice.satadev_state = SATA_PSTATE_PWRON; 4307 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4308 4309 if (dev_exists_now) { 4310 if (dev_existed_previously) { 4311 /* Things are fine now. The loss was temporary. */ 4312 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4313 "ahci_intr_phyrdy_change port %d " 4314 "device link lost/established", port); 4315 4316 mutex_exit(&ahci_portp->ahciport_mutex); 4317 sata_hba_event_notify( 4318 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4319 &sdevice, 4320 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4321 mutex_enter(&ahci_portp->ahciport_mutex); 4322 4323 } else { 4324 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4325 "ahci_intr_phyrdy_change: port %d " 4326 "device link established", port); 4327 4328 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 4329 4330 /* A new device has been detected. */ 4331 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4332 4333 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 4334 4335 /* Try to start the port */ 4336 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4337 != AHCI_SUCCESS) { 4338 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4339 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4340 "ahci_intr_phyrdy_change: port %d failed " 4341 "at start port", port); 4342 } 4343 4344 mutex_exit(&ahci_portp->ahciport_mutex); 4345 sata_hba_event_notify( 4346 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4347 &sdevice, 4348 SATA_EVNT_LINK_ESTABLISHED); 4349 mutex_enter(&ahci_portp->ahciport_mutex); 4350 4351 } 4352 } else { /* No device exists now */ 4353 4354 if (dev_existed_previously) { 4355 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4356 "ahci_intr_phyrdy_change: port %d " 4357 "device link lost", port); 4358 4359 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4360 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 4361 ahci_portp, port); 4362 4363 /* An existing device is lost. */ 4364 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4365 4366 mutex_exit(&ahci_portp->ahciport_mutex); 4367 sata_hba_event_notify( 4368 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4369 &sdevice, 4370 SATA_EVNT_LINK_LOST); 4371 mutex_enter(&ahci_portp->ahciport_mutex); 4372 4373 } else { 4374 4375 /* Spurious interrupt */ 4376 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 4377 "ahci_intr_phyrdy_change: " 4378 "spurious phy ready interrupt"); 4379 } 4380 } 4381 4382 mutex_exit(&ahci_portp->ahciport_mutex); 4383 4384 return (AHCI_SUCCESS); 4385} 4386 4387/* 4388 * PxIS.UFS - Unknown FIS Error 4389 * 4390 * This interrupt event means an unknown FIS was received and has been 4391 * copied into system memory. An unknown FIS is not considered an illegal 4392 * FIS, unless the length received is more than 64 bytes. If an unknown 4393 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 4394 * normal operation. If the unknown FIS is more than 64 bytes, then it 4395 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 4396 * a fatal error. 4397 * 4398 * PxIS.OFS - Overflow Error 4399 * 4400 * Command list overflow is defined as software building a command table 4401 * that has fewer total bytes than the transaction given to the device. 4402 * On device writes, the HBA will run out of data, and on reads, there 4403 * will be no room to put the data. 4404 * 4405 * For an overflow on data read, either PIO or DMA, the HBA will set 4406 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 4407 * non-fatal error when the HBA can continues. Sometimes, it will cause 4408 * a fatal error and need the software to do something. 4409 * 4410 * For an overflow on data write, setting PxIS.OFS is optional for both 4411 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 4412 * software to clean up from this serious error. 4413 * 4414 * PxIS.INFS - Interface Non-Fatal Error 4415 * 4416 * This interrupt event indicates that the HBA encountered an error on 4417 * the Serial ATA interface but was able to continue operation. The kind 4418 * of error usually occurred during a non-Data FIS, and under this condition 4419 * the FIS will be re-transmitted by HBA automatically. 4420 * 4421 * When the FMA is implemented, there should be a stat structure to 4422 * record how many every kind of error happens. 4423 */ 4424static int 4425ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4426 uint8_t port, uint32_t intr_status) 4427{ 4428 uint32_t port_serror; 4429#if AHCI_DEBUG 4430 uint32_t port_cmd_status; 4431 int current_slot; 4432 sata_pkt_t *satapkt; 4433#endif 4434 4435 mutex_enter(&ahci_portp->ahciport_mutex); 4436 4437 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4438 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4439 4440 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 4441 "ahci_intr_non_fatal_error: port %d, " 4442 "port_serror = 0x%x", port, port_serror); 4443 4444 ahci_log_serror_message(ahci_ctlp, port, port_serror); 4445 4446 if (intr_status & AHCI_INTR_STATUS_UFS) { 4447 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4448 "ahci port %d has unknown FIS error", port); 4449 4450 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 4451 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4452 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4453 AHCI_SERROR_DIAG_F); 4454 } 4455 4456#if AHCI_DEBUG 4457 if (intr_status & AHCI_INTR_STATUS_OFS) { 4458 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4459 "ahci port %d has overflow error", port); 4460 } 4461 4462 if (intr_status & AHCI_INTR_STATUS_INFS) { 4463 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4464 "ahci port %d has interface non fatal error", port); 4465 } 4466 4467 /* 4468 * Record the error occurred command's slot. 4469 */ 4470 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4471 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4472 4473 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 4474 AHCI_CMD_STATUS_CCS_SHIFT; 4475 4476 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 4477 if (satapkt != NULL) { 4478 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4479 "ahci_intr_non_fatal_error: pending_tags 0x%x " 4480 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 4481 satapkt->satapkt_cmd.satacmd_cmd_reg); 4482 4483 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4484 "ahci_intr_non_fatal_error: port %d, " 4485 "satapkt 0x%p is being processed when error occurs", 4486 port, (void *)satapkt); 4487 } 4488#endif 4489 mutex_exit(&ahci_portp->ahciport_mutex); 4490 4491 return (AHCI_SUCCESS); 4492} 4493 4494/* 4495 * According to the AHCI spec, the error types include system memory 4496 * errors, interface errors, port multiplier errors, device errors, 4497 * command list overflow, command list underflow, native command 4498 * queuing tag errors and pio data transfer errors. 4499 * 4500 * System memory errors such as target abort, master abort, and parity 4501 * may cause the host to stop, and they are serious errors and needed 4502 * to be recovered with software intervention. When system software 4503 * has given a pointer to the HBA that doesn't exist in physical memory, 4504 * a master/target abort error occurs, and PxIS.HBFS will be set. A 4505 * data error such as CRC or parity occurs, the HBA aborts the transfer 4506 * (if necessary) and PxIS.HBDS will be set. 4507 * 4508 * Interface errors are errors that occur due to electrical issues on 4509 * the interface, or protocol miscommunication between the device and 4510 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 4511 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 4512 * causes PxIS.IFS/PxIS.INFS to be set are 4513 * 1. in PxSERR.ERR, P bit is set to '1' 4514 * 2. in PxSERR.DIAG, C or H bit is set to '1' 4515 * 3. PhyRdy drop unexpectly, N bit is set to '1' 4516 * If the error occurred during a non-data FIS, the FIS must be 4517 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 4518 * the error occurred during a data FIS, the transfer will stop, so 4519 * the error is fatal and PxIS.IFS is set. 4520 * 4521 * When a FIS arrives that updates the taskfile, the HBA checks to see 4522 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 4523 * stops processing any more commands. 4524 * 4525 * Command list overflow is defined as software building a command table 4526 * that has fewer total bytes than the transaction given to the device. 4527 * On device writes, the HBA will run out of data, and on reads, there 4528 * will be no room to put the data. For an overflow on data read, either 4529 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 4530 * For an overflow on data write, setting PxIS.OFS is optional for both 4531 * DMA and PIO, and a COMRESET is required by software to clean up from 4532 * this serious error. 4533 * 4534 * Command list underflow is defined as software building a command 4535 * table that has more total bytes than the transaction given to the 4536 * device. For data writes, both PIO and DMA, the device will detect 4537 * an error and end the transfer. And these errors are most likely going 4538 * to be fatal errors that will cause the port to be restarted. For 4539 * data reads, the HBA updates its PRD byte count, and may be 4540 * able to continue normally, but is not required to. And The HBA is 4541 * not required to detect underflow conditions for native command 4542 * queuing command. 4543 * 4544 * The HBA does not actively check incoming DMA Setup FISes to ensure 4545 * that the PxSACT register bit for that slot is set. Existing error 4546 * mechanisms, such as host bus failure, or bad protocol, are used to 4547 * recover from this case. 4548 * 4549 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 4550 * DATA FIS must be an integral number of Dwords. If the HBA receives 4551 * a request which is not an integral number of Dwords, the HBA 4552 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 4553 * software restarts the port. And the HBA ensures that the size 4554 * of the DATA FIS received during a PIO command matches the size in 4555 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 4556 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 4557 * stop running until software restarts the port. 4558 */ 4559/* 4560 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 4561 * 4562 * PxIS.IFS indicates that the hba encountered an error on the serial ata 4563 * interface which caused the transfer to stop. 4564 * 4565 * PxIS.HBDS indicates that the hba encountered a data error 4566 * (uncorrectable ecc/parity) when reading from or writing to system memory. 4567 * 4568 * PxIS.HBFS indicates that the hba encountered a host bus error that it 4569 * cannot recover from, such as a bad software pointer. 4570 * 4571 * PxIS.TFES is set whenever the status register is updated by the device 4572 * and the error bit (bit 0) is set. 4573 */ 4574static int 4575ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4576 uint8_t port, uint32_t intr_status, uint32_t retrieve_errinfo_slot_status) 4577{ 4578 uint32_t port_cmd_status; 4579 uint32_t port_serror; 4580 uint32_t task_file_status; 4581 int failed_slot; 4582 sata_pkt_t *spkt; 4583 uint8_t err_byte; 4584 ahci_event_arg_t *args; 4585 4586 mutex_enter(&ahci_portp->ahciport_mutex); 4587 4588 /* 4589 * ahci_intr_phyrdy_change() may have rendered it to 4590 * SATA_DTYPE_NONE. 4591 */ 4592 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 4593 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 4594 "ahci_intr_fatal_error: port %d no device attached, " 4595 "and just return without doing anything", port); 4596 goto out0; 4597 } 4598 4599 /* 4600 * Read PxCMD.CCS to determine the slot that the HBA 4601 * was processing when the error occurred. 4602 */ 4603 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4604 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4605 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 4606 AHCI_CMD_STATUS_CCS_SHIFT; 4607 4608 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 4609 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4610 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 4611 "fatal error occurred for port %d", spkt, port); 4612 4613 if (intr_status & AHCI_INTR_STATUS_TFES) { 4614 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4615 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 4616 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4617 "ahci_intr_fatal_error: port %d " 4618 "task_file_status = 0x%x", port, task_file_status); 4619 4620 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 4621 >> AHCI_TFD_ERR_SHIFT; 4622 4623 /* 4624 * Won't emit the error message if it is an IDENTIFY DEVICE 4625 * command sent to an ATAPI device. 4626 */ 4627 if ((spkt != NULL) && 4628 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE) && 4629 (err_byte == SATA_ERROR_ABORT)) 4630 goto out1; 4631 4632 /* 4633 * Won't emit the error message if it is an ATAPI PACKET command 4634 */ 4635 if ((spkt != NULL) && 4636 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 4637 goto out1; 4638 } 4639 4640 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 4641 4642out1: 4643 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4644 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4645 ahci_log_serror_message(ahci_ctlp, port, port_serror); 4646 4647 /* Prepare the argument for the taskq */ 4648 args = ahci_portp->ahciport_event_args; 4649 args->ahciea_ctlp = (void *)ahci_ctlp; 4650 args->ahciea_portp = (void *)ahci_portp; 4651 args->ahciea_event = intr_status; 4652 args->ahciea_retrierr_slot = retrieve_errinfo_slot_status; 4653 4654 /* Start the taskq to handle error recovery */ 4655 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 4656 ahci_events_handler, 4657 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 4658 cmn_err(CE_WARN, "ahci start taskq for event handler failed"); 4659 } 4660out0: 4661 mutex_exit(&ahci_portp->ahciport_mutex); 4662 4663 return (AHCI_SUCCESS); 4664} 4665 4666/* 4667 * Hot Plug Operation for platforms that support Cold Presence Detect. 4668 * 4669 * When set, a device status has changed as detected by the cold presence 4670 * detect logic. This bit can either be set due to a non-connected port 4671 * receiving a device, or a connected port having its device removed. 4672 * This bit is only valid if the port supports cold presence detect as 4673 * indicated by PxCMD.CPD set to '1'. 4674 * 4675 * At the moment, this interrupt is not needed and disabled and we just 4676 * log the debug message. 4677 */ 4678/* ARGSUSED */ 4679static int 4680ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 4681 ahci_port_t *ahci_portp, uint8_t port) 4682{ 4683 uint32_t port_cmd_status; 4684 sata_device_t sdevice; 4685 4686 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4687 "ahci_intr_cold_port_detect enter, port %d", port); 4688 4689 mutex_enter(&ahci_portp->ahciport_mutex); 4690 4691 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4692 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4693 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 4694 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4695 "port %d does not support cold presence detect, so " 4696 "we just ignore this interrupt", port); 4697 mutex_exit(&ahci_portp->ahciport_mutex); 4698 return (AHCI_SUCCESS); 4699 } 4700 4701 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4702 "port %d device status has changed", port); 4703 4704 bzero((void *)&sdevice, sizeof (sata_device_t)); 4705 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4706 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4707 sdevice.satadev_addr.pmport = 0; 4708 sdevice.satadev_state = SATA_PSTATE_PWRON; 4709 4710 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 4711 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4712 "port %d: a device is hot plugged", port); 4713 mutex_exit(&ahci_portp->ahciport_mutex); 4714 sata_hba_event_notify( 4715 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4716 &sdevice, 4717 SATA_EVNT_DEVICE_ATTACHED); 4718 mutex_enter(&ahci_portp->ahciport_mutex); 4719 4720 } else { 4721 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4722 "port %d: a device is hot unplugged", port); 4723 mutex_exit(&ahci_portp->ahciport_mutex); 4724 sata_hba_event_notify( 4725 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4726 &sdevice, 4727 SATA_EVNT_DEVICE_DETACHED); 4728 mutex_enter(&ahci_portp->ahciport_mutex); 4729 } 4730 4731 mutex_exit(&ahci_portp->ahciport_mutex); 4732 4733 return (AHCI_SUCCESS); 4734} 4735 4736/* 4737 * Enable the interrupts for a particular port. 4738 * 4739 * WARNING!!! ahciport_mutex should be acquired before the function 4740 * is called. 4741 */ 4742/* ARGSUSED */ 4743static void 4744ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 4745 ahci_port_t *ahci_portp, uint8_t port) 4746{ 4747 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4748 "ahci_enable_port_intrs enter, port %d", port); 4749 4750 /* 4751 * Clear port interrupt status before enabling interrupt 4752 */ 4753 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4754 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4755 AHCI_PORT_INTR_MASK); 4756 4757 /* 4758 * Clear the pending bit from IS.IPS 4759 */ 4760 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4761 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 4762 4763 /* 4764 * Enable the following interrupts: 4765 * Device to Host Register FIS Interrupt (DHRS) 4766 * PIO Setup FIS Interrupt (PSS) 4767 * Unknown FIS Interrupt (UFS) 4768 * Port Connect Change Status (PCS) 4769 * PhyRdy Change Status (PRCS) 4770 * Overflow Status (OFS) 4771 * Interface Non-fatal Error Status (INFS) 4772 * Interface Fatal Error Status (IFS) 4773 * Host Bus Data Error Status (HBDS) 4774 * Host Bus Fatal Error Status (HBFS) 4775 * Task File Error Status (TFES) 4776 */ 4777 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4778 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 4779 (AHCI_INTR_STATUS_DHRS | 4780 AHCI_INTR_STATUS_PSS | 4781 AHCI_INTR_STATUS_UFS | 4782 AHCI_INTR_STATUS_DPS | 4783 AHCI_INTR_STATUS_PCS | 4784 AHCI_INTR_STATUS_PRCS | 4785 AHCI_INTR_STATUS_OFS | 4786 AHCI_INTR_STATUS_INFS | 4787 AHCI_INTR_STATUS_IFS | 4788 AHCI_INTR_STATUS_HBDS | 4789 AHCI_INTR_STATUS_HBFS | 4790 AHCI_INTR_STATUS_TFES)); 4791} 4792 4793/* 4794 * Enable interrupts for all the ports. 4795 * 4796 * WARNING!!! ahcictl_mutex should be acquired before the function 4797 * is called. 4798 */ 4799static void 4800ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 4801{ 4802 uint32_t ghc_control; 4803 4804 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 4805 4806 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4807 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 4808 4809 ghc_control |= AHCI_HBA_GHC_IE; 4810 4811 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4812 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 4813} 4814 4815/* 4816 * Disable interrupts for a particular port. 4817 * 4818 * WARNING!!! ahciport_mutex should be acquired before the function 4819 * is called. 4820 */ 4821/* ARGSUSED */ 4822static void 4823ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 4824 ahci_port_t *ahci_portp, uint8_t port) 4825{ 4826 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4827 "ahci_disable_port_intrs enter, port %d", port); 4828 4829 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4830 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 4831} 4832 4833/* 4834 * Disable interrupts for the whole HBA. 4835 * 4836 * The global bit is cleared, then all interrupt sources from all 4837 * ports are disabled. 4838 * 4839 * WARNING!!! ahcictl_mutex should be acquired before the function 4840 * is called. 4841 */ 4842static void 4843ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 4844{ 4845 uint32_t ghc_control; 4846 4847 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 4848 4849 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4850 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 4851 4852 ghc_control &= ~ AHCI_HBA_GHC_IE; 4853 4854 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4855 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 4856} 4857 4858/* 4859 * Handle INTx and legacy interrupts. 4860 */ 4861static int 4862ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 4863{ 4864 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 4865 int actual, count = 0; 4866 int x, y, rc, inum = 0; 4867 4868 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 4869 "ahci_add_legacy_intrs enter"); 4870 4871 /* get number of interrupts. */ 4872 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 4873 if ((rc != DDI_SUCCESS) || (count == 0)) { 4874 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4875 "ddi_intr_get_nintrs() failed, " 4876 "rc %d count %d\n", rc, count); 4877 return (DDI_FAILURE); 4878 } 4879 4880 /* Allocate an array of interrupt handles. */ 4881 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 4882 ahci_ctlp->ahcictl_intr_htable = 4883 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 4884 4885 /* call ddi_intr_alloc(). */ 4886 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 4887 DDI_INTR_TYPE_FIXED, 4888 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4889 4890 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4891 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4892 "ddi_intr_alloc() failed, rc %d\n", rc); 4893 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4894 ahci_ctlp->ahcictl_intr_size); 4895 return (DDI_FAILURE); 4896 } 4897 4898 if (actual < count) { 4899 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4900 "Requested: %d, Received: %d", count, actual); 4901 4902 for (x = 0; x < actual; x++) { 4903 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4904 } 4905 4906 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4907 ahci_ctlp->ahcictl_intr_size); 4908 return (DDI_FAILURE); 4909 } 4910 4911 ahci_ctlp->ahcictl_intr_cnt = actual; 4912 4913 /* Get intr priority. */ 4914 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 4915 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 4916 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4917 "ddi_intr_get_pri() failed"); 4918 4919 for (x = 0; x < actual; x++) { 4920 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4921 } 4922 4923 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4924 ahci_ctlp->ahcictl_intr_size); 4925 return (DDI_FAILURE); 4926 } 4927 4928 /* Test for high level interrupt. */ 4929 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4930 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4931 "ahci_add_legacy_intrs: Hi level intr not supported"); 4932 4933 for (x = 0; x < actual; x++) { 4934 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4935 } 4936 4937 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4938 sizeof (ddi_intr_handle_t)); 4939 4940 return (DDI_FAILURE); 4941 } 4942 4943 /* Call ddi_intr_add_handler(). */ 4944 for (x = 0; x < actual; x++) { 4945 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 4946 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 4947 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4948 "ddi_intr_add_handler() failed"); 4949 4950 for (y = 0; y < actual; y++) { 4951 (void) ddi_intr_free( 4952 ahci_ctlp->ahcictl_intr_htable[y]); 4953 } 4954 4955 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4956 ahci_ctlp->ahcictl_intr_size); 4957 return (DDI_FAILURE); 4958 } 4959 } 4960 4961 /* Call ddi_intr_enable() for legacy interrupts. */ 4962 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 4963 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 4964 } 4965 4966 return (DDI_SUCCESS); 4967} 4968 4969/* 4970 * Handle MSI interrupts. 4971 */ 4972static int 4973ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 4974{ 4975 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 4976 int count, avail, actual; 4977 int x, y, rc, inum = 0; 4978 4979 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 4980 "ahci_add_msi_intrs enter"); 4981 4982 /* get number of interrupts. */ 4983 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 4984 if ((rc != DDI_SUCCESS) || (count == 0)) { 4985 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4986 "ddi_intr_get_nintrs() failed, " 4987 "rc %d count %d\n", rc, count); 4988 return (DDI_FAILURE); 4989 } 4990 4991 /* get number of available interrupts. */ 4992 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 4993 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4994 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4995 "ddi_intr_get_navail() failed, " 4996 "rc %d avail %d\n", rc, avail); 4997 return (DDI_FAILURE); 4998 } 4999 5000 if (avail < count) { 5001 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5002 "ddi_intr_get_nvail returned %d, navail() returned %d", 5003 count, avail); 5004 } 5005 5006 /* Allocate an array of interrupt handles. */ 5007 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5008 ahci_ctlp->ahcictl_intr_htable = 5009 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5010 5011 /* call ddi_intr_alloc(). */ 5012 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5013 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5014 5015 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5016 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5017 "ddi_intr_alloc() failed, rc %d\n", rc); 5018 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5019 ahci_ctlp->ahcictl_intr_size); 5020 return (DDI_FAILURE); 5021 } 5022 5023 /* use interrupt count returned */ 5024 if (actual < count) { 5025 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5026 "Requested: %d, Received: %d", count, actual); 5027 } 5028 5029 ahci_ctlp->ahcictl_intr_cnt = actual; 5030 5031 /* 5032 * Get priority for first msi, assume remaining are all the same. 5033 */ 5034 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5035 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5036 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5037 "ddi_intr_get_pri() failed"); 5038 5039 /* Free already allocated intr. */ 5040 for (y = 0; y < actual; y++) { 5041 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5042 } 5043 5044 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5045 ahci_ctlp->ahcictl_intr_size); 5046 return (DDI_FAILURE); 5047 } 5048 5049 /* Test for high level interrupt. */ 5050 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5051 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5052 "ahci_add_msi_intrs: Hi level intr not supported"); 5053 5054 /* Free already allocated intr. */ 5055 for (y = 0; y < actual; y++) { 5056 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5057 } 5058 5059 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5060 sizeof (ddi_intr_handle_t)); 5061 5062 return (DDI_FAILURE); 5063 } 5064 5065 /* Call ddi_intr_add_handler(). */ 5066 for (x = 0; x < actual; x++) { 5067 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5068 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5069 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5070 "ddi_intr_add_handler() failed"); 5071 5072 /* Free already allocated intr. */ 5073 for (y = 0; y < actual; y++) { 5074 (void) ddi_intr_free( 5075 ahci_ctlp->ahcictl_intr_htable[y]); 5076 } 5077 5078 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5079 ahci_ctlp->ahcictl_intr_size); 5080 return (DDI_FAILURE); 5081 } 5082 } 5083 5084 5085 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5086 &ahci_ctlp->ahcictl_intr_cap); 5087 5088 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5089 /* Call ddi_intr_block_enable() for MSI. */ 5090 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5091 ahci_ctlp->ahcictl_intr_cnt); 5092 } else { 5093 /* Call ddi_intr_enable() for MSI non block enable. */ 5094 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5095 (void) ddi_intr_enable( 5096 ahci_ctlp->ahcictl_intr_htable[x]); 5097 } 5098 } 5099 5100 return (DDI_SUCCESS); 5101} 5102 5103/* 5104 * Removes the registered interrupts irrespective of whether they 5105 * were legacy or MSI. 5106 * 5107 * WARNING!!! The controller interrupts must be disabled before calling 5108 * this routine. 5109 */ 5110static void 5111ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5112{ 5113 int x; 5114 5115 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5116 5117 /* Disable all interrupts. */ 5118 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5119 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5120 /* Call ddi_intr_block_disable(). */ 5121 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5122 ahci_ctlp->ahcictl_intr_cnt); 5123 } else { 5124 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5125 (void) ddi_intr_disable( 5126 ahci_ctlp->ahcictl_intr_htable[x]); 5127 } 5128 } 5129 5130 /* Call ddi_intr_remove_handler(). */ 5131 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5132 (void) ddi_intr_remove_handler( 5133 ahci_ctlp->ahcictl_intr_htable[x]); 5134 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5135 } 5136 5137 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5138} 5139 5140/* 5141 * This routine tries to put port into P:NotRunning state by clearing 5142 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5143 * and PxCMD.CR to '0'. 5144 * 5145 * WARNING!!! ahciport_mutex should be acquired before the function 5146 * is called. 5147 */ 5148/* ARGSUSED */ 5149static int 5150ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5151 ahci_port_t *ahci_portp, uint8_t port) 5152{ 5153 uint32_t port_cmd_status; 5154 int loop_count; 5155 5156 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5157 "ahci_put_port_into_notrunning_state enter: port %d", port); 5158 5159 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5160 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5161 5162 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5163 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5164 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5165 5166 /* Wait until PxCMD.CR is cleared */ 5167 loop_count = 0; 5168 do { 5169 port_cmd_status = 5170 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5171 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5172 5173 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5174 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5175 "clearing port %d CMD.CR timeout, " 5176 "port_cmd_status = 0x%x", port, 5177 port_cmd_status); 5178 /* 5179 * We are effectively timing out after 0.5 sec. 5180 * This value is specified in AHCI spec. 5181 */ 5182 break; 5183 } 5184 5185 /* Wait for 10 millisec */ 5186#ifndef __lock_lint 5187 delay(AHCI_10MS_TICKS); 5188#endif /* __lock_lint */ 5189 5190 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5191 5192 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5193 5194 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5195 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5196 "ahci_put_port_into_notrunning_state: failed to clear " 5197 "PxCMD.CR to '0' after loop count: %d, and " 5198 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5199 return (AHCI_FAILURE); 5200 } else { 5201 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5202 "ahci_put_port_into_notrunning_state: succeeded to clear " 5203 "PxCMD.CR to '0' after loop count: %d, and " 5204 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5205 return (AHCI_SUCCESS); 5206 } 5207} 5208 5209/* 5210 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5211 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5212 * stable state, then set PxCMD.ST to '1' to start the port directly. 5213 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5214 * COMRESET to the device to put it in an idle state. 5215 * 5216 * The fifth argument returns whether the port reset is involved during 5217 * the process. 5218 * 5219 * The routine will be called under six scenarios: 5220 * 1. Initialize the port 5221 * 2. To abort the packet(s) 5222 * 3. To reset the port 5223 * 4. To activate the port 5224 * 5. Fatal error recovery 5225 * 6. To abort the timeout packet(s) 5226 * 5227 * WARNING!!! ahciport_mutex should be acquired before the function 5228 * is called. And ahciport_mutex will be released before the reset 5229 * event is reported to sata module by calling sata_hba_event_notify, 5230 * and then be acquired again later. 5231 */ 5232static int 5233ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5234 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5235{ 5236 uint32_t task_file_status; 5237 sata_device_t sdevice; 5238 int rval; 5239 5240 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5241 "ahci_restart_port_wait_till_ready: port %d enter", port); 5242 5243 /* First disable the interrupt */ 5244 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 5245 5246 /* Then clear PxCMD.ST */ 5247 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5248 port); 5249 if (rval != AHCI_SUCCESS) 5250 /* 5251 * If PxCMD.CR does not clear within a reasonable time, it 5252 * may assume the interface is in a hung condition and may 5253 * continue with issuing the port reset. 5254 */ 5255 goto reset; 5256 5257 /* Then clear PxSERR */ 5258 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5259 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5260 AHCI_SERROR_CLEAR_ALL); 5261 5262 /* The get PxTFD */ 5263 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5264 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5265 5266 /* 5267 * Check whether the device is in a stable status, if yes, 5268 * then start the port directly. However for ahci_tran_dport_reset, 5269 * we may have to perform a port reset. 5270 */ 5271 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5272 !(flag & AHCI_PORT_RESET)) 5273 goto out; 5274 5275reset: 5276 /* Set the reset in progress flag */ 5277 if (!(flag & AHCI_RESET_NO_EVENTS_UP)) { 5278 ahci_portp->ahciport_reset_in_progress = 1; 5279 } 5280 5281 /* 5282 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5283 * a COMRESET to the device 5284 */ 5285 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5286 if (rval != AHCI_SUCCESS) 5287 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5288 "ahci_restart_port_wait_till_ready: port %d failed", 5289 port); 5290 5291 if (reset_flag != NULL) 5292 *reset_flag = 1; 5293 5294 /* Indicate to the framework that a reset has happened. */ 5295 if (!(flag & AHCI_RESET_NO_EVENTS_UP)) { 5296 5297 bzero((void *)&sdevice, sizeof (sata_device_t)); 5298 sdevice.satadev_addr.cport = 5299 ahci_ctlp->ahcictl_port_to_cport[port]; 5300 sdevice.satadev_addr.pmport = 0; 5301 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5302 5303 sdevice.satadev_state = SATA_DSTATE_RESET | 5304 SATA_DSTATE_PWR_ACTIVE; 5305 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5306 mutex_exit(&ahci_portp->ahciport_mutex); 5307 sata_hba_event_notify( 5308 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5309 &sdevice, 5310 SATA_EVNT_DEVICE_RESET); 5311 mutex_enter(&ahci_portp->ahciport_mutex); 5312 } 5313 5314 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5315 "port %d sending event up: SATA_EVNT_RESET", port); 5316 } 5317out: 5318 /* Start the port */ 5319 if (!(flag & AHCI_PORT_INIT)) { 5320 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 5321 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 5322 } 5323 5324 return (rval); 5325} 5326 5327/* 5328 * This routine may be called under four scenarios: 5329 * a) do the recovery from fatal error 5330 * b) or we need to timeout some commands 5331 * c) or we need to abort some commands 5332 * d) or we need reset device/port/controller 5333 * 5334 * In all these scenarios, we need to send any pending unfinished 5335 * commands up to sata framework. 5336 * 5337 * WARNING!!! ahciport_mutex should be acquired before the function is called. 5338 */ 5339static void 5340ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 5341 ahci_port_t *ahci_portp, 5342 uint8_t port, 5343 uint32_t slot_status, 5344 uint32_t failed_tags, 5345 uint32_t timeout_tags, 5346 uint32_t aborted_tags, 5347 uint32_t reset_tags) 5348{ 5349 uint32_t finished_tags, unfinished_tags; 5350 int tmp_slot; 5351 sata_pkt_t *satapkt; 5352 5353 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5354 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 5355 port, slot_status); 5356 5357 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5358 "ahci_mop_commands: failed_tags: 0x%x, " 5359 "timeout_tags: 0x%x aborted_tags: 0x%x, " 5360 "reset_tags: 0x%x", failed_tags, 5361 timeout_tags, aborted_tags, reset_tags); 5362 5363 finished_tags = ahci_portp->ahciport_pending_tags & 5364 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 5365 5366 unfinished_tags = slot_status & 5367 AHCI_SLOT_MASK(ahci_ctlp) & 5368 ~failed_tags & 5369 ~aborted_tags & 5370 ~reset_tags & 5371 ~timeout_tags; 5372 5373 /* 5374 * When AHCI_PORT_FLAG_RQSENSE is set, it means REQUEST SENSE 5375 * command doesn't complete successfully due to one of the 5376 * following three conditions: 5377 * 5378 * 1. Fatal error - failed_tags includes its slot 5379 * 2. Timed out - timeout_tags includes its slot 5380 * 3. Aborted when hot unplug - aborted_tags includes its slot 5381 */ 5382 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RQSENSE) { 5383 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands " 5384 "is called for port %d while REQUEST SENSE for error " 5385 "retrieval is being executed", port); 5386 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 5387 finished_tags = 0; 5388 unfinished_tags = 0; 5389 } 5390 5391 /* Send up finished packets with SATA_PKT_COMPLETED */ 5392 while (finished_tags) { 5393 tmp_slot = ddi_ffs(finished_tags) - 1; 5394 if (tmp_slot == -1) { 5395 break; 5396 } 5397 5398 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5399 ASSERT(satapkt != NULL); 5400 5401 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 5402 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 5403 (void *)satapkt); 5404 5405 /* 5406 * Cannot fetch the return register content since the port 5407 * was restarted, so the corresponding tag will be set to 5408 * aborted tags. 5409 */ 5410 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 5411 CLEAR_BIT(finished_tags, tmp_slot); 5412 aborted_tags |= tmp_slot; 5413 continue; 5414 } 5415 5416 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5417 CLEAR_BIT(finished_tags, tmp_slot); 5418 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5419 5420 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 5421 } 5422 5423 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 5424 while (failed_tags) { 5425 tmp_slot = ddi_ffs(failed_tags) - 1; 5426 if (tmp_slot == -1) { 5427 break; 5428 } 5429 5430 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5431 ASSERT(satapkt != NULL); 5432 5433 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5434 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 5435 (void *)satapkt); 5436 5437 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5438 CLEAR_BIT(failed_tags, tmp_slot); 5439 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5440 5441 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 5442 } 5443 5444 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 5445 while (timeout_tags) { 5446 tmp_slot = ddi_ffs(timeout_tags) - 1; 5447 if (tmp_slot == -1) { 5448 break; 5449 } 5450 5451 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5452 ASSERT(satapkt != NULL); 5453 5454 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5455 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 5456 (void *)satapkt); 5457 5458 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5459 CLEAR_BIT(timeout_tags, tmp_slot); 5460 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5461 5462 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 5463 } 5464 5465 /* Send up aborted packets with SATA_PKT_ABORTED */ 5466 while (aborted_tags) { 5467 tmp_slot = ddi_ffs(aborted_tags) - 1; 5468 if (tmp_slot == -1) { 5469 break; 5470 } 5471 5472 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5473 ASSERT(satapkt != NULL); 5474 5475 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5476 "sending up pkt 0x%p with SATA_PKT_ABORTED", 5477 (void *)satapkt); 5478 5479 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5480 CLEAR_BIT(aborted_tags, tmp_slot); 5481 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5482 5483 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 5484 } 5485 5486 /* Send up reset packets with SATA_PKT_RESET. */ 5487 while (reset_tags) { 5488 tmp_slot = ddi_ffs(reset_tags) - 1; 5489 if (tmp_slot == -1) { 5490 break; 5491 } 5492 5493 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5494 ASSERT(satapkt != NULL); 5495 5496 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5497 "sending up pkt 0x%p with SATA_PKT_RESET", 5498 (void *)satapkt); 5499 5500 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5501 CLEAR_BIT(reset_tags, tmp_slot); 5502 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5503 5504 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 5505 } 5506 5507 /* Send up unfinished packets with SATA_PKT_RESET */ 5508 while (unfinished_tags) { 5509 tmp_slot = ddi_ffs(unfinished_tags) - 1; 5510 if (tmp_slot == -1) { 5511 break; 5512 } 5513 5514 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5515 ASSERT(satapkt != NULL); 5516 5517 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5518 "sending up pkt 0x%p with SATA_PKT_RESET", 5519 (void *)satapkt); 5520 5521 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5522 CLEAR_BIT(unfinished_tags, tmp_slot); 5523 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5524 5525 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 5526 } 5527 5528 ahci_portp->ahciport_mop_in_progress--; 5529 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 5530 5531 if (ahci_portp->ahciport_mop_in_progress == 0) 5532 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 5533} 5534 5535/* 5536 * This routine is going to first request a REQUEST SENSE sata pkt from sata 5537 * module, and then deliver it to the HBA to get the sense data and copy 5538 * the sense data back to the orignal failed sata pkt, and free the REQUEST 5539 * SENSE sata pkt later. 5540 */ 5541static void 5542ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5543 uint8_t port, sata_pkt_t *spkt) 5544{ 5545 sata_device_t sdevice; 5546 sata_pkt_t *rs_spkt; 5547 sata_cmd_t *sata_cmd; 5548 ddi_dma_handle_t buf_dma_handle; 5549 int loop_count; 5550 int rval; 5551#if AHCI_DEBUG 5552 struct scsi_extended_sense *rqsense; 5553#endif 5554 5555 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5556 "ahci_get_rqsense_data enter: port %d", port); 5557 5558 /* Prepare the sdevice data */ 5559 bzero((void *)&sdevice, sizeof (sata_device_t)); 5560 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5561 5562 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5563 sdevice.satadev_addr.pmport = 0; 5564 5565 sata_cmd = &spkt->satapkt_cmd; 5566 5567 /* 5568 * Call the sata hba interface to get a rs spkt 5569 */ 5570 loop_count = 0; 5571loop: 5572 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 5573 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 5574 if (rs_spkt == NULL) { 5575 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 5576 /* Sleep for a while */ 5577 delay(AHCI_10MS_TICKS); 5578 goto loop; 5579 5580 } 5581 /* Timed out after 1s */ 5582 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 5583 "failed to get rs spkt for port %d", port); 5584 return; 5585 } 5586 5587 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 5588 5589 /* 5590 * This flag is used to handle the specific error recovery when the 5591 * REQUEST SENSE command gets a faiure (failure error or time-out). 5592 */ 5593 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 5594 5595 /* The driver would like to do it in POLL mode */ 5596 rs_spkt->satapkt_op_mode |= SATA_OPMODE_POLLING; 5597 5598 /* 5599 * This start is not supposed to fail because after port is restarted, 5600 * the command slot is empty 5601 */ 5602 rval = ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 5603 ASSERT(rval != AHCI_FAILURE); 5604 5605 /* Remove the flag after REQUEST SENSE command is completed */ 5606 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 5607 5608 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 5609 /* Update the request sense data */ 5610 buf_dma_handle = *(ddi_dma_handle_t *) 5611 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 5612 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 5613 DDI_DMA_SYNC_FORKERNEL); 5614 if (rval == DDI_SUCCESS) { 5615 /* Copy the request sense data */ 5616 bcopy(rs_spkt-> 5617 satapkt_cmd.satacmd_bp->b_un.b_addr, 5618 &sata_cmd->satacmd_rqsense, 5619 SATA_ATAPI_MIN_RQSENSE_LEN); 5620#if AHCI_DEBUG 5621 rqsense = (struct scsi_extended_sense *) 5622 sata_cmd->satacmd_rqsense; 5623 5624 /* Dump the sense data */ 5625 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 5626 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 5627 "Sense data for satapkt %p ATAPI cmd 0x%x", 5628 spkt, sata_cmd->satacmd_acdb[0]); 5629 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 5630 " es_code 0x%x es_class 0x%x " 5631 "es_key 0x%x es_add_code 0x%x " 5632 "es_qual_code 0x%x", 5633 rqsense->es_code, rqsense->es_class, 5634 rqsense->es_key, rqsense->es_add_code, 5635 rqsense->es_qual_code); 5636#endif 5637 } 5638 } 5639 5640 sata_free_error_retrieval_pkt(rs_spkt); 5641} 5642 5643/* 5644 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 5645 * the port must be restarted. When the HBA detects thus error, it may try 5646 * to abort a transfer. And if the transfer was aborted, the device is 5647 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 5648 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 5649 * that the device is in a stable status and transfers may be restarted without 5650 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 5651 * then the software will send the COMRESET to do the port reset. 5652 * 5653 * Software should perform the appropriate error recovery actions based on 5654 * whether non-queued commands were being issued or natived command queuing 5655 * commands were being issued. 5656 * 5657 * And software will complete the command that had the error with error mark 5658 * to higher level software. 5659 * 5660 * Fatal errors include the following: 5661 * PxIS.IFS - Interface Fatal Error Status 5662 * PxIS.HBDS - Host Bus Data Error Status 5663 * PxIS.HBFS - Host Bus Fatal Error Status 5664 * PxIS.TFES - Task File Error Status 5665 * 5666 * WARNING!!! ahciport_mutex should be acquired before the function is called. 5667 */ 5668static void 5669ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 5670 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status, 5671 uint32_t retrieve_errinfo_slot_status) 5672{ 5673 uint32_t port_cmd_status, port_cmd_issue; 5674 uint32_t failed_tags = 0; 5675 int failed_slot; 5676 int reset_flag = 0; 5677 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 5678 sata_cmd_t *sata_cmd; 5679 sata_pkt_t *spkt; 5680 5681 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5682 "ahci_fatal_error_recovery_handler enter: port %d", port); 5683 5684 /* Read PxCI to see which commands are still outstanding */ 5685 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5686 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5687 5688 /* 5689 * Read PxCMD.CCS to determine the slot that the HBA 5690 * was processing when the error occurred. 5691 */ 5692 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5693 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5694 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5695 AHCI_CMD_STATUS_CCS_SHIFT; 5696 5697 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5698 if (spkt == NULL) { 5699 /* This may happen when interface errors occur */ 5700 goto next; 5701 } 5702 sata_cmd = &spkt->satapkt_cmd; 5703 5704 /* 5705 * We need to set retrieve_errinfo_slot_status to failed_slot 5706 * in case it's an interface error before REQUEST SENSE slot 5707 * is executed, that is spkt is NULL. 5708 */ 5709 if (retrieve_errinfo_slot_status != 0) { 5710 failed_slot = retrieve_errinfo_slot_status; 5711 } 5712 5713 /* The failed command must be one of the outstanding commands */ 5714 failed_tags = 0x1 << failed_slot; 5715 ASSERT(failed_tags & port_cmd_issue); 5716 5717 /* Update the sata registers, especially PxSERR register */ 5718 ahci_update_sata_registers(ahci_ctlp, port, 5719 &spkt->satapkt_device); 5720 5721 /* Fill out the status and error registers for PxIS.TFES */ 5722 if (intr_status & AHCI_INTR_STATUS_TFES) { 5723 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 5724 ahcirf_d2h_register_fis); 5725 5726 /* Copy the error context back to the sata_cmd */ 5727 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 5728 } 5729 5730next: 5731 5732#if AHCI_DEBUG 5733 if (failed_tags == 0) { 5734 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5735 "ahci_fatal_error_recovery_handler: port %d interface " 5736 "error occurred while no command was processing " 5737 "port_cmd_issue = 0x%x", port, port_cmd_issue); 5738 } else { 5739 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, 5740 "ahci_fatal_error_recovery_handler: port %d " 5741 "failed_tags = 0x%x, port_cmd_issue = 0x%x", 5742 port, failed_tags, port_cmd_issue); 5743 } 5744 5745 /* 5746 * retrieve_errinfo_slot_status contains the slot number of REQUEST 5747 * SENSE command. If it is not 0, it means a fatal error happens after 5748 * REQUEST SENSE command is delivered to the HBA during the error 5749 * recovery process. At this time, AHCI_PORT_FLAG_RQSENSE is supposed 5750 * to be set, and the only outstanding command is REQUEST SENSE. 5751 */ 5752 if (retrieve_errinfo_slot_status != 0) { 5753 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5754 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 5755 "command for error retrieval failed", port); 5756 ASSERT(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RQSENSE); 5757 ASSERT(retrieve_errinfo_slot_status == port_cmd_issue); 5758 ASSERT(spkt && spkt->satapkt_cmd.satacmd_acdb[0] == 5759 SCMD_REQUEST_SENSE); 5760 } 5761#endif 5762 5763 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 5764 ahci_portp->ahciport_mop_in_progress++; 5765 5766 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 5767 port, NULL, &reset_flag); 5768 5769 /* 5770 * Won't retrieve error information: 5771 * 1. Port reset was involved to recover 5772 * 2. No spkt is being executed 5773 * 3. IDENTIFY DEVICE command sent to ATAPI device 5774 * 4. REQUEST SENSE command during error recovery 5775 */ 5776 if (reset_flag || spkt == NULL || 5777 spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 5778 retrieve_errinfo_slot_status != 0) 5779 goto out; 5780 5781 /* 5782 * Deliver REQUEST SENSE for ATAPI command to gather information about 5783 * the error when a COMRESET has not been performed as part of the 5784 * error recovery. 5785 */ 5786 if (ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 5787 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 5788 5789out: 5790 ahci_mop_commands(ahci_ctlp, 5791 ahci_portp, 5792 port, 5793 port_cmd_issue, 5794 failed_tags, /* failed tags */ 5795 0, /* timeout tags */ 5796 0, /* aborted tags */ 5797 0); /* reset tags */ 5798} 5799 5800/* 5801 * Handle events - fatal error recovery 5802 */ 5803static void 5804ahci_events_handler(void *args) 5805{ 5806 ahci_event_arg_t *ahci_event_arg; 5807 ahci_ctl_t *ahci_ctlp; 5808 ahci_port_t *ahci_portp; 5809 uint32_t event; 5810 uint32_t retrieve_errinfo_slot_status; 5811 uint8_t port; 5812 5813 ahci_event_arg = (ahci_event_arg_t *)args; 5814 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 5815 ahci_portp = ahci_event_arg->ahciea_portp; 5816 event = ahci_event_arg->ahciea_event; 5817 retrieve_errinfo_slot_status = ahci_event_arg->ahciea_retrierr_slot; 5818 port = ahci_portp->ahciport_port_num; 5819 5820 AHCIDBG3(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5821 "ahci_events_handler enter: " 5822 "port %d intr_status = 0x%x retrieve_errinfo_slot_status = 0x%x", 5823 port, event, retrieve_errinfo_slot_status); 5824 5825 mutex_enter(&ahci_portp->ahciport_mutex); 5826 5827 /* 5828 * ahci_intr_phyrdy_change() may have rendered it to 5829 * SATA_DTYPE_NONE. 5830 */ 5831 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5832 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5833 "ahci_events_handler: port %d no device attached, " 5834 "and just return without doing anything", port); 5835 goto out; 5836 } 5837 5838 if (event & (AHCI_INTR_STATUS_IFS | 5839 AHCI_INTR_STATUS_HBDS | 5840 AHCI_INTR_STATUS_HBFS | 5841 AHCI_INTR_STATUS_TFES)) 5842 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 5843 port, event, retrieve_errinfo_slot_status); 5844 5845out: 5846 mutex_exit(&ahci_portp->ahciport_mutex); 5847} 5848 5849/* 5850 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 5851 * detect there are some commands which are timed out. 5852 */ 5853static void 5854ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5855 uint8_t port, uint32_t tmp_timeout_tags, 5856 uint32_t retrieve_errinfo_slot_status) 5857{ 5858 uint32_t port_cmd_issue; 5859 uint32_t finished_tags, timeout_tags; 5860#ifndef __lock_lint 5861 _NOTE(ARGUNUSED(retrieve_errinfo_slot_status)) 5862#endif 5863 5864 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 5865 "ahci_timeout_pkts enter: port %d", port); 5866 5867 mutex_enter(&ahci_portp->ahciport_mutex); 5868 5869 /* Read PxCI to see which commands are still outstanding */ 5870 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5871 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5872 ASSERT(port_cmd_issue != 0); 5873 ASSERT(tmp_timeout_tags & port_cmd_issue); 5874 5875#if AHCI_DEBUG 5876 /* 5877 * Retrieve_errinfo_slot_status contains the slot number for 5878 * REQUEST SENSE, and if it is not 0, it means REQUEST SENSE 5879 * gets time out. At this time, AHCI_PORT_FLAG_RQSENSE is 5880 * supposed to be set, and REQUEST SENSE is supposed to be 5881 * the only outstanding command. And we can make sure the timed 5882 * out command must be REQUEST SENSE when AHCI_PORT_FLAG_RQSENSE 5883 * is set. 5884 */ 5885 if (retrieve_errinfo_slot_status != 0) { 5886 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 5887 "ahci_timeout_pkts called while REQUEST SENSE " 5888 "command for errror recovery timed out " 5889 "timeout_tags = 0x%x port_cmd_issue = 0x%x", 5890 tmp_timeout_tags, port_cmd_issue); 5891 ASSERT(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RQSENSE); 5892 ASSERT(port_cmd_issue == retrieve_errinfo_slot_status); 5893 } 5894#endif 5895 5896 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 5897 ahci_portp->ahciport_mop_in_progress++; 5898 5899 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 5900 port, NULL, NULL); 5901 5902 /* 5903 * Re-identify timeout tags because some previously checked commands 5904 * could already complete. 5905 */ 5906 finished_tags = ahci_portp->ahciport_pending_tags & 5907 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 5908 timeout_tags = tmp_timeout_tags & ~finished_tags; 5909 5910 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 5911 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 5912 "timeout_tags = 0x%x port_cmd_issue = 0x%x pending_tags = 0x%x ", 5913 port, finished_tags, timeout_tags, 5914 port_cmd_issue, ahci_portp->ahciport_pending_tags); 5915 5916 ahci_mop_commands(ahci_ctlp, 5917 ahci_portp, 5918 port, 5919 port_cmd_issue, 5920 0, /* failed tags */ 5921 timeout_tags, /* timeout tags */ 5922 0, /* aborted tags */ 5923 0); /* reset tags */ 5924 5925 mutex_exit(&ahci_portp->ahciport_mutex); 5926} 5927 5928/* 5929 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5930 * for long time. 5931 */ 5932static void 5933ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 5934{ 5935 ahci_port_t *ahci_portp; 5936 sata_pkt_t *spkt; 5937 uint32_t pending_tags = 0; 5938 uint32_t timeout_tags = 0; 5939 uint32_t port_cmd_status; 5940 uint8_t port; 5941 int tmp_slot; 5942 int current_slot; 5943 /* max number of cycles this packet should survive */ 5944 int max_life_cycles; 5945 5946 /* how many cycles this packet survived so far */ 5947 int watched_cycles; 5948 5949 mutex_enter(&ahci_ctlp->ahcictl_mutex); 5950 5951 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 5952 "ahci_watchdog_handler entered"); 5953 5954 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 5955 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 5956 continue; 5957 } 5958 5959 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 5960 5961 mutex_enter(&ahci_portp->ahciport_mutex); 5962 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5963 mutex_exit(&ahci_portp->ahciport_mutex); 5964 continue; 5965 } 5966 5967 /* Skip the check for those ports in error recovery */ 5968 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 5969 mutex_exit(&ahci_portp->ahciport_mutex); 5970 continue; 5971 } 5972 5973 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5974 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5975 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5976 AHCI_CMD_STATUS_CCS_SHIFT; 5977 5978 pending_tags = ahci_portp->ahciport_pending_tags; 5979 timeout_tags = 0; 5980 while (pending_tags) { 5981 tmp_slot = ddi_ffs(pending_tags) - 1; 5982 if (tmp_slot == -1) { 5983 break; 5984 } 5985 5986 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5987 if ((spkt != NULL) && spkt->satapkt_time && 5988 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 5989 /* 5990 * We are overloading satapkt_hba_driver_private 5991 * with watched_cycle count. 5992 * 5993 * If a packet has survived for more than it's 5994 * max life cycles, it is a candidate for time 5995 * out. 5996 */ 5997 watched_cycles = (int)(intptr_t) 5998 spkt->satapkt_hba_driver_private; 5999 watched_cycles++; 6000 max_life_cycles = (spkt->satapkt_time + 6001 ahci_watchdog_timeout - 1) / 6002 ahci_watchdog_timeout; 6003 6004 spkt->satapkt_hba_driver_private = 6005 (void *)(intptr_t)watched_cycles; 6006 6007 if (watched_cycles <= max_life_cycles) 6008 goto next; 6009 6010 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6011 "the current slot is %d", current_slot); 6012 /* 6013 * We need to check whether the HBA has 6014 * begun to execute the command, if not, 6015 * then re-set the timer of the command. 6016 */ 6017 if (tmp_slot != current_slot) { 6018 spkt->satapkt_hba_driver_private = 6019 (void *)(intptr_t)0; 6020 } else { 6021 timeout_tags |= (0x1 << tmp_slot); 6022 cmn_err(CE_NOTE, "!ahci watchdog: " 6023 "port %d satapkt 0x%p timed out\n", 6024 port, (void *)spkt); 6025 } 6026 } 6027next: 6028 CLEAR_BIT(pending_tags, tmp_slot); 6029 } 6030 6031 if (timeout_tags) { 6032 mutex_exit(&ahci_portp->ahciport_mutex); 6033 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6034 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 6035 port, timeout_tags, 0); 6036 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6037 mutex_enter(&ahci_portp->ahciport_mutex); 6038 } 6039 6040 mutex_exit(&ahci_portp->ahciport_mutex); 6041 } 6042 6043 /* Re-install the watchdog timeout handler */ 6044 if (ahci_ctlp->ahcictl_timeout_id != 0) { 6045 ahci_ctlp->ahcictl_timeout_id = 6046 timeout((void (*)(void *))ahci_watchdog_handler, 6047 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 6048 } 6049 6050 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6051} 6052 6053/* 6054 * Fill the error context into sata_cmd for non-queued command error. 6055 */ 6056static void 6057ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6058{ 6059 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 6060 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6061 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6062 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6063 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6064 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 6065 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 6066 6067 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 6068 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 6069 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 6070 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 6071 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 6072 } 6073} 6074 6075/* 6076 * Put the respective register value to sata_cmd_t for satacmd_flags. 6077 */ 6078static void 6079ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6080{ 6081 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 6082 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 6083 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 6084 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 6085 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 6086 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 6087 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 6088 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 6089 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 6090 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6091 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 6092 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6093 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 6094 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6095 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 6096 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 6097 if (scmd->satacmd_flags.sata_copy_out_device_reg) 6098 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 6099 if (scmd->satacmd_flags.sata_copy_out_error_reg) 6100 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6101} 6102 6103static void 6104ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 6105 uint32_t intr_status) 6106{ 6107#ifndef __lock_lint 6108 _NOTE(ARGUNUSED(ahci_ctlp)) 6109#endif 6110 6111 if (intr_status & AHCI_INTR_STATUS_IFS) 6112 cmn_err(CE_NOTE, "!ahci port %d has interface fatal " 6113 "error", port); 6114 6115 if (intr_status & AHCI_INTR_STATUS_HBDS) 6116 cmn_err(CE_NOTE, "!ahci port %d has bus data error", port); 6117 6118 if (intr_status & AHCI_INTR_STATUS_HBFS) 6119 cmn_err(CE_NOTE, "!ahci port %d has bus fatal error", port); 6120 6121 if (intr_status & AHCI_INTR_STATUS_TFES) 6122 cmn_err(CE_NOTE, "!ahci port %d has task file error", port); 6123 6124 cmn_err(CE_NOTE, "!ahci port %d is trying to do error " 6125 "recovery", port); 6126} 6127 6128/* 6129 * Dump the serror message to the log. 6130 */ 6131static void 6132ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 6133 uint32_t port_serror) 6134{ 6135#ifndef __lock_lint 6136 _NOTE(ARGUNUSED(ahci_ctlp)) 6137#endif 6138 char *err_str; 6139 6140 if (port_serror & AHCI_SERROR_ERR_I) { 6141 err_str = "Recovered Data Integrity Error (I)"; 6142 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6143 "command error: port: %d, error: %s", 6144 port, err_str); 6145 } 6146 6147 if (port_serror & AHCI_SERROR_ERR_M) { 6148 err_str = "Recovered Communication Error (M)"; 6149 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6150 "command error: port: %d, error: %s", 6151 port, err_str); 6152 } 6153 6154 if (port_serror & AHCI_SERROR_ERR_T) { 6155 err_str = "Transient Data Integrity Error (T)"; 6156 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6157 "command error: port: %d, error: %s", 6158 port, err_str); 6159 } 6160 6161 if (port_serror & AHCI_SERROR_ERR_C) { 6162 err_str = 6163 "Persistent Communication or Data Integrity Error (C)"; 6164 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6165 "command error: port: %d, error: %s", 6166 port, err_str); 6167 } 6168 6169 if (port_serror & AHCI_SERROR_ERR_P) { 6170 err_str = "Protocol Error (P)"; 6171 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6172 "command error: port: %d, error: %s", 6173 port, err_str); 6174 } 6175 6176 if (port_serror & AHCI_SERROR_ERR_E) { 6177 err_str = "Internal Error (E)"; 6178 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6179 "command error: port: %d, error: %s", 6180 port, err_str); 6181 } 6182 6183 if (port_serror & AHCI_SERROR_DIAG_N) { 6184 err_str = "PhyRdy Change (N)"; 6185 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6186 "command error: port: %d, error: %s", 6187 port, err_str); 6188 } 6189 6190 if (port_serror & AHCI_SERROR_DIAG_I) { 6191 err_str = "Phy Internal Error (I)"; 6192 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6193 "command error: port: %d, error: %s", 6194 port, err_str); 6195 } 6196 6197 if (port_serror & AHCI_SERROR_DIAG_W) { 6198 err_str = "Comm Wake (W)"; 6199 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6200 "command error: port: %d, error: %s", 6201 port, err_str); 6202 } 6203 6204 if (port_serror & AHCI_SERROR_DIAG_B) { 6205 err_str = "10B to 8B Decode Error (B)"; 6206 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6207 "command error: port: %d, error: %s", 6208 port, err_str); 6209 } 6210 6211 if (port_serror & AHCI_SERROR_DIAG_D) { 6212 err_str = "Disparity Error (D)"; 6213 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6214 "command error: port: %d, error: %s", 6215 port, err_str); 6216 } 6217 6218 if (port_serror & AHCI_SERROR_DIAG_C) { 6219 err_str = "CRC Error (C)"; 6220 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6221 "command error: port: %d, error: %s", 6222 port, err_str); 6223 } 6224 6225 if (port_serror & AHCI_SERROR_DIAG_H) { 6226 err_str = "Handshake Error (H)"; 6227 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6228 "command error: port: %d, error: %s", 6229 port, err_str); 6230 } 6231 6232 if (port_serror & AHCI_SERROR_DIAG_S) { 6233 err_str = "Link Sequence Error (S)"; 6234 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6235 "command error: port: %d, error: %s", 6236 port, err_str); 6237 } 6238 6239 if (port_serror & AHCI_SERROR_DIAG_T) { 6240 err_str = "Transport state transition error (T)"; 6241 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6242 "command error: port: %d, error: %s", 6243 port, err_str); 6244 } 6245 6246 if (port_serror & AHCI_SERROR_DIAG_F) { 6247 err_str = "Unknown FIS Type (F)"; 6248 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6249 "command error: port: %d, error: %s", 6250 port, err_str); 6251 } 6252 6253 if (port_serror & AHCI_SERROR_DIAG_X) { 6254 err_str = "Exchanged (X)"; 6255 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6256 "command error: port: %d, error: %s", 6257 port, err_str); 6258 } 6259} 6260 6261/* 6262 * This routine is to calculate the total number of ports implemented 6263 * by the HBA. 6264 */ 6265static int 6266ahci_get_num_implemented_ports(uint32_t ports_implemented) 6267{ 6268 uint8_t i; 6269 int num = 0; 6270 6271 for (i = 0; i < AHCI_MAX_PORTS; i++) { 6272 if (((uint32_t)0x1 << i) & ports_implemented) 6273 num++; 6274 } 6275 6276 return (num); 6277} 6278 6279static void 6280ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 6281{ 6282 va_list ap; 6283 6284 mutex_enter(&ahci_log_mutex); 6285 6286 va_start(ap, fmt); 6287 if (ahci_ctlp) { 6288 (void) sprintf(ahci_log_buf, "%s-[%d]:", 6289 ddi_get_name(ahci_ctlp->ahcictl_dip), 6290 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 6291 } else { 6292 (void) sprintf(ahci_log_buf, "ahci:"); 6293 } 6294 6295 (void) vsprintf(ahci_log_buf, fmt, ap); 6296 va_end(ap); 6297 6298 cmn_err(level, "%s", ahci_log_buf); 6299 6300 mutex_exit(&ahci_log_mutex); 6301} 6302