nx_hw_pci_regs.h revision 7956:59ff93e4da95
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25#ifndef __NX_HW_REGS_H 26#define __NX_HW_REGS_H 27 28/* 29 * PCI related defines. 30 */ 31 32/* 33 * Interrupt related defines. 34 */ 35#define PCIX_TARGET_STATUS (0x10118) 36#define PCIX_TARGET_STATUS_F1 (0x10160) 37#define PCIX_TARGET_STATUS_F2 (0x10164) 38#define PCIX_TARGET_STATUS_F3 (0x10168) 39#define PCIX_TARGET_STATUS_F4 (0x10360) 40#define PCIX_TARGET_STATUS_F5 (0x10364) 41#define PCIX_TARGET_STATUS_F6 (0x10368) 42#define PCIX_TARGET_STATUS_F7 (0x1036c) 43 44#define PCIX_TARGET_MASK (0x10128) 45#define PCIX_TARGET_MASK_F1 (0x10170) 46#define PCIX_TARGET_MASK_F2 (0x10174) 47#define PCIX_TARGET_MASK_F3 (0x10178) 48#define PCIX_TARGET_MASK_F4 (0x10370) 49#define PCIX_TARGET_MASK_F5 (0x10374) 50#define PCIX_TARGET_MASK_F6 (0x10378) 51#define PCIX_TARGET_MASK_F7 (0x1037c) 52 53/* 54 * Message Signaled Interrupts 55 */ 56#define PCIX_MSI_F0 (0x13000) 57#define PCIX_MSI_F1 (0x13004) 58#define PCIX_MSI_F2 (0x13008) 59#define PCIX_MSI_F3 (0x1300c) 60#define PCIX_MSI_F4 (0x13010) 61#define PCIX_MSI_F5 (0x13014) 62#define PCIX_MSI_F6 (0x13018) 63#define PCIX_MSI_F7 (0x1301c) 64#define PCIX_MSI_F(FUNC) (0x13000 +((FUNC) * 4)) 65 66/* 67 * 68 */ 69#define PCIX_INT_VECTOR (0x10100) 70#define PCIX_INT_MASK (0x10104) 71 72/* 73 * Interrupt state machine and other bits. 74 */ 75#define PCIE_MISCCFG_RC (0x1206c) 76 77 78#define ISR_INT_TARGET_STATUS (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS)) 79#define ISR_INT_TARGET_STATUS_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 80#define ISR_INT_TARGET_STATUS_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 81#define ISR_INT_TARGET_STATUS_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 82#define ISR_INT_TARGET_STATUS_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 83#define ISR_INT_TARGET_STATUS_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 84#define ISR_INT_TARGET_STATUS_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 85#define ISR_INT_TARGET_STATUS_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 86 87#define ISR_INT_TARGET_MASK (UNM_PCIX_PS_REG(PCIX_TARGET_MASK)) 88#define ISR_INT_TARGET_MASK_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 89#define ISR_INT_TARGET_MASK_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 90#define ISR_INT_TARGET_MASK_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 91#define ISR_INT_TARGET_MASK_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 92#define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 93#define ISR_INT_TARGET_MASK_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 94#define ISR_INT_TARGET_MASK_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 95 96#define ISR_INT_VECTOR (UNM_PCIX_PS_REG(PCIX_INT_VECTOR)) 97#define ISR_INT_MASK (UNM_PCIX_PS_REG(PCIX_INT_MASK)) 98#define ISR_INT_STATE_REG (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC)) 99 100#define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 101 102 103#define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 104#define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 105 106/* 107 * PCI Interrupt Vector Values. 108 */ 109#define PCIX_INT_VECTOR_BIT_F0 0x0080 110#define PCIX_INT_VECTOR_BIT_F1 0x0100 111#define PCIX_INT_VECTOR_BIT_F2 0x0200 112#define PCIX_INT_VECTOR_BIT_F3 0x0400 113#define PCIX_INT_VECTOR_BIT_F4 0x0800 114#define PCIX_INT_VECTOR_BIT_F5 0x1000 115#define PCIX_INT_VECTOR_BIT_F6 0x2000 116#define PCIX_INT_VECTOR_BIT_F7 0x4000 117 118struct nx_legacy_intr_set { 119 __uint32_t int_vec_bit; 120 __uint32_t tgt_status_reg; 121 __uint32_t tgt_mask_reg; 122 __uint32_t pci_int_reg; 123}; 124 125#define NX_LEGACY_INTR_CONFIG \ 126{ \ 127 { PCIX_INT_VECTOR_BIT_F0, \ 128 ISR_INT_TARGET_STATUS, \ 129 ISR_INT_TARGET_MASK, \ 130 ISR_MSI_INT_TRIGGER(0) }, \ 131 \ 132 { PCIX_INT_VECTOR_BIT_F1, \ 133 ISR_INT_TARGET_STATUS_F1, \ 134 ISR_INT_TARGET_MASK_F1, \ 135 ISR_MSI_INT_TRIGGER(1) }, \ 136 \ 137 { PCIX_INT_VECTOR_BIT_F2, \ 138 ISR_INT_TARGET_STATUS_F2, \ 139 ISR_INT_TARGET_MASK_F2, \ 140 ISR_MSI_INT_TRIGGER(2) }, \ 141 \ 142 { PCIX_INT_VECTOR_BIT_F3, \ 143 ISR_INT_TARGET_STATUS_F3, \ 144 ISR_INT_TARGET_MASK_F3, \ 145 ISR_MSI_INT_TRIGGER(3) }, \ 146 \ 147 { PCIX_INT_VECTOR_BIT_F4, \ 148 ISR_INT_TARGET_STATUS_F4, \ 149 ISR_INT_TARGET_MASK_F4, \ 150 ISR_MSI_INT_TRIGGER(4) }, \ 151 \ 152 { PCIX_INT_VECTOR_BIT_F5, \ 153 ISR_INT_TARGET_STATUS_F5, \ 154 ISR_INT_TARGET_MASK_F5, \ 155 ISR_MSI_INT_TRIGGER(5) }, \ 156 \ 157 { PCIX_INT_VECTOR_BIT_F6, \ 158 ISR_INT_TARGET_STATUS_F6, \ 159 ISR_INT_TARGET_MASK_F6, \ 160 ISR_MSI_INT_TRIGGER(6) }, \ 161 \ 162 { PCIX_INT_VECTOR_BIT_F7, \ 163 ISR_INT_TARGET_STATUS_F7, \ 164 ISR_INT_TARGET_MASK_F7, \ 165 ISR_MSI_INT_TRIGGER(7) }, \ 166} 167 168#endif /* __NX_HW_REGS_H */ 169