ixgbe_phy.c revision 9353:b9caf92a0042
1/* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24/* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29/* IntelVersion: 1.83 v2-7-8_2009-4-7 */ 30 31#include "ixgbe_api.h" 32#include "ixgbe_common.h" 33#include "ixgbe_phy.h" 34 35static void ixgbe_i2c_start(struct ixgbe_hw *hw); 36static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 45static bool ixgbe_get_i2c_data(u32 *i2cctl); 46void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 47 48/* 49 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 50 * @hw: pointer to the hardware structure 51 * 52 * Initialize the function pointers. 53 */ 54s32 55ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 56{ 57 struct ixgbe_phy_info *phy = &hw->phy; 58 59 /* PHY */ 60 phy->ops.identify = &ixgbe_identify_phy_generic; 61 phy->ops.reset = &ixgbe_reset_phy_generic; 62 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 63 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 64 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 65 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 66 phy->ops.check_link = NULL; 67 phy->ops.get_firmware_version = NULL; 68 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 69 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 70 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 71 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 72 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 73 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 74 phy->sfp_type = ixgbe_sfp_type_unknown; 75 76 return (IXGBE_SUCCESS); 77} 78 79/* 80 * ixgbe_identify_phy_generic - Get physical layer module 81 * @hw: pointer to hardware structure 82 * 83 * Determines the physical layer module found on the current adapter. 84 */ 85s32 86ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 87{ 88 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 89 u32 phy_addr; 90 u16 ext_ability = 0; 91 92 if (hw->phy.type == ixgbe_phy_unknown) { 93 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 94 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 95 hw->phy.addr = phy_addr; 96 (void) ixgbe_get_phy_id(hw); 97 hw->phy.type = 98 ixgbe_get_phy_type_from_id(hw->phy.id); 99 100 if (hw->phy.type == ixgbe_phy_unknown) { 101 hw->phy.ops.read_reg(hw, 102 IXGBE_MDIO_PHY_EXT_ABILITY, 103 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 104 &ext_ability); 105 if (ext_ability & 106 IXGBE_MDIO_PHY_10GBASET_ABILITY || 107 ext_ability & 108 IXGBE_MDIO_PHY_1000BASET_ABILITY) 109 hw->phy.type = 110 ixgbe_phy_cu_unknown; 111 else 112 hw->phy.type = 113 ixgbe_phy_generic; 114 } 115 116 status = IXGBE_SUCCESS; 117 break; 118 } 119 } 120 if (status != IXGBE_SUCCESS) 121 hw->phy.addr = 0; 122 } else { 123 status = IXGBE_SUCCESS; 124 } 125 126 return (status); 127} 128 129/* 130 * ixgbe_validate_phy_addr - Determines phy address is valid 131 * @hw: pointer to hardware structure 132 * 133 */ 134bool 135ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 136{ 137 u16 phy_id = 0; 138 bool valid = false; 139 140 hw->phy.addr = phy_addr; 141 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 142 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 143 144 if (phy_id != 0xFFFF && phy_id != 0x0) 145 valid = true; 146 147 return (valid); 148} 149 150/* 151 * ixgbe_get_phy_id - Get the phy type 152 * @hw: pointer to hardware structure 153 * 154 */ 155s32 156ixgbe_get_phy_id(struct ixgbe_hw *hw) 157{ 158 u32 status; 159 u16 phy_id_high = 0; 160 u16 phy_id_low = 0; 161 162 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 163 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 164 &phy_id_high); 165 166 if (status == IXGBE_SUCCESS) { 167 hw->phy.id = (u32)(phy_id_high << 16); 168 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 169 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 170 &phy_id_low); 171 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 172 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 173 } 174 175 return (status); 176} 177 178/* 179 * ixgbe_get_phy_type_from_id - Get the phy type 180 * @hw: pointer to hardware structure 181 * 182 */ 183enum ixgbe_phy_type 184ixgbe_get_phy_type_from_id(u32 phy_id) 185{ 186 enum ixgbe_phy_type phy_type; 187 188 switch (phy_id) { 189 case TN1010_PHY_ID: 190 phy_type = ixgbe_phy_tn; 191 break; 192 case QT2022_PHY_ID: 193 phy_type = ixgbe_phy_qt; 194 break; 195 case ATH_PHY_ID: 196 phy_type = ixgbe_phy_nl; 197 break; 198 default: 199 phy_type = ixgbe_phy_unknown; 200 break; 201 } 202 203 DEBUGOUT1("phy type found is %d\n", phy_type); 204 205 return (phy_type); 206} 207 208/* 209 * ixgbe_reset_phy_generic - Performs a PHY reset 210 * @hw: pointer to hardware structure 211 */ 212s32 213ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 214{ 215 u32 i; 216 u16 ctrl = 0; 217 s32 status = IXGBE_SUCCESS; 218 219 if (hw->phy.type == ixgbe_phy_unknown) 220 status = ixgbe_identify_phy_generic(hw); 221 222 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 223 goto out; 224 225 /* 226 * Perform soft PHY reset to the PHY_XS. 227 * This will cause a soft reset to the PHY 228 */ 229 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 230 IXGBE_MDIO_PHY_XS_DEV_TYPE, 231 IXGBE_MDIO_PHY_XS_RESET); 232 233 /* Poll for reset bit to self-clear indicating reset is complete */ 234 for (i = 0; i < 500; i++) { 235 msec_delay(1); 236 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 237 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 238 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) 239 break; 240 } 241 242 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 243 status = IXGBE_ERR_RESET_FAILED; 244 DEBUGOUT("PHY reset polling failed to complete.\n"); 245 } 246 247out: 248 return (status); 249} 250 251/* 252 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 253 * @hw: pointer to hardware structure 254 * @reg_addr: 32 bit address of PHY register to read 255 * @phy_data: Pointer to read data from PHY register 256 */ 257s32 258ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 259 u32 device_type, u16 *phy_data) 260{ 261 u32 command; 262 u32 i; 263 u32 data; 264 s32 status = IXGBE_SUCCESS; 265 u16 gssr; 266 267 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 268 gssr = IXGBE_GSSR_PHY1_SM; 269 else 270 gssr = IXGBE_GSSR_PHY0_SM; 271 272 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 273 status = IXGBE_ERR_SWFW_SYNC; 274 275 if (status == IXGBE_SUCCESS) { 276 /* Setup and write the address cycle command */ 277 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 278 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 279 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 280 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 281 282 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 283 284 /* 285 * Check every 10 usec to see if the address cycle completed. 286 * The MDI Command bit will clear when the operation is 287 * complete 288 */ 289 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 290 usec_delay(10); 291 292 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 293 294 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) { 295 break; 296 } 297 } 298 299 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 300 DEBUGOUT("PHY address command did not complete.\n"); 301 status = IXGBE_ERR_PHY; 302 } 303 304 if (status == IXGBE_SUCCESS) { 305 /* 306 * Address cycle complete, setup and write the read 307 * command 308 */ 309 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 310 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 311 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 312 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 313 314 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 315 316 /* 317 * Check every 10 usec to see if the address cycle 318 * completed. The MDI Command bit will clear when the 319 * operation is complete 320 */ 321 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 322 usec_delay(10); 323 324 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 325 326 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 327 break; 328 } 329 330 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 331 DEBUGOUT("PHY read command didn't complete\n"); 332 status = IXGBE_ERR_PHY; 333 } else { 334 /* 335 * Read operation is complete. Get the data 336 * from MSRWD 337 */ 338 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 339 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 340 *phy_data = (u16)(data); 341 } 342 } 343 344 ixgbe_release_swfw_sync(hw, gssr); 345 } 346 347 return (status); 348} 349 350/* 351 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 352 * @hw: pointer to hardware structure 353 * @reg_addr: 32 bit PHY register to write 354 * @device_type: 5 bit device type 355 * @phy_data: Data to write to the PHY register 356 */ 357s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 358 u32 device_type, u16 phy_data) 359{ 360 u32 command; 361 u32 i; 362 s32 status = IXGBE_SUCCESS; 363 u16 gssr; 364 365 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 366 gssr = IXGBE_GSSR_PHY1_SM; 367 else 368 gssr = IXGBE_GSSR_PHY0_SM; 369 370 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 371 status = IXGBE_ERR_SWFW_SYNC; 372 373 if (status == IXGBE_SUCCESS) { 374 /* 375 * Put the data in the MDI single read and write data register 376 */ 377 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 378 379 /* Setup and write the address cycle command */ 380 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 381 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 382 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 383 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 384 385 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 386 387 /* 388 * Check every 10 usec to see if the address cycle completed. 389 * The MDI Command bit will clear when the operation is 390 * complete 391 */ 392 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 393 usec_delay(10); 394 395 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 396 397 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 398 break; 399 } 400 401 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 402 DEBUGOUT("PHY address cmd didn't complete\n"); 403 status = IXGBE_ERR_PHY; 404 } 405 406 if (status == IXGBE_SUCCESS) { 407 /* 408 * Address cycle complete, setup and write the write 409 * command 410 */ 411 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 412 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 413 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 414 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 415 416 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 417 418 /* 419 * Check every 10 usec to see if the address cycle 420 * completed. The MDI Command bit will clear when the 421 * operation is complete 422 */ 423 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 424 usec_delay(10); 425 426 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 427 428 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 429 break; 430 } 431 432 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 433 DEBUGOUT("PHY address cmd didn't complete\n"); 434 status = IXGBE_ERR_PHY; 435 } 436 } 437 438 ixgbe_release_swfw_sync(hw, gssr); 439 } 440 441 return (status); 442} 443 444/* 445 * ixgbe_setup_phy_link_generic - Set and restart autoneg 446 * @hw: pointer to hardware structure 447 * 448 * Restart autonegotiation and PHY and waits for completion. 449 */ 450s32 451ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 452{ 453 s32 status = IXGBE_NOT_IMPLEMENTED; 454 u32 time_out; 455 u32 max_time_out = 10; 456 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 457 458 /* 459 * Set advertisement settings in PHY based on autoneg_advertised 460 * settings. If autoneg_advertised = 0, then advertise default values 461 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 462 * for a 1G. 463 */ 464 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 465 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 466 467 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) 468 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ 469 else 470 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ 471 472 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 473 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 474 475 /* Restart PHY autonegotiation and wait for completion */ 476 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 477 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 478 479 autoneg_reg |= IXGBE_MII_RESTART; 480 481 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 482 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 483 484 /* Wait for autonegotiation to finish */ 485 for (time_out = 0; time_out < max_time_out; time_out++) { 486 usec_delay(10); 487 /* Restart PHY autonegotiation and wait for completion */ 488 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 489 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 490 &autoneg_reg); 491 492 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 493 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 494 status = IXGBE_SUCCESS; 495 break; 496 } 497 } 498 499 if (time_out == max_time_out) 500 status = IXGBE_ERR_LINK_SETUP; 501 502 return (status); 503} 504 505/* 506 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 507 * @hw: pointer to hardware structure 508 * @speed: new link speed 509 * @autoneg: true if autonegotiation enabled 510 */ 511s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 512 ixgbe_link_speed speed, 513 bool autoneg, 514 bool autoneg_wait_to_complete) 515{ 516 UNREFERENCED_PARAMETER(autoneg); 517 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 518 519 /* 520 * Clear autoneg_advertised and set new values based on input link 521 * speed. 522 */ 523 hw->phy.autoneg_advertised = 0; 524 525 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 526 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 527 } 528 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 529 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 530 } 531 532 /* Setup link based on the new speed settings */ 533 hw->phy.ops.setup_link(hw); 534 535 return (IXGBE_SUCCESS); 536} 537 538/* 539 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 540 * @hw: pointer to hardware structure 541 * @speed: pointer to link speed 542 * @autoneg: boolean auto-negotiation value 543 * 544 * Determines the link capabilities by reading the AUTOC register. 545 */ 546s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 547 ixgbe_link_speed *speed, bool *autoneg) 548{ 549 s32 status = IXGBE_ERR_LINK_SETUP; 550 u16 speed_ability; 551 552 *speed = 0; 553 *autoneg = true; 554 555 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 556 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &speed_ability); 557 558 if (status == IXGBE_SUCCESS) { 559 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 560 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 561 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 562 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 563 } 564 565 return (status); 566} 567 568/* 569 * ixgbe_check_phy_link_tnx - Determine link and speed status 570 * @hw: pointer to hardware structure 571 * 572 * Reads the VS1 register to determine if link is up and the current speed for 573 * the PHY. 574 */ 575s32 576ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 577 bool *link_up) 578{ 579 s32 status = IXGBE_SUCCESS; 580 u32 time_out; 581 u32 max_time_out = 10; 582 u16 phy_link = 0; 583 u16 phy_speed = 0; 584 u16 phy_data = 0; 585 586 /* Initialize speed and link to default case */ 587 *link_up = false; 588 *speed = IXGBE_LINK_SPEED_10GB_FULL; 589 590 /* 591 * Check current speed and link status of the PHY register. 592 * This is a vendor specific register and may have to 593 * be changed for other copper PHYs. 594 */ 595 for (time_out = 0; time_out < max_time_out; time_out++) { 596 usec_delay(10); 597 status = hw->phy.ops.read_reg(hw, 598 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 599 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 600 &phy_data); 601 phy_link = phy_data & 602 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 603 phy_speed = phy_data & 604 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 605 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 606 *link_up = true; 607 if (phy_speed == 608 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 609 *speed = IXGBE_LINK_SPEED_1GB_FULL; 610 break; 611 } 612 } 613 614 return (status); 615} 616 617/* 618 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 619 * @hw: pointer to hardware structure 620 * @firmware_version: pointer to the PHY Firmware Version 621 */ 622s32 623ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version) 624{ 625 s32 status = IXGBE_SUCCESS; 626 627 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 628 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 629 630 return (status); 631} 632 633/* 634 * ixgbe_reset_phy_nl - Performs a PHY reset 635 * @hw: pointer to hardware structure 636 */ 637s32 638ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 639{ 640 u16 phy_offset, control, eword, edata, block_crc; 641 bool end_data = false; 642 u16 list_offset, data_offset; 643 u16 phy_data = 0; 644 s32 ret_val = IXGBE_SUCCESS; 645 u32 i; 646 647 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 648 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 649 650 /* reset the PHY and poll for completion */ 651 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 652 IXGBE_MDIO_PHY_XS_DEV_TYPE, 653 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 654 655 for (i = 0; i < 100; i++) { 656 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 657 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 658 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 659 break; 660 msec_delay(10); 661 } 662 663 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 664 DEBUGOUT("PHY reset did not complete.\n"); 665 ret_val = IXGBE_ERR_PHY; 666 goto out; 667 } 668 669 /* Get init offsets */ 670 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 671 &data_offset); 672 if (ret_val != IXGBE_SUCCESS) 673 goto out; 674 675 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 676 data_offset++; 677 while (!end_data) { 678 /* 679 * Read control word from PHY init contents offset 680 */ 681 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 682 control = (eword & IXGBE_CONTROL_MASK_NL) >> 683 IXGBE_CONTROL_SHIFT_NL; 684 edata = eword & IXGBE_DATA_MASK_NL; 685 switch (control) { 686 case IXGBE_DELAY_NL: 687 data_offset++; 688 DEBUGOUT1("DELAY: %d MS\n", edata); 689 msec_delay(edata); 690 break; 691 case IXGBE_DATA_NL: 692 DEBUGOUT("DATA: \n"); 693 data_offset++; 694 hw->eeprom.ops.read(hw, data_offset++, &phy_offset); 695 for (i = 0; i < edata; i++) { 696 hw->eeprom.ops.read(hw, data_offset, &eword); 697 hw->phy.ops.write_reg(hw, phy_offset, 698 IXGBE_TWINAX_DEV, eword); 699 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 700 phy_offset); 701 data_offset++; 702 phy_offset++; 703 } 704 break; 705 case IXGBE_CONTROL_NL: 706 data_offset++; 707 DEBUGOUT("CONTROL: \n"); 708 if (edata == IXGBE_CONTROL_EOL_NL) { 709 DEBUGOUT("EOL\n"); 710 end_data = true; 711 } else if (edata == IXGBE_CONTROL_SOL_NL) { 712 DEBUGOUT("SOL\n"); 713 } else { 714 DEBUGOUT("Bad control value\n"); 715 ret_val = IXGBE_ERR_PHY; 716 goto out; 717 } 718 break; 719 default: 720 DEBUGOUT("Bad control type\n"); 721 ret_val = IXGBE_ERR_PHY; 722 goto out; 723 } 724 } 725 726out: 727 return (ret_val); 728} 729 730/* 731 * ixgbe_identify_sfp_module_generic - Identifies SFP module 732 * @hw: pointer to hardware structure 733 * 734 * Searches for and identifies the SFP module and assigns appropriate PHY type. 735 */ 736s32 737ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 738{ 739 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 740 u32 vendor_oui = 0; 741 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 742 u8 identifier = 0; 743 u8 comp_codes_1g = 0; 744 u8 comp_codes_10g = 0; 745 u8 oui_bytes[3] = {0, 0, 0}; 746 u8 transmission_media = 0; 747 u16 enforce_sfp = 0; 748 749 status = hw->phy.ops.read_i2c_eeprom(hw, 750 IXGBE_SFF_IDENTIFIER, &identifier); 751 752 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 753 status = IXGBE_ERR_SFP_NOT_PRESENT; 754 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 755 if (hw->phy.type != ixgbe_phy_nl) { 756 hw->phy.id = 0; 757 hw->phy.type = ixgbe_phy_unknown; 758 } 759 goto out; 760 } 761 762 /* LAN ID is needed for sfp_type determination */ 763 hw->mac.ops.set_lan_id(hw); 764 765 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { 766 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 767 &comp_codes_1g); 768 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 769 &comp_codes_10g); 770 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA, 771 &transmission_media); 772 773 /* 774 * ID Module 775 * ============ 776 * 0 SFP_DA_CU 777 * 1 SFP_SR 778 * 2 SFP_LR 779 * 3 SFP_DA_CORE0 - 82599-specific 780 * 4 SFP_DA_CORE1 - 82599-specific 781 * 5 SFP_SR/LR_CORE0 - 82599-specific 782 * 6 SFP_SR/LR_CORE1 - 82599-specific 783 */ 784 if (hw->mac.type == ixgbe_mac_82598EB) { 785 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 786 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 787 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 788 hw->phy.sfp_type = ixgbe_sfp_type_sr; 789 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 790 hw->phy.sfp_type = ixgbe_sfp_type_lr; 791 else 792 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 793 } else if (hw->mac.type == ixgbe_mac_82599EB) { 794 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 795 if (hw->bus.lan_id == 0) 796 hw->phy.sfp_type = 797 ixgbe_sfp_type_da_cu_core0; 798 else 799 hw->phy.sfp_type = 800 ixgbe_sfp_type_da_cu_core1; 801 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 802 if (hw->bus.lan_id == 0) 803 hw->phy.sfp_type = 804 ixgbe_sfp_type_srlr_core0; 805 else 806 hw->phy.sfp_type = 807 ixgbe_sfp_type_srlr_core1; 808 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 809 if (hw->bus.lan_id == 0) 810 hw->phy.sfp_type = 811 ixgbe_sfp_type_srlr_core0; 812 else 813 hw->phy.sfp_type = 814 ixgbe_sfp_type_srlr_core1; 815 else 816 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 817 } 818 819 if (hw->phy.sfp_type != stored_sfp_type) 820 hw->phy.sfp_setup_needed = true; 821 822 /* Determine if the SFP+ PHY is dual speed or not. */ 823 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 824 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 825 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 826 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 827 hw->phy.multispeed_fiber = true; 828 829 /* Determine PHY vendor */ 830 if (hw->phy.type != ixgbe_phy_nl) { 831 hw->phy.id = identifier; 832 hw->phy.ops.read_i2c_eeprom(hw, 833 IXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 834 hw->phy.ops.read_i2c_eeprom(hw, 835 IXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 836 hw->phy.ops.read_i2c_eeprom(hw, 837 IXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 838 839 vendor_oui = 840 ((oui_bytes[0] << 841 IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 842 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 843 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 844 845 switch (vendor_oui) { 846 case IXGBE_SFF_VENDOR_OUI_TYCO: 847 if (transmission_media & 848 IXGBE_SFF_TWIN_AX_CAPABLE) 849 hw->phy.type = ixgbe_phy_tw_tyco; 850 break; 851 case IXGBE_SFF_VENDOR_OUI_FTL: 852 hw->phy.type = ixgbe_phy_sfp_ftl; 853 break; 854 case IXGBE_SFF_VENDOR_OUI_AVAGO: 855 hw->phy.type = ixgbe_phy_sfp_avago; 856 break; 857 case IXGBE_SFF_VENDOR_OUI_INTEL: 858 hw->phy.type = ixgbe_phy_sfp_intel; 859 break; 860 default: 861 if (transmission_media & 862 IXGBE_SFF_TWIN_AX_CAPABLE) 863 hw->phy.type = ixgbe_phy_tw_unknown; 864 else 865 hw->phy.type = ixgbe_phy_sfp_unknown; 866 break; 867 } 868 } 869 870 if (hw->mac.type == ixgbe_mac_82598EB || 871 (hw->phy.sfp_type != ixgbe_sfp_type_sr && 872 hw->phy.sfp_type != ixgbe_sfp_type_lr && 873 hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 && 874 hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) { 875 status = IXGBE_SUCCESS; 876 goto out; 877 } 878 879 (void) ixgbe_get_device_caps(hw, &enforce_sfp); 880 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 881 /* Make sure we're a supported PHY type */ 882 if (hw->phy.type == ixgbe_phy_sfp_intel) { 883 status = IXGBE_SUCCESS; 884 } else { 885 DEBUGOUT("SFP+ module not supported\n"); 886 hw->phy.type = ixgbe_phy_sfp_unsupported; 887 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 888 } 889 } else { 890 status = IXGBE_SUCCESS; 891 } 892 } 893 894out: 895 return (status); 896} 897 898 899/* 900 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 901 * @hw: pointer to hardware structure 902 * @list_offset: offset to the SFP ID list 903 * @data_offset: offset to the SFP data block 904 * 905 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 906 * so it returns the offsets to the phy init sequence block. 907 */ 908s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 909 u16 *list_offset, u16 *data_offset) 910{ 911 u16 sfp_id; 912 913 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 914 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 915 916 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 917 return (IXGBE_ERR_SFP_NOT_PRESENT); 918 919 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 920 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 921 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 922 923 /* Read offset to PHY init contents */ 924 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 925 926 if ((!*list_offset) || (*list_offset == 0xFFFF)) 927 return (IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT); 928 929 /* Shift offset to first ID word */ 930 (*list_offset)++; 931 932 /* 933 * Find the matching SFP ID in the EEPROM 934 * and program the init sequence 935 */ 936 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 937 938 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 939 if (sfp_id == hw->phy.sfp_type) { 940 (*list_offset)++; 941 hw->eeprom.ops.read(hw, *list_offset, data_offset); 942 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 943 DEBUGOUT("SFP+ module not supported\n"); 944 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 945 } else { 946 break; 947 } 948 } else { 949 (*list_offset) += 2; 950 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 951 return (IXGBE_ERR_PHY); 952 } 953 } 954 955 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 956 DEBUGOUT("No matching SFP+ module found\n"); 957 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 958 } 959 960 return (IXGBE_SUCCESS); 961} 962 963/* 964 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 965 * @hw: pointer to hardware structure 966 * @byte_offset: EEPROM byte offset to read 967 * @eeprom_data: value read 968 * 969 * Performs byte read operation to SFP module's EEPROM over I2C interface. 970 */ 971s32 972ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 973 u8 *eeprom_data) 974{ 975 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 976 977 return (hw->phy.ops.read_i2c_byte(hw, byte_offset, 978 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 979} 980 981/* 982 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 983 * @hw: pointer to hardware structure 984 * @byte_offset: EEPROM byte offset to write 985 * @eeprom_data: value to write 986 * 987 * Performs byte write operation to SFP module's EEPROM over I2C interface. 988 */ 989s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 990 u8 eeprom_data) 991{ 992 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 993 994 return (hw->phy.ops.write_i2c_byte(hw, byte_offset, 995 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 996} 997 998/* 999 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1000 * @hw: pointer to hardware structure 1001 * @byte_offset: byte offset to read 1002 * @data: value read 1003 * 1004 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1005 * a specified deivce address. 1006 */ 1007s32 1008ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1009 u8 dev_addr, u8 *data) 1010{ 1011 s32 status = IXGBE_SUCCESS; 1012 u32 max_retry = 1; 1013 u32 retry = 0; 1014 u16 swfw_mask = 0; 1015 bool nack = 1; 1016 1017 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1018 1019 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1020 swfw_mask = IXGBE_GSSR_PHY1_SM; 1021 else 1022 swfw_mask = IXGBE_GSSR_PHY0_SM; 1023 1024 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1025 status = IXGBE_ERR_SWFW_SYNC; 1026 goto read_byte_out; 1027 } 1028 1029 do { 1030 ixgbe_i2c_start(hw); 1031 1032 /* Device Address and write indication */ 1033 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1034 if (status != IXGBE_SUCCESS) 1035 goto fail; 1036 1037 status = ixgbe_get_i2c_ack(hw); 1038 if (status != IXGBE_SUCCESS) 1039 goto fail; 1040 1041 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1042 if (status != IXGBE_SUCCESS) 1043 goto fail; 1044 1045 status = ixgbe_get_i2c_ack(hw); 1046 if (status != IXGBE_SUCCESS) 1047 goto fail; 1048 1049 ixgbe_i2c_start(hw); 1050 1051 /* Device Address and read indication */ 1052 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1053 if (status != IXGBE_SUCCESS) 1054 goto fail; 1055 1056 status = ixgbe_get_i2c_ack(hw); 1057 if (status != IXGBE_SUCCESS) 1058 goto fail; 1059 1060 status = ixgbe_clock_in_i2c_byte(hw, data); 1061 if (status != IXGBE_SUCCESS) 1062 goto fail; 1063 1064 status = ixgbe_clock_out_i2c_bit(hw, nack); 1065 if (status != IXGBE_SUCCESS) 1066 goto fail; 1067 1068 ixgbe_i2c_stop(hw); 1069 break; 1070 1071fail: 1072 ixgbe_i2c_bus_clear(hw); 1073 retry++; 1074 if (retry < max_retry) 1075 DEBUGOUT("I2C byte read error - Retrying.\n"); 1076 else 1077 DEBUGOUT("I2C byte read error.\n"); 1078 } while (retry < max_retry); 1079 1080 ixgbe_release_swfw_sync(hw, swfw_mask); 1081 1082read_byte_out: 1083 return (status); 1084} 1085 1086/* 1087 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1088 * @hw: pointer to hardware structure 1089 * @byte_offset: byte offset to write 1090 * @data: value to write 1091 * 1092 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1093 * a specified device address. 1094 */ 1095s32 1096ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1097 u8 dev_addr, u8 data) 1098{ 1099 s32 status = IXGBE_SUCCESS; 1100 u32 max_retry = 1; 1101 u32 retry = 0; 1102 u16 swfw_mask = 0; 1103 1104 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1105 1106 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1107 swfw_mask = IXGBE_GSSR_PHY1_SM; 1108 else 1109 swfw_mask = IXGBE_GSSR_PHY0_SM; 1110 1111 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1112 status = IXGBE_ERR_SWFW_SYNC; 1113 goto write_byte_out; 1114 } 1115 1116 do { 1117 ixgbe_i2c_start(hw); 1118 1119 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1120 if (status != IXGBE_SUCCESS) 1121 goto fail; 1122 1123 status = ixgbe_get_i2c_ack(hw); 1124 if (status != IXGBE_SUCCESS) 1125 goto fail; 1126 1127 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1128 if (status != IXGBE_SUCCESS) 1129 goto fail; 1130 1131 status = ixgbe_get_i2c_ack(hw); 1132 if (status != IXGBE_SUCCESS) 1133 goto fail; 1134 1135 status = ixgbe_clock_out_i2c_byte(hw, data); 1136 if (status != IXGBE_SUCCESS) 1137 goto fail; 1138 1139 status = ixgbe_get_i2c_ack(hw); 1140 if (status != IXGBE_SUCCESS) 1141 goto fail; 1142 1143 ixgbe_i2c_stop(hw); 1144 break; 1145 1146fail: 1147 ixgbe_i2c_bus_clear(hw); 1148 retry++; 1149 if (retry < max_retry) 1150 DEBUGOUT("I2C byte write error - Retrying.\n"); 1151 else 1152 DEBUGOUT("I2C byte write error.\n"); 1153 } while (retry < max_retry); 1154 1155 ixgbe_release_swfw_sync(hw, swfw_mask); 1156 1157write_byte_out: 1158 return (status); 1159} 1160 1161/* 1162 * ixgbe_i2c_start - Sets I2C start condition 1163 * @hw: pointer to hardware structure 1164 * 1165 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1166 */ 1167static void 1168ixgbe_i2c_start(struct ixgbe_hw *hw) 1169{ 1170 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1171 1172 DEBUGFUNC("ixgbe_i2c_start"); 1173 1174 /* Start condition must begin with data and clock high */ 1175 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1176 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1177 1178 /* Setup time for start condition (4.7us) */ 1179 usec_delay(IXGBE_I2C_T_SU_STA); 1180 1181 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1182 1183 /* Hold time for start condition (4us) */ 1184 usec_delay(IXGBE_I2C_T_HD_STA); 1185 1186 ixgbe_lower_i2c_clk(hw, &i2cctl); 1187 1188 /* Minimum low period of clock is 4.7 us */ 1189 usec_delay(IXGBE_I2C_T_LOW); 1190} 1191 1192/* 1193 * ixgbe_i2c_stop - Sets I2C stop condition 1194 * @hw: pointer to hardware structure 1195 * 1196 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1197 */ 1198static void 1199ixgbe_i2c_stop(struct ixgbe_hw *hw) 1200{ 1201 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1202 1203 DEBUGFUNC("ixgbe_i2c_stop"); 1204 1205 /* Stop condition must begin with data low and clock high */ 1206 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1207 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1208 1209 /* Setup time for stop condition (4us) */ 1210 usec_delay(IXGBE_I2C_T_SU_STO); 1211 1212 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1213 1214 /* bus free time between stop and start (4.7us) */ 1215 usec_delay(IXGBE_I2C_T_BUF); 1216} 1217 1218/* 1219 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1220 * @hw: pointer to hardware structure 1221 * @data: data byte to clock in 1222 * 1223 * Clocks in one byte data via I2C data/clock 1224 */ 1225static s32 1226ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1227{ 1228 s32 status = IXGBE_SUCCESS; 1229 s32 i; 1230 bool bit = 0; 1231 1232 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1233 1234 for (i = 7; i >= 0; i--) { 1235 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1236 *data |= bit<<i; 1237 1238 if (status != IXGBE_SUCCESS) 1239 break; 1240 } 1241 1242 return (status); 1243} 1244 1245/* 1246 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1247 * @hw: pointer to hardware structure 1248 * @data: data byte clocked out 1249 * 1250 * Clocks out one byte data via I2C data/clock 1251 */ 1252static s32 1253ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1254{ 1255 s32 status = IXGBE_SUCCESS; 1256 s32 i; 1257 u32 i2cctl; 1258 bool bit = 0; 1259 1260 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1261 1262 for (i = 7; i >= 0; i--) { 1263 bit = (data >> i) & 0x1; 1264 status = ixgbe_clock_out_i2c_bit(hw, bit); 1265 1266 if (status != IXGBE_SUCCESS) 1267 break; 1268 } 1269 1270 /* Release SDA line (set high) */ 1271 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1272 i2cctl |= IXGBE_I2C_DATA_OUT; 1273 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1274 1275 return (status); 1276} 1277 1278/* 1279 * ixgbe_get_i2c_ack - Polls for I2C ACK 1280 * @hw: pointer to hardware structure 1281 * 1282 * Clocks in/out one bit via I2C data/clock 1283 */ 1284static s32 1285ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1286{ 1287 s32 status; 1288 u32 i = 0; 1289 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1290 u32 timeout = 10; 1291 bool ack = 1; 1292 1293 DEBUGFUNC("ixgbe_get_i2c_ack"); 1294 1295 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1296 1297 if (status != IXGBE_SUCCESS) 1298 goto out; 1299 1300 /* Minimum high period of clock is 4us */ 1301 usec_delay(IXGBE_I2C_T_HIGH); 1302 1303 /* 1304 * Poll for ACK. Note that ACK in I2C spec is 1305 * transition from 1 to 0 1306 */ 1307 for (i = 0; i < timeout; i++) { 1308 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1309 ack = ixgbe_get_i2c_data(&i2cctl); 1310 1311 usec_delay(1); 1312 if (ack == 0) 1313 break; 1314 } 1315 1316 if (ack == 1) { 1317 DEBUGOUT("I2C ack was not received.\n"); 1318 status = IXGBE_ERR_I2C; 1319 } 1320 1321 ixgbe_lower_i2c_clk(hw, &i2cctl); 1322 1323 /* Minimum low period of clock is 4.7 us */ 1324 usec_delay(IXGBE_I2C_T_LOW); 1325 1326out: 1327 return (status); 1328} 1329 1330/* 1331 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1332 * @hw: pointer to hardware structure 1333 * @data: read data value 1334 * 1335 * Clocks in one bit via I2C data/clock 1336 */ 1337static s32 1338ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1339{ 1340 s32 status; 1341 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1342 1343 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1344 1345 /* Minimum high period of clock is 4us */ 1346 usec_delay(IXGBE_I2C_T_HIGH); 1347 1348 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1349 *data = ixgbe_get_i2c_data(&i2cctl); 1350 1351 ixgbe_lower_i2c_clk(hw, &i2cctl); 1352 1353 /* Minimum low period of clock is 4.7 us */ 1354 usec_delay(IXGBE_I2C_T_LOW); 1355 1356 return (status); 1357} 1358 1359/* 1360 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1361 * @hw: pointer to hardware structure 1362 * @data: data value to write 1363 * 1364 * Clocks out one bit via I2C data/clock 1365 */ 1366static s32 1367ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1368{ 1369 s32 status; 1370 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1371 1372 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1373 if (status == IXGBE_SUCCESS) { 1374 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1375 1376 /* Minimum high period of clock is 4us */ 1377 usec_delay(IXGBE_I2C_T_HIGH); 1378 1379 ixgbe_lower_i2c_clk(hw, &i2cctl); 1380 1381 /* 1382 * Minimum low period of clock is 4.7 us. 1383 * This also takes care of the data hold time. 1384 */ 1385 usec_delay(IXGBE_I2C_T_LOW); 1386 } else { 1387 status = IXGBE_ERR_I2C; 1388 DEBUGOUT1("I2C data was not set to %X\n", data); 1389 } 1390 1391 return (status); 1392} 1393 1394/* 1395 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1396 * @hw: pointer to hardware structure 1397 * @i2cctl: Current value of I2CCTL register 1398 * 1399 * Raises the I2C clock line '0'->'1' 1400 */ 1401static s32 1402ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1403{ 1404 s32 status = IXGBE_SUCCESS; 1405 1406 *i2cctl |= IXGBE_I2C_CLK_OUT; 1407 1408 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1409 1410 /* SCL rise time (1000ns) */ 1411 usec_delay(IXGBE_I2C_T_RISE); 1412 1413 return (status); 1414} 1415 1416/* 1417 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1418 * @hw: pointer to hardware structure 1419 * @i2cctl: Current value of I2CCTL register 1420 * 1421 * Lowers the I2C clock line '1'->'0' 1422 */ 1423static void 1424ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1425{ 1426 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1427 1428 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1429 1430 /* SCL fall time (300ns) */ 1431 usec_delay(IXGBE_I2C_T_FALL); 1432} 1433 1434/* 1435 * ixgbe_set_i2c_data - Sets the I2C data bit 1436 * @hw: pointer to hardware structure 1437 * @i2cctl: Current value of I2CCTL register 1438 * @data: I2C data value (0 or 1) to set 1439 * 1440 * Sets the I2C data bit 1441 */ 1442static s32 1443ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1444{ 1445 s32 status = IXGBE_SUCCESS; 1446 1447 if (data) 1448 *i2cctl |= IXGBE_I2C_DATA_OUT; 1449 else 1450 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1451 1452 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1453 1454 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1455 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1456 1457 /* Verify data was set correctly */ 1458 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1459 if (data != ixgbe_get_i2c_data(i2cctl)) { 1460 status = IXGBE_ERR_I2C; 1461 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1462 } 1463 1464 return (status); 1465} 1466 1467/* 1468 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1469 * @hw: pointer to hardware structure 1470 * @i2cctl: Current value of I2CCTL register 1471 * 1472 * Returns the I2C data bit value 1473 */ 1474static bool 1475ixgbe_get_i2c_data(u32 *i2cctl) 1476{ 1477 bool data; 1478 1479 if (*i2cctl & IXGBE_I2C_DATA_IN) 1480 data = 1; 1481 else 1482 data = 0; 1483 1484 return (data); 1485} 1486 1487/* 1488 * ixgbe_i2c_bus_clear - Clears the I2C bus 1489 * @hw: pointer to hardware structure 1490 * 1491 * Clears the I2C bus by sending nine clock pulses. 1492 * Used when data line is stuck low. 1493 */ 1494void 1495ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1496{ 1497 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1498 u32 i; 1499 1500 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1501 1502 ixgbe_i2c_start(hw); 1503 1504 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1505 1506 for (i = 0; i < 9; i++) { 1507 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1508 1509 /* Min high period of clock is 4us */ 1510 usec_delay(IXGBE_I2C_T_HIGH); 1511 1512 ixgbe_lower_i2c_clk(hw, &i2cctl); 1513 1514 /* Min low period of clock is 4.7us */ 1515 usec_delay(IXGBE_I2C_T_LOW); 1516 } 1517 1518 ixgbe_i2c_start(hw); 1519 1520 /* Put the i2c bus back to default state */ 1521 ixgbe_i2c_stop(hw); 1522} 1523