hxge_impl.h revision 6349:b4971e04f83d
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_HXGE_HXGE_IMPL_H 27#define _SYS_HXGE_HXGE_IMPL_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#ifndef _ASM 36#include <sys/types.h> 37#include <sys/byteorder.h> 38#include <sys/debug.h> 39#include <sys/stropts.h> 40#include <sys/stream.h> 41#include <sys/strlog.h> 42#include <sys/strsubr.h> 43#include <sys/cmn_err.h> 44#include <sys/vtrace.h> 45#include <sys/kmem.h> 46#include <sys/ddi.h> 47#include <sys/sunddi.h> 48#include <sys/strsun.h> 49#include <sys/stat.h> 50#include <sys/cpu.h> 51#include <sys/kstat.h> 52#include <inet/common.h> 53#include <inet/ip.h> 54#include <inet/ip6.h> 55#include <sys/dlpi.h> 56#include <inet/nd.h> 57#include <netinet/in.h> 58#include <sys/ethernet.h> 59#include <sys/vlan.h> 60#include <sys/pci.h> 61#include <sys/taskq.h> 62#include <sys/atomic.h> 63 64#include <hxge_defs.h> 65#include <hxge_peu.h> 66#include <hxge_pfc.h> 67#include <hxge_pfc_hw.h> 68#include <hxge_vmac.h> 69#include <hxge_fm.h> 70#include <sys/netlb.h> 71#include <sys/ddi_intr.h> 72 73#include <sys/mac.h> 74#include <sys/mac_impl.h> 75#include <sys/mac_ether.h> 76 77/* 78 * Handy macros (taken from bge driver) 79 */ 80#define RBR_SIZE 4 81#define DMA_COMMON_VPTR(area) ((area.kaddrp)) 82#define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 83#define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 84#define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 85#define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 86 (area).offset, (area).alength, \ 87 (flag))) 88#define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 89 ((void) ddi_dma_sync((area).dma_handle,\ 90 (area.offset + bufoffset), len, \ 91 (flag))) 92 93#define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 94#define NEXT_ENTRY_PTR(ptr, first, last) \ 95 ((ptr == last) ? first : (ptr + 1)) 96 97/* 98 * HPI related macros 99 */ 100#define HXGE_DEV_HPI_HANDLE(hxgep) (hxgep->hpi_handle) 101 102#define HPI_PCI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_pci_handle.regh = ah) 103#define HPI_PCI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_pci_handle.regp = ap) 104 105#define HPI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_handle.regh = ah) 106#define HPI_ADD_HANDLE_SET(hxgep, ap) \ 107 hxgep->hpi_handle.is_vraddr = B_FALSE; \ 108 hxgep->hpi_handle.function.instance = hxgep->instance; \ 109 hxgep->hpi_handle.function.function = 0; \ 110 hxgep->hpi_handle.hxgep = (void *) hxgep; \ 111 hxgep->hpi_handle.regp = ap; 112 113#define HPI_REG_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_reg_handle.regh = ah) 114#define HPI_REG_ADD_HANDLE_SET(hxgep, ap) \ 115 hxgep->hpi_reg_handle.is_vraddr = B_FALSE; \ 116 hxgep->hpi_handle.function.instance = hxgep->instance; \ 117 hxgep->hpi_handle.function.function = 0; \ 118 hxgep->hpi_reg_handle.hxgep = (void *) hxgep; \ 119 hxgep->hpi_reg_handle.regp = ap; 120 121#define HPI_MSI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_msi_handle.regh = ah) 122#define HPI_MSI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_msi_handle.regp = ap) 123 124#define HPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->hpi_handle.regh = ah) 125#define HPI_DMA_ACC_HANDLE_GET(dmap) (dmap->hpi_handle.regh) 126 127#define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 128 129typedef uint32_t hxge_status_t; 130 131typedef enum { 132 DVMA, 133 DMA, 134 SDMA 135} dma_method_t; 136 137typedef enum { 138 BKSIZE_4K, 139 BKSIZE_8K, 140 BKSIZE_16K, 141 BKSIZE_32K 142} hxge_rx_block_size_t; 143 144#ifdef TX_ONE_BUF 145#define TX_BCOPY_MAX 1514 146#else 147#define TX_BCOPY_MAX 2048 148#define TX_BCOPY_SIZE 2048 149#endif 150 151#define TX_STREAM_MIN 512 152#define TX_FASTDVMA_MIN 1024 153 154#define HXGE_RDC_RCR_THRESHOLD_MAX 256 155#define HXGE_RDC_RCR_TIMEOUT_MAX 64 156#define HXGE_RDC_RCR_THRESHOLD_MIN 1 157#define HXGE_RDC_RCR_TIMEOUT_MIN 1 158 159#define HXGE_IS_VLAN_PACKET(ptr) \ 160 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 161 htons(VLAN_ETHERTYPE)) 162 163typedef enum { 164 USE_NONE, 165 USE_BCOPY, 166 USE_DVMA, 167 USE_DMA, 168 USE_SDMA 169} dma_type_t; 170 171struct _hxge_block_mv_t { 172 uint32_t msg_type; 173 dma_type_t dma_type; 174}; 175 176typedef struct _hxge_block_mv_t hxge_block_mv_t, *p_hxge_block_mv_t; 177 178typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 179typedef struct ether_header ether_header_t, *p_ether_header_t; 180typedef queue_t *p_queue_t; 181typedef mblk_t *p_mblk_t; 182 183/* 184 * Common DMA data elements. 185 */ 186struct _hxge_dma_common_t { 187 uint16_t dma_channel; 188 void *kaddrp; 189 void *ioaddr_pp; 190 ddi_dma_cookie_t dma_cookie; 191 uint32_t ncookies; 192 193 ddi_dma_handle_t dma_handle; 194 hxge_os_acc_handle_t acc_handle; 195 hpi_handle_t hpi_handle; 196 197 size_t block_size; 198 uint32_t nblocks; 199 size_t alength; 200 uint_t offset; 201 uint_t dma_chunk_index; 202 void *orig_ioaddr_pp; 203 uint64_t orig_vatopa; 204 void *orig_kaddrp; 205 size_t orig_alength; 206 boolean_t contig_alloc_type; 207}; 208 209typedef struct _hxge_t hxge_t, *p_hxge_t; 210typedef struct _hxge_dma_common_t hxge_dma_common_t, *p_hxge_dma_common_t; 211 212typedef struct _hxge_dma_pool_t { 213 p_hxge_dma_common_t *dma_buf_pool_p; 214 uint32_t ndmas; 215 uint32_t *num_chunks; 216 boolean_t buf_allocated; 217} hxge_dma_pool_t, *p_hxge_dma_pool_t; 218 219/* 220 * Each logical device (69): 221 * - LDG # 222 * - flag bits 223 * - masks. 224 * - interrupt handler function. 225 * 226 * Generic system interrupt handler with two arguments: 227 * (hxge_sys_intr_t) 228 * Per device instance data structure 229 * Logical group data structure. 230 * 231 * Logical device interrupt handler with two arguments: 232 * (hxge_ldv_intr_t) 233 * Per device instance data structure 234 * Logical device number 235 */ 236typedef struct _hxge_ldg_t hxge_ldg_t, *p_hxge_ldg_t; 237typedef struct _hxge_ldv_t hxge_ldv_t, *p_hxge_ldv_t; 238typedef uint_t (*hxge_sys_intr_t)(caddr_t arg1, caddr_t arg2); 239typedef uint_t (*hxge_ldv_intr_t)(caddr_t arg1, caddr_t arg2); 240 241/* 242 * Each logical device Group (64) needs to have the following 243 * configurations: 244 * - timer counter (6 bits) 245 * - timer resolution (20 bits, number of system clocks) 246 * - system data (7 bits) 247 */ 248struct _hxge_ldg_t { 249 uint8_t ldg; /* logical group number */ 250 uint8_t vldg_index; 251 boolean_t arm; 252 boolean_t interrupted; 253 uint16_t ldg_timer; /* counter */ 254 uint8_t vector; 255 uint8_t nldvs; 256 p_hxge_ldv_t ldvp; 257 hxge_sys_intr_t sys_intr_handler; 258 p_hxge_t hxgep; 259}; 260 261struct _hxge_ldv_t { 262 uint8_t ldg_assigned; 263 uint8_t ldv; 264 boolean_t is_rxdma; 265 boolean_t is_txdma; 266 boolean_t is_vmac; 267 boolean_t is_syserr; 268 boolean_t is_pfc; 269 boolean_t use_timer; 270 uint8_t channel; 271 uint8_t vdma_index; 272 p_hxge_ldg_t ldgp; 273 uint8_t ldv_ldf_masks; 274 hxge_ldv_intr_t ldv_intr_handler; 275 p_hxge_t hxgep; 276}; 277 278typedef struct _pci_cfg_t { 279 uint16_t vendorid; 280 uint16_t devid; 281 uint16_t command; 282 uint16_t status; 283 uint8_t revid; 284 uint8_t res0; 285 uint16_t junk1; 286 uint8_t cache_line; 287 uint8_t latency; 288 uint8_t header; 289 uint8_t bist; 290 uint32_t base; 291 uint32_t base14; 292 uint32_t base18; 293 uint32_t base1c; 294 uint32_t base20; 295 uint32_t base24; 296 uint32_t base28; 297 uint32_t base2c; 298 uint32_t base30; 299 uint32_t res1[2]; 300 uint8_t int_line; 301 uint8_t int_pin; 302 uint8_t min_gnt; 303 uint8_t max_lat; 304} pci_cfg_t, *p_pci_cfg_t; 305 306typedef struct _dev_regs_t { 307 hxge_os_acc_handle_t hxge_pciregh; /* PCI config DDI IO handle */ 308 p_pci_cfg_t hxge_pciregp; /* mapped PCI registers */ 309 310 hxge_os_acc_handle_t hxge_regh; /* device DDI IO (BAR 0) */ 311 void *hxge_regp; /* mapped device registers */ 312 313 hxge_os_acc_handle_t hxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 314 void *hxge_msix_regp; /* MSI/X register */ 315 316 hxge_os_acc_handle_t hxge_romh; /* fcode rom handle */ 317 unsigned char *hxge_romp; /* fcode pointer */ 318} dev_regs_t, *p_dev_regs_t; 319 320typedef struct _nxge_mac_addr_t { 321 ether_addr_t addr; 322 uint_t flags; 323} hxge_mac_addr_t; 324 325/* 326 * Driver alternate mac address structure. 327 */ 328typedef struct _hxge_mmac_t { 329 uint8_t total_factory_macs; 330 uint8_t num_mmac; 331 uint8_t num_factory_mmac; 332 hxge_mac_addr_t mac_pool[16]; 333 ether_addr_t factory_mac_pool[16]; 334 uint8_t naddrfree; /* number of alt mac addr available */ 335} hxge_mmac_t; 336 337/* 338 * mmac stats structure 339 */ 340typedef struct _hxge_mmac_stats_t { 341 uint8_t mmac_max_cnt; 342 uint8_t mmac_avail_cnt; 343 struct ether_addr mmac_avail_pool[16]; 344} hxge_mmac_stats_t, *p_hxge_mmac_stats_t; 345 346#include <hxge_common_impl.h> 347#include <hxge_common.h> 348#include <hxge_rxdma.h> 349#include <hxge_txdma.h> 350#include <hxge_fzc.h> 351#include <hxge_flow.h> 352#include <hxge_virtual.h> 353#include <hxge.h> 354#include <sys/modctl.h> 355#include <sys/pattr.h> 356#include <hpi_vir.h> 357 358/* 359 * Reconfiguring the network devices requires the net_config privilege 360 * in Solaris 10+. Prior to this, root privilege is required. In order 361 * that the driver binary can run on both S10+ and earlier versions, we 362 * make the decisiion as to which to use at runtime. These declarations 363 * allow for either (or both) to exist ... 364 */ 365extern int secpolicy_net_config(const cred_t *, boolean_t); 366extern void hxge_fm_report_error(p_hxge_t hxgep, 367 uint8_t err_chan, hxge_fm_ereport_id_t fm_ereport_id); 368extern int fm_check_acc_handle(ddi_acc_handle_t); 369extern int fm_check_dma_handle(ddi_dma_handle_t); 370 371#pragma weak secpolicy_net_config 372 373hxge_status_t hxge_classify_init(p_hxge_t hxgep); 374hxge_status_t hxge_classify_uninit(p_hxge_t hxgep); 375void hxge_put_tcam(p_hxge_t hxgep, p_mblk_t mp); 376void hxge_get_tcam(p_hxge_t hxgep, p_mblk_t mp); 377 378hxge_status_t hxge_classify_init_hw(p_hxge_t hxgep); 379hxge_status_t hxge_classify_init_sw(p_hxge_t hxgep); 380hxge_status_t hxge_classify_exit_sw(p_hxge_t hxgep); 381hxge_status_t hxge_pfc_ip_class_config_all(p_hxge_t hxgep); 382hxge_status_t hxge_pfc_ip_class_config(p_hxge_t hxgep, tcam_class_t l3_class, 383 uint32_t class_config); 384hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t hxgep, 385 tcam_class_t l3_class, uint32_t *class_config); 386 387hxge_status_t hxge_pfc_set_hash(p_hxge_t, uint32_t); 388hxge_status_t hxge_pfc_config_tcam_enable(p_hxge_t); 389hxge_status_t hxge_pfc_config_tcam_disable(p_hxge_t); 390hxge_status_t hxge_pfc_ip_class_config(p_hxge_t, tcam_class_t, uint32_t); 391hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t, tcam_class_t, uint32_t *); 392hxge_status_t hxge_pfc_num_macs_get(p_hxge_t, uint32_t *); 393hxge_status_t hxge_pfc_mac_addrs_get(p_hxge_t hxgep); 394 395 396hxge_status_t hxge_pfc_hw_reset(p_hxge_t hxgep); 397hxge_status_t hxge_pfc_handle_sys_errors(p_hxge_t hxgep); 398 399/* hxge_kstats.c */ 400void hxge_init_statsp(p_hxge_t); 401void hxge_setup_kstats(p_hxge_t); 402void hxge_destroy_kstats(p_hxge_t); 403int hxge_port_kstat_update(kstat_t *, int); 404 405int hxge_m_stat(void *arg, uint_t stat, uint64_t *val); 406 407/* hxge_hw.c */ 408void 409hxge_hw_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 410void hxge_loopback_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 411void hxge_global_reset(p_hxge_t); 412uint_t hxge_intr(caddr_t arg1, caddr_t arg2); 413void hxge_intr_enable(p_hxge_t hxgep); 414void hxge_intr_disable(p_hxge_t hxgep); 415void hxge_hw_id_init(p_hxge_t hxgep); 416void hxge_hw_init_niu_common(p_hxge_t hxgep); 417void hxge_intr_hw_enable(p_hxge_t hxgep); 418void hxge_intr_hw_disable(p_hxge_t hxgep); 419void hxge_hw_stop(p_hxge_t hxgep); 420void hxge_global_reset(p_hxge_t hxgep); 421void hxge_check_hw_state(p_hxge_t hxgep); 422 423/* hxge_send.c. */ 424uint_t hxge_reschedule(caddr_t arg); 425 426/* hxge_ndd.c */ 427void hxge_get_param_soft_properties(p_hxge_t); 428void hxge_setup_param(p_hxge_t); 429void hxge_init_param(p_hxge_t); 430void hxge_destroy_param(p_hxge_t); 431boolean_t hxge_check_rxdma_port_member(p_hxge_t, uint8_t); 432boolean_t hxge_check_txdma_port_member(p_hxge_t, uint8_t); 433int hxge_param_get_generic(p_hxge_t, queue_t *, mblk_t *, caddr_t); 434int hxge_param_set_generic(p_hxge_t, queue_t *, mblk_t *, char *, caddr_t); 435int hxge_get_default(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 436int hxge_set_default(p_hxge_t, queue_t *, p_mblk_t, char *, caddr_t); 437int hxge_nd_get_names(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 438int hxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size); 439void hxge_param_ioctl(p_hxge_t hxgep, queue_t *, mblk_t *, struct iocblk *); 440boolean_t hxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 441void hxge_nd_free(caddr_t *); 442int hxge_nd_getset(p_hxge_t, queue_t *, caddr_t, p_mblk_t); 443boolean_t hxge_set_lb(p_hxge_t, queue_t *wq, p_mblk_t mp); 444 445/* hxge_virtual.c */ 446hxge_status_t hxge_get_config_properties(p_hxge_t); 447hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, 448 p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p); 449hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 450 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 451hxge_status_t hxge_init_fzc_rx_common(p_hxge_t hxgep); 452hxge_status_t hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep, 453 uint16_t channel, p_rx_rbr_ring_t rbr_p); 454hxge_status_t hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, 455 uint16_t channel, p_tx_ring_t tx_ring_p); 456hxge_status_t hxge_intr_mask_mgmt_set(p_hxge_t hxgep, boolean_t on); 457 458/* MAC functions */ 459hxge_status_t hxge_vmac_init(p_hxge_t hxgep); 460hxge_status_t hxge_link_init(p_hxge_t hxgep); 461hxge_status_t hxge_tx_vmac_init(p_hxge_t hxgep); 462hxge_status_t hxge_rx_vmac_init(p_hxge_t hxgep); 463hxge_status_t hxge_tx_vmac_enable(p_hxge_t hxgep); 464hxge_status_t hxge_tx_vmac_disable(p_hxge_t hxgep); 465hxge_status_t hxge_rx_vmac_enable(p_hxge_t hxgep); 466hxge_status_t hxge_rx_vmac_disable(p_hxge_t hxgep); 467hxge_status_t hxge_tx_vmac_reset(p_hxge_t hxgep); 468hxge_status_t hxge_rx_vmac_reset(p_hxge_t hxgep); 469hxge_status_t hxge_add_mcast_addr(p_hxge_t, struct ether_addr *); 470hxge_status_t hxge_del_mcast_addr(p_hxge_t, struct ether_addr *); 471hxge_status_t hxge_set_mac_addr(p_hxge_t hxgep, struct ether_addr *addr); 472hxge_status_t hxge_set_promisc(p_hxge_t hxgep, boolean_t on); 473void hxge_save_cntrs(p_hxge_t hxgep); 474 475void hxge_debug_msg(p_hxge_t, uint64_t, char *, ...); 476 477#ifdef HXGE_DEBUG 478char *hxge_dump_packet(char *addr, int size); 479#endif 480 481#endif /* !_ASM */ 482 483#ifdef __cplusplus 484} 485#endif 486 487#endif /* _SYS_HXGE_HXGE_IMPL_H */ 488