e1000g_sw.h revision 7656:2621e50fdf4a
1/* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _E1000G_SW_H 27#define _E1000G_SW_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33/* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45#include <sys/types.h> 46#include <sys/conf.h> 47#include <sys/debug.h> 48#include <sys/stropts.h> 49#include <sys/stream.h> 50#include <sys/strsun.h> 51#include <sys/strlog.h> 52#include <sys/kmem.h> 53#include <sys/stat.h> 54#include <sys/kstat.h> 55#include <sys/modctl.h> 56#include <sys/errno.h> 57#include <sys/mac.h> 58#include <sys/mac_ether.h> 59#include <sys/vlan.h> 60#include <sys/ddi.h> 61#include <sys/sunddi.h> 62#include <sys/disp.h> 63#include <sys/pci.h> 64#include <sys/sdt.h> 65#include <sys/ethernet.h> 66#include <sys/pattr.h> 67#include <sys/strsubr.h> 68#include <sys/netlb.h> 69#include <inet/common.h> 70#include <inet/ip.h> 71#include <inet/tcp.h> 72#include <inet/mi.h> 73#include <inet/nd.h> 74#include <sys/ddifm.h> 75#include <sys/fm/protocol.h> 76#include <sys/fm/util.h> 77#include <sys/fm/io/ddi.h> 78#include "e1000_api.h" 79 80#define JUMBO_FRAG_LENGTH 4096 81 82#define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 83#define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 84#define MAX_NUM_MULTICAST_ADDRESSES 256 85 86/* 87 * MAX_COOKIES = max_packet_size/page_size + one for cross page split 88 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 89 * two for the workaround of the 82546 chip 90 */ 91#define MAX_COOKIES 18 92#define MAX_TX_DESC_PER_PACKET 21 93 94/* 95 * constants used in setting flow control thresholds 96 */ 97#define E1000_PBA_10K 0x000A 98#define E1000_PBA_MASK 0xffff 99#define E1000_PBA_SHIFT 10 100#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 101#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 102#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 103 104#define MAX_NUM_TX_DESCRIPTOR 4096 105#define MAX_NUM_RX_DESCRIPTOR 4096 106#define MAX_NUM_RX_FREELIST 4096 107#define MAX_NUM_TX_FREELIST 4096 108#define MAX_RX_LIMIT_ON_INTR 4096 109#define MAX_RX_INTR_DELAY 65535 110#define MAX_RX_INTR_ABS_DELAY 65535 111#define MAX_TX_INTR_DELAY 65535 112#define MAX_TX_INTR_ABS_DELAY 65535 113#define MAX_INTR_THROTTLING 65535 114#define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 115#define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 116#define MAX_TX_RECYCLE_THRESHOLD MAX_NUM_TX_DESCRIPTOR 117#define MAX_TX_RECYCLE_NUM MAX_NUM_TX_DESCRIPTOR 118 119#define MIN_NUM_TX_DESCRIPTOR 80 120#define MIN_NUM_RX_DESCRIPTOR 80 121#define MIN_NUM_RX_FREELIST 64 122#define MIN_NUM_TX_FREELIST 80 123#define MIN_RX_LIMIT_ON_INTR 16 124#define MIN_RX_INTR_DELAY 0 125#define MIN_RX_INTR_ABS_DELAY 0 126#define MIN_TX_INTR_DELAY 0 127#define MIN_TX_INTR_ABS_DELAY 0 128#define MIN_INTR_THROTTLING 0 129#define MIN_RX_BCOPY_THRESHOLD 0 130#define MIN_TX_BCOPY_THRESHOLD ETHERMIN 131#define MIN_TX_RECYCLE_THRESHOLD 0 132#define MIN_TX_RECYCLE_NUM MAX_TX_DESC_PER_PACKET 133 134#define DEFAULT_NUM_RX_DESCRIPTOR 2048 135#define DEFAULT_NUM_TX_DESCRIPTOR 2048 136#define DEFAULT_NUM_RX_FREELIST 4096 137#define DEFAULT_NUM_TX_FREELIST 2304 138#define DEFAULT_RX_LIMIT_ON_INTR 128 139 140#ifdef __sparc 141#define MAX_INTR_PER_SEC 7100 142#define MIN_INTR_PER_SEC 3000 143#define DEFAULT_INTR_PACKET_LOW 5 144#define DEFAULT_INTR_PACKET_HIGH 128 145#define DEFAULT_TX_RECYCLE_THRESHOLD 512 146#else 147#define MAX_INTR_PER_SEC 15000 148#define MIN_INTR_PER_SEC 4000 149#define DEFAULT_INTR_PACKET_LOW 10 150#define DEFAULT_INTR_PACKET_HIGH 48 151#define DEFAULT_TX_RECYCLE_THRESHOLD DEFAULT_TX_NO_RESOURCE 152#endif 153 154#define DEFAULT_RX_INTR_DELAY 0 155#define DEFAULT_RX_INTR_ABS_DELAY 64 156#define DEFAULT_TX_INTR_DELAY 64 157#define DEFAULT_TX_INTR_ABS_DELAY 64 158#define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 159#define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 160#define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 161 162#define DEFAULT_RX_BCOPY_THRESHOLD 128 163#define DEFAULT_TX_BCOPY_THRESHOLD 512 164#define DEFAULT_TX_RECYCLE_NUM 64 165#define DEFAULT_TX_UPDATE_THRESHOLD 256 166#define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 167 168#define DEFAULT_TX_INTR_ENABLE 1 169#define DEFAULT_FLOW_CONTROL 3 170#define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 171 /* which is normally 0x040 */ 172#define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 173#define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 174#define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 175#define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 176 177#define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 178 179/* 180 * The size of the receive/transmite buffers 181 */ 182#define E1000_RX_BUFFER_SIZE_2K (2048) 183#define E1000_RX_BUFFER_SIZE_4K (4096) 184#define E1000_RX_BUFFER_SIZE_8K (8192) 185#define E1000_RX_BUFFER_SIZE_16K (16384) 186 187#define E1000_TX_BUFFER_SIZE_2K (2048) 188#define E1000_TX_BUFFER_SIZE_4K (4096) 189#define E1000_TX_BUFFER_SIZE_8K (8192) 190#define E1000_TX_BUFFER_SIZE_16K (16384) 191 192#define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 193 194#define E1000G_RX_SW_FREE 0x0 195#define E1000G_RX_SW_SENDUP 0x1 196#define E1000G_RX_SW_STOP 0x2 197#define E1000G_RX_SW_DETACH 0x3 198 199/* 200 * definitions for smartspeed workaround 201 */ 202#define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 203 /* or 30 seconds */ 204#define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 205 /* or 6 seconds */ 206 207/* 208 * Definitions for module_info. 209 */ 210#define WSNAME "e1000g" /* module name */ 211 212/* 213 * Defined for IP header alignment. We also need to preserve space for 214 * VLAN tag (4 bytes) 215 */ 216#define E1000G_IPALIGNROOM 6 217#define E1000G_IPALIGNPRESERVEROOM 64 218 219/* 220 * bit flags for 'attach_progress' which is a member variable in struct e1000g 221 */ 222#define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 223#define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 224#define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 225#define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 226#define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 227#define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 228#define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 229#define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 230#define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 231/* 0200 used to be PROGRESS_NDD. Now unused */ 232#define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 233#define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 234#define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 235 236/* 237 * Speed and Duplex Settings 238 */ 239#define GDIAG_10_HALF 1 240#define GDIAG_10_FULL 2 241#define GDIAG_100_HALF 3 242#define GDIAG_100_FULL 4 243#define GDIAG_1000_FULL 6 244#define GDIAG_ANY 7 245 246/* 247 * Coexist Workaround RP: 07/04/03 248 * 82544 Workaround : Co-existence 249 */ 250#define MAX_TX_BUF_SIZE (8 * 1024) 251 252#define ROUNDOFF 0x1000 253 254/* 255 * Defines for Jumbo Frame 256 */ 257#define FRAME_SIZE_UPTO_2K 2048 258#define FRAME_SIZE_UPTO_4K 4096 259#define FRAME_SIZE_UPTO_8K 8192 260#define FRAME_SIZE_UPTO_16K 16384 261#define FRAME_SIZE_UPTO_9K 9234 262 263#define MAXIMUM_MTU 9000 264#define DEFAULT_MTU ETHERMTU 265 266#define DEFAULT_FRAME_SIZE \ 267 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 268#define MAXIMUM_FRAME_SIZE \ 269 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 270 271#define E1000_LSO_MAXLEN 65535 272 273/* Defines for Tx stall check */ 274#define E1000G_STALL_WATCHDOG_COUNT 8 275 276#define MAX_TX_LINK_DOWN_TIMEOUT 8 277 278/* Defines for DVMA */ 279#ifdef __sparc 280#define E1000G_DEFAULT_DVMA_PAGE_NUM 2 281#endif 282 283/* 284 * Loopback definitions 285 */ 286#define E1000G_LB_NONE 0 287#define E1000G_LB_EXTERNAL_1000 1 288#define E1000G_LB_EXTERNAL_100 2 289#define E1000G_LB_EXTERNAL_10 3 290#define E1000G_LB_INTERNAL_PHY 4 291 292/* 293 * Private dip list definitions 294 */ 295#define E1000G_PRIV_DEVI_ATTACH 0x0 296#define E1000G_PRIV_DEVI_DETACH 0x1 297 298/* 299 * Tx descriptor LENGTH field mask 300 */ 301#define E1000G_TBD_LENGTH_MASK 0x000fffff 302 303/* 304 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 305 */ 306#define QUEUE_INIT_LIST(_LH) \ 307 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 308 309/* 310 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 311 */ 312#define IS_QUEUE_EMPTY(_LH) \ 313 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 314 315/* 316 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 317 * not remove the head from the queue. 318 */ 319#define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 320 321/* 322 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 323 */ 324#define QUEUE_REMOVE_HEAD(_LH) \ 325{ \ 326 PSINGLE_LIST_LINK ListElem; \ 327 if (ListElem = (_LH)->Flink) \ 328 { \ 329 if (!((_LH)->Flink = ListElem->Flink)) \ 330 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 331 } \ 332} 333 334/* 335 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 336 * and return it (this differs from QUEUE_REMOVE_HEAD only in 337 * the 1st line). 338 */ 339#define QUEUE_POP_HEAD(_LH) \ 340 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 341 { \ 342 PSINGLE_LIST_LINK ListElem; \ 343 ListElem = (_LH)->Flink; \ 344 if (ListElem) \ 345 { \ 346 (_LH)->Flink = ListElem->Flink; \ 347 if (!(_LH)->Flink) \ 348 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 349 } \ 350 } 351 352/* 353 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 354 * remove the tail from the queue. 355 */ 356#define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 357 358/* 359 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 360 */ 361#define QUEUE_PUSH_TAIL(_LH, _E) \ 362 if ((_LH)->Blink) \ 363 { \ 364 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 365 (PSINGLE_LIST_LINK)(_E); \ 366 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 367 } else { \ 368 (_LH)->Flink = \ 369 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 370 } \ 371 (_E)->Flink = (PSINGLE_LIST_LINK)0; 372 373/* 374 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 375 */ 376#define QUEUE_PUSH_HEAD(_LH, _E) \ 377 if (!((_E)->Flink = (_LH)->Flink)) \ 378 { \ 379 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 380 } \ 381 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 382 383/* 384 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 385 * current element. 386 */ 387#define QUEUE_GET_NEXT(_LH, _E) \ 388 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 389 (0) : ((_E)->Flink)) 390 391/* 392 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 393 */ 394#define QUEUE_APPEND(_LH1, _LH2) \ 395 if ((_LH2)->Flink) { \ 396 if ((_LH1)->Flink) { \ 397 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 398 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 399 } else { \ 400 (_LH1)->Flink = \ 401 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 402 } \ 403 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 404 } 405 406/* 407 * Property lookups 408 */ 409#define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 410 DDI_PROP_DONTPASS, (n)) 411#define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 412 DDI_PROP_DONTPASS, (n), -1) 413 414#ifdef E1000G_DEBUG 415/* 416 * E1000G-specific ioctls ... 417 */ 418#define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 419 + 'K') << 4) + 'G') << 4) 420 421/* 422 * These diagnostic IOCTLS are enabled only in DEBUG drivers 423 */ 424#define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 425#define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 426#define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 427 428#define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 429#define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 430 431typedef struct { 432 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 433 uint64_t pp_acc_space; /* See #defines below */ 434 uint64_t pp_acc_offset; /* See regs definition */ 435 uint64_t pp_acc_data; /* output for peek */ 436 /* input for poke */ 437} e1000g_peekpoke_t; 438#endif /* E1000G_DEBUG */ 439 440/* 441 * (Internal) return values from ioctl subroutines 442 */ 443enum ioc_reply { 444 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 445 IOC_DONE, /* OK, reply sent */ 446 IOC_ACK, /* OK, just send ACK */ 447 IOC_REPLY /* OK, just send reply */ 448}; 449 450/* 451 * Named Data (ND) Parameter Management Structure 452 */ 453typedef struct { 454 uint32_t ndp_info; 455 uint32_t ndp_min; 456 uint32_t ndp_max; 457 uint32_t ndp_val; 458 struct e1000g *ndp_instance; 459 char *ndp_name; 460} nd_param_t; 461 462/* 463 * The entry of the private dip list 464 */ 465typedef struct _private_devi_list { 466 dev_info_t *priv_dip; 467 uint16_t flag; 468 struct _private_devi_list *next; 469} private_devi_list_t; 470 471/* 472 * A structure that points to the next entry in the queue. 473 */ 474typedef struct _SINGLE_LIST_LINK { 475 struct _SINGLE_LIST_LINK *Flink; 476} SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 477 478/* 479 * A "ListHead" structure that points to the head and tail of a queue 480 */ 481typedef struct _LIST_DESCRIBER { 482 struct _SINGLE_LIST_LINK *volatile Flink; 483 struct _SINGLE_LIST_LINK *volatile Blink; 484} LIST_DESCRIBER, *PLIST_DESCRIBER; 485 486/* 487 * Address-Length pair structure that stores descriptor info 488 */ 489typedef struct _sw_desc { 490 uint64_t address; 491 uint32_t length; 492} sw_desc_t, *p_sw_desc_t; 493 494typedef struct _desc_array { 495 sw_desc_t descriptor[4]; 496 uint32_t elements; 497} desc_array_t, *p_desc_array_t; 498 499typedef enum { 500 USE_NONE, 501 USE_BCOPY, 502 USE_DVMA, 503 USE_DMA 504} dma_type_t; 505 506typedef enum { 507 E1000G_STOP, 508 E1000G_START, 509 E1000G_ERROR 510} chip_state_t; 511 512typedef struct _dma_buffer { 513 caddr_t address; 514 uint64_t dma_address; 515 ddi_acc_handle_t acc_handle; 516 ddi_dma_handle_t dma_handle; 517 size_t size; 518 size_t len; 519} dma_buffer_t, *p_dma_buffer_t; 520 521/* 522 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 523 * structure stores the additional information that is 524 * associated with every packet to be transmitted. It stores the 525 * message block pointer and the TBD addresses associated with 526 * the m_blk and also the link to the next tcb in the chain 527 */ 528typedef struct _tx_sw_packet { 529 /* Link to the next tx_sw_packet in the list */ 530 SINGLE_LIST_LINK Link; 531 mblk_t *mp; 532 uint32_t num_desc; 533 uint32_t num_mblk_frag; 534 dma_type_t dma_type; 535 dma_type_t data_transfer_type; 536 ddi_dma_handle_t tx_dma_handle; 537 dma_buffer_t tx_buf[1]; 538 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 539} tx_sw_packet_t, *p_tx_sw_packet_t; 540 541/* 542 * This structure is similar to the rx_sw_packet structure used 543 * for Ndis. This structure stores information about the 2k 544 * aligned receive buffer into which the FX1000 DMA's frames. 545 * This structure is maintained as a linked list of many 546 * receiver buffer pointers. 547 */ 548typedef struct _rx_sw_packet { 549 /* Link to the next rx_sw_packet_t in the list */ 550 SINGLE_LIST_LINK Link; 551 struct _rx_sw_packet *next; 552 uint16_t flag; 553 mblk_t *mp; 554 caddr_t rx_ring; 555 dma_type_t dma_type; 556 frtn_t free_rtn; 557 dma_buffer_t rx_buf[1]; 558} rx_sw_packet_t, *p_rx_sw_packet_t; 559 560typedef struct _mblk_list { 561 mblk_t *head; 562 mblk_t *tail; 563} mblk_list_t, *p_mblk_list_t; 564 565typedef struct _context_data { 566 uint32_t ether_header_size; 567 uint32_t cksum_flags; 568 uint32_t cksum_start; 569 uint32_t cksum_stuff; 570 uint16_t mss; 571 uint8_t hdr_len; 572 uint32_t pay_len; 573 boolean_t lso_flag; 574} context_data_t; 575 576typedef union _e1000g_ether_addr { 577 struct { 578 uint32_t high; 579 uint32_t low; 580 } reg; 581 struct { 582 uint8_t set; 583 uint8_t redundant; 584 uint8_t addr[ETHERADDRL]; 585 } mac; 586} e1000g_ether_addr_t; 587 588typedef struct _e1000g_stat { 589 590 kstat_named_t link_speed; /* Link Speed */ 591 kstat_named_t reset_count; /* Reset Count */ 592 593 kstat_named_t rx_error; /* Rx Error in Packet */ 594 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 595 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 596 597 kstat_named_t tx_no_desc; /* Tx No Desc */ 598 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 599 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 600 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 601 kstat_named_t tx_reschedule; /* Tx Reschedule */ 602 603#ifdef E1000G_DEBUG 604 kstat_named_t rx_none; /* Rx No Incoming Data */ 605 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 606 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 607 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 608 609 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 610 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 611 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 612 kstat_named_t tx_recycle; /* Tx Recycle */ 613 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 614 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 615 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 616 kstat_named_t tx_copy; /* Tx Send Copy */ 617 kstat_named_t tx_bind; /* Tx Send Bind */ 618 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 619 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 620 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 621#endif 622 623 kstat_named_t Crcerrs; /* CRC Error Count */ 624 kstat_named_t Symerrs; /* Symbol Error Count */ 625 kstat_named_t Mpc; /* Missed Packet Count */ 626 kstat_named_t Scc; /* Single Collision Count */ 627 kstat_named_t Ecol; /* Excessive Collision Count */ 628 kstat_named_t Mcc; /* Multiple Collision Count */ 629 kstat_named_t Latecol; /* Late Collision Count */ 630 kstat_named_t Colc; /* Collision Count */ 631 kstat_named_t Dc; /* Defer Count */ 632 kstat_named_t Sec; /* Sequence Error Count */ 633 kstat_named_t Rlec; /* Receive Length Error Count */ 634 kstat_named_t Xonrxc; /* XON Received Count */ 635 kstat_named_t Xontxc; /* XON Xmitted Count */ 636 kstat_named_t Xoffrxc; /* XOFF Received Count */ 637 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 638 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 639#ifdef E1000G_DEBUG 640 kstat_named_t Prc64; /* Packets Received - 64b */ 641 kstat_named_t Prc127; /* Packets Received - 65-127b */ 642 kstat_named_t Prc255; /* Packets Received - 127-255b */ 643 kstat_named_t Prc511; /* Packets Received - 256-511b */ 644 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 645 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 646#endif 647 kstat_named_t Gprc; /* Good Packets Received Count */ 648 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 649 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 650 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 651 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 652 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 653 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 654 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 655 kstat_named_t Rnbc; /* Receive No Buffers Count */ 656 kstat_named_t Ruc; /* Receive Undersize Count */ 657 kstat_named_t Rfc; /* Receive Frag Count */ 658 kstat_named_t Roc; /* Receive Oversize Count */ 659 kstat_named_t Rjc; /* Receive Jabber Count */ 660 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 661 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 662 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 663 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 664 kstat_named_t Tpr; /* Total Packets Received */ 665 kstat_named_t Tpt; /* Total Packets Xmitted */ 666#ifdef E1000G_DEBUG 667 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 668 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 669 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 670 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 671 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 672 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 673#endif 674 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 675 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 676 kstat_named_t Algnerrc; /* Alignment Error count */ 677 kstat_named_t Tuc; /* Transmit Underrun count */ 678 kstat_named_t Rxerrc; /* Rx Error Count */ 679 kstat_named_t Tncrs; /* Transmit with no CRS */ 680 kstat_named_t Cexterr; /* Carrier Extension Error count */ 681 kstat_named_t Rutec; /* Receive DMA too Early count */ 682 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 683 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 684} e1000g_stat_t, *p_e1000g_stat_t; 685 686typedef struct _e1000g_tx_ring { 687 kmutex_t tx_lock; 688 kmutex_t freelist_lock; 689 kmutex_t usedlist_lock; 690 /* 691 * Descriptor queue definitions 692 */ 693 ddi_dma_handle_t tbd_dma_handle; 694 ddi_acc_handle_t tbd_acc_handle; 695 struct e1000_tx_desc *tbd_area; 696 uint64_t tbd_dma_addr; 697 struct e1000_tx_desc *tbd_first; 698 struct e1000_tx_desc *tbd_last; 699 struct e1000_tx_desc *tbd_oldest; 700 struct e1000_tx_desc *tbd_next; 701 uint32_t tbd_avail; 702 /* 703 * Software packet structures definitions 704 */ 705 p_tx_sw_packet_t packet_area; 706 LIST_DESCRIBER used_list; 707 LIST_DESCRIBER free_list; 708 /* 709 * TCP/UDP Context Data Information 710 */ 711 context_data_t pre_context; 712 /* 713 * Timer definitions for 82547 714 */ 715 timeout_id_t timer_id_82547; 716 boolean_t timer_enable_82547; 717 /* 718 * reschedule when tx resource is available 719 */ 720 boolean_t resched_needed; 721 uint32_t stall_watchdog; 722 uint32_t recycle_fail; 723 mblk_list_t mblks; 724 /* 725 * Statistics 726 */ 727 uint32_t stat_no_swpkt; 728 uint32_t stat_no_desc; 729 uint32_t stat_send_fail; 730 uint32_t stat_reschedule; 731 uint32_t stat_over_size; 732#ifdef E1000G_DEBUG 733 uint32_t stat_under_size; 734 uint32_t stat_exceed_frags; 735 uint32_t stat_empty_frags; 736 uint32_t stat_recycle; 737 uint32_t stat_recycle_intr; 738 uint32_t stat_recycle_retry; 739 uint32_t stat_recycle_none; 740 uint32_t stat_copy; 741 uint32_t stat_bind; 742 uint32_t stat_multi_copy; 743 uint32_t stat_multi_cookie; 744 uint32_t stat_lack_desc; 745#endif 746 /* 747 * Pointer to the adapter 748 */ 749 struct e1000g *adapter; 750} e1000g_tx_ring_t, *pe1000g_tx_ring_t; 751 752typedef struct _e1000g_rx_ring { 753 kmutex_t rx_lock; 754 kmutex_t freelist_lock; 755 /* 756 * Descriptor queue definitions 757 */ 758 ddi_dma_handle_t rbd_dma_handle; 759 ddi_acc_handle_t rbd_acc_handle; 760 struct e1000_rx_desc *rbd_area; 761 uint64_t rbd_dma_addr; 762 struct e1000_rx_desc *rbd_first; 763 struct e1000_rx_desc *rbd_last; 764 struct e1000_rx_desc *rbd_next; 765 /* 766 * Software packet structures definitions 767 */ 768 p_rx_sw_packet_t packet_area; 769 LIST_DESCRIBER recv_list; 770 LIST_DESCRIBER free_list; 771 772 p_rx_sw_packet_t pending_list; 773 uint32_t pending_count; 774 uint32_t avail_freepkt; 775 uint32_t rx_mblk_len; 776 mblk_t *rx_mblk; 777 mblk_t *rx_mblk_tail; 778 /* 779 * Statistics 780 */ 781 uint32_t stat_error; 782 uint32_t stat_esballoc_fail; 783 uint32_t stat_allocb_fail; 784 uint32_t stat_exceed_pkt; 785#ifdef E1000G_DEBUG 786 uint32_t stat_none; 787 uint32_t stat_multi_desc; 788 uint32_t stat_no_freepkt; 789#endif 790 /* 791 * Pointer to the adapter 792 */ 793 struct e1000g *adapter; 794} e1000g_rx_ring_t, *pe1000g_rx_ring_t; 795 796typedef struct e1000g { 797 int instance; 798 dev_info_t *dip; 799 dev_info_t *priv_dip; 800 mac_handle_t mh; 801 mac_resource_handle_t mrh; 802 struct e1000_hw shared; 803 struct e1000g_osdep osdep; 804 805 chip_state_t chip_state; 806 boolean_t e1000g_promisc; 807 boolean_t strip_crc; 808 boolean_t rx_buffer_setup; 809 boolean_t esb2_workaround; 810 link_state_t link_state; 811 uint32_t link_speed; 812 uint32_t link_duplex; 813 uint32_t master_latency_timer; 814 uint32_t smartspeed; /* smartspeed w/a counter */ 815 uint32_t init_count; 816 uint32_t reset_count; 817 uint32_t attach_progress; /* attach tracking */ 818 uint32_t loopback_mode; 819 820 uint32_t tx_desc_num; 821 uint32_t tx_freelist_num; 822 uint32_t rx_desc_num; 823 uint32_t rx_freelist_num; 824 uint32_t tx_buffer_size; 825 uint32_t rx_buffer_size; 826 827 uint32_t tx_link_down_timeout; 828 uint32_t tx_bcopy_thresh; 829 uint32_t rx_limit_onintr; 830 uint32_t rx_bcopy_thresh; 831 uint32_t rx_buf_align; 832 833 boolean_t intr_adaptive; 834 boolean_t tx_intr_enable; 835 uint32_t tx_recycle_thresh; 836 uint32_t tx_recycle_num; 837 uint32_t tx_intr_delay; 838 uint32_t tx_intr_abs_delay; 839 uint32_t rx_intr_delay; 840 uint32_t rx_intr_abs_delay; 841 uint32_t intr_throttling_rate; 842 843 uint32_t default_mtu; 844 uint32_t max_frame_size; 845 uint32_t min_frame_size; 846 847 boolean_t watchdog_timer_enabled; 848 boolean_t watchdog_timer_started; 849 timeout_id_t watchdog_tid; 850 boolean_t link_complete; 851 timeout_id_t link_tid; 852 853 e1000g_rx_ring_t rx_ring[1]; 854 e1000g_tx_ring_t tx_ring[1]; 855 856 /* 857 * Rx and Tx packet count for interrupt adaptive setting 858 */ 859 uint32_t rx_pkt_cnt; 860 uint32_t tx_pkt_cnt; 861 862 /* 863 * The watchdog_lock must be held when updateing the 864 * timeout fields in struct e1000g, that is, 865 * watchdog_tid, watchdog_timer_started. 866 */ 867 kmutex_t watchdog_lock; 868 /* 869 * The link_lock protects the link fields in struct e1000g, 870 * such as link_state, link_speed, link_duplex, link_complete, and 871 * link_tid. 872 */ 873 kmutex_t link_lock; 874 /* 875 * The chip_lock assures that the Rx/Tx process must be 876 * stopped while other functions change the hardware 877 * configuration of e1000g card, such as e1000g_reset(), 878 * e1000g_reset_hw() etc are executed. 879 */ 880 krwlock_t chip_lock; 881 882 boolean_t unicst_init; 883 uint32_t unicst_avail; 884 uint32_t unicst_total; 885 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 886 887 uint32_t mcast_count; 888 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 889 890#ifdef __sparc 891 ulong_t sys_page_sz; 892 uint_t dvma_page_num; 893#endif 894 895 boolean_t msi_enable; 896 boolean_t tx_hcksum_enable; 897 boolean_t lso_enable; 898 boolean_t lso_premature_issue; 899 int intr_type; 900 int intr_cnt; 901 int intr_cap; 902 size_t intr_size; 903 uint_t intr_pri; 904 ddi_intr_handle_t *htable; 905 906 int tx_softint_pri; 907 ddi_softint_handle_t tx_softint_handle; 908 909 kstat_t *e1000g_ksp; 910 911 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 912 uint16_t phy_status; /* contents of PHY_STATUS */ 913 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 914 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 915 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 916 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 917 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 918 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 919 920 /* 921 * FMA capabilities 922 */ 923 int fm_capabilities; 924 925 uint32_t param_en_1000fdx:1, 926 param_en_1000hdx:1, 927 param_en_100fdx:1, 928 param_en_100hdx:1, 929 param_en_10fdx:1, 930 param_en_10hdx:1, 931 param_autoneg_cap:1, 932 param_pause_cap:1, 933 param_asym_pause_cap:1, 934 param_1000fdx_cap:1, 935 param_1000hdx_cap:1, 936 param_100t4_cap:1, 937 param_100fdx_cap:1, 938 param_100hdx_cap:1, 939 param_10fdx_cap:1, 940 param_10hdx_cap:1, 941 param_adv_autoneg:1, 942 param_adv_pause:1, 943 param_adv_asym_pause:1, 944 param_adv_1000fdx:1, 945 param_adv_1000hdx:1, 946 param_adv_100t4:1, 947 param_adv_100fdx:1, 948 param_adv_100hdx:1, 949 param_adv_10fdx:1, 950 param_adv_10hdx:1, 951 param_lp_autoneg:1, 952 param_lp_pause:1, 953 param_lp_asym_pause:1, 954 param_lp_1000fdx:1, 955 param_lp_1000hdx:1, 956 param_lp_100t4:1; 957 958 uint32_t param_lp_100fdx:1, 959 param_lp_100hdx:1, 960 param_lp_10fdx:1, 961 param_lp_10hdx:1, 962 param_pad_to_32:28; 963 964} e1000g_t; 965 966 967/* 968 * Function prototypes 969 */ 970int e1000g_alloc_dma_resources(struct e1000g *Adapter); 971void e1000g_release_dma_resources(struct e1000g *Adapter); 972void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 973void e1000g_tx_setup(struct e1000g *Adapter); 974void e1000g_rx_setup(struct e1000g *Adapter); 975void e1000g_setup_multicast(struct e1000g *Adapter); 976 977int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 978void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 979void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 980uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 981mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 982mblk_t *e1000g_receive(struct e1000g *Adapter); 983void e1000g_rxfree_func(p_rx_sw_packet_t packet); 984 985int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 986int e1000g_init_stats(struct e1000g *Adapter); 987void e1000_tbi_adjust_stats(struct e1000g *Adapter, 988 uint32_t frame_len, uint8_t *mac_addr); 989 990void e1000g_clear_interrupt(struct e1000g *Adapter); 991void e1000g_mask_interrupt(struct e1000g *Adapter); 992void e1000g_clear_all_interrupts(struct e1000g *Adapter); 993void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 994void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 995void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 996void e1000_enable_pciex_master(struct e1000_hw *hw); 997int e1000g_check_acc_handle(ddi_acc_handle_t handle); 998int e1000g_check_dma_handle(ddi_dma_handle_t handle); 999void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1000void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1001int e1000g_reset_link(struct e1000g *Adapter); 1002 1003/* 1004 * Global variables 1005 */ 1006extern boolean_t e1000g_force_detach; 1007extern uint32_t e1000g_mblks_pending; 1008extern krwlock_t e1000g_rx_detach_lock; 1009extern private_devi_list_t *e1000g_private_devi_list; 1010 1011#ifdef __cplusplus 1012} 1013#endif 1014 1015#endif /* _E1000G_SW_H */ 1016