e1000_osdep.c revision 8479:ad81b6a87fd7 
1/*
2 * This file is provided under a CDDLv1 license.  When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 *	http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21/*
22 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
24 */
25
26#include "e1000_osdep.h"
27#include "e1000_api.h"
28
29void
30e1000_pci_set_mwi(struct e1000_hw *hw)
31{
32	uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE;
33
34	e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
35}
36
37void
38e1000_pci_clear_mwi(struct e1000_hw *hw)
39{
40	uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
41
42	e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
43}
44
45void
46e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
47{
48	pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value);
49}
50
51void
52e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
53{
54	*value =
55	    pci_config_get16(OS_DEP(hw)->cfg_handle, reg);
56}
57
58/*
59 * phy_spd_state - set smart-power-down (SPD) state
60 *
61 * This only acts on the 82541/47 family and the 82571/72 family.
62 * For any others, return without doing anything.
63 */
64void
65phy_spd_state(struct e1000_hw *hw, boolean_t enable)
66{
67	int32_t offset;		/* offset to register */
68	uint16_t spd_bit;	/* bit to be set */
69	uint16_t reg;		/* register contents */
70
71	switch (hw->mac.type) {
72	case e1000_82541:
73	case e1000_82547:
74	case e1000_82541_rev_2:
75	case e1000_82547_rev_2:
76		offset = IGP01E1000_GMII_FIFO;
77		spd_bit = IGP01E1000_GMII_SPD;
78		break;
79	case e1000_82571:
80	case e1000_82572:
81		offset = IGP02E1000_PHY_POWER_MGMT;
82		spd_bit = IGP02E1000_PM_SPD;
83		break;
84	default:
85		return;		/* no action */
86	}
87
88	(void) e1000_read_phy_reg(hw, offset, &reg);
89
90	if (enable)
91		reg |= spd_bit;		/* enable: set the spd bit */
92	else
93		reg &= ~spd_bit;	/* disable: clear the spd bit */
94
95	(void) e1000_write_phy_reg(hw, offset, reg);
96}
97
98/*
99 * The real intent of this routine is to return the value from pci-e
100 * config space at offset reg into the capability space.
101 * ICH devices are "PCI Express"-ish.  They have a configuration space,
102 * but do not contain PCI Express Capability registers, so this returns
103 * the equivalent of "not supported"
104 */
105int32_t
106e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
107{
108	*value = pci_config_get16(OS_DEP(hw)->cfg_handle,
109	    PCI_EX_CONF_CAP + reg);
110
111	return (0);
112}
113
114/*
115 * Enables PCI-Express master access.
116 *
117 * hw: Struct containing variables accessed by shared code
118 *
119 * returns: - none.
120 */
121void
122e1000_enable_pciex_master(struct e1000_hw *hw)
123{
124	uint32_t ctrl;
125
126	if (hw->bus.type != e1000_bus_type_pci_express)
127		return;
128
129	ctrl = E1000_READ_REG(hw, E1000_CTRL);
130	ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
131	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
132}
133