qlt.h revision 12314:0ed71edeac88
133965Sjdp/* 2218822Sdim * CDDL HEADER START 3218822Sdim * 433965Sjdp * The contents of this file are subject to the terms of the 533965Sjdp * Common Development and Distribution License (the "License"). 633965Sjdp * You may not use this file except in compliance with the License. 733965Sjdp * 833965Sjdp * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 933965Sjdp * or http://www.opensolaris.org/os/licensing. 1033965Sjdp * See the License for the specific language governing permissions 1133965Sjdp * and limitations under the License. 1233965Sjdp * 1333965Sjdp * When distributing Covered Code, include this CDDL HEADER in each 1433965Sjdp * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1533965Sjdp * If applicable, add the following below this CDDL HEADER, with the 1633965Sjdp * fields enclosed by brackets "[]" replaced with your own identifying 1733965Sjdp * information: Portions Copyright [yyyy] [name of copyright owner] 1833965Sjdp * 1933965Sjdp * CDDL HEADER END 2033965Sjdp */ 21218822Sdim 22218822Sdim/* 2333965Sjdp * Copyright 2009 QLogic Corporation. All rights reserved. 2433965Sjdp * Use is subject to license terms. 2533965Sjdp */ 2633965Sjdp 2733965Sjdp/* 2833965Sjdp * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 2933965Sjdp */ 3033965Sjdp 3189857Sobrien#ifndef _QLT_H 3233965Sjdp#define _QLT_H 3333965Sjdp 3433965Sjdp#include <stmf_defines.h> 3533965Sjdp#include <qlt_regs.h> 3633965Sjdp 3733965Sjdp#ifdef __cplusplus 3833965Sjdpextern "C" { 3933965Sjdp#endif 4033965Sjdp 4133965Sjdp/* 4233965Sjdp * Qlogic logging 4333965Sjdp */ 4489857Sobrienextern int enable_extended_logging; 4533965Sjdp 4633965Sjdp/* 4733965Sjdp * Caution: 1) LOG will be available in debug/non-debug mode 4833965Sjdp * 2) Anything which can potentially flood the log should be under 4933965Sjdp * extended logging, and use QLT_EXT_LOG. 5033965Sjdp * 3) Don't use QLT_EXT_LOG in performance-critical code path, such 5133965Sjdp * as normal SCSI I/O code path. It could hurt system performance. 5233965Sjdp * 4) Use kmdb to change enable_extened_logging in the fly to adjust 5333965Sjdp * tracing 5433965Sjdp */ 5533965Sjdp#define QLT_EXT_LOG(log_ident, ...) \ 5633965Sjdp if (enable_extended_logging) { \ 5733965Sjdp stmf_trace(log_ident, __VA_ARGS__); \ 5833965Sjdp } 5933965Sjdp 6033965Sjdp#define QLT_LOG(log_ident, ...) \ 6133965Sjdp stmf_trace(log_ident, __VA_ARGS__) 6233965Sjdp 6333965Sjdp/* 6433965Sjdp * Error codes. FSC stands for Failure sub code. 6533965Sjdp */ 6660484Sobrien#define QLT_FAILURE FCT_FCA_FAILURE 6733965Sjdp#define QLT_SUCCESS FCT_SUCCESS 6833965Sjdp#define QLT_FSC(x) ((uint64_t)(x) << 40) 6933965Sjdp#define QLT_DMA_STUCK (QLT_FAILURE | QLT_FSC(1)) 7033965Sjdp#define QLT_MAILBOX_STUCK (QLT_FAILURE | QLT_FSC(2)) 7133965Sjdp#define QLT_ROM_STUCK (QLT_FAILURE | QLT_FSC(3)) 7233965Sjdp#define QLT_UNEXPECTED_RESPONSE (QLT_FAILURE | QLT_FSC(4)) 7333965Sjdp#define QLT_MBOX_FAILED (QLT_FAILURE | QLT_FSC(5)) 7433965Sjdp#define QLT_MBOX_NOT_INITIALIZED (QLT_FAILURE | QLT_FSC(6)) 7533965Sjdp#define QLT_MBOX_BUSY (QLT_FAILURE | QLT_FSC(7)) 7689857Sobrien#define QLT_MBOX_ABORTED (QLT_FAILURE | QLT_FSC(8)) 7789857Sobrien#define QLT_MBOX_TIMEOUT (QLT_FAILURE | QLT_FSC(9)) 7889857Sobrien#define QLT_RESP_TIMEOUT (QLT_FAILURE | QLT_FSC(10)) 7933965Sjdp#define QLT_FLASH_TIMEOUT (QLT_FAILURE | QLT_FSC(11)) 8089857Sobrien#define QLT_FLASH_ACCESS_ERROR (QLT_FAILURE | QLT_FSC(12)) 8133965Sjdp#define QLT_BAD_NVRAM_DATA (QLT_FAILURE | QLT_FSC(13)) 8233965Sjdp#define QLT_FIRMWARE_ERROR_CODE (QLT_FAILURE | QLT_FSC(14)) 8333965Sjdp 8433965Sjdp#define QLT_FIRMWARE_ERROR(s, c1, c2) (QLT_FIRMWARE_ERROR_CODE | \ 8533965Sjdp (((uint64_t)s) << 32) | (((uint64_t)c1) << 24) | ((uint64_t)c2)) 8633965Sjdp 8733965Sjdpextern uint32_t fw2400_code01[]; 8833965Sjdpextern uint32_t fw2400_length01; 8960484Sobrienextern uint32_t fw2400_addr01; 9060484Sobrienextern uint32_t fw2400_code02[]; 9160484Sobrienextern uint32_t fw2400_length02; 9260484Sobrienextern uint32_t fw2400_addr02; 9360484Sobrien 9460484Sobrienextern uint32_t fw2500_code01[]; 9560484Sobrienextern uint32_t fw2500_length01; 9660484Sobrienextern uint32_t fw2500_addr01; 9760484Sobrienextern uint32_t fw2500_code02[]; 9860484Sobrienextern uint32_t fw2500_length02; 9960484Sobrienextern uint32_t fw2500_addr02; 10060484Sobrien 10160484Sobrienextern uint32_t fw8100_code01[]; 10260484Sobrienextern uint32_t fw8100_length01; 10333965Sjdpextern uint32_t fw8100_addr01; 10433965Sjdpextern uint32_t fw8100_code02[]; 10533965Sjdpextern uint32_t fw8100_length02; 10633965Sjdpextern uint32_t fw8100_addr02; 10733965Sjdp 10833965Sjdptypedef enum { 10989857Sobrien MBOX_STATE_UNKNOWN = 0, 11089857Sobrien MBOX_STATE_READY, 11133965Sjdp MBOX_STATE_CMD_RUNNING, 11233965Sjdp MBOX_STATE_CMD_DONE 11333965Sjdp} mbox_state_t; 11433965Sjdp 11533965Sjdp/* 11633965Sjdp * ISP mailbox commands 11733965Sjdp */ 11833965Sjdp#define MBC_LOAD_RAM 0x01 /* Load RAM. */ 11989857Sobrien#define MBC_EXECUTE_FIRMWARE 0x02 /* Execute firmware. */ 12033965Sjdp#define MBC_DUMP_RAM 0x03 /* Dump RAM. */ 12133965Sjdp#define MBC_WRITE_RAM_WORD 0x04 /* Write RAM word. */ 12289857Sobrien#define MBC_READ_RAM_WORD 0x05 /* Read RAM word. */ 12333965Sjdp#define MBC_MAILBOX_REGISTER_TEST 0x06 /* Wrap incoming mailboxes */ 12433965Sjdp#define MBC_VERIFY_CHECKSUM 0x07 /* Verify checksum. */ 12560484Sobrien#define MBC_ABOUT_FIRMWARE 0x08 /* About Firmware. */ 12633965Sjdp#define MBC_DUMP_RISC_RAM 0x0a /* Dump RISC RAM command. */ 12733965Sjdp#define MBC_LOAD_RAM_EXTENDED 0x0b /* Load RAM extended. */ 12833965Sjdp#define MBC_DUMP_RAM_EXTENDED 0x0c /* Dump RAM extended. */ 12933965Sjdp#define MBC_WRITE_RAM_EXTENDED 0x0d /* Write RAM word. */ 13033965Sjdp#define MBC_READ_RAM_EXTENDED 0x0f /* Read RAM extended. */ 13133965Sjdp#define MBC_SERDES_TRANSMIT_PARAMETERS 0x10 /* Serdes Xmit Parameters */ 13289857Sobrien#define MBC_2300_EXECUTE_IOCB 0x12 /* ISP2300 Execute IOCB cmd */ 13389857Sobrien#define MBC_GET_IO_STATUS 0x12 /* ISP2422 Get I/O Status */ 13433965Sjdp#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 13589857Sobrien#define MBC_ABORT_COMMAND_IOCB 0x15 /* Abort IOCB command. */ 13633965Sjdp#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 13733965Sjdp#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 13833965Sjdp#define MBC_RESET 0x18 /* Target reset. */ 13989857Sobrien#define MBC_XMIT_PARM 0x19 /* Change default xmit parms */ 14033965Sjdp#define MBC_PORT_PARAM 0x1a /* Get/set port speed parms */ 14133965Sjdp#define MBC_GET_ID 0x20 /* Get loop id of ISP2200. */ 14233965Sjdp#define MBC_GET_TIMEOUT_PARAMETERS 0x22 /* Get Timeout Parameters. */ 14333965Sjdp#define MBC_TRACE_CONTROL 0x27 /* Trace control. */ 14433965Sjdp#define MBC_GET_FIRMWARE_OPTIONS 0x28 /* Get firmware options */ 14533965Sjdp#define MBC_READ_SFP 0x31 /* Read SFP. */ 14633965Sjdp 14733965Sjdp#define MBC_SET_ADDITIONAL_FIRMWARE_OPT 0x38 /* set firmware options */ 14833965Sjdp 14989857Sobrien#define OPT_PUREX_ENABLE (BIT_10) 15033965Sjdp 15133965Sjdp#define MBC_RESET_MENLO 0x3a /* Reset Menlo. */ 15233965Sjdp#define MBC_RESTART_MPI 0x3d /* Restart MPI. */ 15333965Sjdp#define MBC_FLASH_ACCESS 0x3e /* Flash Access Control */ 15433965Sjdp#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 15533965Sjdp#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 15633965Sjdp#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 15733965Sjdp#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 15833965Sjdp#define MBC_ECHO 0x44 /* ELS ECHO */ 15933965Sjdp#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 16033965Sjdp#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 16133965Sjdp#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get Port Database + login */ 16233965Sjdp#define MBC_INITIALIZE_MULTI_ID_FW 0x48 /* Initialize multi-id fw */ 16333965Sjdp#define MBC_GET_DCBX_PARAMS 0x51 /* Get DCBX parameters */ 16433965Sjdp#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 16533965Sjdp#define MBC_EXECUTE_IOCB 0x54 /* 64 Bit Execute IOCB cmd. */ 16633965Sjdp#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 16733965Sjdp 16833965Sjdp#define MBC_SET_PARAMETERS 0x59 /* Set parameters */ 16933965Sjdp 17033965Sjdp#define RNID_PARAMS_DF_FMT 0x00 17133965Sjdp#define RNID_PARAMS_E0_FMT 0x01 17233965Sjdp#define PUREX_ELS_CMDS 0x05 17333965Sjdp#define FLOGI_PARAMS 0x06 17433965Sjdp 17533965Sjdp#define PARAM_TYPE_FIELD_MASK 0xff 17633965Sjdp#define PARAM_TYPE_FIELD_SHIFT 8 17733965Sjdp#define PARAM_TYPE(type) ((type & PARAM_TYPE_FIELD_MASK) << \ 17833965Sjdp PARAM_TYPE_FIELD_SHIFT) 17933965Sjdp 18033965Sjdp#define MBC_GET_PARAMETERS 0x5a /* Get RNID parameters */ 18133965Sjdp#define MBC_DATA_RATE 0x5d /* Data Rate */ 18233965Sjdp#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 18333965Sjdp#define MBC_INITIATE_LIP 0x62 /* Initiate LIP */ 18489857Sobrien#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 18533965Sjdp#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 18633965Sjdp#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 18733965Sjdp#define MBC_TARGET_RESET 0x66 /* Target Reset. */ 18833965Sjdp#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 18933965Sjdp#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 19033965Sjdp#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 19133965Sjdp#define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 19233965Sjdp#define MBC_GET_LINK_STATUS 0x6b /* Get Link Status. */ 19333965Sjdp#define MBC_LIP_RESET 0x6c /* LIP reset. */ 19433965Sjdp#define MBC_GET_STATUS_COUNTS 0x6d /* Get Link Statistics and */ 19533965Sjdp /* Private Data Counts */ 19689857Sobrien#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 19733965Sjdp#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 19833965Sjdp#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 19933965Sjdp#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 20033965Sjdp#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 20133965Sjdp#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 20233965Sjdp#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list */ 20333965Sjdp#define MBC_INITIALIZE_IP 0x77 /* Initialize IP */ 20433965Sjdp#define MBC_SEND_FARP_REQ_COMMAND 0x78 /* FARP request. */ 20533965Sjdp#define MBC_UNLOAD_IP 0x79 /* Unload IP */ 20633965Sjdp#define MBC_GET_XGMAC_STATS 0x7a /* Get XGMAC Statistics. */ 20733965Sjdp#define MBC_GET_ID_LIST 0x7c /* Get port ID list. */ 20833965Sjdp#define MBC_SEND_LFA_COMMAND 0x7d /* Send Loop Fabric Address */ 20933965Sjdp#define MBC_LUN_RESET 0x7e /* Send Task mgmt LUN reset */ 21033965Sjdp#define MBC_IDC_REQUEST 0x100 /* IDC request */ 211#define MBC_IDC_ACK 0x101 /* IDC acknowledge */ 212#define MBC_IDC_TIME_EXTEND 0x102 /* IDC extend time */ 213#define MBC_PORT_RESET 0x120 /* Port Reset */ 214#define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 215#define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 216 217#define IOCB_SIZE 64 218 219/* 220 * These should not be constents but should be obtained from fw. 221 */ 222#define QLT_MAX_LOGINS 2048 223#define QLT_MAX_XCHGES 2048 224 225#define MAX_MBOXES 32 226#define MBOX_TIMEOUT (2*1000*1000) 227#define DEREG_RP_TIMEOUT (2*1000*1000) 228 229typedef struct { 230 uint16_t to_fw[MAX_MBOXES]; 231 uint32_t to_fw_mask; 232 uint16_t from_fw[MAX_MBOXES]; 233 uint32_t from_fw_mask; 234 stmf_data_buf_t *dbuf; 235} mbox_cmd_t; 236 237typedef struct qlt_abts_cmd { 238 uint8_t buf[IOCB_SIZE]; 239} qlt_abts_cmd_t; 240 241struct qlt_dmem_bucket; 242struct qlt_ddi_dma_handle_pool; 243 244#define QLT_INTR_FIXED 0x1 245#define QLT_INTR_MSI 0x2 246#define QLT_INTR_MSIX 0x4 247 248typedef struct qlt_el_trace_desc { 249 kmutex_t mutex; 250 uint16_t next; 251 uint32_t trace_buffer_size; 252 char *trace_buffer; 253} qlt_el_trace_desc_t; 254 255typedef struct qlt_state { 256 dev_info_t *dip; 257 char qlt_minor_name[16]; 258 char qlt_port_alias[16]; 259 fct_local_port_t *qlt_port; 260 struct qlt_dmem_bucket **dmem_buckets; 261 262 struct qlt_dma_handle_pool 263 *qlt_dma_handle_pool; 264 265 int instance; 266 uint8_t qlt_state:7, 267 qlt_state_not_acked:1; 268 uint8_t qlt_intr_enabled:1, 269 qlt_25xx_chip:1, 270 qlt_stay_offline:1, 271 qlt_link_up, 272 qlt_81xx_chip:1, 273 qlt_rsvd1:3; 274 uint8_t cur_topology; 275 276 /* Registers */ 277 caddr_t regs; 278 ddi_acc_handle_t regs_acc_handle; 279 ddi_acc_handle_t pcicfg_acc_handle; 280 281 /* Interrupt stuff */ 282 kmutex_t intr_lock; /* Only used by intr routine */ 283 int intr_sneak_counter; 284 ddi_intr_handle_t *htable; 285 int intr_size; 286 int intr_cnt; 287 uint_t intr_pri; 288 int intr_cap; 289 int intr_flags; 290 291 /* Queues */ 292 ddi_dma_handle_t queue_mem_dma_handle; 293 ddi_acc_handle_t queue_mem_acc_handle; 294 caddr_t queue_mem_ptr; 295 ddi_dma_cookie_t queue_mem_cookie; 296 297 kmutex_t req_lock; 298 caddr_t req_ptr; 299 uint32_t req_ndx_to_fw; 300 uint32_t req_ndx_from_fw; 301 uint32_t req_available; 302 303 caddr_t resp_ptr; 304 uint32_t resp_ndx_to_fw; 305 uint32_t resp_ndx_from_fw; 306 307 kmutex_t preq_lock; 308 caddr_t preq_ptr; 309 uint32_t preq_ndx_to_fw; 310 uint32_t preq_ndx_from_fw; 311 312 kcondvar_t rp_dereg_cv; /* for deregister cmd */ 313 uint32_t rp_id_in_dereg; /* remote port in deregistering */ 314 fct_status_t rp_dereg_status; 315 316 caddr_t atio_ptr; 317 uint16_t atio_ndx_to_fw; 318 uint16_t atio_ndx_from_fw; 319 320 kmutex_t dma_mem_lock; 321 322 /* MailBox data */ 323 kmutex_t mbox_lock; 324 kcondvar_t mbox_cv; 325 mbox_state_t mbox_io_state; 326 mbox_cmd_t *mcp; 327 qlt_nvram_t *nvram; 328 329 uint8_t link_speed; /* Cached from intr routine */ 330 uint16_t fw_major; 331 uint16_t fw_minor; 332 uint16_t fw_subminor; 333 uint16_t fw_endaddrlo; 334 uint16_t fw_endaddrhi; 335 uint16_t fw_attr; 336 337 uint32_t fw_addr01; 338 uint32_t fw_length01; 339 uint32_t *fw_code01; 340 uint32_t fw_addr02; 341 uint32_t fw_length02; 342 uint32_t *fw_code02; 343 344 uint32_t qlt_ioctl_flags; 345 kmutex_t qlt_ioctl_lock; 346 caddr_t qlt_fwdump_buf; /* FWDUMP will use ioctl flags/lock */ 347 uint32_t qlt_change_state_flags; /* Cached for ACK handling */ 348 349 qlt_el_trace_desc_t *el_trace_desc; 350 351 /* temp ref & stat counters */ 352 uint32_t qlt_bucketcnt[5]; /* element 0 = 2k */ 353 uint64_t qlt_bufref[5]; /* element 0 = 2k */ 354 uint64_t qlt_bumpbucket; /* bigger buffer supplied */ 355 uint64_t qlt_pmintry; 356 uint64_t qlt_pmin_ok; 357} qlt_state_t; 358 359/* 360 * FWDUMP flags (part of IOCTL flags) 361 */ 362#define QLT_FWDUMP_INPROGRESS 0x0100 /* if it's dumping now */ 363#define QLT_FWDUMP_TRIGGERED_BY_USER 0x0200 /* if users triggered it */ 364#define QLT_FWDUMP_FETCHED_BY_USER 0x0400 /* if users have viewed it */ 365#define QLT_FWDUMP_ISVALID 0x0800 366 367/* 368 * IOCTL supporting stuff 369 */ 370#define QLT_IOCTL_FLAG_MASK 0xFF 371#define QLT_IOCTL_FLAG_IDLE 0x00 372#define QLT_IOCTL_FLAG_OPEN 0x01 373#define QLT_IOCTL_FLAG_EXCL 0x02 374 375typedef struct qlt_cmd { 376 stmf_data_buf_t *dbuf; /* dbuf with handle 0 for SCSI cmds */ 377 stmf_data_buf_t *dbuf_rsp_iu; /* dbuf for possible FCP_RSP IU */ 378 uint32_t fw_xchg_addr; 379 uint16_t flags; 380 union { 381 uint16_t resp_offset; 382 uint8_t atio_byte3; 383 } param; 384} qlt_cmd_t; 385 386/* 387 * cmd flags 388 */ 389#define QLT_CMD_ABORTING 1 390#define QLT_CMD_ABORTED 2 391#define QLT_CMD_TYPE_SOLICITED 4 392 393typedef struct { 394 int dummy; 395} qlt_remote_port_t; 396 397#define REQUEST_QUEUE_ENTRIES 2048 398#define RESPONSE_QUEUE_ENTRIES 2048 399#define ATIO_QUEUE_ENTRIES 2048 400#define PRIORITY_QUEUE_ENTRIES 128 401 402#define REQUEST_QUEUE_OFFSET 0 403#define RESPONSE_QUEUE_OFFSET (REQUEST_QUEUE_OFFSET + \ 404 (REQUEST_QUEUE_ENTRIES * IOCB_SIZE)) 405#define ATIO_QUEUE_OFFSET (RESPONSE_QUEUE_OFFSET + \ 406 (RESPONSE_QUEUE_ENTRIES * IOCB_SIZE)) 407#define PRIORITY_QUEUE_OFFSET (ATIO_QUEUE_OFFSET + \ 408 (ATIO_QUEUE_ENTRIES * IOCB_SIZE)) 409#define MBOX_DMA_MEM_SIZE 4096 410#define MBOX_DMA_MEM_OFFSET (PRIORITY_QUEUE_OFFSET + \ 411 (PRIORITY_QUEUE_ENTRIES * IOCB_SIZE)) 412#define TOTAL_DMA_MEM_SIZE (MBOX_DMA_MEM_OFFSET + MBOX_DMA_MEM_SIZE) 413 414#define QLT_MAX_ITERATIONS_PER_INTR 32 415 416#define REG_RD16(qlt, addr) \ 417 ddi_get16(qlt->regs_acc_handle, (uint16_t *)(qlt->regs + addr)) 418#define REG_RD32(qlt, addr) \ 419 ddi_get32(qlt->regs_acc_handle, (uint32_t *)(qlt->regs + addr)) 420#define REG_WR16(qlt, addr, data) \ 421 ddi_put16(qlt->regs_acc_handle, (uint16_t *)(qlt->regs + addr), \ 422 (uint16_t)(data)) 423#define REG_WR32(qlt, addr, data) \ 424 ddi_put32(qlt->regs_acc_handle, (uint32_t *)(qlt->regs + addr), \ 425 (uint32_t)(data)) 426#define PCICFG_RD16(qlt, addr) \ 427 pci_config_get16(qlt->pcicfg_acc_handle, (off_t)(addr)) 428#define PCICFG_RD32(qlt, addr) \ 429 pci_config_get32(qlt->pcicfg_acc_handle, (off_t)(addr)) 430#define PCICFG_WR16(qlt, addr, data) \ 431 pci_config_put16(qlt->pcicfg_acc_handle, (off_t)(addr), \ 432 (uint16_t)(data)) 433#define QMEM_RD16(qlt, addr) \ 434 ddi_get16(qlt->queue_mem_acc_handle, (uint16_t *)(addr)) 435#define DMEM_RD16(qlt, addr) LE_16((uint16_t)(*((uint16_t *)(addr)))) 436#define QMEM_RD32(qlt, addr) \ 437 ddi_get32(qlt->queue_mem_acc_handle, (uint32_t *)(addr)) 438#define DMEM_RD32(qlt, addr) LE_32((uint32_t)(*((uint32_t *)(addr)))) 439/* 440 * #define QMEM_RD64(qlt, addr) \ 441 * ddi_get64(qlt->queue_mem_acc_handle, (uint64_t *)(addr)) 442 */ 443#define QMEM_WR16(qlt, addr, data) \ 444 ddi_put16(qlt->queue_mem_acc_handle, (uint16_t *)(addr), \ 445 (uint16_t)(data)) 446#define DMEM_WR16(qlt, addr, data) (*((uint16_t *)(addr)) = \ 447 (uint16_t)LE_16((uint16_t)(data))) 448#define QMEM_WR32(qlt, addr, data) \ 449 ddi_put32(qlt->queue_mem_acc_handle, (uint32_t *)(addr), \ 450 (uint32_t)(data)) 451#define DMEM_WR32(qlt, addr, data) (*((uint32_t *)(addr)) = \ 452 LE_32((uint32_t)(data))) 453 454/* 455 * [QD]MEM is always little endian so the [QD]MEM_WR64 macro works for 456 * both sparc and x86. 457 */ 458#define QMEM_WR64(qlt, addr, data) \ 459 QMEM_WR32(qlt, addr, (data & 0xffffffff)), \ 460 QMEM_WR32(qlt, (addr)+4, ((uint64_t)data) >> 32) 461 462#define DMEM_WR64(qlt, addr, data) \ 463 DMEM_WR32(qlt, addr, (data & 0xffffffff)), \ 464 DMEM_WR32(qlt, (addr)+4, ((uint64_t)data) >> 32) 465 466/* 467 * Structure used to associate values with strings which describe them. 468 */ 469typedef struct string_table_entry { 470 uint32_t value; 471 char *string; 472} string_table_t; 473 474char *prop_text(int prop_status); 475char *value2string(string_table_t *entry, int value, int delimiter); 476 477#define PROP_STATUS_DELIMITER ((uint32_t)0xFFFF) 478 479#define DDI_PROP_STATUS() \ 480{ \ 481 {DDI_PROP_SUCCESS, "DDI_PROP_SUCCESS"}, \ 482 {DDI_PROP_NOT_FOUND, "DDI_PROP_NOT_FOUND"}, \ 483 {DDI_PROP_UNDEFINED, "DDI_PROP_UNDEFINED"}, \ 484 {DDI_PROP_NO_MEMORY, "DDI_PROP_NO_MEMORY"}, \ 485 {DDI_PROP_INVAL_ARG, "DDI_PROP_INVAL_ARG"}, \ 486 {DDI_PROP_BUF_TOO_SMALL, "DDI_PROP_BUF_TOO_SMALL"}, \ 487 {DDI_PROP_CANNOT_DECODE, "DDI_PROP_CANNOT_DECODE"}, \ 488 {DDI_PROP_CANNOT_ENCODE, "DDI_PROP_CANNOT_ENCODE"}, \ 489 {DDI_PROP_END_OF_DATA, "DDI_PROP_END_OF_DATA"}, \ 490 {PROP_STATUS_DELIMITER, "DDI_PROP_UNKNOWN"} \ 491} 492 493#ifndef TRUE 494#define TRUE B_TRUE 495#endif 496 497#ifndef FALSE 498#define FALSE B_FALSE 499#endif 500 501/* Little endian machine correction defines. */ 502#ifdef _LITTLE_ENDIAN 503#define LITTLE_ENDIAN_16(x) 504#define LITTLE_ENDIAN_24(x) 505#define LITTLE_ENDIAN_32(x) 506#define LITTLE_ENDIAN_64(x) 507#define LITTLE_ENDIAN(bp, bytes) 508#define BIG_ENDIAN_16(x) qlt_chg_endian((uint8_t *)x, 2) 509#define BIG_ENDIAN_24(x) qlt_chg_endian((uint8_t *)x, 3) 510#define BIG_ENDIAN_32(x) qlt_chg_endian((uint8_t *)x, 4) 511#define BIG_ENDIAN_64(x) qlt_chg_endian((uint8_t *)x, 8) 512#define BIG_ENDIAN(bp, bytes) qlt_chg_endian((uint8_t *)bp, bytes) 513#endif /* _LITTLE_ENDIAN */ 514 515/* Big endian machine correction defines. */ 516#ifdef _BIG_ENDIAN 517#define LITTLE_ENDIAN_16(x) qlt_chg_endian((uint8_t *)x, 2) 518#define LITTLE_ENDIAN_24(x) qlt_chg_endian((uint8_t *)x, 3) 519#define LITTLE_ENDIAN_32(x) qlt_chg_endian((uint8_t *)x, 4) 520#define LITTLE_ENDIAN_64(x) qlt_chg_endian((uint8_t *)x, 8) 521#define LITTLE_ENDIAN(bp, bytes) qlt_chg_endian((uint8_t *)bp, bytes) 522#define BIG_ENDIAN_16(x) 523#define BIG_ENDIAN_24(x) 524#define BIG_ENDIAN_32(x) 525#define BIG_ENDIAN_64(x) 526#define BIG_ENDIAN(bp, bytes) 527#endif /* _BIG_ENDIAN */ 528 529#define LSB(x) (uint8_t)(x) 530#define MSB(x) (uint8_t)((uint16_t)(x) >> 8) 531#define MSW(x) (uint16_t)((uint32_t)(x) >> 16) 532#define LSW(x) (uint16_t)(x) 533#define LSD(x) (uint32_t)(x) 534#define MSD(x) (uint32_t)((uint64_t)(x) >> 32) 535 536void qlt_chg_endian(uint8_t *, size_t); 537 538void qlt_el_msg(qlt_state_t *qlt, const char *fn, int ce, ...); 539void qlt_dump_el_trace_buffer(qlt_state_t *qlt); 540#define EL(qlt, ...) qlt_el_msg(qlt, __func__, CE_CONT, __VA_ARGS__); 541#define EL_TRACE_BUF_SIZE 8192 542#define EL_BUFFER_RESERVE 256 543#define DEBUG_STK_DEPTH 24 544#define EL_TRACE_BUF_SIZE 8192 545 546#ifdef __cplusplus 547} 548#endif 549 550#endif /* _QLT_H */ 551