cardbus_cfg.c revision 2305:7954d746a1b5
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25/* 26 * Copyright (c) * Copyright (c) 2001 Tadpole Technology plc 27 * All rights reserved. 28 * From "@(#)pcicfg.c 1.31 99/06/18 SMI" 29 */ 30 31#pragma ident "%Z%%M% %I% %E% SMI" 32 33/* 34 * Cardbus configurator 35 */ 36 37#include <sys/ddi.h> 38#include <sys/sunndi.h> 39#include <sys/ndi_impldefs.h> 40 41#include <sys/pci.h> 42#include <sys/ebus.h> 43#include <sys/hotplug/hpctrl.h> 44#include <sys/hotplug/pci/pcicfg.h> 45 46#include <sys/pctypes.h> 47#include <sys/pcmcia.h> 48 49#include <sys/isa_defs.h> 50 51#include <sys/note.h> 52 53#include <sys/ethernet.h> 54 55#include "cardbus.h" 56#include "cardbus_parse.h" 57#include "cardbus_cfg.h" 58 59/* 60 * ************************************************************************ 61 * *** Implementation specific local data structures/definitions. *** 62 * ************************************************************************ 63 */ 64 65#define PCICFG_MAX_DEVICE 32 66#define PCICFG_MAX_FUNCTION 8 67 68static uint32_t pcicfg_max_device = PCICFG_MAX_DEVICE; 69static uint32_t pcicfg_max_function = PCICFG_MAX_FUNCTION; 70 71#define PCICFG_NODEVICE 42 72#define PCICFG_NOMEMORY 43 73#define PCICFG_NOMULTI 44 74 75#define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & 0xFFFFFFFF00000000)>> 32)) 76#define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 77#define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 78 79#define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 80#define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 81#define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 82#define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 83 84#define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 85#define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 86 87#define PCICFG_MEMGRAN 0x100000 88#define PCICFG_IOGRAN 0x1000 89#define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 90#define CBCFG_MEMGRAN 0x1000 91#define CBCFG_IOGRAN 0x4 92 93#define PCICFG_MEM_MULT 4 94#define PCICFG_IO_MULT 4 95#define PCICFG_RANGE_LEN 2 /* Number of range entries */ 96 97/* 98 * ISA node declaration structure. 99 */ 100struct isa_node { 101 char *name; 102 char *compatible[5]; 103 char *type; 104 char *model; 105 uint16_t reg; 106 uint16_t span; 107}; 108 109struct cardbus_name_entry { 110 uint32_t class_code; 111 char *name; 112 int pil; 113}; 114 115struct cardbus_find_ctrl { 116 uint_t bus; 117 uint_t device; 118 uint_t function; 119 dev_info_t *dip; 120}; 121 122#define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 123 (\ 124 ((ulong_t)(busnum & 0xff) << 16) |\ 125 ((ulong_t)(devnum & 0x1f) << 11) |\ 126 ((ulong_t)(funcnum & 0x7) << 8) |\ 127 ((ulong_t)(register & 0x3f))) 128 129typedef struct cardbus_phdl cardbus_phdl_t; 130 131struct cardbus_phdl { 132 133 dev_info_t *dip; /* Associated with the attach point */ 134 cardbus_phdl_t *next; 135 136 uint64_t memory_base; /* Memory base for this attach point */ 137 uint64_t memory_last; 138 uint64_t memory_len; 139 uint32_t memory_gran; 140 uint32_t io_base; /* I/O base for this attach point */ 141 uint32_t io_last; 142 uint32_t io_len; 143 uint32_t io_gran; 144 145 int error; 146 uint_t highest_bus; /* Highest bus seen on the probe */ 147 ndi_ra_request_t mem_req; /* allocator request for memory */ 148 ndi_ra_request_t io_req; /* allocator request for I/O */ 149}; 150 151typedef struct { 152 dev_info_t *dip; /* Associated with the attach point */ 153 ddi_acc_handle_t handle; /* open handle on parent PCI config space */ 154 uint32_t io_base; /* I/O base for this attach point */ 155 int io_decode_reg; 156} isa_phdl_t; 157 158 159/* 160 * forward declarations for routines defined in this module (called here) 161 */ 162static cardbus_phdl_t *cardbus_find_phdl(dev_info_t *dip); 163static cardbus_phdl_t *cardbus_create_phdl(dev_info_t *dip); 164static int cardbus_destroy_phdl(dev_info_t *dip); 165static int cardbus_program_ap(dev_info_t *); 166static void cardbus_topbridge_assign(dev_info_t *, cardbus_phdl_t *); 167static int cardbus_bridge_ranges(dev_info_t *, cardbus_phdl_t *, 168 ddi_acc_handle_t); 169static int cardbus_bridge_assign(dev_info_t *, void *); 170static int cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 171 ddi_acc_handle_t handle); 172static int cardbus_add_isa_reg(dev_info_t *, void *); 173static int cardbus_allocate_chunk(dev_info_t *, uint8_t, uint8_t); 174static int cardbus_free_chunk(dev_info_t *); 175static void cardbus_setup_bridge(dev_info_t *, cardbus_phdl_t *, 176 ddi_acc_handle_t); 177static void cardbus_update_bridge(dev_info_t *, cardbus_phdl_t *, 178 ddi_acc_handle_t); 179static void cardbus_get_mem(dev_info_t *, cardbus_phdl_t *, uint32_t, 180 uint64_t *); 181static void cardbus_get_io(dev_info_t *, cardbus_phdl_t *, uint32_t, 182 uint32_t *); 183static int cardbus_sum_resources(dev_info_t *, void *); 184static int cardbus_free_bridge_resources(dev_info_t *); 185static int cardbus_free_device_resources(dev_info_t *); 186static int cardbus_free_resources(dev_info_t *); 187static int cardbus_probe_bridge(cbus_t *, dev_info_t *, uint_t, 188 uint_t, uint_t); 189static int cardbus_probe_children(cbus_t *, dev_info_t *, uint_t, uint_t, 190 uint_t, uint8_t *); 191static int cardbus_add_config_reg(dev_info_t *, uint_t, uint_t, uint_t); 192static int cardbus_add_isa_node(cbus_t *, dev_info_t *, struct isa_node *); 193static int cardbus_config_setup(dev_info_t *, ddi_acc_handle_t *); 194static void cardbus_config_teardown(ddi_acc_handle_t *); 195static void cardbus_reparent_children(dev_info_t *, dev_info_t *); 196static int cardbus_update_assigned_prop(dev_info_t *, pci_regspec_t *); 197static int cardbus_update_available_prop(dev_info_t *, uint32_t, 198 uint64_t, uint64_t); 199static int cardbus_update_ranges_prop(dev_info_t *, cardbus_range_t *); 200static int cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, 201 uint_t reg_offset); 202static int cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 203 ddi_acc_handle_t config_handle); 204static int cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 205 char *name, char *compat[]); 206static int cardbus_set_busnode_props(dev_info_t *); 207static int cardbus_set_busnode_isaprops(dev_info_t *); 208static int cardbus_set_childnode_props(dev_info_t *dip, 209 ddi_acc_handle_t config_handle); 210static void cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 211 uint_t primary, uint_t secondary); 212static void enable_pci_isa_bridge(dev_info_t *dip, 213 ddi_acc_handle_t config_handle); 214static void enable_pci_pci_bridge(dev_info_t *dip, 215 ddi_acc_handle_t config_handle); 216static void enable_cardbus_bridge(dev_info_t *dip, 217 ddi_acc_handle_t config_handle); 218static void disable_pci_pci_bridge(dev_info_t *dip, 219 ddi_acc_handle_t config_handle); 220static void disable_cardbus_bridge(dev_info_t *dip, 221 ddi_acc_handle_t config_handle); 222static void enable_cardbus_device(dev_info_t *, ddi_acc_handle_t); 223static void disable_cardbus_device(ddi_acc_handle_t config_handle); 224static void cardbus_force_boolprop(dev_info_t *dip, char *pname); 225static void cardbus_force_intprop(dev_info_t *dip, char *pname, 226 int *pval, int len); 227static void cardbus_force_stringprop(dev_info_t *dip, char *pname, 228 char *pval); 229static void split_addr(char *, int *, int *); 230#ifdef DEBUG 231static void cardbus_dump_common_config(ddi_acc_handle_t config_handle); 232static void cardbus_dump_device_config(ddi_acc_handle_t config_handle); 233static void cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 234 uint8_t header_type); 235static void cardbus_dump_config(ddi_acc_handle_t config_handle); 236static void cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, 237 int nelems); 238#endif 239 240static cardbus_phdl_t *cardbus_phdl_list = NULL; 241 242static struct cardbus_name_entry cardbus_class_lookup [] = { 243 { 0x001, "display", 9 }, 244 { 0x100, "scsi", 4 }, 245 { 0x101, "ide", 4 }, 246 { 0x102, "fdc", 4 }, 247 { 0x103, "ipi", 4 }, 248 { 0x104, "raid", 4 }, 249 { 0x200, "ethernet", 6 }, 250 { 0x201, "token-ring", 6 }, 251 { 0x202, "fddi", 6 }, 252 { 0x203, "atm", 6 }, 253 { 0x300, "display", 9 }, /* VGA card */ 254 { 0x380, "display", 9 }, /* other - for the Raptor Card */ 255 { 0x400, "video", 11 }, 256 { 0x401, "sound", 11 }, 257 { 0x500, "memory", 11 }, 258 { 0x501, "flash", 11 }, 259 { 0x600, "host", 11 }, 260 { 0x601, "isa", 11 }, 261 { 0x602, "eisa", 11 }, 262 { 0x603, "mca", 11 }, 263 { 0x604, "pci", 11 }, 264 { 0x605, "pcmcia", 11 }, 265 { 0x606, "nubus", 11 }, 266 { 0x607, "cardbus", 11 }, 267 { 0x680, NULL, 8 }, 268 { 0x700, "serial", 11 }, 269 { 0x701, "parallel", 6 }, 270 { 0x800, "interrupt-controller", 3 }, 271 { 0x801, "dma-controller", 3 }, 272 { 0x802, "timer", 3 }, 273 { 0x803, "rtc", 3 }, 274 { 0x900, "keyboard", 8 }, 275 { 0x901, "pen", 8 }, 276 { 0x902, "mouse", 8 }, 277 { 0xa00, "dock", 1 }, 278 { 0xb00, "cpu", 1 }, 279 { 0xc00, "firewire", 9 }, 280 { 0xc01, "access-bus", 4 }, 281 { 0xc02, "ssa", 4 }, 282 { 0xc03, "usb", 9 }, 283 { 0xc04, "fibre-channel", 6 }, 284 { 0, 0 } 285}; 286 287#ifndef _DONT_USE_1275_GENERIC_NAMES 288static char *cardbus_get_class_name(uint32_t classcode); 289#endif /* _DONT_USE_1275_GENERIC_NAMES */ 290 291/* 292 * Reprogram ILINE with default value only if BIOS doesn't program it 293 */ 294int 295cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle) 296{ 297 uint8_t intline = 0xff; 298 299 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 300 intline = pci_config_get8(handle, PCI_CONF_ILINE); 301 if ((intline == 0) || (intline == 0xff)) { 302 intline = ddi_getprop(DDI_DEV_T_ANY, dip, 303 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 304 "interrupt-line", 0xff); 305 if (intline == (uint8_t)0xff) { 306 intline = ddi_getprop(DDI_DEV_T_ANY, 307 ddi_get_parent(dip), 308 DDI_PROP_CANSLEEP /* |DDI_PROP_DONTPASS */, 309 "interrupt-line", 0xb); 310 } 311 312 pci_config_put8(handle, PCI_CONF_ILINE, intline); 313 } 314 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 315 "interrupt-line", intline); 316 } 317 return (intline); 318} 319 320/* 321 * This entry point is called to configure a device (and 322 * all its children) on the given bus. It is called when 323 * a new device is added to the PCI domain. This routine 324 * will create the device tree and program the devices 325 * registers. 326 */ 327int 328cardbus_configure(cbus_t *cbp) 329{ 330 uint_t bus; 331 int cardbus_dev, func; 332 dev_info_t *attach_point; 333 334 cardbus_err(cbp->cb_dip, 6, "cardbus_configure ()\n"); 335 336 bus = cardbus_primary_busno(cbp->cb_dip); 337 338 if (ndi_devi_alloc(cbp->cb_dip, DEVI_PSEUDO_NEXNAME, 339 (pnode_t)DEVI_SID_NODEID, 340 &attach_point) != NDI_SUCCESS) { 341 cardbus_err(cbp->cb_dip, 1, 342 "cardbus_configure(): Failed to alloc probe node\n"); 343 return (PCICFG_FAILURE); 344 } 345 346 /* 347 * Node name marks this node as the "attachment point". 348 */ 349 if (ndi_devi_set_nodename(attach_point, 350 "hp_attachment", 0) != NDI_SUCCESS) { 351 cardbus_err(cbp->cb_dip, 1, 352 "Failed to set nodename for attachment node\n"); 353 (void) ndi_devi_free(attach_point); 354 return (PCICFG_FAILURE); 355 } 356 357 cardbus_err(ddi_get_parent(attach_point), 8, 358 "Set bus type to cardbus\n"); 359 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 360 ddi_get_parent(attach_point), PCM_DEVICETYPE, 361 "cardbus"); 362 363 split_addr(ddi_get_name_addr(cbp->cb_dip), &cardbus_dev, &func); 364 365 cardbus_err(attach_point, 8, 366 "Configuring [0x%x][0x%x][0x%x]\n", bus, cardbus_dev, func); 367 368 switch (cardbus_probe_bridge(cbp, attach_point, 369 bus, cardbus_dev, func)) { 370 case PCICFG_FAILURE: 371 cardbus_err(cbp->cb_dip, 4, 372 "configure failed: bus [0x%x] slot [0x%x] func [0x%x]\n", 373 bus, cardbus_dev, func); 374 goto cleanup; 375 case PCICFG_NODEVICE: 376 cardbus_err(cbp->cb_dip, 4, 377 "no device: bus [0x%x] slot [0x%x] func [0x%x]\n", 378 bus, cardbus_dev, func); 379 goto cleanup; 380 default: 381 cardbus_err(cbp->cb_dip, 9, 382 "configure: bus => [%d] slot => [%d] func => [%d]\n", 383 bus, cardbus_dev, func); 384 break; 385 } 386 387 if (cardbus_program_ap(cbp->cb_dip) == PCICFG_SUCCESS) { 388 (void) cardbus_reparent_children(attach_point, cbp->cb_dip); 389 (void) ndi_devi_free(attach_point); 390 cbp->cb_nex_ops->enable_intr(cbp->cb_dip); 391 return (PCICFG_SUCCESS); 392 } 393 394 cardbus_err(cbp->cb_dip, 1, "Failed to program devices\n"); 395 396cleanup: 397 /* 398 * Clean up a partially created "probe state" tree. 399 * There are no resources allocated to the in the 400 * probe state. 401 */ 402 403 cardbus_err(cbp->cb_dip, 6, 404 "Look up device [0x%x] function [0x%x] to clean up\n", 405 cardbus_dev, func); 406 407 cardbus_err(cbp->cb_dip, 6, 408 "Cleaning up device [0x%x] function [0x%x]\n", 409 cardbus_dev, func); 410 411 /* 412 * If this was a bridge device it will have a 413 * probe handle - if not, no harm in calling this. 414 */ 415 (void) cardbus_destroy_phdl(cbp->cb_dip); 416 417 if (ddi_get_child(attach_point)) { 418 /* 419 * This will free up the node 420 */ 421 (void) ndi_devi_offline(ddi_get_child(attach_point), 422 NDI_UNCONFIG|NDI_DEVI_REMOVE); 423 } 424 (void) ndi_devi_free(attach_point); 425 426 return (PCICFG_FAILURE); 427} 428 429int 430cardbus_unconfigure(cbus_t *cbp) 431{ 432 ddi_acc_handle_t config_handle; 433 dev_info_t *dip = cbp->cb_dip; 434 435 cbp->cb_nex_ops->disable_intr(dip); 436 if (pci_config_setup(dip, &config_handle) == DDI_SUCCESS) { 437 disable_cardbus_bridge(dip, config_handle); 438 (void) pci_config_teardown(&config_handle); 439 } else { 440 cardbus_err(dip, 1, 441 "cardbus_unconfigure(): Failed to setup config space\n"); 442 } 443 444 (void) cardbus_free_chunk(dip); 445 cardbus_err(dip, 6, 446 "cardbus_unconfigure: calling cardbus_free_bridge_resources\n"); 447 (void) cardbus_free_bridge_resources(dip); 448 449 return (PCICFG_SUCCESS); 450} 451 452int 453cardbus_teardown_device(dev_info_t *dip) 454{ 455 /* 456 * Free up resources associated with 'dip' 457 */ 458 459 if (cardbus_free_resources(dip) != PCICFG_SUCCESS) { 460 cardbus_err(dip, 1, 461 "cardbus_teardown_device: Failed to free resources\n"); 462 return (PCICFG_FAILURE); 463 } 464 465 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 466 cardbus_err(dip, 1, 467 "cardbus_teardown_device: " 468 "Failed to offline and remove node\n"); 469 return (PCICFG_FAILURE); 470 } 471 472 return (PCICFG_SUCCESS); 473} 474 475/* 476 * Get the primary pci bus number. This should be the lowest number 477 * in the bus-range property of our parent. 478 */ 479int 480cardbus_primary_busno(dev_info_t *dip) 481{ 482 int len, rval; 483 char bus_type[16] = "(unknown)"; 484 dev_info_t *par = ddi_get_parent(dip); 485 cardbus_bus_range_t *bus_range; 486 487 ASSERT(strcmp(ddi_driver_name(dip), "pcic") == 0); 488 len = sizeof (bus_type); 489 if ((ddi_prop_op(DDI_DEV_T_ANY, par, PROP_LEN_AND_VAL_BUF, 490 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 491 "device_type", 492 (caddr_t)&bus_type, &len) == DDI_SUCCESS)) { 493 ASSERT((strcmp(bus_type, "pci") == 0) || 494 (strcmp(bus_type, "cardbus") == 0)); 495 if (ddi_getlongprop(DDI_DEV_T_ANY, par, 0, "bus-range", 496 (caddr_t)&bus_range, &len) == DDI_PROP_SUCCESS) { 497 cardbus_err(dip, 9, 498 "cardbus_primary_busno: bus range is %d to %d\n", 499 bus_range->lo, bus_range->hi); 500 rval = (int)bus_range->lo; 501 kmem_free((caddr_t)bus_range, len); 502 return (rval); 503 } 504 } 505 506 cardbus_err(dip, 2, 507 "cardbus_primary_busno: Not a pci device or no bus-range\n"); 508 return (-1); 509} 510 511static cardbus_phdl_t * 512cardbus_find_phdl(dev_info_t *dip) 513{ 514 cardbus_phdl_t *entry; 515 516 mutex_enter(&cardbus_list_mutex); 517 for (entry = cardbus_phdl_list; entry != NULL; entry = entry->next) { 518 if (entry->dip == dip) { 519 mutex_exit(&cardbus_list_mutex); 520 return (entry); 521 } 522 } 523 mutex_exit(&cardbus_list_mutex); 524 525 /* 526 * Did'nt find entry - create one 527 */ 528 return (cardbus_create_phdl(dip)); 529} 530 531static cardbus_phdl_t * 532cardbus_create_phdl(dev_info_t *dip) 533{ 534 cardbus_phdl_t *new; 535 536 new = (cardbus_phdl_t *)kmem_zalloc(sizeof (cardbus_phdl_t), KM_SLEEP); 537 538 new->dip = dip; 539 new->io_gran = CBCFG_IOGRAN; 540 new->memory_gran = CBCFG_MEMGRAN; 541 mutex_enter(&cardbus_list_mutex); 542 new->next = cardbus_phdl_list; 543 cardbus_phdl_list = new; 544 mutex_exit(&cardbus_list_mutex); 545 546 return (new); 547} 548 549static int 550cardbus_destroy_phdl(dev_info_t *dip) 551{ 552 cardbus_phdl_t *entry; 553 cardbus_phdl_t *follow = NULL; 554 555 mutex_enter(&cardbus_list_mutex); 556 for (entry = cardbus_phdl_list; entry != NULL; follow = entry, 557 entry = entry->next) { 558 if (entry->dip == dip) { 559 if (entry == cardbus_phdl_list) { 560 cardbus_phdl_list = entry->next; 561 } else { 562 follow->next = entry->next; 563 } 564 /* 565 * If this entry has any allocated memory 566 * or IO space associated with it, that 567 * must be freed up. 568 */ 569 if (entry->memory_len > 0) { 570 (void) ndi_ra_free(dip, 571 entry->memory_base, entry->memory_len, 572 NDI_RA_TYPE_MEM, NDI_RA_PASS); 573#ifdef _LP64 574 cardbus_err(dip, 8, 575 "cardbus_destroy_phdl: " 576 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 577 entry->memory_base, entry->memory_len); 578#else 579 cardbus_err(dip, 8, 580 "cardbus_destroy_phdl: " 581 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 582 entry->memory_base, entry->memory_len); 583#endif 584 } 585 if (entry->io_len > 0) { 586 (void) ndi_ra_free(dip, 587 entry->io_base, entry->io_len, 588 NDI_RA_TYPE_IO, NDI_RA_PASS); 589 cardbus_err(dip, 8, 590 "cardbus_destroy_phdl: " 591 "IO BASE = [0x%x] length [0x%x]\n", 592 entry->io_base, entry->io_len); 593 } 594 /* 595 * Destroy this entry 596 */ 597 kmem_free((caddr_t)entry, sizeof (cardbus_phdl_t)); 598 mutex_exit(&cardbus_list_mutex); 599 return (PCICFG_SUCCESS); 600 } 601 } 602 603 mutex_exit(&cardbus_list_mutex); 604 605 /* 606 * Didn't find the entry 607 */ 608 return (PCICFG_FAILURE); 609} 610 611static int 612cardbus_program_ap(dev_info_t *dip) 613{ 614 cardbus_phdl_t *phdl; 615 uint8_t header_type, sec_bus; 616 ddi_acc_handle_t handle; 617 618 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 619 cardbus_err(dip, 1, 620 "cardbus_program_ap: Failed to map config space!\n"); 621 return (PCICFG_FAILURE); 622 } 623 624 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 625 sec_bus = pci_config_get8(handle, PCI_BCNF_SECBUS); 626 627 cardbus_err(dip, 6, 628 "cardbus_program_ap (header_type=0x%x)\n", header_type); 629 (void) pci_config_teardown(&handle); 630 631 /* 632 * Header type two is PCI to Cardbus bridge, see page 43 of the 633 * CL-PD6832 data sheet 634 */ 635 switch (header_type & PCI_HEADER_TYPE_M) { 636 case PCI_HEADER_CARDBUS: 637 cardbus_err(dip, 8, 638 "cardbus_program_ap calling cardbus_allocate_chunk\n"); 639 if (cardbus_allocate_chunk(dip, 640 header_type & PCI_HEADER_TYPE_M, 641 sec_bus) != PCICFG_SUCCESS) { 642 cardbus_err(dip, 1, 643 "cardbus_program_ap: " 644 "Not enough memory to hotplug\n"); 645 (void) cardbus_destroy_phdl(dip); 646 return (PCICFG_FAILURE); 647 } 648 649 cardbus_err(dip, 8, 650 "cardbus_program_ap calling cardbus_find_phdl\n"); 651 phdl = cardbus_find_phdl(dip); 652 ASSERT(phdl); 653 654 if (phdl == NULL) { 655 cardbus_err(dip, 1, "cardbus_find_phdl failed\n"); 656 return (PCICFG_FAILURE); 657 } 658 phdl->error = PCICFG_SUCCESS; 659 cardbus_err(dip, 8, 660 "cardbus_program_ap calling cardbus_topbridge_assign\n"); 661 cardbus_topbridge_assign(dip, phdl); 662 663 if (phdl->error != PCICFG_SUCCESS) { 664 cardbus_err(dip, 1, "Problem assigning bridge\n"); 665 (void) cardbus_destroy_phdl(dip); 666 return (phdl->error); 667 } 668 break; 669 670 default: 671 return (PCICFG_FAILURE); 672 } 673 674 return (PCICFG_SUCCESS); 675} 676 677static void 678cardbus_topbridge_assign(dev_info_t *dip, cardbus_phdl_t *entry) 679{ 680 ddi_acc_handle_t handle; 681 uint8_t header_type; 682 683 cardbus_err(dip, 6, "cardbus_topbridge_assign\n"); 684 685 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 686 cardbus_err(dip, 1, 687 "cardbus_topbridge_bridge_assign: " 688 "Failed to map config space!\n"); 689 return; 690 } 691 692 header_type = pci_config_get8(handle, 693 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 694 695 /* cardbus bridge is the same as PCI-PCI bridge */ 696 ASSERT((header_type == PCI_HEADER_PPB) || 697 (header_type == PCI_HEADER_CARDBUS)); 698 699 (void) cardbus_bridge_ranges(dip, entry, handle); 700 701 (void) pci_config_teardown(&handle); 702} 703 704static int 705cardbus_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 706 ddi_acc_handle_t handle) 707{ 708 cardbus_range_t range[PCICFG_RANGE_LEN]; 709 int bus_range[2]; 710 int count; 711 int i; 712 713 cardbus_err(dip, 8, "cardbus_bridge_ranges\n"); 714 715 bzero((caddr_t)range, sizeof (cardbus_range_t) * PCICFG_RANGE_LEN); 716 717 (void) cardbus_setup_bridge(dip, entry, handle); 718 719 range[0].child_hi = range[0].parent_hi |= (PCI_REG_REL_M | PCI_ADDR_IO); 720 range[0].child_lo = range[0].parent_lo = entry->io_last; 721 range[1].child_hi = range[1].parent_hi |= (PCI_REG_REL_M | 722 PCI_ADDR_MEM32); 723 range[1].child_lo = range[1].parent_lo = entry->memory_last; 724 725 ndi_devi_enter(dip, &count); 726 ddi_walk_devs(ddi_get_child(dip), cardbus_bridge_assign, (void *)entry); 727 ndi_devi_exit(dip, count); 728 729 (void) cardbus_update_bridge(dip, entry, handle); 730 731 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 732 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 733 734 cardbus_err(dip, 8, 735 "Set up bus-range property to %u->%u\n", 736 bus_range[0], bus_range[1]); 737 738 if ((i = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 739 "bus-range", 740 bus_range, 2)) != DDI_SUCCESS) { 741 742 if (i == DDI_PROP_NOT_FOUND) { 743 cardbus_err(dip, 8, 744 "Create bus-range property, %u->%u\n", 745 bus_range[0], bus_range[1]); 746 i = ddi_prop_create(DDI_DEV_T_NONE, dip, 747 DDI_PROP_CANSLEEP, 748 "bus-range", (caddr_t)bus_range, 749 sizeof (bus_range)); 750 } 751 752 if (i != DDI_PROP_SUCCESS) { 753 cardbus_err(dip, 1, 754 "Failed to set bus-range property, %u->%u (%d)\n", 755 bus_range[0], bus_range[1], i); 756 entry->error = PCICFG_FAILURE; 757 return (DDI_WALK_TERMINATE); 758 } 759 } 760 761 if (entry->io_len > 0) { 762 range[0].size_lo = entry->io_last - entry->io_base; 763 if (cardbus_update_ranges_prop(dip, &range[0])) { 764 cardbus_err(dip, 1, "Failed to update ranges (i/o)\n"); 765 entry->error = PCICFG_FAILURE; 766 return (DDI_WALK_TERMINATE); 767 } 768 } 769 if (entry->memory_len > 0) { 770 range[1].size_lo = entry->memory_last - entry->memory_base; 771 if (cardbus_update_ranges_prop(dip, &range[1])) { 772 cardbus_err(dip, 1, 773 "Failed to update ranges (memory)\n"); 774 entry->error = PCICFG_FAILURE; 775 return (DDI_WALK_TERMINATE); 776 } 777 } 778 779 return (DDI_WALK_PRUNECHILD); 780} 781static int 782cardbus_bridge_assign(dev_info_t *dip, void *hdl) 783{ 784 ddi_acc_handle_t handle; 785 pci_regspec_t *reg; 786 int length; 787 int rcount; 788 int i; 789 int offset; 790 uint64_t mem_answer; 791 uint32_t io_answer, request; 792 uint8_t header_type, base_class; 793 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 794 795 /* 796 * Ignore the attachment point and pcs. 797 */ 798 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 799 strcmp(ddi_binding_name(dip), "pcs") == 0) { 800 cardbus_err(dip, 8, "cardbus_bridge_assign: Ignoring\n"); 801 return (DDI_WALK_CONTINUE); 802 } 803 804 805 cardbus_err(dip, 6, "cardbus_bridge_assign\n"); 806 807 if (entry == NULL) { 808 cardbus_err(dip, 1, "Failed to get entry\n"); 809 return (DDI_WALK_TERMINATE); 810 } 811 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 812 cardbus_err(dip, 1, 813 "cardbus_bridge_assign: Failed to map config space!\n"); 814 entry->error = PCICFG_FAILURE; 815 return (DDI_WALK_TERMINATE); 816 } 817 818 header_type = pci_config_get8(handle, PCI_CONF_HEADER) & 819 PCI_HEADER_TYPE_M; 820 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 821 822 /* 823 * This function is not called for the top bridge and we are 824 * not enumerating down a further cardbus interface yet! 825 */ 826 if (base_class == PCI_CLASS_BRIDGE) { 827 uint8_t sub_class; 828 829 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 830 831 switch (sub_class) { 832 case PCI_BRIDGE_PCI: 833 if (header_type == PCI_HEADER_PPB) { 834 i = cardbus_bridge_ranges(dip, entry, handle); 835 (void) cardbus_config_teardown(&handle); 836 return (i); 837 } 838 goto bad_device; 839 840 case PCI_BRIDGE_ISA: 841 i = cardbus_isa_bridge_ranges(dip, entry, handle); 842 (void) cardbus_config_teardown(&handle); 843 return (i); 844 845 case PCI_BRIDGE_CARDBUS: 846 /* 847 * Fall through, there should be at least one register 848 * set for this. 849 */ 850 break; 851 852 case PCI_BRIDGE_OTHER: 853 default: 854 break; 855 } 856 } 857 858#ifdef sparc 859 /* 860 * If there is an interrupt pin set program 861 * interrupt line with default values. 862 */ 863 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 864 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 865 } 866#else 867 (void) cardbus_validate_iline(dip, handle); 868#endif 869 870 /* 871 * A single device (under a bridge). 872 * For each "reg" property with a length, allocate memory 873 * and program the base registers. 874 */ 875 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 876 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 877 &length) != DDI_PROP_SUCCESS) { 878 cardbus_err(dip, 1, "Failed to read reg property\n"); 879 entry->error = PCICFG_FAILURE; 880 (void) cardbus_config_teardown(&handle); 881 return (DDI_WALK_TERMINATE); 882 } 883 884 rcount = length / sizeof (pci_regspec_t); 885 cardbus_err(dip, 9, "rcount = %d\n", rcount); 886 887 for (i = 0; i < rcount; i++) { 888 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 889 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 890 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 891 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 892 893 (void) cardbus_get_mem(ddi_get_parent(dip), 894 entry, reg[i].pci_size_low, &mem_answer); 895 ASSERT(!PCICFG_HIADDR(mem_answer)); 896 pci_config_put32(handle, offset, 897 PCICFG_LOADDR(mem_answer)); 898 pci_config_put32(handle, offset + 4, 899 PCICFG_HIADDR(mem_answer)); 900 cardbus_err(dip, 8, 901 "REGISTER (64)LO [0x%x] ----> [0x%02x]\n", 902 pci_config_get32(handle, offset), offset); 903 cardbus_err(dip, 8, 904 "REGISTER (64)HI [0x%x] ----> [0x%02x]\n", 905 pci_config_get32(handle, offset+4), 906 offset+4); 907 reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer); 908 reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer); 909 break; 910 911 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 912 /* allocate memory space from the allocator */ 913 914 (void) cardbus_get_mem(ddi_get_parent(dip), 915 entry, reg[i].pci_size_low, &mem_answer); 916 pci_config_put32(handle, offset, 0xffffffff); 917 request = pci_config_get32(handle, offset); 918 919 pci_config_put32(handle, offset, 920 (uint32_t)mem_answer); 921 reg[i].pci_phys_low = (uint32_t)mem_answer; 922 reg[i].pci_phys_mid = 0; 923 if (((PCI_BASE_TYPE_M & request) == 924 PCI_BASE_TYPE_ALL) && 925 ((PCI_BASE_SPACE_M & request) == 926 PCI_BASE_SPACE_MEM)) { 927 cardbus_err(dip, 8, 928 "REGISTER (64)LO [0x%x] ----> " 929 "[0x%02x]\n", 930 pci_config_get32(handle, offset), 931 offset); 932 pci_config_put32(handle, 933 offset + 4, 0); 934 cardbus_err(dip, 8, 935 "REGISTER (64)HI [0x%x] ----> " 936 "[0x%02x]\n", 937 pci_config_get32(handle, offset+4), 938 offset+4); 939 } else { 940 cardbus_err(dip, 8, 941 "REGISTER (32)LO [0x%x] ----> " 942 "[0x%02x]\n", 943 pci_config_get32(handle, offset), 944 offset); 945 } 946 break; 947 948 case PCI_REG_ADDR_G(PCI_ADDR_IO): 949 /* allocate I/O space from the allocator */ 950 951 (void) cardbus_get_io(ddi_get_parent(dip), 952 entry, reg[i].pci_size_low, &io_answer); 953 pci_config_put32(handle, offset, io_answer); 954 cardbus_err(dip, 8, 955 "REGISTER (I/O)LO [0x%x] ----> [0x%02x]\n", 956 pci_config_get32(handle, offset), offset); 957 reg[i].pci_phys_low = io_answer; 958 break; 959 960 default: 961 cardbus_err(dip, 1, "Unknown register type\n"); 962 kmem_free(reg, length); 963 (void) cardbus_config_teardown(&handle); 964 entry->error = PCICFG_FAILURE; 965 return (DDI_WALK_TERMINATE); 966 } /* switch */ 967 968 /* 969 * Now that memory locations are assigned, 970 * update the assigned address property. 971 */ 972 if (cardbus_update_assigned_prop(dip, 973 ®[i]) != PCICFG_SUCCESS) { 974 kmem_free(reg, length); 975 (void) cardbus_config_teardown(&handle); 976 entry->error = PCICFG_FAILURE; 977 return (DDI_WALK_TERMINATE); 978 } 979 } 980 } 981 kmem_free(reg, length); 982 enable_cardbus_device(dip, handle); 983#ifdef CARDBUS_DEBUG 984 if (cardbus_debug >= 9) { 985 cardbus_dump_config(handle); 986 } 987#endif 988bad_device: 989 (void) cardbus_config_teardown(&handle); 990 return (DDI_WALK_CONTINUE); 991} 992 993static int 994cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 995 ddi_acc_handle_t handle) 996{ 997 struct ebus_pci_rangespec range; 998 int count; 999 pci_regspec_t *reg; 1000 int length; 1001 int rcount; 1002 uint32_t io_answer = 0xffffffff; 1003 isa_phdl_t isa_phdl; 1004 int i; 1005 1006 cardbus_err(dip, 8, "cardbus_isa_bridge_ranges\n"); 1007 1008 bzero((caddr_t)&range, sizeof (range)); 1009 1010#ifdef sparc 1011 /* 1012 * If there is an interrupt pin set program 1013 * interrupt line with default values. 1014 */ 1015 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1016 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1017 } 1018#else 1019 (void) cardbus_validate_iline(dip, handle); 1020#endif 1021 1022 /* 1023 * For each "reg" property with a length, allocate memory. 1024 */ 1025 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1026 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1027 &length) != DDI_PROP_SUCCESS) { 1028 cardbus_err(dip, 1, "Failed to read reg property\n"); 1029 entry->error = PCICFG_FAILURE; 1030 return (DDI_WALK_TERMINATE); 1031 } 1032 1033 rcount = length / sizeof (pci_regspec_t); 1034 1035 for (i = 0; i < rcount; i++) { 1036 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 1037 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1038 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1039 /* allocate I/O space from the allocator */ 1040 1041 (void) cardbus_get_io(ddi_get_parent(dip), 1042 entry, reg[i].pci_size_low, &io_answer); 1043 cardbus_err(dip, 8, 1044 "ISA (I/O)LO ----> [0x%x]\n", io_answer); 1045 reg[i].pci_phys_low = io_answer; 1046 range.phys_hi = 0; 1047 range.phys_low = io_answer; 1048 range.par_phys_hi = reg[i].pci_phys_hi | 1049 PCI_REG_REL_M; 1050 range.par_phys_low = reg[i].pci_phys_low; 1051 range.par_phys_mid = reg[i].pci_phys_mid; 1052 range.rng_size = reg[i].pci_size_low; 1053 i = rcount; 1054 break; 1055 1056 default: 1057 cardbus_err(dip, 1, "Unknown register type\n"); 1058 kmem_free(reg, length); 1059 (void) cardbus_config_teardown(&handle); 1060 entry->error = PCICFG_FAILURE; 1061 return (DDI_WALK_TERMINATE); 1062 } /* switch */ 1063 } 1064 } 1065 kmem_free(reg, length); 1066 1067 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1068 dip, "ranges", (int *)&range, 1069 sizeof (range)/sizeof (int)); 1070 if (io_answer != 0xffffffff) { 1071 isa_phdl.dip = dip; 1072 isa_phdl.handle = handle; 1073 isa_phdl.io_base = io_answer; 1074 isa_phdl.io_decode_reg = 0x58; /* Pos decoded IO space 0 reg */ 1075 /* i_ndi_block_device_tree_changes(&count); */ 1076 ndi_devi_enter(dip, &count); 1077 ddi_walk_devs(ddi_get_child(dip), 1078 cardbus_add_isa_reg, (void *)&isa_phdl); 1079 /* i_ndi_allow_device_tree_changes(count); */ 1080 ndi_devi_exit(dip, count); 1081 } 1082 return (DDI_WALK_PRUNECHILD); 1083} 1084 1085/* 1086 * This is specific to ITE8888 chip. 1087 */ 1088static int 1089cardbus_add_isa_reg(dev_info_t *dip, void *arg) 1090{ 1091 uint32_t io_reg = 0; 1092 int length; 1093 uint32_t reg[3], *breg; 1094 isa_phdl_t *phdl; 1095 uint8_t sz; 1096 1097 phdl = (isa_phdl_t *)arg; 1098 cardbus_err(dip, 6, 1099 "cardbus_add_isa_reg, base 0x%x\n", phdl->io_base); 1100 1101 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1102 DDI_PROP_DONTPASS, "basereg", (caddr_t)&breg, 1103 &length) != DDI_PROP_SUCCESS) { 1104 return (DDI_WALK_CONTINUE); 1105 } 1106 1107 if ((length / sizeof (reg)) < 1) { 1108 kmem_free(breg, length); 1109 return (DDI_WALK_CONTINUE); 1110 } 1111 1112 /* 1113 * Add the "reg" property. 1114 */ 1115 reg[0] = 0; 1116 reg[1] = breg[1] + phdl->io_base; 1117 reg[2] = breg[2]; 1118 1119 /* 1120 * Generate the postive IO decode register setting. 1121 */ 1122 for (sz = 0; sz < 8; sz++) 1123 if ((1<<sz) >= breg[2]) { 1124 io_reg = breg[1] 1125 | (1uL <<31) /* Enable */ 1126 | (2uL <<29) /* Medium speed */ 1127 | (1uL <<28) /* Aliase enable, */ 1128 /* Don't care A[15:10] */ 1129 | (sz<<24); /* Size code */ 1130 break; 1131 } 1132 1133 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1134 "reg", (int *)reg, 3); 1135 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "basereg"); 1136 1137 if (io_reg) { 1138 pci_config_put32(phdl->handle, phdl->io_decode_reg, io_reg); 1139 cardbus_err(dip, 6, 1140 "cardbus_add_isa_reg: I/O decode reg (0x%x) set to 0x%x\n", 1141 phdl->io_decode_reg, 1142 pci_config_get32(phdl->handle, phdl->io_decode_reg)); 1143 phdl->io_decode_reg += sizeof (io_reg); 1144 } else 1145 cardbus_err(dip, 1, 1146 "cardbus_add_isa_reg: register size (0x%x) too large\n", 1147 breg[2]); 1148 kmem_free(breg, length); 1149 return (DDI_WALK_CONTINUE); 1150} 1151 1152/* 1153 * In case we want to ensure that some space is allocated to the 1154 * device tree below the cardbus bridge. 1155 * This is only necessary if there is a device that needs to allocate 1156 * resource below us. This can happen if there is another cardbus/PCMCIA 1157 * bridge downstream. 1158 */ 1159static uint32_t cardbus_min_spare_mem = 0; 1160static uint32_t cardbus_min_spare_io = 0; 1161 1162/* 1163 * The "dip" passed to this routine is assumed to be 1164 * the device at the attachment point. Currently it is 1165 * assumed to be a bridge. 1166 */ 1167static int 1168cardbus_allocate_chunk(dev_info_t *dip, uint8_t type, uint8_t sec_bus) 1169{ 1170 cardbus_phdl_t *phdl; 1171 ndi_ra_request_t *mem_request; 1172 ndi_ra_request_t *io_request; 1173 uint64_t mem_answer; 1174 uint64_t io_answer; 1175 int count; 1176 uint64_t alen; 1177 1178 /* 1179 * This should not find an existing entry - so 1180 * it will create a new one. 1181 */ 1182 phdl = cardbus_find_phdl(dip); 1183 ASSERT(phdl); 1184 1185 mem_request = &phdl->mem_req; 1186 io_request = &phdl->io_req; 1187 1188 /* 1189 * Set highest_bus here. 1190 * Otherwise if we don't find another bridge 1191 * this never gets set. 1192 */ 1193 phdl->highest_bus = sec_bus; 1194 1195 /* 1196 * From this point in the tree - walk the devices, 1197 * The function passed in will read and "sum" up 1198 * the memory and I/O requirements and put them in 1199 * structure "phdl". 1200 */ 1201 phdl->error = PCICFG_SUCCESS; 1202 ndi_devi_enter(dip, &count); 1203 ddi_walk_devs(ddi_get_child(dip), cardbus_sum_resources, (void *)phdl); 1204 ndi_devi_exit(dip, count); 1205 1206 if (phdl->error != PCICFG_SUCCESS) { 1207 cardbus_err(dip, 1, "Failure summing resources\n"); 1208 return (phdl->error); 1209 } 1210 1211 /* 1212 * Call into the memory allocator with the request. 1213 * Record the addresses returned in the phdl 1214 */ 1215#ifdef _LP64 1216 cardbus_err(dip, 8, 1217 "AP requires [0x%lx] bytes of memory space, alligned 0x%x\n", 1218 mem_request->ra_len, phdl->memory_gran); 1219 cardbus_err(dip, 8, 1220 "AP requires [0x%lx] bytes of I/O space, alligned 0x%x\n", 1221 io_request->ra_len, phdl->io_gran); 1222#else 1223 cardbus_err(dip, 8, 1224 "AP requires [0x%llx] bytes of memory space, alligned 0x%x\n", 1225 mem_request->ra_len, phdl->memory_gran); 1226 cardbus_err(dip, 8, 1227 "AP requires [0x%llx] bytes of I/O space, alligned 0x%x\n", 1228 io_request->ra_len, phdl->io_gran); 1229#endif 1230 1231 ASSERT(type == PCI_HEADER_CARDBUS); 1232 1233 mem_request->ra_align_mask = phdl->memory_gran - 1; 1234 io_request->ra_align_mask = phdl->io_gran - 1; 1235 1236 mem_request->ra_len += cardbus_min_spare_mem; 1237 if (mem_request->ra_len) { 1238 mem_request->ra_len = PCICFG_ROUND_UP( 1239 mem_request->ra_len, 1240 phdl->memory_gran); 1241#ifdef _LP64 1242 cardbus_err(dip, 8, 1243 "cardbus_allocate_chunk: ndi_ra_alloc 0x%lx bytes\n", 1244 mem_request->ra_len); 1245#else 1246 cardbus_err(dip, 8, 1247 "cardbus_allocate_chunk: ndi_ra_alloc 0x%llx bytes\n", 1248 mem_request->ra_len); 1249#endif 1250 1251 if (ndi_ra_alloc(dip, mem_request, &mem_answer, &alen, 1252 NDI_RA_TYPE_MEM, NDI_RA_PASS) != NDI_SUCCESS) { 1253 cardbus_err(dip, 1, "Failed to allocate memory\n"); 1254 return (PCICFG_FAILURE); 1255 } 1256 1257 phdl->memory_base = phdl->memory_last = mem_answer; 1258 phdl->memory_len = alen; 1259 } 1260 1261 io_request->ra_len += cardbus_min_spare_io; 1262 if (io_request->ra_len) { 1263 1264 io_request->ra_boundbase = 0; 1265 io_request->ra_boundlen = PCICFG_4GIG_LIMIT; 1266 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1267 io_request->ra_len = PCICFG_ROUND_UP(io_request->ra_len, 1268 phdl->io_gran); 1269 1270 if (ndi_ra_alloc(dip, io_request, &io_answer, 1271 &alen, NDI_RA_TYPE_IO, NDI_RA_PASS) != NDI_SUCCESS) { 1272 cardbus_err(dip, 1, "Failed to allocate I/O space\n"); 1273 if (mem_request->ra_len) { 1274 (void) ndi_ra_free(dip, mem_answer, 1275 alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 1276 phdl->memory_len = phdl->io_len = 0; 1277 } 1278 return (PCICFG_FAILURE); 1279 } 1280 1281 phdl->io_base = phdl->io_last = (uint32_t)io_answer; 1282 phdl->io_len = (uint32_t)alen; 1283 } 1284 1285#ifdef _LP64 1286 cardbus_err(dip, 6, 1287 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 1288 phdl->memory_base, phdl->memory_len); 1289#else 1290 cardbus_err(dip, 6, 1291 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 1292 phdl->memory_base, phdl->memory_len); 1293#endif 1294 cardbus_err(dip, 6, 1295 "IO BASE = [0x%x] length [0x%x]\n", 1296 phdl->io_base, phdl->io_len); 1297 1298 return (PCICFG_SUCCESS); 1299} 1300 1301static int 1302cardbus_free_chunk(dev_info_t *dip) 1303{ 1304 uint_t *bus; 1305 int k; 1306 1307 cardbus_err(dip, 6, "cardbus_free_chunk\n"); 1308 1309 (void) cardbus_destroy_phdl(dip); 1310 1311 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1312 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 1313 &k) != DDI_PROP_SUCCESS) { 1314 cardbus_err(dip, 1, 1315 "cardbus_free_chunk: Failed to read bus-range property\n"); 1316 return (PCICFG_FAILURE); 1317 } 1318 1319 cardbus_err(dip, 6, 1320 "cardbus_free_chunk: Freeing bus [%d] range [%d]\n", 1321 bus[0], bus[1] - bus[0] + 1); 1322 1323 if (ndi_ra_free(dip, 1324 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 1325 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1326 cardbus_err(dip, 1, 1327 "cardbus_free_chunk: Failed to free bus numbers\n"); 1328 1329 kmem_free(bus, k); 1330 return (PCICFG_FAILURE); 1331 } 1332 1333 kmem_free(bus, k); 1334 return (PCICFG_SUCCESS); 1335} 1336 1337/* 1338 * Put bridge registers into initial state 1339 */ 1340static void 1341cardbus_setup_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1342 ddi_acc_handle_t handle) 1343{ 1344 uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1345 1346#ifdef _LP64 1347 cardbus_err(NULL, 6, 1348 "cardbus_setup_bridge: " 1349 "highest bus %d, mem_last 0x%lx, io_last 0x%x\n", 1350 entry->highest_bus, entry->memory_last, entry->io_last); 1351#else 1352 cardbus_err(NULL, 6, 1353 "cardbus_setup_bridge: " 1354 "highest bus %d, mem_last 0x%llx, io_last 0x%x\n", 1355 entry->highest_bus, entry->memory_last, entry->io_last); 1356#endif 1357 1358 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1359 uint32_t uval; 1360 1361 /* 1362 * The highest bus seen during probing is 1363 * the max-subordinate bus 1364 */ 1365 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 1366 1367 uval = PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN); 1368 if (uval != entry->memory_last) { 1369#ifdef _LP64 1370 cardbus_err(dip, 8, 1371 "Adding [0x%lx] before bridge (mem)\n", 1372 uval - entry->memory_last); 1373#else 1374 cardbus_err(dip, 8, 1375 "Adding [0x%llx] before bridge (mem)\n", 1376 uval - entry->memory_last); 1377#endif 1378 (void) cardbus_get_mem(ddi_get_parent(dip), entry, 1379 uval - entry->memory_last, NULL); 1380 } 1381 1382 /* 1383 * Program the memory base register with the 1384 * start of the memory range 1385 */ 1386#ifdef _LP64 1387 cardbus_err(NULL, 8, 1388 "store 0x%x(0x%lx) in pci bridge memory base register\n", 1389 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1390 entry->memory_last); 1391#else 1392 cardbus_err(NULL, 8, 1393 "store 0x%x(0x%llx) in pci bridge memory base register\n", 1394 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1395 entry->memory_last); 1396#endif 1397 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 1398 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1399 1400 uval = PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN); 1401 if (uval != entry->io_last) { 1402 cardbus_err(dip, 8, 1403 "Adding [0x%x] before bridge (I/O)\n", 1404 uval - entry->io_last); 1405 (void) cardbus_get_io(ddi_get_parent(dip), entry, 1406 uval - entry->io_last, NULL); 1407 } 1408 cardbus_err(NULL, 8, 1409 "store 0x%02x/0x%04x(0x%x) in " 1410 "pci bridge I/O hi/low base register\n", 1411 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1412 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval))), 1413 entry->io_last); 1414 /* 1415 * Program the I/O base register with the start of the I/O range 1416 */ 1417 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 1418 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval)))); 1419 1420 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 1421 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1422 1423 /* 1424 * Clear status bits 1425 */ 1426 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 1427 1428 /* 1429 * Turn off prefetchable range 1430 */ 1431 pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff); 1432 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 1433 1434 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0); 1435 1436#ifdef sparc 1437 /* 1438 * If there is an interrupt pin set program 1439 * interrupt line with default values. 1440 */ 1441 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1442 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1443 } 1444#else 1445 (void) cardbus_validate_iline(dip, handle); 1446#endif 1447 1448 1449 } else if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_CARDBUS) { 1450 1451 /* 1452 * The highest bus seen during probing is 1453 * the max-subordinate bus 1454 */ 1455 pci_config_put8(handle, PCI_CBUS_SUB_BUS_NO, 1456 entry->highest_bus); 1457 1458 /* 1459 * Program the memory base register with the 1460 * start of the memory range 1461 */ 1462#ifdef _LP64 1463 cardbus_err(NULL, 8, 1464 "store 0x%x(0x%lx) in " 1465 "cardbus memory base register 0, len 0x%lx\n", 1466 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1467 entry->memory_len); 1468#else 1469 cardbus_err(NULL, 8, 1470 "store 0x%x(0x%llx) in " 1471 "cardbus memory base register 0, len 0x%llx\n", 1472 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1473 entry->memory_len); 1474#endif 1475 1476 pci_config_put32(handle, PCI_CBUS_MEM_BASE0, 1477 PCICFG_LOADDR(entry->memory_last)); 1478 1479 /* 1480 * Program the I/O base register with the start of the I/O range 1481 */ 1482 cardbus_err(NULL, 8, 1483 "store 0x%x in cb IO base register 0 len 0x%x\n", 1484 PCICFG_LOADDR(entry->io_last), 1485 entry->io_len); 1486 1487 pci_config_put32(handle, PCI_CBUS_IO_BASE0, 1488 PCICFG_LOADDR(entry->io_last)); 1489 1490 /* 1491 * Clear status bits 1492 */ 1493 pci_config_put16(handle, PCI_CBUS_SEC_STATUS, 0xffff); 1494 1495#ifdef sparc 1496 /* 1497 * If there is an interrupt pin set program 1498 * interrupt line with default values. 1499 */ 1500 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1501 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1502 } 1503#else 1504 (void) cardbus_validate_iline(dip, handle); 1505#endif 1506 1507 1508 /* 1509 * LATER: use these registers 1510 */ 1511 pci_config_put32(handle, PCI_CBUS_MEM_BASE1, 0); 1512 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT1, 0); 1513 pci_config_put32(handle, PCI_CBUS_IO_BASE1, 0); 1514 pci_config_put32(handle, PCI_CBUS_IO_LIMIT1, 0); 1515 } else { 1516 cmn_err(CE_WARN, "header type 0x%x, probably unknown bridge\n", 1517 header_type & PCI_HEADER_TYPE_M); 1518 } 1519 1520 cardbus_err(NULL, 7, "cardbus_setup_bridge complete\n"); 1521} 1522 1523static void 1524cardbus_update_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1525 ddi_acc_handle_t handle) 1526{ 1527 uint_t length; 1528 uint16_t word16 = pci_config_get16(handle, PCI_CONF_COMM); 1529 const uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER) 1530 & PCI_HEADER_TYPE_M; 1531 uint32_t bridge_gran; 1532 uint64_t rlval; 1533 1534 if (header_type == PCI_HEADER_CARDBUS) 1535 bridge_gran = CBCFG_MEMGRAN; 1536 else 1537 bridge_gran = PCICFG_MEMGRAN; 1538 1539 /* 1540 * Program the memory limit register with the end of the memory range 1541 */ 1542#ifdef _LP64 1543 cardbus_err(dip, 6, 1544 "cardbus_update_bridge: Mem base 0x%lx len 0x%lx " 1545 "last 0x%lx gran 0x%x gran end 0x%lx\n", 1546 entry->memory_base, entry->memory_len, 1547 entry->memory_last, entry->memory_gran, 1548 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1549#else 1550 cardbus_err(dip, 6, 1551 "cardbus_update_bridge: Mem base 0x%llx len 0x%llx " 1552 "last 0x%llx gran 0x%x gran end 0x%lx\n", 1553 entry->memory_base, entry->memory_len, 1554 entry->memory_last, entry->memory_gran, 1555 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1556#endif 1557 /* 1558 * Since this is a bridge, the rest of this range will 1559 * be responded to by the bridge. We have to round up 1560 * so no other device claims it. 1561 */ 1562 length = PCICFG_ROUND_UP(entry->memory_last + cardbus_min_spare_mem, 1563 bridge_gran) - entry->memory_last; 1564 1565 if (length > 0) { 1566 /* 1567 * This is to allow space that isn't actually being used by 1568 * anything to be allocated by devices such as a downstream 1569 * PCMCIA controller. 1570 */ 1571 (void) cardbus_get_mem(dip, entry, length, NULL); 1572 cardbus_err(dip, 8, 1573 "Added [0x%x] at the top of the bridge (mem)\n", length); 1574 } 1575 1576 if (entry->memory_len) { 1577 if (header_type == PCI_HEADER_CARDBUS) { 1578 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1579 CBCFG_MEMGRAN); 1580#ifdef _LP64 1581 cardbus_err(dip, 8, 1582 "store 0x%x(0x%lx) in memory limit register 0\n", 1583 PCICFG_LOADDR(rlval), rlval); 1584#else 1585 cardbus_err(dip, 8, 1586 "store 0x%x(0x%llx) in memory limit register 0\n", 1587 PCICFG_LOADDR(rlval), rlval); 1588#endif 1589 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT0, 1590 PCICFG_LOADDR(rlval)); 1591 } else { 1592 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1593 PCICFG_MEMGRAN); 1594#ifdef _LP64 1595 cardbus_err(dip, 8, 1596 "store 0x%x(0x%lx) in memory limit register\n", 1597 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1598 rlval); 1599#else 1600 cardbus_err(dip, 8, 1601 "store 0x%x(0x%llx) in memory limit register\n", 1602 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1603 rlval); 1604#endif 1605 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 1606 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1607 } 1608 word16 |= PCI_COMM_MAE; 1609 } 1610 1611 cardbus_err(dip, 6, 1612 "cardbus_update_bridge: I/O base 0x%x len 0x%x last 0x%x " 1613 "gran 0x%x gran_end 0x%lx\n", 1614 entry->io_base, entry->io_len, entry->io_last, entry->io_gran, 1615 PCICFG_ROUND_UP(entry->io_last, entry->io_gran)); 1616 1617 if (header_type == PCI_HEADER_CARDBUS) 1618 bridge_gran = CBCFG_IOGRAN; 1619 else 1620 bridge_gran = PCICFG_IOGRAN; 1621 1622 /* 1623 * Same as above for I/O space. Since this is a 1624 * bridge, the rest of this range will be responded 1625 * to by the bridge. We have to round up so no 1626 * other device claims it. 1627 */ 1628 length = PCICFG_ROUND_UP(entry->io_last + cardbus_min_spare_io, 1629 bridge_gran) - entry->io_last; 1630 if (length > 0) { 1631 (void) cardbus_get_io(dip, entry, length, NULL); 1632 cardbus_err(dip, 8, 1633 "Added [0x%x] at the top of the bridge (I/O)\n", length); 1634 } 1635 1636 /* 1637 * Program the I/O limit register with the end of the I/O range 1638 */ 1639 if (entry->io_len) { 1640 if (header_type == PCI_HEADER_CARDBUS) { 1641 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1642 CBCFG_IOGRAN); 1643#ifdef _LP64 1644 cardbus_err(dip, 8, 1645 "store 0x%lx in IO limit register 0\n", rlval); 1646#else 1647 cardbus_err(dip, 8, 1648 "store 0x%llx in IO limit register 0\n", rlval); 1649#endif 1650 pci_config_put32(handle, PCI_CBUS_IO_LIMIT0, rlval); 1651 } else { 1652 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1653 PCICFG_IOGRAN); 1654#ifdef _LP64 1655 cardbus_err(dip, 8, 1656 "store 0x%x/0x%x(0x%lx) in " 1657 "IO limit low/hi register\n", 1658 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1659 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1660 rlval); 1661#else 1662 cardbus_err(dip, 8, 1663 "store 0x%x/0x%x(0x%llx) in " 1664 "IO limit low/hi register\n", 1665 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1666 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1667 rlval); 1668#endif 1669 1670 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 1671 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval)))); 1672 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, 1673 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1674 } 1675 word16 |= PCI_COMM_IO; 1676 } 1677 1678 pci_config_put16(handle, PCI_CONF_COMM, word16); 1679} 1680 1681static void 1682cardbus_get_mem(dev_info_t *dip, cardbus_phdl_t *entry, 1683 uint32_t length, uint64_t *ans) 1684{ 1685 uint32_t hole; 1686 1687#ifdef _LP64 1688 cardbus_err(NULL, 6, 1689 "cardbus_get_mem: memory_last 0x%lx, length 0x%x, " 1690 "memory_base 0x%lx, memory_len 0x%lx ans=0x%p\n", 1691 entry->memory_last, length, 1692 entry->memory_base, entry->memory_len, (void *) ans); 1693#else 1694 cardbus_err(NULL, 6, 1695 "cardbus_get_mem: memory_last 0x%llx, length 0x%x, " 1696 "memory_base 0x%llx, memory_len 0x%llx ans=0x%p\n", 1697 entry->memory_last, length, 1698 entry->memory_base, entry->memory_len, (void *) ans); 1699#endif 1700 1701 if (ans) { 1702 /* 1703 * Round up the request to the "size" boundary 1704 */ 1705 hole = PCICFG_ROUND_UP(entry->memory_last, length) 1706 - entry->memory_last; 1707 if (hole != 0) { 1708 (void) cardbus_update_available_prop(dip, 1709 PCI_ADDR_MEM32, 1710 entry->memory_last, 1711 (uint64_t)hole); 1712 entry->memory_last += hole; 1713 1714#ifdef _LP64 1715 cardbus_err(NULL, 6, 1716 "cardbus_get_mem: " 1717 "rounded memory_last up by 0x%x to 0x%lx, ", 1718 hole, entry->memory_last); 1719#else 1720 cardbus_err(NULL, 6, 1721 "cardbus_get_mem: " 1722 "rounded memory_last up by 0x%x to 0x%llx, ", 1723 hole, entry->memory_last); 1724#endif 1725 } 1726 } else 1727 (void) cardbus_update_available_prop(dip, PCI_ADDR_MEM32, 1728 entry->memory_last, 1729 (uint64_t)length); 1730 1731 /* 1732 * These routines should parcel out the memory 1733 * completely. There should never be a case of 1734 * over running the bounds. 1735 */ 1736 if ((entry->memory_last + length) > 1737 (entry->memory_base + entry->memory_len)) 1738#ifdef _LP64 1739 cardbus_err(NULL, 1, 1740 "cardbus_get_mem: assert will fail %ld <= %ld," 1741 "(0x%lx + 0x%x) <= (0x%lx + 0x%lx)\n", 1742#else 1743 cardbus_err(NULL, 1, 1744 "cardbus_get_mem: assert will fail %lld <= %lld, " 1745 "(0x%llx + 0x%x) <= (0x%llx + 0x%llx)\n", 1746#endif 1747 entry->memory_last + length, 1748 entry->memory_base + entry->memory_len, 1749 entry->memory_last, 1750 length, 1751 entry->memory_base, 1752 entry->memory_len); 1753 1754 ASSERT((entry->memory_last + length) <= 1755 (entry->memory_base + entry->memory_len)); 1756 /* 1757 * If ans is NULL don't return anything, 1758 * they are just asking to reserve the memory. 1759 */ 1760 if (ans != NULL) 1761 *ans = entry->memory_last; 1762 1763 /* 1764 * Increment to the next location 1765 */ 1766 entry->memory_last += length; 1767} 1768 1769static void 1770cardbus_get_io(dev_info_t *dip, cardbus_phdl_t *entry, 1771 uint32_t length, uint32_t *ans) 1772{ 1773 uint32_t hole; 1774 1775 cardbus_err(NULL, 6, 1776 "cardbus_get_io: io_last 0x%x, length 0x%x, " 1777 "io_base 0x%x, io_len 0x%x ans=0x%p\n", 1778 entry->io_last, length, 1779 entry->io_base, entry->io_len, (void *) ans); 1780 1781 if (ans) { 1782 /* 1783 * Round up the request to the "size" boundary 1784 */ 1785 hole = PCICFG_ROUND_UP(entry->io_last, length) - entry->io_last; 1786 if (hole != 0) { 1787 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1788 (uint64_t)entry->io_last, 1789 (uint64_t)hole); 1790 entry->io_last += hole; 1791 1792 cardbus_err(NULL, 6, 1793 "cardbus_get_io: " 1794 "rounded io_last up by 0x%x to 0x%x, ", 1795 hole, entry->io_last); 1796 } 1797 } else 1798 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1799 (uint64_t)entry->io_last, 1800 (uint64_t)length); 1801 /* 1802 * These routines should parcel out the memory 1803 * completely. There should never be a case of 1804 * over running the bounds. 1805 */ 1806 ASSERT((entry->io_last + length) <= 1807 (entry->io_base + entry->io_len)); 1808 1809 /* 1810 * If ans is NULL don't return anything, 1811 * they are just asking to reserve the memory. 1812 */ 1813 if (ans != NULL) 1814 *ans = entry->io_last; 1815 1816 /* 1817 * Increment to the next location 1818 */ 1819 entry->io_last += length; 1820} 1821 1822static int 1823cardbus_sum_resources(dev_info_t *dip, void *hdl) 1824{ 1825 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 1826 pci_regspec_t *pci_rp; 1827 int length; 1828 int rcount; 1829 int i, ret; 1830 ndi_ra_request_t *mem_request; 1831 ndi_ra_request_t *io_request; 1832 uint8_t header_type, base_class; 1833 ddi_acc_handle_t handle; 1834 1835 /* 1836 * Ignore the attachment point and pcs. 1837 */ 1838 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 1839 strcmp(ddi_binding_name(dip), "pcs") == 0) { 1840 cardbus_err(dip, 8, "cardbus_sum_resources: Ignoring\n"); 1841 return (DDI_WALK_CONTINUE); 1842 } 1843 1844 mem_request = &entry->mem_req; 1845 io_request = &entry->io_req; 1846 1847 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 1848 cardbus_err(dip, 1, 1849 "cardbus_sum_resources: Failed to map config space!\n"); 1850 entry->error = PCICFG_FAILURE; 1851 return (DDI_WALK_TERMINATE); 1852 } 1853 1854 ret = DDI_WALK_CONTINUE; 1855 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1856 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 1857 1858 /* 1859 * If its a bridge - just record the highest bus seen 1860 */ 1861 if (base_class == PCI_CLASS_BRIDGE) { 1862 uint8_t sub_class; 1863 1864 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 1865 1866 switch (sub_class) { 1867 case PCI_BRIDGE_PCI: 1868 if ((header_type & PCI_HEADER_TYPE_M) 1869 == PCI_HEADER_PPB) { 1870 1871 if (entry->highest_bus < pci_config_get8(handle, 1872 PCI_BCNF_SECBUS)) { 1873 entry->highest_bus = pci_config_get8( 1874 handle, PCI_BCNF_SECBUS); 1875 } 1876 1877 (void) cardbus_config_teardown(&handle); 1878#if defined(CARDBUS_DEBUG) 1879 if (mem_request->ra_len != 1880 PCICFG_ROUND_UP(mem_request->ra_len, 1881 PCICFG_MEMGRAN)) { 1882 1883#ifdef _LP64 1884 cardbus_err(dip, 8, 1885 "Pre-align [0x%lx] to PCI bridge " 1886 "memory gran " 1887 "[0x%lx] -> [0x%lx]\n", 1888 PCICFG_ROUND_UP(mem_request->ra_len, 1889 PCICFG_MEMGRAN) - 1890 mem_request->ra_len, 1891 mem_request->ra_len, 1892 PCICFG_ROUND_UP(mem_request->ra_len, 1893 PCICFG_MEMGRAN)); 1894#else 1895 cardbus_err(dip, 8, 1896 "Pre-align [0x%llx] to PCI bridge " 1897 "memory gran " 1898 "[0x%llx] -> [0x%lx]\n", 1899 PCICFG_ROUND_UP(mem_request->ra_len, 1900 PCICFG_MEMGRAN) - 1901 mem_request->ra_len, 1902 mem_request->ra_len, 1903 PCICFG_ROUND_UP(mem_request->ra_len, 1904 PCICFG_MEMGRAN)); 1905#endif 1906 } 1907 1908 if (io_request->ra_len != 1909 PCICFG_ROUND_UP(io_request->ra_len, 1910 PCICFG_IOGRAN)) { 1911 1912#ifdef _LP64 1913 cardbus_err(dip, 8, 1914 "Pre-align [0x%lx] to PCI bridge " 1915 "I/O gran " 1916 "[0x%lx] -> [0x%lx]\n", 1917 PCICFG_ROUND_UP(io_request->ra_len, 1918 PCICFG_IOGRAN) - 1919 io_request->ra_len, 1920 io_request->ra_len, 1921 PCICFG_ROUND_UP(io_request->ra_len, 1922 PCICFG_IOGRAN)); 1923#else 1924 cardbus_err(dip, 8, 1925 "Pre-align [0x%llx] to PCI bridge " 1926 "I/O gran " 1927 "[0x%llx] -> [0x%lx]\n", 1928 PCICFG_ROUND_UP(io_request->ra_len, 1929 PCICFG_IOGRAN) - 1930 io_request->ra_len, 1931 io_request->ra_len, 1932 PCICFG_ROUND_UP(io_request->ra_len, 1933 PCICFG_IOGRAN)); 1934#endif 1935 } 1936 1937#endif 1938 mem_request->ra_len = PCICFG_ROUND_UP( 1939 mem_request->ra_len, 1940 PCICFG_MEMGRAN); 1941 io_request->ra_len = PCICFG_ROUND_UP( 1942 io_request->ra_len, 1943 PCICFG_IOGRAN); 1944 if (entry->memory_gran < PCICFG_MEMGRAN) 1945 entry->memory_gran = PCICFG_MEMGRAN; 1946 if (entry->io_gran < PCICFG_IOGRAN) 1947 entry->io_gran = PCICFG_IOGRAN; 1948 ddi_walk_devs(ddi_get_child(dip), 1949 cardbus_sum_resources, 1950 (void *)entry); 1951#if defined(CARDBUS_DEBUG) 1952 if (mem_request->ra_len != 1953 PCICFG_ROUND_UP(mem_request->ra_len + 1954 cardbus_min_spare_mem, PCICFG_MEMGRAN)) { 1955 1956#ifdef _LP64 1957 cardbus_err(dip, 8, 1958 "Post-align [0x%lx] to PCI bridge " 1959 "memory gran " 1960 "[0x%lx] -> [0x%lx]\n", 1961 PCICFG_ROUND_UP( 1962 mem_request->ra_len + 1963 cardbus_min_spare_mem, 1964 PCICFG_MEMGRAN) - 1965 mem_request->ra_len, 1966 mem_request->ra_len, 1967 PCICFG_ROUND_UP(mem_request->ra_len 1968 + cardbus_min_spare_mem, 1969 PCICFG_MEMGRAN)); 1970#else 1971 cardbus_err(dip, 8, 1972 "Post-align [0x%llx] to PCI bridge " 1973 "memory gran " 1974 "[0x%llx] -> [0x%lx]\n", 1975 PCICFG_ROUND_UP( 1976 mem_request->ra_len + 1977 cardbus_min_spare_mem, 1978 PCICFG_MEMGRAN) - 1979 mem_request->ra_len, 1980 mem_request->ra_len, 1981 PCICFG_ROUND_UP(mem_request->ra_len 1982 + cardbus_min_spare_mem, 1983 PCICFG_MEMGRAN)); 1984#endif 1985 } 1986 1987 if (io_request->ra_len != 1988 PCICFG_ROUND_UP(io_request->ra_len + 1989 cardbus_min_spare_io, 1990 PCICFG_IOGRAN)) { 1991 1992#ifdef _LP64 1993 cardbus_err(dip, 8, 1994 "Post-align [0x%lx] to PCI bridge " 1995 "I/O gran " 1996 "[0x%lx] -> [0x%lx]\n", 1997 PCICFG_ROUND_UP(io_request->ra_len + 1998 cardbus_min_spare_io, 1999 PCICFG_IOGRAN) - 2000 io_request->ra_len, 2001 io_request->ra_len, 2002 PCICFG_ROUND_UP(io_request->ra_len + 2003 cardbus_min_spare_io, 2004 PCICFG_IOGRAN)); 2005#else 2006 cardbus_err(dip, 8, 2007 "Post-align [0x%llx] to PCI bridge " 2008 "I/O gran " 2009 "[0x%llx] -> [0x%lx]\n", 2010 PCICFG_ROUND_UP(io_request->ra_len + 2011 cardbus_min_spare_io, 2012 PCICFG_IOGRAN) - 2013 io_request->ra_len, 2014 io_request->ra_len, 2015 PCICFG_ROUND_UP(io_request->ra_len + 2016 cardbus_min_spare_io, 2017 PCICFG_IOGRAN)); 2018#endif 2019 } 2020#endif 2021 mem_request->ra_len = PCICFG_ROUND_UP( 2022 mem_request->ra_len + 2023 cardbus_min_spare_mem, 2024 PCICFG_MEMGRAN); 2025 io_request->ra_len = PCICFG_ROUND_UP( 2026 io_request->ra_len + 2027 cardbus_min_spare_io, 2028 PCICFG_IOGRAN); 2029 } 2030 return (DDI_WALK_PRUNECHILD); 2031 2032 case PCI_BRIDGE_CARDBUS: 2033 /* 2034 * Cardbus has I/O registers. 2035 */ 2036 break; 2037 2038 case PCI_BRIDGE_ISA: 2039 /* 2040 * All the registers requirements for ISA 2041 * are stored in the reg structure of the bridge. 2042 * Children of ISA are not of type PCI 2043 * so must not come through here because 2044 * cardbus_config_setup() will fail. 2045 */ 2046 ret = DDI_WALK_PRUNECHILD; 2047 break; 2048 2049 default: 2050 /* 2051 * Treat other bridges as leaf nodes. 2052 */ 2053 break; 2054 } 2055 } 2056 2057 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2058 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, 2059 &length) != DDI_PROP_SUCCESS) { 2060 /* 2061 * If one node in (the subtree of nodes) 2062 * does'nt have a "reg" property fail the 2063 * allocation. 2064 */ 2065 entry->memory_len = 0; 2066 entry->io_len = 0; 2067 entry->error = PCICFG_FAILURE; 2068 (void) cardbus_config_teardown(&handle); 2069 return (DDI_WALK_TERMINATE); 2070 } 2071 2072 /* 2073 * For each "reg" property with a length, add that to the 2074 * total memory (or I/O) to allocate. 2075 */ 2076 rcount = length / sizeof (pci_regspec_t); 2077 2078 for (i = 0; i < rcount; i++) { 2079 2080 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2081 2082 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2083 mem_request->ra_len = 2084 pci_rp[i].pci_size_low + 2085 PCICFG_ROUND_UP(mem_request->ra_len, 2086 pci_rp[i].pci_size_low); 2087 2088 cardbus_err(dip, 8, 2089 "ADDING 32 --->0x%x for BAR@0x%x\n", 2090 pci_rp[i].pci_size_low, 2091 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2092 /* 2093 * the granualarity needs to be the larger of 2094 * the maximum amount of memory that we're going to 2095 * ask for, and the PCI-PCI bridge granularity (1M) 2096 */ 2097 if (pci_rp[i].pci_size_low > entry->memory_gran) 2098 entry->memory_gran = pci_rp[i].pci_size_low; 2099 break; 2100 2101 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2102 mem_request->ra_len = 2103 pci_rp[i].pci_size_low + 2104 PCICFG_ROUND_UP(mem_request->ra_len, 2105 pci_rp[i].pci_size_low); 2106 cardbus_err(dip, 8, 2107 "ADDING 64 --->0x%x for BAR@0x%x\n", 2108 pci_rp[i].pci_size_low, 2109 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2110 2111 if (pci_rp[i].pci_size_low > entry->memory_gran) 2112 entry->memory_gran = pci_rp[i].pci_size_low; 2113 break; 2114 2115 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2116 io_request->ra_len = 2117 pci_rp[i].pci_size_low + 2118 PCICFG_ROUND_UP(io_request->ra_len, 2119 pci_rp[i].pci_size_low); 2120 cardbus_err(dip, 8, 2121 "ADDING I/O --->0x%x for BAR@0x%x\n", 2122 pci_rp[i].pci_size_low, 2123 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2124 2125 if (pci_rp[i].pci_size_low > entry->io_gran) 2126 entry->io_gran = pci_rp[i].pci_size_low; 2127 break; 2128 2129 default: 2130 /* Config space register - not included */ 2131 break; 2132 } 2133 } 2134 2135 /* 2136 * free the memory allocated by ddi_getlongprop 2137 */ 2138 kmem_free(pci_rp, length); 2139 2140 /* 2141 * continue the walk to the next sibling to sum memory 2142 */ 2143 2144 (void) cardbus_config_teardown(&handle); 2145 2146#ifdef _LP64 2147 cardbus_err(dip, 8, 2148 "Memory 0x%lx bytes, I/O 0x%lx bytes, " 2149 "Memgran 0x%x, IOgran 0x%x\n", 2150 mem_request->ra_len, io_request->ra_len, 2151 entry->memory_gran, entry->io_gran); 2152#else 2153 cardbus_err(dip, 8, 2154 "Memory 0x%llx bytes, I/O 0x%llx bytes, " 2155 "Memgran 0x%x, IOgran 0x%x\n", 2156 mem_request->ra_len, io_request->ra_len, 2157 entry->memory_gran, entry->io_gran); 2158#endif 2159 2160 return (ret); 2161} 2162 2163/* 2164 * Free resources allocated to a bridge. 2165 * Note that this routine does not call ndi_ra_free() to actually 2166 * free memory/IO/Bus. This is done as a single chunk for the entire 2167 * device tree in cardbus_free_chunk(). 2168 */ 2169static int 2170cardbus_free_bridge_resources(dev_info_t *dip) 2171{ 2172 cardbus_range_t *ranges; 2173 uint_t *bus; 2174 int k; 2175 int length; 2176 int i; 2177 2178 cardbus_err(dip, 6, "cardbus_free_bridge_resources\n"); 2179 2180 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2181 DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges, 2182 &length) == DDI_PROP_SUCCESS) { 2183 for (i = 0; i < length / sizeof (cardbus_range_t); i++) { 2184 if (ranges[i].size_lo != 0 || ranges[i].size_hi != 0) { 2185 switch (ranges[i].parent_hi & PCI_REG_ADDR_M) { 2186 case PCI_ADDR_IO: 2187 cardbus_err(dip, 6, 2188 "Need to Free I/O " 2189 "base/length = [0x%x]/[0x%x]\n", 2190 ranges[i].child_lo, 2191 ranges[i].size_lo); 2192 break; 2193 2194 case PCI_ADDR_MEM32: 2195 case PCI_ADDR_MEM64: 2196 cardbus_err(dip, 6, 2197 "Need to Free Memory base/length = " 2198 "[0x%x.%x]/[0x%x]\n", 2199 ranges[i].child_mid, 2200 ranges[i].child_lo, 2201 ranges[i].size_lo); 2202 break; 2203 2204 default: 2205 cardbus_err(dip, 6, 2206 "Unknown memory space\n"); 2207 break; 2208 } 2209 } 2210 } 2211 2212 kmem_free(ranges, length); 2213 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "ranges"); 2214 } else { 2215 cardbus_err(dip, 8, 2216 "cardbus_free_bridge_resources: Failed" 2217 "to read ranges property\n"); 2218 } 2219 2220 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2221 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 2222 &k) != DDI_PROP_SUCCESS) { 2223 cardbus_err(dip, 6, "Failed to read bus-range property\n"); 2224 return (PCICFG_FAILURE); 2225 } 2226 2227 cardbus_err(dip, 6, 2228 "Need to free bus [%d] range [%d]\n", 2229 bus[0], bus[1] - bus[0] + 1); 2230 2231 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "available"); 2232 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "bus-range"); 2233 2234 return (PCICFG_SUCCESS); 2235} 2236 2237static int 2238cardbus_free_device_resources(dev_info_t *dip) 2239{ 2240 pci_regspec_t *assigned; 2241 2242 int length; 2243 int acount; 2244 int i; 2245 2246 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2247 DDI_PROP_DONTPASS, "assigned-addresses", 2248 (caddr_t)&assigned, 2249 &length) != DDI_PROP_SUCCESS) { 2250 cardbus_err(dip, 1, 2251 "Failed to read assigned-addresses property\n"); 2252 return (PCICFG_FAILURE); 2253 } 2254 2255 /* 2256 * For each "assigned-addresses" property entry with a length, 2257 * call the memory allocation routines to return the 2258 * resource. 2259 */ 2260 acount = length / sizeof (pci_regspec_t); 2261 for (i = 0; i < acount; i++) { 2262 2263 /* 2264 * Free the resource if the size of it is not zero. 2265 */ 2266 if ((assigned[i].pci_size_low != 0)|| 2267 (assigned[i].pci_size_hi != 0)) { 2268 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2269 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2270 cardbus_err(dip, 6, 2271 "Need to return 0x%x of 32 bit MEM space" 2272 " @ 0x%x from register 0x%x\n", 2273 assigned[i].pci_size_low, 2274 assigned[i].pci_phys_low, 2275 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2276 2277 break; 2278 2279 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2280 cardbus_err(dip, 6, 2281 "Need to return 0x%x of 64 bit MEM space" 2282 " @ 0x%x.%x from register 0x%x\n", 2283 assigned[i].pci_size_low, 2284 assigned[i].pci_phys_mid, 2285 assigned[i].pci_phys_low, 2286 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2287 2288 break; 2289 2290 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2291 cardbus_err(dip, 6, 2292 "Need to return 0x%x of IO space @ 0x%x" 2293 " from register 0x%x\n", 2294 assigned[i].pci_size_low, 2295 assigned[i].pci_phys_low, 2296 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2297 break; 2298 2299 default: 2300 cardbus_err(dip, 1, "Unknown register type\n"); 2301 kmem_free(assigned, length); 2302 return (PCICFG_FAILURE); 2303 } /* switch */ 2304 } 2305 } 2306 kmem_free(assigned, length); 2307 return (PCICFG_SUCCESS); 2308} 2309 2310static int 2311cardbus_free_resources(dev_info_t *dip) 2312{ 2313 uint32_t classcode; 2314 2315 classcode = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2316 "class-code", -1); 2317 /* 2318 * A different algorithim is used for bridges and leaf devices. 2319 */ 2320 if (classcode != -1) { 2321 classcode = ((uint_t)classcode & 0xffff00) >> 8; 2322 if (classcode == 0x604 || classcode == 0x607) { 2323 if (cardbus_free_bridge_resources(dip) 2324 != PCICFG_SUCCESS) { 2325 cardbus_err(dip, 1, 2326 "Failed freeing up bridge resources\n"); 2327 return (PCICFG_FAILURE); 2328 } 2329 return (PCICFG_SUCCESS); 2330 } 2331 } 2332 2333 if (cardbus_free_device_resources(dip) != PCICFG_SUCCESS) { 2334 cardbus_err(dip, 1, "Failed freeing up device resources\n"); 2335 return (PCICFG_FAILURE); 2336 } 2337 return (PCICFG_SUCCESS); 2338} 2339 2340static int 2341cardbus_probe_bridge(cbus_t *cbp, dev_info_t *attpt, uint_t bus, 2342 uint_t device, uint_t func) 2343{ 2344 /* Declairations */ 2345 cardbus_bus_range_t *bus_range; 2346 int i, j; 2347 uint8_t header_type; 2348 ddi_acc_handle_t config_handle; 2349 ndi_ra_request_t req; 2350 uint_t new_bus; 2351 uint64_t blen; 2352 uint64_t next_bus; 2353 int circ; 2354 2355 cardbus_err(cbp->cb_dip, 6, 2356 "cardbus_probe_bridge bus %d device %d func %d\n", 2357 bus, device, func); 2358 2359 ndi_devi_enter(cbp->cb_dip, &circ); 2360 if (pci_config_setup(cbp->cb_dip, &config_handle) != DDI_SUCCESS) { 2361 2362 cardbus_err(cbp->cb_dip, 1, 2363 "cardbus_probe_bridge(): Failed to setup config space\n"); 2364 2365 ndi_devi_exit(cbp->cb_dip, circ); 2366 return (PCICFG_FAILURE); 2367 } 2368 2369 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2370 2371 /* 2372 * As soon as we have access to config space, check device 2373 * is a bridge. 2374 */ 2375 if ((header_type & PCI_HEADER_TYPE_M) != PCI_HEADER_CARDBUS) 2376 goto failed; 2377 2378 cardbus_err(cbp->cb_dip, 8, 2379 "---Vendor ID = [0x%04x]\n", 2380 pci_config_get16(config_handle, PCI_CONF_VENID)); 2381 cardbus_err(cbp->cb_dip, 8, 2382 "---Device ID = [0x%04x]\n", 2383 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2384 2385 /* say what type of header */ 2386 cardbus_err(cbp->cb_dip, 8, 2387 "--%s bridge found root bus [0x%x] device [0x%x] func [0x%x]\n", 2388 ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) ? 2389 "PCI-PCI" : "Cardbus", 2390 bus, device, func); 2391 2392 if (ddi_getlongprop(DDI_DEV_T_ANY, cbp->cb_dip, 0, "bus-range", 2393 (caddr_t)&bus_range, &i) != DDI_PROP_SUCCESS) 2394 cardbus_err(cbp->cb_dip, 1, 2395 "No bus-range property seems to have been set up\n"); 2396 else { 2397 cardbus_err(cbp->cb_dip, 8, 2398 "allowable bus range is %u->%u\n", 2399 bus_range->lo, bus_range->hi); 2400 kmem_free((caddr_t)bus_range, i); 2401 } 2402 2403 /* 2404 * Get next bus in sequence and program device. 2405 */ 2406 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2407 req.ra_len = 1; 2408 2409 if (ndi_ra_alloc(cbp->cb_dip, &req, 2410 &next_bus, &blen, NDI_RA_TYPE_PCI_BUSNUM, 2411 NDI_RA_PASS) != NDI_SUCCESS) { 2412 cardbus_err(cbp->cb_dip, 1, "Failed to get a bus number\n"); 2413 goto failed; 2414 } 2415 2416 new_bus = next_bus; 2417 cardbus_err(cbp->cb_dip, 8, 2418 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2419 2420 (void) cardbus_set_bus_numbers(config_handle, bus, new_bus); 2421 2422 /* Enable it all */ 2423 enable_cardbus_bridge(cbp->cb_dip, config_handle); 2424 2425 /* 2426 * Probe all children devices 2427 */ 2428 for (i = 0; i < pcicfg_max_device; i++) 2429 for (j = 0; j < pcicfg_max_function; j++) 2430 switch (cardbus_probe_children(cbp, attpt, new_bus, i, 2431 j, &header_type)) { 2432 2433 case PCICFG_FAILURE: 2434 cardbus_err(cbp->cb_dip, 1, 2435 "Failed to configure bus " 2436 "[0x%x] device [0x%x] func [0x%x]\n", 2437 new_bus, i, j); 2438 disable_cardbus_bridge(cbp->cb_dip, 2439 config_handle); 2440 goto failed; 2441 2442 case PCICFG_NODEVICE: 2443 /* 2444 * if there's no function 0 2445 * there's no point in probing other 2446 * functions 2447 */ 2448 if (j != 0) 2449 break; 2450 /* FALLTHROUGH */ 2451 case PCICFG_NOMULTI: 2452 j = pcicfg_max_function; 2453 break; 2454 2455 default: 2456 break; 2457 } 2458 2459 (void) pci_config_teardown(&config_handle); 2460 (void) i_ndi_config_node(attpt, DS_LINKED, 0); 2461 ndi_devi_exit(cbp->cb_dip, circ); 2462 2463 return (PCICFG_SUCCESS); 2464 2465failed: 2466 (void) pci_config_teardown(&config_handle); 2467 ndi_devi_exit(cbp->cb_dip, circ); 2468 2469 return (PCICFG_FAILURE); 2470} 2471 2472static struct isa_node isa_nodes[] = { 2473 {"dummy", {NULL, NULL, NULL, NULL, NULL}, "serial", "", 0x4e, 0x2} 2474}; 2475 2476static int 2477cardbus_probe_children(cbus_t *cbp, dev_info_t *parent, uint_t bus, 2478 uint_t device, uint_t func, uint8_t *header_type) 2479{ 2480 dev_info_t *new_child; 2481 ddi_acc_handle_t config_handle; 2482 int i, j; 2483 ndi_ra_request_t req; 2484 uint64_t next_bus; 2485 uint64_t blen; 2486 uint32_t request; 2487 uint8_t base_class; 2488 uint_t new_bus; 2489 int ret; 2490 int circ; 2491 2492 cardbus_err(parent, 6, 2493 "cardbus_probe_children bus %d device %d func %d\n", 2494 bus, device, func); 2495 2496 /* 2497 * This node will be put immediately below 2498 * "parent". Allocate a blank device node. It will either 2499 * be filled in or freed up based on further probing. 2500 */ 2501 2502 ndi_devi_enter(parent, &circ); 2503 2504 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 2505 (pnode_t)DEVI_SID_NODEID, 2506 &new_child) != NDI_SUCCESS) { 2507 cardbus_err(parent, 1, 2508 "cardbus_probe_children(): Failed to alloc child node\n"); 2509 ndi_devi_exit(parent, circ); 2510 return (PCICFG_FAILURE); 2511 } 2512 2513 if (cardbus_add_config_reg(new_child, bus, 2514 device, func) != DDI_SUCCESS) { 2515 cardbus_err(parent, 1, 2516 "cardbus_probe_children(): Failed to add candidate REG\n"); 2517 goto failedconfig; 2518 } 2519 2520 if ((ret = cardbus_config_setup(new_child, &config_handle)) 2521 != PCICFG_SUCCESS) { 2522 2523 if (ret == PCICFG_NODEVICE) { 2524 (void) ndi_devi_free(new_child); 2525 return (ret); 2526 } 2527 cardbus_err(parent, 1, 2528 "cardbus_probe_children(): Failed to setup config space\n"); 2529 2530 goto failedconfig; 2531 } 2532 2533 base_class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 2534 2535 if (func == 0) { 2536 /* 2537 * Preserve the header type from function 0. 2538 * Additional functions may not preserve the PCI_HEADER_MULTI 2539 * bit. 2540 */ 2541 *header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2542 } else if (!(*header_type & PCI_HEADER_MULTI) || 2543 ((*header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) || 2544 (base_class == PCI_CLASS_BRIDGE)) { 2545 2546 (void) cardbus_config_teardown(&config_handle); 2547 (void) ndi_devi_free(new_child); 2548 return (PCICFG_NOMULTI); 2549 } 2550 2551 /* 2552 * As soon as we have access to config space, 2553 * turn off device. It will get turned on 2554 * later (after memory is assigned). 2555 * not if it's a cardbus device. It may be OK to leave 2556 * it on - try LATER 2557 */ 2558 disable_cardbus_device(config_handle); 2559 2560 /* 2561 * Set 1275 properties common to all devices 2562 */ 2563 if (cardbus_set_standard_props(parent, new_child, 2564 config_handle) != PCICFG_SUCCESS) { 2565 cardbus_err(parent, 1, "Failed to set standard properties\n"); 2566 goto failedchild; 2567 } 2568 2569 /* 2570 * Child node properties NOTE: Both for PCI-PCI bridge and child node 2571 */ 2572 if (cardbus_set_childnode_props(new_child, 2573 config_handle) != PCICFG_SUCCESS) { 2574 goto failedchild; 2575 } 2576 2577 cardbus_err(parent, 8, 2578 "---Vendor ID = [0x%04x]\n", 2579 pci_config_get16(config_handle, PCI_CONF_VENID)); 2580 cardbus_err(parent, 8, 2581 "---Device ID = [0x%04x]\n", 2582 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2583 2584 if (base_class == PCI_CLASS_BRIDGE) { 2585 uint8_t sub_class; 2586 2587 sub_class = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 2588 2589 switch (sub_class) { 2590 case PCI_BRIDGE_PCI: 2591 if ((*header_type & PCI_HEADER_TYPE_M) 2592 == PCI_HEADER_PPB) { 2593 cardbus_bus_range_t *bus_range; 2594 int k; 2595 2596 /* say what type of header */ 2597 cardbus_err(parent, 8, 2598 "-- Found PCI-PCI bridge @ " 2599 " bus [0x%x] device [0x%x] func [0x%x]\n", 2600 bus, device, func); 2601 2602 if (ddi_getlongprop(DDI_DEV_T_ANY, 2603 new_child, 0, "bus-range", 2604 (caddr_t)&bus_range, 2605 &k) != DDI_PROP_SUCCESS) 2606 cardbus_err(new_child, 1, 2607 "No bus-range property" 2608 " seems to have been set up\n"); 2609 else { 2610 cardbus_err(new_child, 8, 2611 "allowable bus range is %u->%u\n", 2612 bus_range->lo, bus_range->hi); 2613 kmem_free((caddr_t)bus_range, k); 2614 } 2615 2616 /* 2617 * Get next bus in sequence and program device. 2618 */ 2619 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2620 req.ra_len = 1; 2621 2622 if (ndi_ra_alloc(new_child, &req, 2623 &next_bus, &blen, 2624 NDI_RA_TYPE_PCI_BUSNUM, 2625 NDI_RA_PASS) != NDI_SUCCESS) { 2626 cardbus_err(new_child, 1, 2627 "Failed to get a bus number\n"); 2628 goto failedchild; 2629 } 2630 2631 new_bus = next_bus; 2632 2633 cardbus_err(new_child, 8, 2634 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2635 2636 /* Enable it all */ 2637 enable_pci_pci_bridge(new_child, config_handle); 2638 (void) cardbus_set_bus_numbers(config_handle, 2639 bus, new_bus); 2640 2641#if defined(CARDBUS_DEBUG) 2642 if (cardbus_debug >= 9) { 2643 cardbus_dump_config(config_handle); 2644 } 2645#endif 2646 2647 /* 2648 * Set bus properties 2649 */ 2650 if (cardbus_set_busnode_props(new_child) 2651 != PCICFG_SUCCESS) { 2652 cardbus_err(new_child, 1, 2653 "Failed to set busnode props\n"); 2654 disable_pci_pci_bridge(new_child, 2655 config_handle); 2656 goto failedchild; 2657 } 2658 2659 /* 2660 * Probe all children devices 2661 */ 2662 for (i = 0; i < pcicfg_max_device; i++) 2663 for (j = 0; j < pcicfg_max_function; 2664 j++) 2665 switch (cardbus_probe_children( 2666 cbp, 2667 new_child, 2668 new_bus, i, 2669 j, header_type)) { 2670 case PCICFG_FAILURE: 2671 cardbus_err(parent, 1, 2672 "Failed to " 2673 "configure " 2674 "bus [0x%x] " 2675 "device [0x%x] " 2676 "func [0x%x]\n", 2677 new_bus, i, j); 2678 disable_pci_pci_bridge( 2679 new_child, 2680 config_handle); 2681 goto failedchild; 2682 2683 case PCICFG_NODEVICE: 2684 /* 2685 * if there's no 2686 * function 0 2687 * there's no point in 2688 * probing other 2689 * functions 2690 */ 2691 if (j != 0) 2692 break; 2693 /* FALLTHROUGH */ 2694 case PCICFG_NOMULTI: 2695 j = pcicfg_max_function; 2696 break; 2697 2698 default: 2699 break; 2700 } 2701 } 2702 break; 2703 2704 case PCI_BRIDGE_CARDBUS: 2705 cardbus_err(parent, 8, 2706 "--Found Cardbus bridge @ " 2707 "bus [0x%x] device [0x%x] func [0x%x]\n", 2708 bus, device, func); 2709 pci_config_put32(config_handle, 2710 PCI_CONF_BASE0, 0xffffffff); 2711 2712 request = pci_config_get32(config_handle, 2713 PCI_CONF_BASE0); 2714 2715 /* 2716 * If its a zero length, don't do 2717 * any programming. 2718 */ 2719 if (request != 0) { 2720 if (request == (uint32_t)0xffffffff) { 2721 cmn_err(CE_WARN, 2722 "cardbus_probe_children: " 2723 "can't access device"); 2724 goto failedchild; 2725 } 2726 /* 2727 * Add to the "reg" property 2728 */ 2729 if (cardbus_update_reg_prop(new_child, 2730 request, 2731 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2732 goto failedchild; 2733 } 2734 cardbus_err(parent, 8, 2735 "BASE register [0x%x] asks for " 2736 "[0x%x]=[0x%x](32)\n", 2737 PCI_CONF_BASE0, request, 2738 (~(PCI_BASE_M_ADDR_M & request))+1); 2739 } 2740 break; 2741 2742 case PCI_BRIDGE_ISA: 2743 cardbus_err(parent, 8, 2744 "--Found ISA bridge @ " 2745 "bus [0x%x] device [0x%x] func [0x%x]\n", 2746 bus, device, func); 2747 enable_pci_isa_bridge(new_child, config_handle); 2748 2749#if defined(CARDBUS_DEBUG) 2750 if (cardbus_debug >= 4) { 2751 cardbus_dump_common_config(config_handle); 2752 cardbus_err(NULL, 1, 2753 " DDMA SlvCh0 = [0x%04x] " 2754 "DDMA SlvCh1 = [0x%04x]\n", 2755 pci_config_get16(config_handle, 0x40), 2756 pci_config_get16(config_handle, 0x42)); 2757 cardbus_err(NULL, 1, 2758 " DDMA SlvCh2 = [0x%04x] " 2759 "DDMA SlvCh3 = [0x%04x]\n", 2760 pci_config_get16(config_handle, 0x44), 2761 pci_config_get16(config_handle, 0x46)); 2762 cardbus_err(NULL, 1, 2763 " DDMA SlvCh5 = [0x%04x] " 2764 "DDMA SlvCh6 = [0x%04x]\n", 2765 pci_config_get16(config_handle, 0x4a), 2766 pci_config_get16(config_handle, 0x4c)); 2767 cardbus_err(NULL, 1, 2768 " DDMA SlvCh7 = [0x%04x] " 2769 "Misc Cntrl = [0x%02x]\n", 2770 pci_config_get16(config_handle, 0x4e), 2771 pci_config_get8(config_handle, 0x57)); 2772 cardbus_err(NULL, 1, 2773 " DMA Cntl = [0x%02x] " 2774 "DMA TyF Tim = [0x%02x]\n", 2775 pci_config_get8(config_handle, 0x48), 2776 pci_config_get8(config_handle, 0x49)); 2777 cardbus_err(NULL, 1, 2778 " TimCntrl = [0x%02x] " 2779 "MTOP = [0x%02x]\n", 2780 pci_config_get8(config_handle, 0x50), 2781 pci_config_get8(config_handle, 0x51)); 2782 cardbus_err(NULL, 1, 2783 " MDMA Access = [0x%02x] " 2784 "ROMCS = [0x%02x]\n", 2785 pci_config_get8(config_handle, 0x52), 2786 pci_config_get8(config_handle, 0x53)); 2787 cardbus_err(NULL, 1, 2788 " Dscrd Tmr = [0x%02x] " 2789 "Retry Tmr = [0x%02x]\n", 2790 pci_config_get8(config_handle, 0x55), 2791 pci_config_get8(config_handle, 0x54)); 2792 cardbus_err(NULL, 1, 2793 " I/O Spc 0 = [0x%08x] " 2794 "I/O Spc 1 = [0x%08x]\n", 2795 pci_config_get32(config_handle, 0x58), 2796 pci_config_get32(config_handle, 0x5c)); 2797 cardbus_err(NULL, 1, 2798 " I/O Spc 2 = [0x%08x] " 2799 "I/O Spc 3 = [0x%08x]\n", 2800 pci_config_get32(config_handle, 0x60), 2801 pci_config_get32(config_handle, 0x64)); 2802 cardbus_err(NULL, 1, 2803 " I/O Spc 4 = [0x%08x] " 2804 "I/O Spc 5 = [0x%08x]\n", 2805 pci_config_get32(config_handle, 0x68), 2806 pci_config_get32(config_handle, 0x6c)); 2807 cardbus_err(NULL, 1, 2808 " Mem Spc 0 = [0x%08x] " 2809 "Mem Spc 1 = [0x%08x]\n", 2810 pci_config_get32(config_handle, 0x70), 2811 pci_config_get32(config_handle, 0x74)); 2812 cardbus_err(NULL, 1, 2813 " Mem Spc 2 = [0x%08x] " 2814 "Mem Spc 3 = [0x%08x]\n", 2815 pci_config_get32(config_handle, 0x78), 2816 pci_config_get32(config_handle, 0x7c)); 2817 } 2818#endif 2819 /* 2820 * Set bus properties 2821 */ 2822 if (cardbus_set_busnode_isaprops(new_child) 2823 != PCICFG_SUCCESS) { 2824 cardbus_err(new_child, 1, 2825 "Failed to set busnode props\n"); 2826 disable_cardbus_device(config_handle); 2827 goto failedchild; 2828 } 2829 2830 /* 2831 * Add to the "reg" property. 2832 * Simply grab 1K of I/O space. 2833 */ 2834 if (cardbus_update_reg_prop(new_child, 2835 0xfffffc00 | PCI_BASE_SPACE_IO, 2836 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2837 goto failedchild; 2838 } 2839 2840 /* 2841 * Probe all potential children devices. 2842 */ 2843 for (i = 0; 2844 i < sizeof (isa_nodes) / sizeof (isa_nodes[0]); 2845 i++) 2846 switch (cardbus_add_isa_node(cbp, new_child, 2847 &isa_nodes[i])) { 2848 case PCICFG_FAILURE: 2849 cardbus_err(parent, 1, 2850 "Failed to configure isa bus\n"); 2851 disable_cardbus_device(config_handle); 2852 goto failedchild; 2853 2854 case PCICFG_NODEVICE: 2855 continue; 2856 } 2857 2858 break; 2859 2860 case PCI_BRIDGE_OTHER: 2861 default: 2862 cardbus_err(parent, 8, 2863 "--Found unknown bridge, subclass 0x%x @ " 2864 "bus [0x%x] device [0x%x] func [0x%x]\n", 2865 sub_class, bus, device, func); 2866 goto leaf_node; 2867 } 2868 } else { 2869 cardbus_err(parent, 8, 2870 "--Leaf device found " 2871 "bus [0x%x] device [0x%x] func [0x%x]\n", 2872 bus, device, func); 2873 /* 2874 * Ethernet devices. 2875 */ 2876 if (strcmp(ddi_binding_name(new_child), "ethernet") == 0) { 2877 extern int localetheraddr(struct ether_addr *, 2878 struct ether_addr *); 2879 uchar_t mac[6]; 2880 2881 cardbus_force_stringprop(new_child, 2882 "device_type", "network"); 2883 2884 if (localetheraddr(NULL, (struct ether_addr *)mac)) { 2885 (void) ddi_prop_create(DDI_DEV_T_NONE, 2886 new_child, 2887 DDI_PROP_CANSLEEP, "local-mac-address", 2888 (caddr_t)mac, 6); 2889 } 2890 } 2891leaf_node: 2892 if (cbp->cb_dsp) { 2893 struct cb_deviceset_props *cdsp = cbp->cb_dsp; 2894 uint16_t venid = pci_config_get16(config_handle, 2895 PCI_CONF_VENID); 2896 uint16_t devid = pci_config_get16(config_handle, 2897 PCI_CONF_DEVID); 2898 ddi_prop_t *propp; 2899 2900 for (cdsp = cbp->cb_dsp; cdsp; cdsp = cdsp->next) { 2901 if (cdsp->binding_name && 2902 strcmp(ddi_binding_name(new_child), 2903 cdsp->binding_name)) 2904 continue; 2905 if (cdsp->venid && (cdsp->venid != venid)) 2906 continue; 2907 if (cdsp->devid && (cdsp->devid != devid)) 2908 continue; 2909 if (cdsp->nodename) { 2910 if (ndi_devi_set_nodename(new_child, 2911 cdsp->nodename, 2912 0) != NDI_SUCCESS) 2913 cardbus_err(new_child, 1, 2914 "Failed to set nodename\n"); 2915 } 2916 for (propp = cdsp->prop_list; propp; 2917 propp = propp->prop_next) { 2918 switch (propp->prop_flags) { 2919 case DDI_PROP_TYPE_INT: 2920 cardbus_force_intprop( 2921 new_child, 2922 propp->prop_name, 2923 (int *)propp->prop_val, 2924 propp->prop_len); 2925 break; 2926 case DDI_PROP_TYPE_STRING: 2927 cardbus_force_stringprop( 2928 new_child, 2929 propp->prop_name, 2930 (char *)propp->prop_val); 2931 break; 2932 case DDI_PROP_TYPE_ANY: 2933 cardbus_force_boolprop( 2934 new_child, 2935 propp->prop_name); 2936 break; 2937 } 2938 } 2939 } 2940 } 2941 2942#if defined(CARDBUS_DEBUG) 2943 if (cardbus_debug >= 9) { 2944 cardbus_dump_config(config_handle); 2945 } 2946#endif 2947 2948 i = PCI_CONF_BASE0; 2949 2950 while (i <= PCI_CONF_BASE5) { 2951 pci_config_put32(config_handle, i, 0xffffffff); 2952 2953 request = pci_config_get32(config_handle, i); 2954 2955 /* 2956 * If its a zero length, don't do 2957 * any programming. 2958 */ 2959 if (request != 0) { 2960 if (request == (uint32_t)0xffffffff) { 2961 cmn_err(CE_WARN, 2962 "cardbus_probe_children: " 2963 "can't access device"); 2964 goto failedchild; 2965 } 2966 /* 2967 * Add to the "reg" property 2968 */ 2969 if (cardbus_update_reg_prop(new_child, 2970 request, i) != PCICFG_SUCCESS) { 2971 goto failedchild; 2972 } 2973 } else { 2974 cardbus_err(parent, 8, "All memory found\n"); 2975 break; 2976 } 2977 2978 /* 2979 * Increment by eight if it is 64 bit address space 2980 * only if memory space 2981 */ 2982 if (((PCI_BASE_TYPE_M & request) 2983 == PCI_BASE_TYPE_ALL) && 2984 ((PCI_BASE_SPACE_M & request) 2985 == PCI_BASE_SPACE_MEM)) { 2986 cardbus_err(parent, 8, 2987 "BASE register [0x%x] asks for " 2988 "[0x%x]=[0x%x] (64)\n", 2989 i, request, 2990 (~(PCI_BASE_M_ADDR_M & request))+1); 2991 i += 8; 2992 } else { 2993 cardbus_err(parent, 8, 2994 "BASE register [0x%x] asks for " 2995 "[0x%x]=[0x%x](32)\n", 2996 i, request, 2997 (~(PCI_BASE_M_ADDR_M & request))+1); 2998 i += 4; 2999 } 3000 } 3001 3002 /* 3003 * Get the ROM size and create register for it 3004 */ 3005 pci_config_put32(config_handle, PCI_CONF_ROM, 0xffffffff); 3006 3007 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3008 /* 3009 * If its a zero length, don't do 3010 * any programming. 3011 */ 3012 3013 if (request != 0) { 3014 cardbus_err(parent, 9, 3015 "BASE register [0x%x] asks for " 3016 "[0x%x]=[0x%x] (ROM)\n", 3017 PCI_CONF_ROM, request, 3018 (~(PCI_BASE_ROM_ADDR_M & request))+1); 3019 /* 3020 * Add to the "reg" property 3021 */ 3022 if (cardbus_update_reg_prop(new_child, 3023 request, 3024 PCI_CONF_ROM) != PCICFG_SUCCESS) { 3025 goto failedchild; 3026 } 3027 } 3028 } 3029 3030 (void) cardbus_config_teardown(&config_handle); 3031 3032 /* 3033 * Attach the child to its parent 3034 */ 3035 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3036 ndi_devi_exit(parent, circ); 3037 3038 return (PCICFG_SUCCESS); 3039failedchild: 3040 /* 3041 * check if it should be taken offline (if online) 3042 */ 3043 (void) cardbus_config_teardown(&config_handle); 3044 3045failedconfig: 3046 3047 (void) ndi_devi_free(new_child); 3048 ndi_devi_exit(parent, circ); 3049 3050 return (PCICFG_FAILURE); 3051} 3052 3053static int 3054cardbus_add_config_reg(dev_info_t *dip, 3055 uint_t bus, uint_t device, uint_t func) 3056{ 3057 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 3058 3059 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 3060 3061 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3062 "reg", reg, 5)); 3063} 3064 3065static int 3066cardbus_add_isa_node(cbus_t *cbp, dev_info_t *parent, struct isa_node *node) 3067{ 3068 dev_info_t *new_child; 3069 int ret; 3070 uint32_t reg[3]; 3071 3072 _NOTE(ARGUNUSED(cbp)) 3073 3074 cardbus_err(parent, 6, "cardbus_add_isa_node\n"); 3075 3076 /* 3077 * This node will be put immediately below 3078 * "parent". Allocate a blank device node. 3079 */ 3080 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 3081 (pnode_t)DEVI_SID_NODEID, 3082 &new_child) != NDI_SUCCESS) { 3083 cardbus_err(parent, 1, 3084 "cardbus_add_isa_child(): Failed to alloc child node\n"); 3085 return (PCICFG_FAILURE); 3086 } 3087 3088 /* 3089 * Set properties common to ISA devices 3090 */ 3091 if (cardbus_set_isa_props(parent, new_child, node->name, 3092 node->compatible) != PCICFG_SUCCESS) { 3093 cardbus_err(parent, 1, "Failed to set ISA properties\n"); 3094 goto failed; 3095 } 3096 3097 cardbus_err(new_child, 8, "--Leaf ISA device\n"); 3098 3099 /* 3100 * Add the "reg" property. 3101 */ 3102 reg[0] = 0; 3103 reg[1] = node->reg; 3104 reg[2] = node->span; 3105 3106 ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 3107 "basereg", (int *)reg, 3); 3108 if (ret != DDI_SUCCESS) 3109 goto failed; 3110 3111 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3112 3113 return (PCICFG_SUCCESS); 3114 3115failed: 3116 (void) ndi_devi_free(new_child); 3117 3118 return (PCICFG_FAILURE); 3119} 3120 3121static int 3122cardbus_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 3123{ 3124 caddr_t cfgaddr; 3125 ddi_device_acc_attr_t attr; 3126 dev_info_t *anode; 3127 int status; 3128 int rlen; 3129 pci_regspec_t *reg; 3130 int ret; 3131#ifdef sparc 3132 int16_t val; 3133#endif 3134 3135 cardbus_err(dip, 10, 3136 "cardbus_config_setup(dip=0x%p)\n", (void *) dip); 3137 3138 /* 3139 * Get the pci register spec from the node 3140 */ 3141 status = ddi_getlongprop(DDI_DEV_T_NONE, 3142 dip, DDI_PROP_DONTPASS, "reg", 3143 (caddr_t)®, &rlen); 3144 3145 cardbus_err(dip, 10, 3146 "cardbus_config_setup, reg = 0x%p\n", (void *) reg); 3147 3148 switch (status) { 3149 case DDI_PROP_SUCCESS: 3150 break; 3151 case DDI_PROP_NO_MEMORY: 3152 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3153 return (PCICFG_FAILURE); 3154 default: 3155 cardbus_err(dip, 1, "no reg property\n"); 3156 return (PCICFG_FAILURE); 3157 } 3158 3159 anode = dip; 3160 3161 /* 3162 * Find the attachment point node 3163 */ 3164 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 3165 "hp_attachment") != 0)) { 3166 anode = ddi_get_parent(anode); 3167 } 3168 3169 if (anode == NULL) { 3170 cardbus_err(dip, 1, "Tree not in PROBE state\n"); 3171 kmem_free((caddr_t)reg, rlen); 3172 return (PCICFG_FAILURE); 3173 } 3174 3175 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, anode, 3176 "reg", (int *)reg, 5)) != 0) { 3177 cardbus_err(dip, 1, 3178 "Failed to update reg property, error code %d\n", ret); 3179 kmem_free((caddr_t)reg, rlen); 3180 return (PCICFG_FAILURE); 3181 } 3182 3183 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3184 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 3185 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3186 3187 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 3188 0, /* PCI_CONF_HDR_SIZE */ 3189 0, 3190 &attr, handle) != DDI_SUCCESS) { 3191 cardbus_err(dip, 1, 3192 "Failed to setup registers for [0x%x][0x%x][0x%x]\n", 3193 PCI_REG_BUS_G(reg->pci_phys_hi), 3194 PCI_REG_DEV_G(reg->pci_phys_hi), 3195 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3196 kmem_free((caddr_t)reg, rlen); 3197 return (PCICFG_FAILURE); 3198 } 3199 3200 cardbus_err(dip, 9, 3201 "PROBING =>->->->->->-> [0x%x][0x%x][0x%x] 0x%x 0x%p\n", 3202 PCI_REG_BUS_G(reg->pci_phys_hi), 3203 PCI_REG_DEV_G(reg->pci_phys_hi), 3204 PCI_REG_FUNC_G(reg->pci_phys_hi), 3205 reg->pci_phys_hi, (void *) cfgaddr); 3206 3207 /* 3208 * must do peek16 otherwise the system crashes when probing 3209 * a non zero function on a non-multi-function card. 3210 */ 3211#ifdef sparc 3212 if (ddi_peek16(anode, (int16_t *)cfgaddr, &val) != DDI_SUCCESS) { 3213 cardbus_err(dip, 8, 3214 "cardbus_config_setup peek failed\n"); 3215 ret = PCICFG_NODEVICE; 3216 } else if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3217 cardbus_err(dip, 8, 3218 "cardbus_config_setup PCICFG_NODEVICE\n"); 3219 ret = PCICFG_NODEVICE; 3220#elif defined(__x86) || defined(__amd64) 3221 if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3222 cardbus_err(dip, 8, 3223 "cardbus_config_setup PCICFG_NODEVICE\n"); 3224 ret = PCICFG_NODEVICE; 3225#endif 3226 } else { 3227 cardbus_err(dip, 1, 3228 "cardbus_config_setup found device at:[0x%x][0x%x][0x%x]\n", 3229 PCI_REG_BUS_G(reg->pci_phys_hi), 3230 PCI_REG_DEV_G(reg->pci_phys_hi), 3231 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3232 3233 ret = PCICFG_SUCCESS; 3234 } 3235 3236 kmem_free((caddr_t)reg, rlen); 3237 if (ret != PCICFG_SUCCESS) { 3238 cardbus_config_teardown(handle); 3239 } 3240 3241 cardbus_err(dip, 7, 3242 "cardbus_config_setup returning %d\n", ret); 3243 3244 return (ret); 3245} 3246 3247static void 3248cardbus_config_teardown(ddi_acc_handle_t *handle) 3249{ 3250 (void) ddi_regs_map_free(handle); 3251} 3252 3253static void 3254cardbus_reparent_children(dev_info_t *dip, dev_info_t *parent) 3255{ 3256 dev_info_t *child; 3257 int circ; 3258 3259 while (child = ddi_get_child(dip)) { 3260 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 3261 /* 3262 * Unlink node from tree before reparenting 3263 */ 3264 ndi_devi_enter(dip, &circ); 3265 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 3266 ndi_devi_exit(dip, circ); 3267 DEVI(child)->devi_parent = DEVI(parent); 3268 DEVI(child)->devi_bus_ctl = DEVI(parent); 3269 ndi_devi_enter(parent, &circ); 3270 (void) i_ndi_config_node(child, DS_LINKED, 0); 3271 ndi_devi_exit(parent, circ); 3272 } 3273} 3274 3275static int 3276cardbus_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 3277{ 3278 int alen; 3279 pci_regspec_t *assigned; 3280 caddr_t newreg; 3281 uint_t status; 3282 3283 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3284 "assigned-addresses", (caddr_t)&assigned, &alen); 3285 switch (status) { 3286 case DDI_PROP_SUCCESS: 3287 cardbus_err(dip, 5, 3288 "cardbus_update_assigned_prop: found prop len %d\n", 3289 alen); 3290 /* 3291 * Allocate memory for the existing 3292 * assigned-addresses(s) plus one and then 3293 * build it. 3294 */ 3295 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 3296 3297 bcopy(assigned, newreg, alen); 3298 bcopy(newone, newreg + alen, sizeof (*newone)); 3299 break; 3300 3301 case DDI_PROP_NO_MEMORY: 3302 cardbus_err(dip, 1, 3303 "no memory for assigned-addresses property\n"); 3304 return (PCICFG_FAILURE); 3305 3306 default: 3307 cardbus_err(dip, 5, 3308 "cardbus_update_assigned_prop: creating prop\n"); 3309 alen = 0; 3310 newreg = (caddr_t)newone; 3311 break; 3312 } 3313 3314 /* 3315 * Write out the new "assigned-addresses" spec 3316 */ 3317 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3318 "assigned-addresses", (int *)newreg, 3319 (alen + sizeof (*newone))/sizeof (int)); 3320 3321 if (status == DDI_PROP_SUCCESS) 3322 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 3323 3324 if (alen) 3325 kmem_free(assigned, alen); 3326 3327 return (PCICFG_SUCCESS); 3328} 3329 3330static int 3331cardbus_update_available_prop(dev_info_t *dip, uint32_t hi_type, 3332 uint64_t base, uint64_t size) 3333{ 3334 int alen, rlen; 3335 pci_regspec_t *available, *reg; 3336 pci_regspec_t addition; 3337 caddr_t newreg; 3338 uint_t status; 3339 3340 cardbus_err(dip, 6, "cardbus_update_available_prop\n"); 3341 3342 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3343 "reg", (caddr_t)®, &rlen); 3344 3345 switch (status) { 3346 case DDI_PROP_SUCCESS: 3347 break; 3348 case DDI_PROP_NO_MEMORY: 3349 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3350 return (PCICFG_FAILURE); 3351 default: 3352 cardbus_err(dip, 1, "no reg property\n"); 3353 return (PCICFG_FAILURE); 3354 } 3355 3356 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3357 "available", (caddr_t)&available, &alen); 3358 switch (status) { 3359 case DDI_PROP_SUCCESS: 3360 break; 3361 case DDI_PROP_NO_MEMORY: 3362 cardbus_err(dip, 1, "no memory for available property\n"); 3363 kmem_free((caddr_t)reg, rlen); 3364 return (PCICFG_FAILURE); 3365 default: 3366 alen = 0; 3367 } 3368 3369 /* 3370 * Allocate memory for the existing 3371 * available(s) plus one and then 3372 * build it. 3373 */ 3374 newreg = kmem_zalloc(alen + sizeof (pci_regspec_t), KM_SLEEP); 3375 3376 /* 3377 * Build the regspec, then add it to the existing one(s) 3378 */ 3379 addition.pci_phys_hi = hi_type | 3380 PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3381 PCI_REG_DEV_G(reg->pci_phys_hi), 3382 PCI_REG_FUNC_G(reg->pci_phys_hi), 0); 3383 3384 addition.pci_phys_mid = (uint32_t)((base>>32) & 0xffffffff); 3385 addition.pci_phys_low = (uint32_t)(base & 0xffffffff); 3386 addition.pci_size_hi = (uint32_t)((size>>32) & 0xffffffff); 3387 addition.pci_size_low = (uint32_t)(size & 0xffffffff); 3388 3389#ifdef DEBUG 3390 cardbus_dump_reg(dip, &addition, 1); 3391#endif 3392 3393 if (alen) 3394 bcopy(available, newreg, alen); 3395 bcopy(&addition, newreg + alen, sizeof (pci_regspec_t)); 3396 3397 /* 3398 * Write out the new "available" spec 3399 */ 3400 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3401 "available", (int *)newreg, 3402 (alen + sizeof (pci_regspec_t))/sizeof (int)); 3403 3404 if (alen) 3405 kmem_free((caddr_t)available, alen); 3406 kmem_free((caddr_t)reg, rlen); 3407 kmem_free((caddr_t)newreg, alen + sizeof (pci_regspec_t)); 3408 3409 return (PCICFG_SUCCESS); 3410} 3411 3412static int 3413cardbus_update_ranges_prop(dev_info_t *dip, cardbus_range_t *addition) 3414{ 3415 int rlen; 3416 cardbus_range_t *ranges; 3417 caddr_t newreg; 3418 uint_t status; 3419#if defined(CARDBUS_DEBUG) 3420 int i, nrange; 3421 const cardbus_range_t *nr; 3422#endif 3423 3424 cardbus_err(dip, 6, "cardbus_update_ranges_prop\n"); 3425 3426 status = ddi_getlongprop(DDI_DEV_T_NONE, 3427 dip, DDI_PROP_DONTPASS, "ranges", 3428 (caddr_t)&ranges, &rlen); 3429 3430 switch (status) { 3431 case DDI_PROP_SUCCESS: 3432 break; 3433 case DDI_PROP_NO_MEMORY: 3434 cardbus_err(dip, 1, 3435 "ranges present, but unable to get memory\n"); 3436 return (PCICFG_FAILURE); 3437 default: 3438 cardbus_err(dip, 8, "no ranges property - creating one\n"); 3439 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 3440 dip, "ranges", (int *)addition, 3441 sizeof (cardbus_range_t)/sizeof (int)) 3442 != DDI_SUCCESS) { 3443 cardbus_err(dip, 1, "Did'nt create ranges property\n"); 3444 return (PCICFG_FAILURE); 3445 } 3446 return (PCICFG_SUCCESS); 3447 } 3448 3449 /* 3450 * Allocate memory for the existing reg(s) plus one and then 3451 * build it. 3452 */ 3453 newreg = kmem_zalloc(rlen+sizeof (cardbus_range_t), KM_SLEEP); 3454 3455 bcopy(ranges, newreg, rlen); 3456 bcopy(addition, newreg + rlen, sizeof (cardbus_range_t)); 3457 3458 /* 3459 * Write out the new "ranges" property 3460 */ 3461 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3462 dip, "ranges", (int *)newreg, 3463 (rlen + sizeof (cardbus_range_t))/sizeof (int)); 3464 3465#if defined(CARDBUS_DEBUG) 3466 cardbus_err(dip, 8, "cardbus_update_ranges_prop ranges property:\n"); 3467 3468 nrange = rlen / sizeof (cardbus_range_t); 3469 nr = (cardbus_range_t *)newreg; 3470 for (i = 0; i <= nrange; i++) { 3471 /* nrange is one higher for new entry */ 3472 cardbus_err(dip, 9, 3473 "\trange parent addr 0x%x.0x%x.0x%x " 3474 "child addr 0x%x.0x%x.0x%x size 0x%x.0x%x\n", 3475 nr->parent_hi, 3476 nr->parent_mid, nr->parent_lo, 3477 nr->child_hi, 3478 nr->child_mid, nr->child_lo, 3479 nr->size_hi, nr->size_lo); 3480 nr++; 3481 } 3482#endif 3483 3484 kmem_free((caddr_t)newreg, rlen+sizeof (cardbus_range_t)); 3485 kmem_free((caddr_t)ranges, rlen); 3486 3487 return (PCICFG_SUCCESS); 3488} 3489 3490static int 3491cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 3492{ 3493 int rlen; 3494 pci_regspec_t *reg; 3495 caddr_t newreg; 3496 uint32_t hiword; 3497 pci_regspec_t addition; 3498 uint32_t size; 3499 uint_t status; 3500 3501 status = ddi_getlongprop(DDI_DEV_T_NONE, 3502 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3503 3504 switch (status) { 3505 case DDI_PROP_SUCCESS: 3506 break; 3507 case DDI_PROP_NO_MEMORY: 3508 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3509 return (PCICFG_FAILURE); 3510 default: 3511 cardbus_err(dip, 1, "no reg property\n"); 3512 return (PCICFG_FAILURE); 3513 } 3514 3515 /* 3516 * Allocate memory for the existing reg(s) plus one and then 3517 * build it. 3518 */ 3519 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 3520 3521 /* 3522 * Build the regspec, then add it to the existing one(s) 3523 */ 3524 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3525 PCI_REG_DEV_G(reg->pci_phys_hi), 3526 PCI_REG_FUNC_G(reg->pci_phys_hi), 3527 reg_offset); 3528 3529 if (reg_offset == PCI_CONF_ROM) { 3530 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 3531 hiword |= PCI_ADDR_MEM32; 3532 } else { 3533 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 3534 3535 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 3536 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 3537 hiword |= PCI_ADDR_MEM32; 3538 } else if ((PCI_BASE_TYPE_M & regvalue) 3539 == PCI_BASE_TYPE_ALL) { 3540 /* 3541 * This is a 64 bit PCI memory space. 3542 * It needs to be allocated as 32 bit 3543 * for bus map purposes. 3544 */ 3545 hiword |= PCI_ADDR_MEM32; 3546 } 3547 } else { 3548 hiword |= PCI_ADDR_IO; 3549 } 3550 } 3551 3552 addition.pci_phys_hi = hiword; 3553 addition.pci_phys_mid = 0; 3554 addition.pci_phys_low = 0; 3555 addition.pci_size_hi = 0; 3556 addition.pci_size_low = size; 3557 3558 cardbus_err(dip, 8, 3559 "cardbus_update_reg_prop, phys_hi 0x%08x," 3560 " phys_mid 0x%08x, phys_low 0x%08x, size_hi 0x%08x," 3561 " size_low 0x%08x\n", hiword, 0, 0, 0, size); 3562 3563 bcopy(reg, newreg, rlen); 3564 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 3565 3566 /* 3567 * Write out the new "reg" property 3568 */ 3569 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3570 dip, "reg", (int *)newreg, 3571 (rlen + sizeof (pci_regspec_t))/sizeof (int)); 3572 3573 kmem_free((caddr_t)reg, rlen); 3574 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 3575 3576 return (PCICFG_SUCCESS); 3577} 3578 3579/* 3580 * Setup the basic 1275 properties based on information found in the config 3581 * header of the PCI device 3582 */ 3583static int 3584cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 3585 ddi_acc_handle_t config_handle) 3586{ 3587 int ret; 3588 uint16_t val; 3589 uint32_t wordval; 3590 uint8_t byteval; 3591 3592 /* These two exists only for non-bridges */ 3593 if ((pci_config_get8(config_handle, 3594 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 3595 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 3596 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3597 "min-grant", byteval)) != DDI_SUCCESS) { 3598 cardbus_err(dip, 1, "Failed to sent min-grant\n"); 3599 return (ret); 3600 } 3601 3602 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 3603 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3604 "max-latency", byteval)) != DDI_SUCCESS) { 3605 return (ret); 3606 } 3607 } 3608 3609 /* 3610 * These should always exist and have the value of the 3611 * corresponding register value 3612 */ 3613 val = pci_config_get16(config_handle, PCI_CONF_VENID); 3614 3615 /* 3616 * according to section 6.2.1 of revision 2 of the PCI local 3617 * bus specification - 0FFFFh is an invalid value for the vendor ID 3618 */ 3619 if (val == 0xffff) { 3620 cardbus_err(dip, 1, "Illegal vendor-id 0x%x\n", val); 3621 return (PCICFG_FAILURE); 3622 } 3623 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3624 "vendor-id", val)) != DDI_SUCCESS) { 3625 return (ret); 3626 } 3627 3628 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 3629 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3630 "device-id", val)) != DDI_SUCCESS) { 3631 return (ret); 3632 } 3633 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 3634 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3635 "revision-id", byteval)) != DDI_SUCCESS) { 3636 return (ret); 3637 } 3638 3639 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3640 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3641 3642 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3643 "class-code", wordval)) != DDI_SUCCESS) { 3644 return (ret); 3645 } 3646 val = (pci_config_get16(config_handle, 3647 PCI_CONF_STAT) & PCI_STAT_DEVSELT); 3648 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3649 "devsel-speed", val)) != DDI_SUCCESS) { 3650 return (ret); 3651 } 3652 3653 /* 3654 * The next three are bits set in the status register. The property is 3655 * present (but with no value other than its own existence) if the bit 3656 * is set, non-existent otherwise 3657 */ 3658 if (ddi_prop_exists(DDI_DEV_T_ANY, parent, DDI_PROP_DONTPASS, 3659 "fast-back-to-back") && 3660 pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC) { 3661 3662 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3663 "fast-back-to-back", 0)) != DDI_SUCCESS) { 3664 return (ret); 3665 } 3666 } 3667 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ) { 3668 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3669 "66mhz-capable", 0)) != DDI_SUCCESS) { 3670 return (ret); 3671 } 3672 } 3673 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 3674 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3675 "udf-supported", 0)) != DDI_SUCCESS) { 3676 return (ret); 3677 } 3678 } 3679 3680 /* 3681 * These next three are optional and are not present 3682 * if the corresponding register is zero. If the value 3683 * is non-zero then the property exists with the value 3684 * of the register. 3685 */ 3686 3687 /* look in the correct place for header type 2 */ 3688 byteval = pci_config_get8(config_handle, PCI_CONF_HEADER); 3689 if ((byteval & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3690 if ((val = pci_config_get16(config_handle, 3691 PCI_CBUS_SUBVENID)) != 0) { 3692 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3693 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3694 return (ret); 3695 } 3696 } 3697 if ((val = pci_config_get16(config_handle, 3698 PCI_CBUS_SUBSYSID)) != 0) { 3699 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3700 "subsystem-id", val)) != DDI_SUCCESS) { 3701 return (ret); 3702 } 3703 } 3704 } else { 3705 if ((val = pci_config_get16(config_handle, 3706 PCI_CONF_SUBVENID)) != 0) { 3707 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3708 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3709 return (ret); 3710 } 3711 } 3712 if ((val = pci_config_get16(config_handle, 3713 PCI_CONF_SUBSYSID)) != 0) { 3714 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3715 "subsystem-id", val)) != DDI_SUCCESS) { 3716 return (ret); 3717 } 3718 } 3719 } 3720 3721 if ((val = pci_config_get8(config_handle, 3722 PCI_CONF_CACHE_LINESZ)) != 0) { 3723 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3724 "cache-line-size", val)) != DDI_SUCCESS) { 3725 return (ret); 3726 } 3727 } 3728 3729 /* 3730 * If the Interrupt Pin register is non-zero then the 3731 * interrupts property exists 3732 */ 3733 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 3734 /* 3735 * If interrupt pin is non-zero, 3736 * record the interrupt line used 3737 */ 3738 cardbus_err(dip, 8, "Adding interrupts property\n"); 3739 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3740 "interrupts", byteval)) != DDI_SUCCESS) { 3741 return (ret); 3742 } 3743 } 3744 return (PCICFG_SUCCESS); 3745} 3746 3747/* 3748 * Setup the basic properties required by the ISA node. 3749 */ 3750static int 3751cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 3752 char *name, char *compat[]) 3753{ 3754 int ret, n; 3755 3756 _NOTE(ARGUNUSED(parent)) 3757 3758 cardbus_err(dip, 8, "Adding interrupts property\n"); 3759 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3760 "interrupts", 1)) != DDI_SUCCESS) { 3761 return (ret); 3762 } 3763 3764 /* 3765 * The node name field needs to be filled in with the name 3766 */ 3767 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3768 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3769 return (PCICFG_FAILURE); 3770 } 3771 3772 /* 3773 * Create the compatible property as an array of pointers 3774 * to strings. Start with the buffer created above. 3775 */ 3776 n = 0; 3777 while (compat[n] != NULL) 3778 n++; 3779 3780 if (n != 0) 3781 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3782 "compatible", compat, n)) != DDI_SUCCESS) 3783 return (ret); 3784 3785 return (PCICFG_SUCCESS); 3786} 3787 3788static int 3789cardbus_set_busnode_props(dev_info_t *dip) 3790{ 3791 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3792 3793 cardbus_force_stringprop(dip, "device_type", "pci"); 3794 3795 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3796 "#address-cells", 3) != DDI_SUCCESS) { 3797 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3798 } 3799 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3800 "#size-cells", 2) != DDI_SUCCESS) { 3801 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3802 } 3803 return (PCICFG_SUCCESS); 3804} 3805 3806static int 3807cardbus_set_busnode_isaprops(dev_info_t *dip) 3808{ 3809 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3810 3811 cardbus_force_stringprop(dip, "device_type", "isa"); 3812 3813 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3814 "#address-cells", 2) != DDI_SUCCESS) { 3815 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3816 } 3817 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3818 "#size-cells", 1) != DDI_SUCCESS) { 3819 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3820 } 3821 return (PCICFG_SUCCESS); 3822} 3823 3824/* 3825 * Use cb%x,%x rather than pci%x,%x so that we can use specific cardbus 3826 * drivers in /etc/driver_aliases if required 3827 */ 3828static int 3829cardbus_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle) 3830{ 3831 int ret; 3832#ifndef _DONT_USE_1275_GENERIC_NAMES 3833 uint32_t wordval; 3834#endif 3835 char *name; 3836 char buffer[64]; 3837 uint32_t classcode; 3838 char *compat[8]; 3839 int i, n; 3840 uint16_t subsysid, subvenid, devid, venid; 3841 uint8_t header_type; 3842 3843 /* 3844 * NOTE: These are for both a child and PCI-PCI bridge node 3845 */ 3846#ifndef _DONT_USE_1275_GENERIC_NAMES 3847 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3848 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3849#endif 3850 3851 /* Cardbus support */ 3852 venid = pci_config_get16(config_handle, PCI_CONF_VENID); 3853 devid = pci_config_get16(config_handle, PCI_CONF_DEVID); 3854 3855 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3856 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3857 subvenid = pci_config_get16(config_handle, PCI_CBUS_SUBVENID); 3858 subsysid = pci_config_get16(config_handle, PCI_CBUS_SUBSYSID); 3859 } else { 3860 subvenid = pci_config_get16(config_handle, PCI_CONF_SUBVENID); 3861 subsysid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3862 } 3863 3864 if (subsysid != 0) { 3865 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3866 } else { 3867 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3868 } 3869 3870 cardbus_err(dip, 8, "Childname is %s\n", buffer); 3871 3872 /* 3873 * In some environments, trying to use "generic" 1275 names is 3874 * not the convention. In those cases use the name as created 3875 * above. In all the rest of the cases, check to see if there 3876 * is a generic name first. 3877 */ 3878#ifdef _DONT_USE_1275_GENERIC_NAMES 3879 name = buffer; 3880#else 3881 if ((name = cardbus_get_class_name(wordval>>8)) == NULL) { 3882 /* 3883 * Set name to the above fabricated name 3884 */ 3885 name = buffer; 3886 } 3887 3888 cardbus_err(dip, 8, "Set nodename to %s\n", name); 3889#endif 3890 3891 /* 3892 * The node name field needs to be filled in with the name 3893 */ 3894 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3895 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3896 return (PCICFG_FAILURE); 3897 } 3898 3899 /* 3900 * Create the compatible property as an array of pointers 3901 * to strings. Start with the cb name. 3902 */ 3903 n = 0; 3904 3905 if (subsysid != 0) { 3906 (void) sprintf(buffer, "cb%x,%x", subvenid, subsysid); 3907 } else { 3908 (void) sprintf(buffer, "cb%x,%x", venid, devid); 3909 } 3910 3911 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3912 (void) strcpy(compat[n++], buffer); 3913 3914 if (subsysid != 0) { 3915 /* 3916 * Add subsys numbers as pci compatible. 3917 */ 3918 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3919 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3920 (void) strcpy(compat[n++], buffer); 3921 } 3922 3923 /* 3924 * Add in the VendorID/DeviceID compatible name. 3925 */ 3926 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3927 3928 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3929 (void) strcpy(compat[n++], buffer); 3930 3931 classcode = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3932 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3933 3934 /* 3935 * Add in the Classcode 3936 */ 3937 (void) sprintf(buffer, "pciclass,%06x", classcode); 3938 3939 cardbus_err(dip, 8, "class code %s\n", buffer); 3940 3941 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3942 (void) strcpy(compat[n++], buffer); 3943 3944 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3945 "compatible", (char **)compat, n)) != DDI_SUCCESS) { 3946 return (ret); 3947 } 3948 3949 for (i = 0; i < n; i++) { 3950 kmem_free(compat[i], strlen(compat[i]) + 1); 3951 } 3952 3953 return (PCICFG_SUCCESS); 3954} 3955 3956/* 3957 * Program the bus numbers into the bridge 3958 */ 3959static void 3960cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 3961 uint_t primary, uint_t secondary) 3962{ 3963 cardbus_err(NULL, 8, 3964 "cardbus_set_bus_numbers [%d->%d]\n", primary, secondary); 3965 3966 /* 3967 * Primary bus# 3968 */ 3969 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3970 3971 /* 3972 * Secondary bus# 3973 */ 3974 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3975 3976 /* 3977 * Set the subordinate bus number to ff in order to pass through any 3978 * type 1 cycle with a bus number higher than the secondary bus# 3979 * Note that this is reduced once the probe is complete in the 3980 * cardbus_setup_bridge() function. 3981 */ 3982 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0xFF); 3983} 3984 3985static void 3986enable_pci_isa_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 3987{ 3988 uint16_t comm, stat; 3989 3990 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 3991 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 3992 3993 /* 3994 * Enable memory, IO, bus mastership and error detection. 3995 */ 3996 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 3997 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 3998 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3999 "fast-back-to-back")) 4000 comm |= PCI_COMM_BACK2BACK_ENAB; 4001 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4002 cardbus_err(NULL, 8, 4003 "enable_pci_isa_bridge stat 0x%04x comm 0x%04x\n", stat, comm); 4004 4005 /* 4006 * ITE8888 Specific registers. 4007 */ 4008 pci_config_put8(config_handle, 0x50, 0x00); /* Timing Control */ 4009 pci_config_put8(config_handle, 0x52, 0x00); /* Master DMA Access */ 4010 pci_config_put8(config_handle, 0x53, 0x01); /* ROMCS */ 4011} 4012 4013static void 4014enable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4015{ 4016 uint16_t comm, stat, bctrl; 4017 4018 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4019 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4020 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4021 4022 comm &= ~(PCI_COMM_IO | PCI_COMM_MAE); 4023 comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4024 4025 /* 4026 * Enable back to back. 4027 */ 4028 if (stat & PCI_STAT_FBBC) 4029 comm |= PCI_COMM_BACK2BACK_ENAB; 4030 4031 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4032 4033 /* 4034 * Reset the sub-ordinate bus. 4035 */ 4036 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4037 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4038 bctrl | PCI_BCNF_BCNTRL_RESET); 4039 else 4040 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4041 4042 /* 4043 * Enable error reporting. 4044 */ 4045 bctrl |= (PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4046 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4047 4048 /* 4049 * Enable back to back on secondary bus. 4050 */ 4051 if (stat & PCI_STAT_FBBC) 4052 bctrl |= PCI_BCNF_BCNTRL_B2B_ENAB; 4053 4054 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4055 cardbus_err(dip, 8, 4056 "enable_pci_pci_bridge stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4057 stat, comm, bctrl); 4058} 4059 4060static int cardbus_reset_wait = 20; 4061 4062static void 4063enable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4064{ 4065 uint16_t comm, stat, bctrl; 4066 4067 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4068 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4069 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4070 4071 /* 4072 * Don't mess with the command register on the cardbus bridge 4073 * itself. This should have been done when it's parent 4074 * did the setup. Some devices *require* certain things to 4075 * disabled, this can be done using the "command-preserve" 4076 * property and if we mess with it here it breaks that. 4077 * 4078 * comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | 4079 * PCI_COMM_SERR_ENABLE); 4080 */ 4081 4082 /* 4083 * Reset the sub-ordinate bus. 4084 */ 4085 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4086 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4087 bctrl | PCI_BCNF_BCNTRL_RESET); 4088 else 4089 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4090 4091 /* 4092 * Turn off pre-fetch. 4093 */ 4094 bctrl &= ~(CB_BCNF_BCNTRL_MEM0_PREF | CB_BCNF_BCNTRL_MEM1_PREF | 4095 PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE); 4096 4097 /* 4098 * Enable error reporting. 4099 */ 4100 bctrl |= (PCI_BCNF_BCNTRL_MAST_AB_MODE | CB_BCNF_BCNTRL_WRITE_POST); 4101 if (comm & PCI_COMM_PARITY_DETECT) 4102 bctrl |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 4103 if (comm & PCI_COMM_SERR_ENABLE) 4104 bctrl |= PCI_BCNF_BCNTRL_SERR_ENABLE; 4105 4106 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4107 pci_config_put8(config_handle, PCI_CBUS_LATENCY_TIMER, 4108 cardbus_latency_timer); 4109 4110 pci_config_put16(config_handle, PCI_CONF_STAT, stat); 4111 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4112 4113 cardbus_err(dip, 8, 4114 "enable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4115 stat, comm, bctrl); 4116 4117 /* after resetting the bridge, wait for everything to stablize */ 4118 delay(drv_usectohz(cardbus_reset_wait * 1000)); 4119 4120} 4121 4122static void 4123disable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4124{ 4125 uint16_t comm, bctrl; 4126 4127 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4128 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4129 4130 /* 4131 * Turn off subordinate bus access. 4132 */ 4133 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4134 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4135 4136 /* 4137 * Disable error reporting. 4138 */ 4139 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4140 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4141 comm = 0; 4142 4143 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4144 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4145 4146 cardbus_err(dip, 6, 4147 "disable_pci_pci_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4148 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4149} 4150 4151static void 4152disable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4153{ 4154 uint16_t comm, bctrl; 4155 4156 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4157 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4158 4159 /* 4160 * Turn off subordinate bus access. 4161 */ 4162 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4163 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4164 4165 /* 4166 * Disable error reporting. 4167 */ 4168 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4169 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4170 4171 pci_config_put32(config_handle, PCI_CBUS_MEM_LIMIT0, 0); 4172 pci_config_put32(config_handle, PCI_CBUS_MEM_BASE0, 0); 4173 pci_config_put32(config_handle, PCI_CBUS_IO_LIMIT0, 0); 4174 pci_config_put32(config_handle, PCI_CBUS_IO_BASE0, 0); 4175 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4176 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4177 4178 cardbus_err(dip, 6, 4179 "disable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4180 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4181} 4182 4183static void 4184enable_cardbus_device(dev_info_t *dip, ddi_acc_handle_t config_handle) 4185{ 4186 uint16_t comm, stat; 4187 4188 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4189 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4190 4191 /* 4192 * Enable memory, IO, bus mastership and error detection. 4193 */ 4194 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4195 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4196 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4197 "fast-back-to-back")) 4198 comm |= PCI_COMM_BACK2BACK_ENAB; 4199 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4200 cardbus_err(NULL, 8, 4201 "enable_cardbus_device stat 0x%04x comm 0x%04x\n", stat, comm); 4202} 4203 4204static void 4205disable_cardbus_device(ddi_acc_handle_t config_handle) 4206{ 4207 cardbus_err(NULL, 8, "disable_cardbus_device\n"); 4208 4209 /* 4210 * Turn off everything in the command register. 4211 */ 4212 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 4213} 4214 4215#ifndef _DONT_USE_1275_GENERIC_NAMES 4216static char * 4217cardbus_get_class_name(uint32_t classcode) 4218{ 4219 struct cardbus_name_entry *ptr; 4220 4221 for (ptr = &cardbus_class_lookup[0]; ptr->name != NULL; ptr++) { 4222 if (ptr->class_code == classcode) { 4223 return (ptr->name); 4224 } 4225 } 4226 return (NULL); 4227} 4228#endif /* _DONT_USE_1275_GENERIC_NAMES */ 4229 4230/* 4231 * Work out a pil for a device based on the PCI class code. 4232 * Mostly taken from iline_to_pil() in sun4u/io/pci/pcic_intr.c. 4233 */ 4234#ifdef sparc 4235int 4236cardbus_get_class_pil(dev_info_t *rdip) 4237{ 4238 uint32_t classcode; 4239 struct cardbus_name_entry *ptr; 4240 int pil = 1; 4241 4242 classcode = ddi_prop_get_int(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 4243 "class-code", -1); 4244 if (classcode != -1) { 4245 classcode = ((uint_t)classcode & 0xffff00) >> 8; 4246 } else { 4247 cardbus_err(rdip, 1, 4248 "%s%d has no class-code property\n", 4249 ddi_driver_name(rdip), ddi_get_instance(rdip)); 4250 return (pil); 4251 } 4252 4253 for (ptr = &cardbus_class_lookup[0]; ptr->name != NULL; ptr++) { 4254 if (ptr->class_code == classcode) { 4255 if (ptr->pil <= 0x9) 4256 return (ptr->pil); 4257 else { 4258 cardbus_err(rdip, 1, 4259 "%s%d has high pil 0xb => 0x9\n", 4260 ddi_driver_name(rdip), 4261 ddi_get_instance(rdip)); 4262 return (0x9); 4263 } 4264 } 4265 } 4266 4267 /* 4268 * Not in our table - make a decision using the base-class-code. 4269 */ 4270 classcode = classcode >> 16; /* Base classcode */ 4271 switch (classcode) { 4272 default: 4273 case PCI_CLASS_NONE: 4274 pil = 1; 4275 break; 4276 4277 case PCI_CLASS_MASS: 4278 case PCI_CLASS_SERIALBUS: 4279 pil = 0x4; 4280 break; 4281 4282 case PCI_CLASS_NET: 4283 pil = 0x6; 4284 break; 4285 4286 case PCI_CLASS_DISPLAY: 4287 pil = 0x9; 4288 break; 4289 4290 case PCI_CLASS_MM: 4291 case PCI_CLASS_MEM: 4292 case PCI_CLASS_BRIDGE: 4293 cardbus_err(rdip, 1, 4294 "%s%d has high pil 0xb => 0x9\n", 4295 ddi_driver_name(rdip), ddi_get_instance(rdip)); 4296 pil = 0x9; 4297 break; 4298 } 4299 return (pil); 4300} 4301#endif 4302 4303static void 4304cardbus_force_boolprop(dev_info_t *dip, char *pname) 4305{ 4306 int ret; 4307 4308 if ((ret = ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 4309 pname)) != DDI_SUCCESS) { 4310 if (ret == DDI_PROP_NOT_FOUND) 4311 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4312 DDI_PROP_CANSLEEP, pname, 4313 (caddr_t)NULL, 0) != DDI_SUCCESS) 4314 cardbus_err(dip, 4, 4315 "Failed to set boolean property " 4316 "\"%s\"\n", pname); 4317 } 4318} 4319 4320static void 4321cardbus_force_intprop(dev_info_t *dip, char *pname, int *pval, int len) 4322{ 4323 int ret; 4324 4325 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 4326 pname, pval, len)) != DDI_SUCCESS) { 4327 if (ret == DDI_PROP_NOT_FOUND) 4328 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4329 DDI_PROP_CANSLEEP, pname, 4330 (caddr_t)pval, len*sizeof (int)) 4331 != DDI_SUCCESS) 4332 cardbus_err(dip, 4, 4333 "Failed to set int property \"%s\"\n", 4334 pname); 4335 } 4336} 4337 4338static void 4339cardbus_force_stringprop(dev_info_t *dip, char *pname, char *pval) 4340{ 4341 int ret; 4342 4343 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 4344 pname, pval)) != DDI_SUCCESS) { 4345 if (ret == DDI_PROP_NOT_FOUND) 4346 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4347 DDI_PROP_CANSLEEP, pname, 4348 pval, strlen(pval) + 1) != DDI_SUCCESS) 4349 cardbus_err(dip, 4, 4350 "Failed to set string property " 4351 "\"%s\" to \"%s\"\n", 4352 pname, pval); 4353 } 4354} 4355 4356static void 4357split_addr(char *naddr, int *dev, int *func) 4358{ 4359 char c; 4360 int *ip = dev; 4361 4362 *dev = 0; 4363 *func = 0; 4364 4365 while (c = *naddr++) { 4366 if (c == ',') { 4367 ip = func; 4368 continue; 4369 } 4370 if (c >= '0' && c <= '9') { 4371 *ip = (*ip * 16) + (c - '0'); 4372 } else if (c >= 'a' && c <= 'f') { 4373 *ip = (*ip * 16) + 10 + (c - 'a'); 4374 } else 4375 break; 4376 } 4377} 4378 4379#ifdef DEBUG 4380static void 4381cardbus_dump_common_config(ddi_acc_handle_t config_handle) 4382{ 4383 cardbus_err(NULL, 1, 4384 " Vendor ID = [0x%04x] " 4385 "Device ID = [0x%04x]\n", 4386 pci_config_get16(config_handle, PCI_CONF_VENID), 4387 pci_config_get16(config_handle, PCI_CONF_DEVID)); 4388 cardbus_err(NULL, 1, 4389 " Command REG = [0x%04x] " 4390 "Status REG = [0x%04x]\n", 4391 pci_config_get16(config_handle, PCI_CONF_COMM), 4392 pci_config_get16(config_handle, PCI_CONF_STAT)); 4393 cardbus_err(NULL, 1, 4394 " Revision ID = [0x%02x] " 4395 "Prog Class = [0x%02x]\n", 4396 pci_config_get8(config_handle, PCI_CONF_REVID), 4397 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 4398 cardbus_err(NULL, 1, 4399 " Dev Class = [0x%02x] " 4400 "Base Class = [0x%02x]\n", 4401 pci_config_get8(config_handle, PCI_CONF_SUBCLASS), 4402 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 4403 cardbus_err(NULL, 1, 4404 " Cache LnSz = [0x%02x] " 4405 "Latency Tmr = [0x%02x]\n", 4406 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ), 4407 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER)); 4408 cardbus_err(NULL, 1, 4409 " Header Type = [0x%02x] " 4410 "BIST = [0x%02x]\n", 4411 pci_config_get8(config_handle, PCI_CONF_HEADER), 4412 pci_config_get8(config_handle, PCI_CONF_BIST)); 4413} 4414 4415static void 4416cardbus_dump_device_config(ddi_acc_handle_t config_handle) 4417{ 4418 cardbus_dump_common_config(config_handle); 4419 4420 cardbus_err(NULL, 1, 4421 " BASE 0 = [0x%08x] BASE 1 = [0x%08x]\n", 4422 pci_config_get32(config_handle, PCI_CONF_BASE0), 4423 pci_config_get32(config_handle, PCI_CONF_BASE1)); 4424 cardbus_err(NULL, 1, 4425 " BASE 2 = [0x%08x] BASE 3 = [0x%08x]\n", 4426 pci_config_get32(config_handle, PCI_CONF_BASE2), 4427 pci_config_get32(config_handle, PCI_CONF_BASE3)); 4428 cardbus_err(NULL, 1, 4429 " BASE 4 = [0x%08x] BASE 5 = [0x%08x]\n", 4430 pci_config_get32(config_handle, PCI_CONF_BASE4), 4431 pci_config_get32(config_handle, PCI_CONF_BASE5)); 4432 cardbus_err(NULL, 1, 4433 " Cardbus CIS = [0x%08x] ROM = [0x%08x]\n", 4434 pci_config_get32(config_handle, PCI_CONF_CIS), 4435 pci_config_get32(config_handle, PCI_CONF_ROM)); 4436 cardbus_err(NULL, 1, 4437 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4438 pci_config_get16(config_handle, PCI_CONF_SUBVENID), 4439 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 4440 cardbus_err(NULL, 1, 4441 " I Line = [0x%02x] I Pin = [0x%02x]\n", 4442 pci_config_get8(config_handle, PCI_CONF_ILINE), 4443 pci_config_get8(config_handle, PCI_CONF_IPIN)); 4444 cardbus_err(NULL, 1, 4445 " Max Grant = [0x%02x] Max Latent = [0x%02x]\n", 4446 pci_config_get8(config_handle, PCI_CONF_MIN_G), 4447 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 4448} 4449 4450static void 4451cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 4452 uint8_t header_type) 4453{ 4454 if (header_type == PCI_HEADER_PPB) { 4455 cardbus_dump_common_config(config_handle); 4456 cardbus_err(NULL, 1, 4457 "........................................\n"); 4458 } else { 4459 cardbus_dump_common_config(config_handle); 4460 cardbus_err(NULL, 1, 4461 " Mem Base = [0x%08x] CBus Status = [0x%04x]\n", 4462 pci_config_get32(config_handle, PCI_CBUS_SOCK_REG), 4463 pci_config_get16(config_handle, PCI_CBUS_SEC_STATUS)); 4464 } 4465 4466 cardbus_err(NULL, 1, 4467 " Pri Bus = [0x%02x] Sec Bus = [0x%02x]\n", 4468 pci_config_get8(config_handle, PCI_BCNF_PRIBUS), 4469 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 4470 cardbus_err(NULL, 1, 4471 " Sub Bus = [0x%02x] Sec Latency = [0x%02x]\n", 4472 pci_config_get8(config_handle, PCI_BCNF_SUBBUS), 4473 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 4474 4475 switch (header_type) { 4476 case PCI_HEADER_PPB: 4477 cardbus_err(NULL, 1, 4478 " I/O Base LO = [0x%02x] I/O Lim LO = [0x%02x]\n", 4479 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW), 4480 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 4481 cardbus_err(NULL, 1, 4482 " Sec. Status = [0x%04x]\n", 4483 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 4484 cardbus_err(NULL, 1, 4485 " Mem Base = [0x%04x] Mem Limit = [0x%04x]\n", 4486 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE), 4487 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 4488 cardbus_err(NULL, 1, 4489 " PF Mem Base = [0x%04x] PF Mem Lim = [0x%04x]\n", 4490 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW), 4491 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 4492 cardbus_err(NULL, 1, 4493 " PF Base HI = [0x%08x] PF Lim HI = [0x%08x]\n", 4494 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH), 4495 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 4496 cardbus_err(NULL, 1, 4497 " I/O Base HI = [0x%04x] I/O Lim HI = [0x%04x]\n", 4498 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI), 4499 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 4500 cardbus_err(NULL, 1, 4501 " ROM addr = [0x%08x]\n", 4502 pci_config_get32(config_handle, PCI_BCNF_ROM)); 4503 break; 4504 case PCI_HEADER_CARDBUS: 4505 cardbus_err(NULL, 1, 4506 " Mem Base 0 = [0x%08x] Mem Limit 0 = [0x%08x]\n", 4507 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE0), 4508 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT0)); 4509 cardbus_err(NULL, 1, 4510 " Mem Base 1 = [0x%08x] Mem Limit 1 = [0x%08x]\n", 4511 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE1), 4512 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1)); 4513 cardbus_err(NULL, 1, 4514 " IO Base 0 = [0x%08x] IO Limit 0 = [0x%08x]\n", 4515 pci_config_get32(config_handle, PCI_CBUS_IO_BASE0), 4516 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT0)); 4517 cardbus_err(NULL, 1, 4518 " IO Base 1 = [0x%08x] IO Limit 1 = [0x%08x]\n", 4519 pci_config_get32(config_handle, PCI_CBUS_IO_BASE1), 4520 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT1)); 4521 break; 4522 } 4523 cardbus_err(NULL, 1, 4524 " Intr Line = [0x%02x] Intr Pin = [0x%02x]\n", 4525 pci_config_get8(config_handle, PCI_BCNF_ILINE), 4526 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 4527 cardbus_err(NULL, 1, 4528 " Bridge Ctrl = [0x%04x]\n", 4529 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 4530 4531 switch (header_type) { 4532 case PCI_HEADER_CARDBUS: 4533 cardbus_err(NULL, 1, 4534 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4535 pci_config_get16(config_handle, PCI_CBUS_SUBVENID), 4536 pci_config_get16(config_handle, PCI_CBUS_SUBSYSID)); 4537 /* LATER: TI1250 only */ 4538 cardbus_err(NULL, 1, 4539 " Sys Control = [0x%08x]\n", 4540 pci_config_get32(config_handle, 0x80)); 4541 } 4542} 4543 4544static void 4545cardbus_dump_config(ddi_acc_handle_t config_handle) 4546{ 4547 uint8_t header_type = pci_config_get8(config_handle, 4548 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 4549 4550 if (header_type == PCI_HEADER_PPB || header_type == PCI_HEADER_CARDBUS) 4551 cardbus_dump_bridge_config(config_handle, header_type); 4552 else 4553 cardbus_dump_device_config(config_handle); 4554} 4555 4556static void 4557cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, int nelems) 4558{ 4559 /* int rlen = nelems * sizeof(pci_regspec_t); */ 4560 4561 cardbus_err(dip, 6, 4562 "cardbus_dump_reg: \"reg\" has %d elements\n", nelems); 4563 4564#if defined(CARDBUS_DEBUG) 4565 if (cardbus_debug >= 1) { 4566 int i; 4567 uint32_t *regs = (uint32_t *)regspec; 4568 4569 for (i = 0; i < nelems; i++) { 4570 4571 cardbus_err(NULL, 6, 4572 "\t%d:%08x %08x %08x %08x %08x\n", 4573 i, regs[0], regs[1], regs[2], regs[3], regs[4]); 4574 } 4575 } 4576#endif 4577} 4578 4579#endif 4580 4581#if defined(CARDBUS_DEBUG) 4582void 4583cardbus_dump_children(dev_info_t *dip, int level) 4584{ 4585 dev_info_t *next; 4586 4587 cardbus_err(dip, 1, 4588 "\t%d: %s: 0x%p\n", level, ddi_node_name(dip), (void *) dip); 4589 for (next = ddi_get_child(dip); next; 4590 next = ddi_get_next_sibling(next)) 4591 cardbus_dump_children(next, level + 1); 4592} 4593 4594void 4595cardbus_dump_family_tree(dev_info_t *dip) 4596{ 4597 cardbus_err(dip, 1, "0x%p family tree:\n", (void *) dip); 4598 cardbus_dump_children(dip, 1); 4599} 4600#endif 4601