audiots.h revision 9484:fbd5ddc28e96
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _AUDIOTS_H 27#define _AUDIOTS_H 28 29/* 30 * Header file for the audiots device driver. 31 */ 32 33/* 34 * Values returned by the AUDIO_GETDEV ioctl() 35 */ 36#define TS_DEV_NAME "SUNW,audiots" 37#define TS_DEV_CONFIG "onboard1" 38#define TS_DEV_VERSION_A "a" /* grover, sngl strming play */ 39#define TS_DEV_VERSION_B "b" /* birdsnest, sngl strm play */ 40 41/* 42 * Driver supported configuration information 43 */ 44#define TS_NAME "audiots" 45#define TS_MOD_NAME "audiots audio driver" 46 47#define TS_RATE (48000) 48#define TS_STEREO (2) /* stereo */ 49#define TS_FRAMESZ (4) /* 16-bit stereo */ 50/* 51 * This is how much buffer space we at minimum need. The worst 52 * (biggest) case is 48000 kHz, at 4 bytes per frame (16-bit stereo), 53 * with the lowest interrupt frequency. 48000 x 4 bytes per sample / 54 * 24 is 8000 bytes per fragment. Two such fragments would be 16000. 55 * (At higher data rates, we get better buffering, with more frags.) 56 */ 57#define TS_BUFSZ (16000) /* maximum buffer size */ 58#define TS_INTS (175) /* default interrupt rate */ 59#define TS_MIN_INTS (24) /* minimum interrupt rate */ 60#define TS_MAX_INTS (2000) /* maximum interrupt rate */ 61 62/* 63 * Misc. defines 64 */ 65#define TS_IO_MAPPED_REGS (1) 66#define TS_MEM_MAPPED_REGS (2) 67#define TS_ALL_DMA_ENGINES (0xffffffff) 68#define TS_ALL_DMA_OFF (0x00000000) 69 70#define TS_20MS (20000) /* 20,000 microseconds */ 71#define TS_20US (20) /* 20 microseconds */ 72#define TS_SRC_SHIFT (12) 73 74#define TS_NUM_PORTS (2) 75#define TS_OUTPUT_PORT (0) 76#define TS_INPUT_PORT (1) 77 78#define TS_MAX_HW_CHANNELS (32) 79 80#define TS_KIOP(X) ((kstat_intr_t *)(X->ts_ksp->ks_data)) 81#define TS_WAIT_CNT (512) 82#define TS_LOOP_CNT (10) 83#define TS_DELAY_CNT (25) 84#define TS_CODEC_REG(r) ((r) >> 1) 85 86/* ALI Hacks */ 87#define TS_READ_TRIES (TS_WAIT_CNT/10) 88#define TS_RESET_TRIES (16) 89#define TS_SB_RESET (0x7fff) 90 91/* These are the devices we know about */ 92#define TS_DEVICE_ALI_M5451 ((0x10b9 << 16) | (0x5451)) 93#define TS_DEVICE_TRIDENT_4DWAVEDX ((0x1023 << 16) | (0x2000)) 94#define TS_DEVICE_TRIDENT_4DWAVENX ((0x1023 << 16) | (0x2001)) 95#define TS_DEVICE_SIS_7018 ((0x1039 << 16) | (0x7018)) 96 97#define TS_AD_CODEC_ID 0x4144 98#define TS_AD_REV_ID 0x5340 99#define AC_REV_ID1 0x0001 100#define AC_REV_ID2 0x0002 101 102#define TS_CAP_PTR 0xdc 103#define TS_PWR_D0 0x0000 104#define TS_PWR_D1 0x0001 105#define TS_PWR_D2 0x0002 106#define TS_PWR_D3 0x0003 107#define TS_PWR_PME 0x8000 108 109/* 110 * audiots_aram_t - ARAM registers 111 */ 112struct audiots_aram { 113 uint16_t aram_alpha_fms; /* e0h - e1h */ 114 uint16_t aram_cso; /* e2h - e3h */ 115 uint32_t aram_cptr_lba; /* e4h - e7h */ 116 uint16_t aram_delta; /* e8h - e9h */ 117 uint16_t aram_eso; /* eah - ebh */ 118 uint32_t aram_reserved; /* ech - efh */ 119}; 120typedef struct audiots_aram audiots_aram_t; 121 122/* aram_cso_alpha_fms register defines */ 123#define ARAM_FMS_MASK 0x000f 124#define ARAM_ALPHA_MASK 0xfff0 125 126/* aram_cptr_lba register defines */ 127#define ARAM_LBA_MASK 0x7fffffff 128#define ARAM_CPTR_MASK 0x80000000 129 130/* 131 * audiots_eram_t - ERAM registers 132 */ 133struct audiots_eram { 134 uint16_t eram_ctrl_ec; /* f0h - f1h */ 135 uint16_t eram_gvsel_pan_vol; /* f2h - f3h */ 136 uint32_t eram_ebuf1; /* f4h - f7h */ 137 uint32_t eram_ebuf2; /* f8h - fbh */ 138 uint32_t eram_reserved; /* fch - ffh */ 139}; 140typedef struct audiots_eram audiots_eram_t; 141 142/* eram_ctrl_ec register defines */ 143#define ERAM_EC_MASK 0x0fff 144#define ERAM_CTRL_MASK 0xf000 145#define ERAM_LOOP_MODE 0x1000 146#define ERAM_NOLOOP_MODE 0x0000 147#define ERAM_SIGNED_PCM 0x2000 148#define ERAM_UNSIGNED_PCM 0x0000 149#define ERAM_STEREO 0x4000 150#define ERAM_MONO 0x0000 151#define ERAM_16_BITS 0x8000 152#define ERAM_8_BITS 0x0000 153 154/* eram_gvsel_pan_vol register defines */ 155#define ERAM_VOL_MASK 0x00ff 156#define ERAM_VOL_0dB 0x0000 157#define ERAM_VOL_DEFAULT 0x000f 158#define ERAM_VOL_MAX_ATTEN 0x00ff 159#define ERAM_PAN_MASK 0x3f00 160#define ERAM_PAN_0dB 0x0000 161#define ERAM_PAN_MAX_ATTEN 0x3f00 162#define ERAM_PAN_LEFT 0x0000 163#define ERAM_PAN_RIGHT 0x4000 164#define ERAM_MUSIC_VOL 0x0000 165#define ERAM_WAVE_VOL 0x8000 166 167/* eram_ebuf register defines */ 168#define ERAM_EBUF_STILL 0x30000000 169 170/* 171 * audiots_processor_t - Audio Processor registers via I/O space 172 * 173 * NOTE: Soutbridge rev 1535D+ uses a read/write register at AudioBase +40 174 * Previous SB chip revs had a seperate write register at AudioBase +40, and 175 * a read register at AudioBase +44. 176 * 177 */ 178struct audiots_processor { 179 uint32_t ap_dmar0_1_2_3; /* 00h - 03h */ 180 uint32_t ap_dmar4_5_6_7; /* 04h - 07h */ 181 uint32_t ap_dmar8_9_10_11; /* 08h - 0bh */ 182 uint32_t ap_dmar12_13_14_15; /* 0ch - 0fh */ 183 uint32_t ap_sbr0_1_2_3; /* 10h - 13h */ 184 uint32_t ap_sbr4_5_6; /* 14h - 17h */ 185 uint32_t ap_svbr7; /* 18h - 1bh */ 186 uint32_t ap_sbr8_9_10; /* 1ch - 1fh */ 187 uint32_t ap_mpur0_1_2_3; /* 20h - 23h */ 188 uint32_t ap_rsvd1[3]; /* 24h - 2fh */ 189 uint32_t ap_gamer0_1; /* 30h - 33h */ 190 uint32_t ap_gamer2; /* 34h - 37h */ 191 uint32_t ap_gamer3; /* 38h - 3bh */ 192 uint32_t ap_rsvd2; /* 3ch - 3fh */ 193 uint16_t ap_acrdwr_reg; /* 40h - 41h */ 194 uint16_t ap_acrdwr_data; /* 42h - 43h */ 195 uint16_t ap_acrd_35D_reg; /* 44h - 45h */ 196 uint16_t ap_acrd_35D_data; /* 46h - 47h */ 197 uint32_t ap_sctrl; /* 48h - 4bh */ 198 uint32_t ap_acgpio; /* 4ch - 4fh */ 199 uint32_t ap_asr0; /* 50h - 53h */ 200 uint32_t ap_asr1_2; /* 54h - 57h */ 201 uint32_t ap_asr3; /* 58h - 5bh */ 202 uint32_t ap_asr4_5_6; /* 5ch - 5fh */ 203 uint32_t ap_aoplsr0; /* 60h - 63h */ 204 uint32_t ap_rsvd3[6]; /* 64h - 7bh */ 205 uint32_t ap_gp; /* 7ch - 7fh */ 206 uint32_t ap_start; /* 80h - 83h */ 207 uint32_t ap_stop; /* 84h - 87h */ 208 uint32_t ap_delay; /* 88h - 8bh */ 209 uint32_t ap_sign_cso; /* 8ch - 8fh */ 210 uint32_t ap_cspf; /* 90h - 93h */ 211 uint32_t ap_cebc; /* 94h - 97h */ 212 uint32_t ap_aint; /* 98h - 9bh */ 213 uint32_t ap_eint; /* 9ch - 9fh */ 214 uint32_t ap_cir_gc; /* a0h - a3h */ 215 uint32_t ap_ainten; /* a4h - a7h */ 216 uint32_t ap_volume; /* a8h - abh */ 217 uint32_t ap_sbdelta; /* ach - afh */ 218 uint32_t ap_miscint; /* b0h - b3h */ 219 uint32_t ap_rsvd4[3]; /* b4h - bfh */ 220 uint32_t ap_sbdm; /* c0h - c3h */ 221 uint32_t ap_sb; /* c4h - c7h */ 222 uint32_t ap_stimer; /* c8h - cbh */ 223 uint32_t ap_lfo_i2s_delta; /* cch - cfh */ 224 uint32_t ap_st_target; /* d0h - d3h */ 225 uint32_t ap_global_control; /* d4h - d7h */ 226 uint32_t ap_rsvd5[2]; /* d8h - dfh */ 227 audiots_aram_t ap_aram; /* e0h - efh */ 228 audiots_eram_t ap_eram; /* f0h - ffh */ 229}; 230typedef struct audiots_processor audiots_processor_t; 231 232/* ap_acwr_reg register defines (40h - 41h) */ 233#define AP_ACWR_INDEX_MASK 0x007f 234#define AP_ACWR_W_PRIMARY_CODEC 0x0000 235#define AP_ACWR_W_SECONDARY_CODEC 0x0080 236#define AP_ACWR_W_WRITE_MIXER_REG 0x8000 237#define AP_ACWR_W_SELECT_WRITE 0x0100 238#define AP_ACWR_R_PRIMARY_CODEC 0x0000 239#define AP_ACWR_R_SECONDARY_CODEC 0x0080 240#define AP_ACWR_R_WRITE_BUSY 0x8000 241 242/* ap_acrd_reg register defines (44h - 45h) */ 243#define AP_ACRD_INDEX_MASK 0x007f 244#define AP_ACRD_W_PRIMARY_CODEC 0x0000 245#define AP_ACRD_W_SECONDARY_CODEC 0x0080 246#define AP_ACRD_W_MODEM_READ_REQ 0x2000 247#define AP_ACRD_W_AUDIO_READ_REQ 0x4000 248#define AP_ACRD_W_READ_MIXER_REG 0x8000 249#define AP_ACRD_R_PRIMARY_CODEC 0x0000 250#define AP_ACRD_R_SECONDARY_CODEC 0x0080 251#define AP_ACRD_R_MODEM_READ_REQ 0x2000 252#define AP_ACRD_R_AUDIO_READ_REQ 0x4000 253#define AP_ACRD_R_READ_BUSY 0x8000 254 255/* ap_sctrl register defines (48h - 4bh) */ 256#define AP_SCTRL_WRST_CODEC 0x00000001 257#define AP_SCTRL_CRST_CODEC 0x00000002 258#define AP_SCTRL_12288K_CLOCK 0x00000000 259#define AP_SCTRL_6144K_CLOCK 0x00000004 260#define AP_SCTRL_PCM_TO_PRIMARY 0x00000000 261#define AP_SCTRL_PCM_TO_SECONDARY 0x00000008 262#define AP_SCTRL_DOUPLE_RATE_DISABLE 0x00000000 263#define AP_SCTRL_DOUPLE_RATE_ENABLE 0x00000010 264#define AP_SCTRL_I2S_DISABLE 0x00000000 265#define AP_SCTRL_I2S_ENABLE 0x00000080 266#define AP_SCTRL_PCMIN_SEL_PRIMARY_CODEC 0x00000000 267#define AP_SCTRL_PCMIN_SEL_SECONDARY_CODEC 0x00000100 268#define AP_SCTRL_LINE1IN_SEL_PRIMARY_CODEC 0x00000000 269#define AP_SCTRL_LINE1IN_SEL_SECONDARY_CODEC 0x00000200 270#define AP_SCTRL_MICIN_SEL_PRIMARY_CODEC 0x00000000 271#define AP_SCTRL_MICIN_SEL_SECONDARY_CODEC 0x00000400 272#define AP_SCTRL_LINE2IN_SEL_PRIMARY_CODEC 0x00000000 273#define AP_SCTRL_LINE2IN_SEL_SECONDARY_CODEC 0x00000800 274#define AP_SCTRL_HSETIN_SEL_PRIMARY_CODEC 0x00000000 275#define AP_SCTRL_HSETIN_SEL_SECONDARY_CODEC 0x00001000 276#define AP_SCTRL_GPIOIN_SEL_PRIMARY_CODEC 0x00000000 277#define AP_SCTRL_GPIOIN_SEL_SECONDARY_CODEC 0x00002000 278#define AP_SCTRL_SECONDARY_CODEC_MASK 0x0000c000 279#define AP_SCTRL_SECONDARY_CODEC_DEFAULT 0x00004000 280#define AP_SCTRL_PCMOUT_EN 0x00010000 281#define AP_SCTRL_SURROUT_EN 0x00020000 282#define AP_SCTRL_CENTEROUT_EN 0x00040000 283#define AP_SCTRL_LFEOUT_EN 0x00080000 284#define AP_SCTRL_LINE1OUT_EN 0x00100000 285#define AP_SCTRL_LINE2OUT_EN 0x00200000 286#define AP_SCTRL_HSETOUT_EN 0x00400000 287#define AP_SCTRL_GPIOOUT_EN 0x00800000 288#define AP_SCTRL_CODECA_RDY 0x01000000 /* primary */ 289#define AP_SCTRL_CODECB_RDY 0x02000000 /* secondary */ 290#define AP_SCTRL_CODEC_PD 0x04000000 291 292/* ap_acgpio resister defines (4ch - 4fh) */ 293#define AP_ACGPIO_IRQ1 0x00000002 /* primary */ 294#define AP_ACGPIO_IRQ2 0x00000004 /* secondary */ 295#define AP_ACGPIO_INT1_ENABLE 0x00000008 296#define AP_ACGPIO_INT1_DISABLE 0x00000000 297#define AP_ACGPIO_INT2_ENABLE 0x00000010 298#define AP_ACGPIO_INT2_DISABLE 0x00000000 299#define AP_ACGPIO_WRITE_SLOT_12 0x00008000 300#define AP_ACGPIO_R_SLOT_12_BUSY 0x00008000 301#define AP_ACGPIO_DATA_MASK 0xffff0000 302 303/* ap_asr0 resgister defines (50h - 53h) */ 304#define AP_ASR0_CODEC_READY 0x00008000 305 306/* ap_asr4_5_6 register defines (5ch - 5fh) */ 307#define AP_ASR4_REV_A 0x00000080 308#define AP_ASR4_REV_BC 0x00000049 309#define AP_ASR5_ESP_VERSION 0x00040000 310#define AP_ASR6_ESP_VERSION 0x02000000 311 312/* ap_ain register defines (98h - 9bh) */ 313#define AP_AIN_RESET_ALL 0xffffffff 314 315/* ap_eain register defines (9ch - 9fh) */ 316#define AP_EAIN_RESET_ALL 0xffffffff 317 318/* ap_cir_gc register defines (a0h - a3h) */ 319#define AP_CIR_GC_CHANNEL_INDEX_MASK 0x0000001f 320#define AP_CIR_GC_RST_STIMER 0x00000100 321#define AP_CIR_GC_PAUSE 0x00000200 322#define AP_CIR_GC_OVERUN_IE 0x00000400 323#define AP_CIR_GC_UNDERUN_IE 0x00000800 324#define AP_CIR_GC_ENDLP_IE 0x00001000 325#define AP_CIR_GC_MIDLP_IE 0x00002000 326#define AP_CIR_GC_ETOG_IE 0x00004000 327#define AP_CIR_GC_EDROP_IE 0x00008000 328#define AP_CIR_GC_SYS_MEM_4G_ENABLE 0x00010000 329#define AP_CIR_GC_PCM_FIFO 0x00000000 330#define AP_CIR_GC_MMC_BUFFER 0x00100000 331#define AP_CIR_GC_NORMAL_MODE 0x00000000 332#define AP_CIR_GC_EXPROM_DUMP_MODE_ENABLE 0x00800000 333#define AP_CIR_GC_EXPROM_DEBUG_MODE 0x04000000 334#define AP_CIR_GC_TEST_LOOPBACK_ON 0x08000000 335 336/* ap_ainten register defines (a4h - a7h) */ 337#define AP_AINTEN_DISABLE_ALL 0x00000000 338 339/* ap_volume regsiter defines (a8h - abh) */ 340#define AP_VOLUME_WAVE_LEFT_MASK 0x000000ff 341#define AP_VOLUME_WAVE_LEFT_MUTE 0x000000ff 342#define AP_VOLUME_WAVE_LEFT_FULL 0x00000000 343#define AP_VOLUME_WAVE_LEFT_SHIFT 0 344#define AP_VOLUME_WAVE_RIGHT_MASK 0x0000ff00 345#define AP_VOLUME_WAVE_RIGHT_MUTE 0x0000ff00 346#define AP_VOLUME_WAVE_RIGHT_FULL 0x00000000 347#define AP_VOLUME_WAVE_RIGHT_SHIFT 8 348#define AP_VOLUME_MUSIC_LEFT_MASK 0x00ff0000 349#define AP_VOLUME_MUSIC_LEFT_MUTE 0x00ff0000 350#define AP_VOLUME_MUSIC_LEFT_FULL 0x00000000 351#define AP_VOLUME_MUSIC_LEFT_SHIFT 16 352#define AP_VOLUME_MUSIC_RIGHT_MASK 0xff000000 353#define AP_VOLUME_MUSIC_RIGHT_MUTE 0xff000000 354#define AP_VOLUME_MUSIC_RIGHT_FULL 0x00000000 355#define AP_VOLUME_MUSIC_RIGHT_SHIFT 24 356 357/* ap_miscint register defines (b0h - b3h) */ 358#define AP_MISCINT_PB_UNDERUN_IRQ 0x00000001 359#define AP_MISCINT_REC_OVERRUN_IRQ 0x00000002 360#define AP_MISCINT_SB_IRQ 0x00000004 361#define AP_MISCINT_MPU401_IRQ 0x00000008 362#define AP_MISCINT_OPL3_IRQ 0x00000010 363#define AP_MISCINT_ADDRESS_IRQ 0x00000020 364#define AP_MISCINT_ENVELOPE_IRQ 0x00000040 365#define AP_MISCINT_ST_IRQ 0x00000080 366#define AP_MISCINT_PB_UNDERUN 0x00000100 367#define AP_MISCINT_REC_OVERUN 0x00000200 368#define AP_MISCINT_MIXER_UNDERFLOW_FLAG 0x00000400 369#define AP_MISCINT_MIXER_OVERFLOW_FLAG 0x00000800 370#define AP_MISCINT_ST_TARGET_REACHED 0x00008000 371#define AP_MISCINT_PB_24K_MODE 0x00010000 372#define AP_MISCINT_OPLTIMER_IE 0x00020000 373#define AP_MISCINT_GPIO_IE 0x00040000 374#define AP_MISCINT_ST_IRQ_EN 0x00800000 375#define AP_MISCINT_ACGPIO_IRQ 0x01000000 376#define AP_MISCINT_GPIO_IRQ 0x02000000 377 378/* ap_lfo_i2s_delta register defines (cch - cfh) */ 379#define AP_I2S_DELTA_MASK 0x00001fff 380#define AP_LFO_INIT_MASK 0x00ff0000 381#define AP_LFO_48KHZ 0x00000000 382#define AP_LFO_48KHZ_BY_4 0x01000000 383#define AP_LFO_48KHZ_BY_16 0x02000000 384#define AP_LFO_48KHZ_BY_64 0x03000000 385#define AP_LFO_ENABLE 0x04000000 386 387/* ap_global_control register defines (d4h - d7h) */ 388#define AP_GLOBAL_CTRL_ENABLE_HW_VOLUME 0x00000001 389#define AP_CLOGAL_CTRL_PCM_OUT_AC97 0x00000000 390#define AP_CLOGAL_CTRL_PCM_OUT_I2S 0x00000080 391#define AP_CLOGAL_CTRL_I2SIN_TO_SYS_MEMORY 0x00000000 392#define AP_CLOGAL_CTRL_I2SIN_TO_AC97 0x00001000 393#define AP_CLOGAL_CTRL_I2SIN_TO_SYS_MEMORY_AC97 0x00002000 394#define AP_CLOGAL_CTRL_MMC_FROM_MIXER 0x00000000 395#define AP_CLOGAL_CTRL_MMC_FROM_PCM_OUT 0x00004000 396#define AP_CLOGAL_CTRL_PCM_OUT_TO_AC97 0x00000000 397#define AP_CLOGAL_CTRL_PCM_OUT_TO_I2S 0x00008000 398#define AP_CLOGAL_CTRL_E_HSETOUT_CH16 0x00010000 399#define AP_CLOGAL_CTRL_E_HSETIN_CH17 0x00020000 400#define AP_CLOGAL_CTRL_E_LINE2OUT_CH18 0x00040000 401#define AP_CLOGAL_CTRL_E_LINE2IN_CH19 0x00080000 402#define AP_CLOGAL_CTRL_E_LINE1OUT_CH20 0x00100000 403#define AP_CLOGAL_CTRL_E_LINE1IN_CH21 0x00200000 404#define AP_CLOGAL_CTRL_E_MIC_CH22 0x00400000 405#define AP_CLOGAL_CTRL_E_LFE_CH23 0x00800000 406#define AP_CLOGAL_CTRL_E_CENTER_CH24 0x01000000 407#define AP_CLOGAL_CTRL_E_SURR_R_CH25 0x02000000 408#define AP_CLOGAL_CTRL_E_SURR_L_CH26 0x04000000 409#define AP_CLOGAL_CTRL_E_PCMOUT_R_CH27 0x08000000 410#define AP_CLOGAL_CTRL_E_PCMOUT_L_CH28 0x10000000 411#define AP_CLOGAL_CTRL_E_I2SIN_CH29 0x20000000 412#define AP_CLOGAL_CTRL_E_MMC_CH30 0x40000000 413#define AP_CLOGAL_CTRL_E_PCMIN_CH31 0x80000000 414 415/* 416 * audiots_regs_t - Audio processor registers via memory space. 417 */ 418struct audiots_regs { 419 audiots_processor_t aud_regs; 420 uint32_t aud_rsvd1[64]; 421 uint32_t aud_oplram[128]; 422 uint32_t aud_rsvd2[256]; 423 struct { 424 audiots_aram_t aram; 425 audiots_eram_t eram; 426 } aud_ram[TS_MAX_HW_CHANNELS]; /* 32 channels */ 427 struct { 428 audiots_aram_t aram; 429 audiots_eram_t eram; 430 } aud_rsvd3[TS_MAX_HW_CHANNELS]; /* another 32 chs not implemented */ 431}; 432typedef struct audiots_regs audiots_regs_t; 433 434/* 435 * audiots_save_regs_t - Saved audio controller registers. 436 */ 437 438struct audiots_port { 439 struct audiots_state *tp_state; 440 int tp_num; 441 int tp_dma_stream; 442 int tp_int_stream; 443 444 uint32_t tp_dma_mask; 445 uint32_t tp_int_mask; 446 447 boolean_t tp_started; 448 unsigned tp_intrs; 449 unsigned tp_fragfr; 450 unsigned tp_nframes; 451 unsigned tp_rate; 452 uint64_t tp_count; 453 size_t tp_size; 454 caddr_t tp_kaddr; 455 uint32_t tp_paddr; 456 ddi_dma_handle_t tp_dmah; 457 ddi_acc_handle_t tp_acch; 458 unsigned tp_sync_dir; 459 460 audio_engine_t *tp_engine; 461 /* counting cso */ 462 uint16_t tp_cso; 463}; 464typedef struct audiots_port audiots_port_t; 465 466/* 467 * audiots_state_t - per instance state and operation data 468 */ 469struct audiots_state { 470 kmutex_t ts_lock; /* state protection lock */ 471 ddi_iblock_cookie_t ts_iblock; /* iblock cookie */ 472 uint_t ts_flags; /* flags */ 473 kstat_t *ts_ksp; /* kernel statistics */ 474 dev_info_t *ts_dip; /* used by ts_getinfo() */ 475 audio_dev_t *ts_adev; /* audio device handle */ 476 ac97_t *ts_ac97; /* ac97 common handle */ 477 audiots_regs_t *ts_regs; /* memory mapped registers */ 478 audiots_port_t *ts_ports[TS_NUM_PORTS]; 479 /* hardware engines */ 480 481 ddi_acc_handle_t ts_pcih; /* handle to config regs */ 482 ddi_acc_handle_t ts_acch; /* handle to mapped regs */ 483 boolean_t ts_suspended; /* power management state */ 484 boolean_t ts_swapped; /* swapped left/right? */ 485 486 uint32_t ts_devid; 487 uint8_t ts_revid; /* SB Chip Revision ID */ 488 489}; 490typedef struct audiots_state audiots_state_t; 491 492_NOTE(MUTEX_PROTECTS_DATA(audiots_state::ts_lock, audiots_state)) 493_NOTE(READ_ONLY_DATA(audiots_state::ts_instance)) 494_NOTE(READ_ONLY_DATA(audiots_state::ts_dip)) 495_NOTE(READ_ONLY_DATA(audiots_state::ts_adev)) 496 497/* audiots_state.ts_flags defines */ 498#define TS_MUTEX_INIT 0x0001u /* mutex initialized */ 499#define TS_INTR_INSTALLED 0x0002u /* intr handler installeld */ 500#define TS_AUDIO_READ_FAILED 0x0020u /* reading the AC97 register */ 501 /* has stopped working */ 502#define TS_READ_FAILURE_PRINTED 0x0040u /* Flag to avoid flooding the */ 503 /* console with AC97 failure */ 504 /* messages */ 505 506/* 507 * Read and write the AC-97 Codec's registers 508 */ 509#define AC97_RETRIES 1000 510#define AC97_WAIT 1 511 512/* 513 * Useful bit twiddlers 514 */ 515#define OR_SET_BYTE(handle, addr, val) \ 516 ddi_put8((handle), (uint8_t *)(addr), \ 517 (ddi_get8((handle), (uint8_t *)(addr)) | (uint8_t)(val))); 518 519#define OR_SET_SHORT(handle, addr, val) \ 520 ddi_put16((handle), (uint16_t *)(addr), \ 521 (ddi_get16((handle), (uint16_t *)(addr)) | (uint16_t)(val))); 522 523#define OR_SET_WORD(handle, addr, val) \ 524 ddi_put32((handle), (uint32_t *)(addr), \ 525 (ddi_get32((handle), (uint32_t *)(addr)) | (uint32_t)(val))); 526 527#define AND_SET_BYTE(handle, addr, val) \ 528 ddi_put8((handle), (uint8_t *)(addr), \ 529 (ddi_get8((handle), (uint8_t *)(addr)) & (uint8_t)(val))); 530 531#define AND_SET_SHORT(handle, addr, val) \ 532 ddi_put16((handle), (uint16_t *)(addr), \ 533 (ddi_get16((handle), (uint16_t *)(addr)) & (uint16_t)(val))); 534 535#define AND_SET_WORD(handle, addr, val) \ 536 ddi_put32((handle), (uint32_t *)(addr), \ 537 (ddi_get32((handle), (uint32_t *)(addr)) & (uint32_t)(val))); 538 539#endif /* _AUDIOTS_H */ 540