audiopci.h revision 9484:fbd5ddc28e96
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25/* 26 * Purpose: Definitions for the Creative/Ensoniq AudioPCI97 driver. 27 */ 28/* 29 * This file is part of Open Sound System 30 * 31 * Copyright (C) 4Front Technologies 1996-2008. 32 * 33 * This software is released under CDDL 1.0 source license. 34 * See the COPYING file included in the main directory of this source 35 * distribution for the license terms and conditions. 36 */ 37 38#ifndef _AUDIOPCI_H 39#define _AUDIOPCI_H 40 41/* CONCERT PCI-SIG defines */ 42#define CONC_PCI_VENDID 0x1274U 43#define CONC_PCI_DEVID 0x5000U 44 45/* used for the development board only!! */ 46#define CONC_DEV_PCI_VENDID 0x1274U 47#define CONC_DEV_PCI_DEVID 0x5000U 48 49 50/* 51 * CONCERT Registers 52 */ 53 54#define DAC_CLOCK_DIVIDE 22579200UL /* DAC2 (CODEC) clock divide */ 55 56/* Concert direct register offset defines */ 57 58#define CONC_bDEVCTL_OFF 0x00 /* Device control/enable */ 59#define CONC_bMISCCTL_OFF 0x01 /* Miscellaneous control */ 60#define CONC_wDACRATE_OFF 0x02 /* CODEC clock divider for PLL */ 61#define CONC_dSTATUS_OFF 0x04 /* long status register */ 62#define CONC_bCODECSTAT_OFF 0x05 /* CODEC interface status */ 63#define CONC_bUARTDATA_OFF 0x08 /* UART data R/W - read clears RX int */ 64#define CONC_bUARTCSTAT_OFF 0x09 /* UART control and status */ 65#define CONC_bMEMPAGE_OFF 0x0c /* Memory page select */ 66#define CONC_wCODECCTL_OFF 0x10 /* CODEC control - word-write-only */ 67#define CONC_wNMISTAT_OFF 0x18 /* Legacy NMI status */ 68#define CONC_bNMIENA_OFF 0x1a /* Legacy NMI enable */ 69#define CONC_bNMICTL_OFF 0x1b /* Legacy control */ 70#define CONC_bSERFMT_OFF 0x20 /* Serial device control */ 71#define CONC_bSERCTL_OFF 0x21 /* Serial device format */ 72#define CONC_bSKIPC_OFF 0x22 /* Skip counts for DAC (wave) */ 73#define CONC_wSYNIC_OFF 0x24 /* Synth int count in sample frames */ 74#define CONC_wSYNCIC_OFF 0x26 /* Synth current int count */ 75#define CONC_wDACIC_OFF 0x28 /* DAC int count in sample frames */ 76#define CONC_wDACCIC_OFF 0x2a /* DAC current int count */ 77#define CONC_wADCIC_OFF 0x2c /* ADC int count in sample frames */ 78#define CONC_wADCCIC_OFF 0x2e /* ADC current int count */ 79#define CONC_MEMBASE_OFF 0x30 /* Memory window base - 16 bytes */ 80 81/* Device Control defines */ 82#define CONC_DEVCTL_SERR_DIS 0x01 /* internal PCI serr bus enable */ 83#define CONC_DEVCTL_CODEC_EN 0x02 /* CoDec Enable */ 84#define CONC_DEVCTL_JSTICK_EN 0x04 /* Joystick Enable */ 85#define CONC_DEVCTL_UART_EN 0x08 /* UART Enable */ 86#define CONC_DEVCTL_ADC_EN 0x10 /* ADC Enable (record) */ 87#define CONC_DEVCTL_DAC_EN 0x20 /* DAC Enable (playback) */ 88#define CONC_DEVCTL_SYN_EN 0x40 /* Synth Enable */ 89#define CONC_DEVCTL_MICBIAS 0x4000L /* mic bias switch */ 90 91/* Misc Control defines */ 92#define CONC_MISCCTL_MUTE 0x01 /* XTL0 wired to mute */ 93#define CONC_MISCCTL_CCB_INTRM 0x04 /* CCB interrupt mask */ 94#define CONC_MISCCTL_SYN_5KHZ 0x00 /* synth: 5512 Hz */ 95#define CONC_MISCCTL_SYN_11KHZ 0x10 /* synth: 11025 Hz */ 96#define CONC_MISCCTL_SYN_22KHZ 0x20 /* synth: 22050 Hz */ 97#define CONC_MISCCTL_SYN_44KHZ 0x30 /* synth: 44100 Hz */ 98 99/* Interrupt Status defines */ 100#define CONC_INTSTAT_ADCINT 0x01 /* A/D interrupt pending bit */ 101#define CONC_INTSTAT_DACINT 0x02 /* DAC interrupt pending bit */ 102#define CONC_INTSTAT_SYNINT 0x04 /* synth interrupt pending bit */ 103#define CONC_INTSTAT_UARTINT 0x08 /* UART interrupt pending bit */ 104#define CONC_INTSTAT_PENDING 0x80000000 105 /* this bit set high while'st we have an interrupt */ 106 107/* Codec Status defines */ 108#define CONC_CSTAT_CSTAT 0x4 109#define CONC_CSTAT_CBUSY 0x2 110#define CONC_CSTAT_CWRIP 0x1 111 112/* SERFMT PCM format defines */ 113#define CONC_PCM_SYN_STEREO 0x01 114#define CONC_PCM_SYN_16BIT 0x02 115#define CONC_PCM_DAC_STEREO 0x04 116#define CONC_PCM_DAC_16BIT 0x08 117#define CONC_PCM_ADC_STEREO 0x10 118#define CONC_PCM_ADC_16BIT 0x20 119 120/* Serial Control defines */ 121#define CONC_SERCTL_SYNIE 0x01 /* synth int enable */ 122#define CONC_SERCTL_DACIE 0x02 /* playback interrupt enable */ 123#define CONC_SERCTL_ADCIE 0x04 /* record interrupt enable */ 124#define CONC_SERCTL_SYNPAUSE 0x10 /* playback pause */ 125 126/* Concert memory page-banked register offset defines */ 127#define CONC_dSYNPADDR_OFF 0x30 /* Synth host frame PCI phys addr */ 128#define CONC_wSYNFC_OFF 0x34 /* Synth host frame count in DWORDS */ 129#define CONC_wSYNCFC_OFF 0x36 /* Synth host current frame count */ 130#define CONC_dDACPADDR_OFF 0x38 /* DAC host frame PCI phys addr */ 131#define CONC_wDACFC_OFF 0x3c /* DAC host frame count in DWORDS */ 132#define CONC_wDACCFC_OFF 0x3e /* DAC host current frame count */ 133#define CONC_dADCPADDR_OFF 0x30 /* ADC host frame PCI phys addr */ 134#define CONC_wADCFC_OFF 0x34 /* ADC host frame count in DWORDS */ 135#define CONC_wADCCFC_OFF 0x36 /* ADC host current frame count */ 136 137/* Concert memory page number defines */ 138#define CONC_SYNRAM_PAGE 0x00 /* Synth host/serial I/F RAM */ 139#define CONC_DACRAM_PAGE 0x04 /* DAC host/serial I/F RAM */ 140#define CONC_ADCRAM_PAGE 0x08 /* ADC host/serial I/F RAM */ 141#define CONC_SYNCTL_PAGE 0x0c /* Page bank for synth host control */ 142#define CONC_DACCTL_PAGE 0x0c /* Page bank for DAC host control */ 143#define CONC_ADCCTL_PAGE 0x0d /* Page bank for ADC host control */ 144#define CONC_FIFO0_PAGE 0x0e /* page 0 of UART "FIFO" (rx stash) */ 145#define CONC_FIFO1_PAGE 0x0f /* page 1 of UART "FIFO" (rx stash) */ 146 147/* UARTCSTAT register masks */ 148#define CONC_UART_RXRDY 0x01 149#define CONC_UART_TXRDY 0x02 150#define CONC_UART_TXINT 0x04 151#define CONC_UART_RXINT 0x80 152 153#define CONC_UART_CTL 0x03 154#define CONC_UART_TXINTEN 0x20 155#define CONC_UART_RXINTEN 0x80 156 157/* 158 * CODEC register map 159 */ 160#define NUMREGS 32 /* total number of registers */ 161#define NUMVOLS 16 /* number of vol regs */ 162 163/* Source and output volume control defines */ 164#define CODEC_VOL_MASTER_L 0x00U /* Master out, left */ 165#define CODEC_VOL_MASTER_R 0x01U /* Master out, right */ 166#define CODEC_VOL_WAVE_L 0x02U /* Wave DAC, left */ 167#define CODEC_VOL_WAVE_R 0x03U /* Wave DAC, right */ 168#define CODEC_VOL_SYNTH_L 0x04U /* Synth DAC, left */ 169#define CODEC_VOL_SYNTH_R 0x05U /* Synth DAC, right */ 170#define CODEC_VOL_CD_L 0x06U /* CD audio, left */ 171#define CODEC_VOL_CD_R 0x07U /* CD audio, right */ 172#define CODEC_VOL_AUX_L 0x08U /* Aux line source, left */ 173#define CODEC_VOL_AUX_R 0x09U /* Aux line source, right */ 174#define CODEC_VOL_TV_L 0x0aU /* TV Tuner, left */ 175#define CODEC_VOL_TV_R 0x0bU /* TV Tuner, right */ 176#define CODEC_VOL_TAD 0x0cU /* TAD monitor, mono */ 177#define CODEC_VOL_MONO2 0x0dU /* Unused MONO2 */ 178#define CODEC_VOL_MIC 0x0eU /* Mic, mono */ 179#define CODEC_VOL_MONO 0x0fU /* Mono out volume */ 180 181/* Input bus enable defines -SW1 */ 182#define CODEC_IN_ENABLE_MIC 0x01U /* Mic enable, mono */ 183#define CODEC_IN_ENABLE_CD_R 0x02U /* CD audio enable, right */ 184#define CODEC_IN_ENABLE_CD_L 0x04U /* CD audio enable, left */ 185#define CODEC_IN_ENABLE_AUX_R 0x08U /* Aux line source enable, right */ 186#define CODEC_IN_ENABLE_AUX_L 0x10U /* Aux line source enable, left */ 187#define CODEC_IN_ENABLE_SYNTH_R 0x20U /* Synth DAC enable, right */ 188#define CODEC_IN_ENABLE_SYNTH_L 0x40U /* Synth DAC enable, left */ 189 190/* Input bus enable defines - SW2 */ 191#define CODEC_IN_ENABLE_TAD 0x01U /* TAD monitor enable, mono */ 192#define CODEC_IN_ENABLE_MONO2 0x02U /* Unused MONO2 enable, mono */ 193#define CODEC_IN_ENABLE_WAVE 0x04U /* Wave DAC enable */ 194#define CODEC_IN_ENABLE_TV_R 0x08U /* TV Tuner enable, right */ 195#define CODEC_IN_ENABLE_TV_L 0x10U /* TV Tuner enable, left */ 196#define CODEC_IN_ENABLE_TMONO2 0x20U /* unboosted MONO2 */ 197#define CODEC_IN_ENABLE_TMONO1 0x40U /* unboosted MONO1 */ 198#define CODEC_IN_ENABLE_TMIC 0x80U /* unboosted MONO3 (mic) */ 199 200/* Output bus enable defines - SW1 */ 201#define CODEC_OUT_ENABLE_MIC 0x01U /* Mic enable, mono */ 202#define CODEC_OUT_ENABLE_CD 0x06U /* CD audio enable, stereo */ 203#define CODEC_OUT_ENABLE_AUX 0x18U /* Aux line source enable, stereo */ 204#define CODEC_OUT_ENABLE_SYNTH 0x60U /* Synth DAC enable, stereo */ 205 206/* Output bus enable defines - SW2 */ 207#define CODEC_OUT_ENABLE_TAD 0x01U /* TAD monitor enable, mono */ 208#define CODEC_OUT_ENABLE_MONO2 0x02U /* Unused MONO2 enable, mono */ 209#define CODEC_OUT_ENABLE_WAVE 0x0cU /* Wave DAC enable, stereo */ 210#define CODEC_OUT_ENABLE_TV 0x30U /* TV Tuner enable, stereo */ 211 212/* Volume setting constants */ 213#define CODEC_ATT_MUTE 0x80U 214#define CODEC_ATT_MAX 0x1fU 215#define CODEC_ATT_MONO 0x07U 216 217/* Control function defines */ 218#define CODEC_CTL_4SPKR 0x00U /* 4-spkr output mode enable */ 219#define CODEC_CTL_MICBOOST 0x01U /* Mic boost (+30 dB) enable */ 220 221/* Miscellaneous CODEC defines for internal use */ 222#define CODEC_OUT_SW1 0x10U 223#define CODEC_OUT_SW2 0x11U 224#define CODEC_LIN_SW1 0x12U 225#define CODEC_RIN_SW1 0x13U 226#define CODEC_LIN_SW2 0x14U 227#define CODEC_RIN_SW2 0x15U 228#define CODEC_RESET_PWRD 0x16U 229#define CODEC_CLKSELECT 0x17U 230#define CODEC_ADSELECT 0x18U 231#define CODEC_MICBOOST 0x19U 232 233#endif /* _AUDIOPCI_H */ 234