audioixp.h revision 9484:fbd5ddc28e96 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef	_AUDIOIXP_H_
27#define	_AUDIOIXP_H_
28
29/*
30 * Header file for the audioixp device driver
31 */
32
33#define	IXP_DEV_CONFIG		"onboard1"
34#define	IXP_DEV_VERSION		"a"
35
36/*
37 * Driver supported configuration information
38 */
39#define	IXP_NAME		"audioixp"
40#define	IXP_MOD_NAME		"ATI IXP audio driver"
41#define	IXP_CONFIG_REGS		(0)	/* PCI configure register */
42#define	IXP_IO_AM_REGS		(1)	/* PCI base register 0x10 */
43
44#define	IXP_PLAY		0
45#define	IXP_REC			1
46
47#define	IXP_ROUNDUP(x, algn)		(((x) + ((algn) - 1)) & ~((algn) - 1))
48#define	IXP_KIOP(X)			((kstat_intr_t *)(X->ksp->ks_data))
49
50#define	IXP_BD_NUMS			(8)
51#define	IXP_MOD_SIZE			(32)
52
53
54/*
55 * PCI configuration registers and bits
56 */
57#define	IXP_PCI_ID_200		(0x10024341U)
58#define	IXP_PCI_ID_300		(0x10024361U)
59#define	IXP_PCI_ID_400		(0x10024370U)
60#define	IXP_PCI_ID_SB600	(0x10024382U)
61
62/*
63 * Audio controller registers and bits
64 */
65#define	IXP_AUDIO_INT				(0x00)
66#define	IXP_AUDIO_INT_IN_DMA_OVERFLOW		(1U<<0)
67#define	IXP_AUDIO_INT_IN_DMA			(1U<<1)
68#define	IXP_AUDIO_INT_OUT_DMA_UNDERFLOW		(1U<<2)
69#define	IXP_AUDIO_INT_OUT_DMA			(1U<<3)
70#define	IXP_AUDIO_INT_CODEC0_NOT_READY		(1U<<10)
71#define	IXP_AUDIO_INT_CODEC1_NOT_READY		(1U<<11)
72#define	IXP_AUDIO_INT_CODEC2_NOT_READY		(1U<<12)
73#define	IXP_AUDIO_INT_NEW_FRAME			(1U<<13)
74
75#define	IXP_AUDIO_INT_EN			(0x04)
76#define	IXP_AUDIO_INT_EN_IN_DMA_OVERFLOW	(1U<<0)
77#define	IXP_AUDIO_INT_EN_STATUS			(1U<<1)
78#define	IXP_AUDIO_INT_EN_OUT_DMA_UNDERFLOW	(1U<<2)
79#define	IXP_AUDIO_INT_EN_CODEC0_NOT_READY	(1U<<10)
80#define	IXP_AUDIO_INT_EN_CODEC1_NOT_READY	(1U<<11)
81#define	IXP_AUDIO_INT_EN_CODEC2_NOT_READY	(1U<<12)
82#define	IXP_AUDIO_INT_EN_NEW_FRAME		(1U<<13)
83
84#define	IXP_AUDIO_CMD				(0x08)
85#define	IXP_AUDIO_CMD_POWER_DOWN		(1U<<0)
86#define	IXP_AUDIO_CMD_EN_IN			(1U<<1)
87#define	IXP_AUDIO_CMD_EN_OUT			(1U<<2)
88#define	IXP_AUDIO_CMD_EN_IN_DMA			(1U<<8)
89#define	IXP_AUDIO_CMD_EN_OUT_DMA		(1U<<9)
90#define	IXP_AUDIO_CMD_INTER_IN			(1U<<21)
91#define	IXP_AUDIO_CMD_INTER_OUT			(1U<<22)
92#define	IXP_AUDIO_CMD_BURST_EN			(1U<<25)
93#define	IXP_AUDIO_CMD_AC_ACTIVE			(1U<<28)
94#define	IXP_AUDIO_CMD_AC_SOFT_RESET		(1U<<29)
95#define	IXP_AUDIO_CMD_AC_SYNC			(1U<<30)
96#define	IXP_AUDIO_CMD_AC_RESET			(1U<<31)
97
98#define	IXP_AUDIO_OUT_PHY_ADDR_DATA		(0x0c)
99#define	IXP_AUDIO_OUT_PHY_PRIMARY_CODEC	(0u)
100#define	IXP_AUDIO_OUT_PHY_SECOND_CODEC	(1u)
101#define	IXP_AUDIO_OUT_PHY_THIRD_CODEC	(2u)
102#define	IXP_AUDIO_OUT_PHY_READ		(1u<<2)
103#define	IXP_AUDIO_OUT_PHY_WRITE		(0u)
104#define	IXP_AUDIO_OUT_PHY_EN			(1u<<8)
105#define	IXP_AUDIO_OUT_PHY_ADDR_SHIFT		(9)
106#define	IXP_AUDIO_OUT_PHY_ADDR_MASK		(0x7fu<<9)
107#define	IXP_AUDIO_OUT_PHY_DATA_SHIFT		(16)
108#define	IXP_AUDIO_OUT_PHY_DATA_MASK		(0xffffu<<16)
109
110#define	IXP_AUDIO_IN_PHY_ADDR_DATA		(0x10)
111#define	IXP_AUDIO_IN_PHY_READY			(1u<<8)
112#define	IXP_AUDIO_IN_PHY_ADDR_SHIFT		(9)
113#define	IXP_AUDIO_IN_PHY_ADDR_MASK		(0x7fu<<9)
114#define	IXP_AUDIO_IN_PHY_DATA_SHIFT		(16)
115#define	IXP_AUDIO_IN_PHY_DATA_MASK		(0xffffu<<16)
116
117#define	IXP_AUDIO_SLOTREQ			(0x14)
118#define	IXP_AUDIO_COUNTER			(0x18)
119#define	IXP_AUDIO_IN_FIFO_THRESHOLD		(0x1c)
120#define	IXP_AUDIO_IN_DMA_LINK_P			(0x20)
121#define	IXP_AUDIO_IN_DMA_LINK_P_EN		(1u<<0)
122
123#define	IXP_AUDIO_IN_DMA_DT_START		(0x24)
124#define	IXP_AUDIO_IN_DMA_DT_NEXT		(0x28)
125#define	IXP_AUDIO_IN_DMA_DT_CUR			(0x2c)
126#define	IXP_AUDIO_IN_DT_SIZE_FIFO_INFO		(0x30)
127
128#define	IXP_AUDIO_OUT_DMA_SLOT_EN_THRESHOLD	(0x34)
129#define	IXP_AUDIO_OUT_DMA_SLOT_3		(1U<<0)
130#define	IXP_AUDIO_OUT_DMA_SLOT_4		(1U<<1)
131#define	IXP_AUDIO_OUT_DMA_SLOT_5		(1U<<2)
132#define	IXP_AUDIO_OUT_DMA_SLOT_6		(1U<<3)
133#define	IXP_AUDIO_OUT_DMA_SLOT_7		(1U<<4)
134#define	IXP_AUDIO_OUT_DMA_SLOT_8		(1U<<5)
135#define	IXP_AUDIO_OUT_DMA_SLOT_9		(1U<<6)
136#define	IXP_AUDIO_OUT_DMA_SLOT_10		(1U<<7)
137#define	IXP_AUDIO_OUT_DMA_SLOT_11		(1U<<8)
138#define	IXP_AUDIO_OUT_DMA_SLOT_12		(1U<<9)
139#define	IXP_AUDIO_OUT_DMA_THRESHOLD_MASK	(0x7fU<<11)
140#define	IXP_AUDIO_OUT_DMA_THRESHOLD_SHIFT	(11)
141
142#define	IXP_AUDIO_OUT_DMA_LINK_P		(0x38)
143#define	IXP_AUDIO_OUT_DMA_LINK_P_EN		(1U<<0)
144
145#define	IXP_AUDIO_OUT_DMA_DT_START		(0x3c)
146#define	IXP_AUDIO_OUT_DMA_DT_NEXT		(0x40)
147#define	IXP_AUDIO_OUT_DMA_DT_CUR		(0x44)
148#define	IXP_AUDIO_OUT_DT_SIZE_USED_FREE		(0x48)
149#define	IXP_AUDIO_SPDIF_CMD			(0x4c)
150#define	IXP_AUDIO_SPDIF_LINK_P			(0x50)
151#define	IXP_AUDIO_SPDIF_DT_START		(0x54)
152#define	IXP_AUDIO_SPDIF_DT_NEXT			(0x58)
153#define	IXP_AUDIO_SPDIF_DT_CUR			(0x5c)
154#define	IXP_AUDIO_SPDIF_DT_SIZE_FIFO_INFO	(0x60)
155#define	IXP_AUDIO_MODEM_MIRROR			(0x7c)
156#define	IXP_AUDIO_AUDIO_MIRROR			(0x80)
157#define	IXP_AUDIO_6CH_RECORDER_EN		(0x84)
158#define	IXP_AUDIO_FIFO_FLUSH		(0x88)
159#define	IXP_AUDIO_FIFO_FLUSH_OUT		(1u<<0)
160#define	IXP_AUDIO_FIFO_FLUSH_IN			(1u<<1)
161
162#define	IXP_AUDIO_OUT_FIFO_INFO		(0x8c)
163#define	IXP_AUDIO_SPDIF_STATUS_BITS_REG1	(0x90)
164#define	IXP_AUDIO_SPDIF_STATUS_BITS_REG2	(0x94)
165#define	IXP_AUDIO_SPDIF_STATUS_BITS_REG3	(0x98)
166#define	IXP_AUDIO_SPDIF_STATUS_BITS_REG4	(0x9c)
167#define	IXP_AUDIO_SPDIF_STATUS_BITS_REG5	(0xa0)
168#define	IXP_AUDIO_SPDIF_STATUS_BITS_REG6	(0xa4)
169#define	IXP_AUDIO_PHY_SEMA			(0xa8)
170
171/*
172 * AC97 status and link control registers are located
173 * in PCI configuration space.
174 */
175#define	IXP_REG_GSR				0x40
176#define	IXP_REG_GCR				0x41
177
178/* AC link interface status register */
179#define	IXP_GSR_PRI_READY			0x01
180#define	IXP_GSR_SEC_READY			0x04
181#define	IXP_GSR_TRI_READY			0x10
182#define	IXP_GSR_FOUR_READY			0x20
183
184/* AC link interface control register */
185#define	IXP_GCR_ENAC97				0x80
186#define	IXP_GCR_RST				0x40
187#define	IXP_GCR_RSYNCHI				0x20
188#define	IXP_GCR_SDO				0x10
189#define	IXP_GCR_VSR				0x08
190#define	IXP_GCR_3D_AUDIO_CHANNEL		0x04
191
192/*
193 * Macro for AD1980 codec
194 */
195#define	AD1980_VID1		0x4144
196#define	AD1980_VID2		0x5370
197#define	AD1985_VID2		0x5375
198#define	CODEC_AD_REG_MISC	0x76	/* offset of ad1980 misc control reg */
199#define	AD1980_MISC_LOSEL	0x0020	/* Line-out amplifier output selector */
200#define	AD1980_MISC_HPSEL	0x0400	/* HP-out amplifier output selector */
201
202struct audioixp_port {
203	int			num;
204	struct audioixp_state	*statep;
205	ddi_dma_handle_t	samp_dmah;
206	ddi_acc_handle_t	samp_acch;
207	size_t			samp_size;
208	caddr_t			samp_kaddr;
209	uint32_t		samp_paddr;
210
211	ddi_dma_handle_t	bdl_dmah;
212	ddi_acc_handle_t	bdl_acch;
213	size_t			bdl_size;
214	caddr_t			bdl_kaddr;
215	uint32_t		bdl_paddr;
216
217	unsigned		intrs;
218	unsigned		fragfr;
219	unsigned		fragsz;
220	uint64_t		count;
221	uint32_t		offset;
222	uint8_t			nchan;
223
224	unsigned		sync_dir;
225
226	boolean_t		started;
227
228	audio_engine_t		*engine;
229};
230typedef struct audioixp_port audioixp_port_t;
231
232/*
233 * buffer descriptor list entry, see datasheet
234 */
235struct audioixp_bd_entry {
236	uint32_t	buf_base;	/* the address of the buffer */
237	uint16_t	status;		/* status of the buffer */
238	uint16_t	buf_len;	/* size of the buffer in DWORD */
239	uint32_t	next;		/* physical addr of next bd_entry */
240};
241typedef struct	audioixp_bd_entry	audioixp_bd_entry_t;
242
243/*
244 * audioixp_state_t	-per instance state and operation data
245 */
246struct audioixp_state {
247	kmutex_t		inst_lock;	/* state protection lock */
248	ddi_iblock_cookie_t	iblock;
249	dev_info_t		*dip;
250	audio_dev_t		*adev;		/* audio handle */
251	ac97_t			*ac97;
252	audioixp_port_t		*play_port;
253	audioixp_port_t		*rec_port;
254
255	ddi_acc_handle_t	pcih;		/* pci configuration space */
256	ddi_acc_handle_t	regsh;		/* for audio mixer register */
257	caddr_t			regsp;		/* base of audio mixer regs */
258
259	boolean_t		suspended;
260	boolean_t		intr_added;
261	boolean_t		swap_out;	/* swap line-out and sur-out */
262
263	kstat_t			*ksp;		/* kernel statistics */
264
265	uint32_t		ixp_codec_not_ready_bits; /* for codec detect */
266};
267typedef struct audioixp_state	 audioixp_state_t;
268
269/*
270 * Useful bit twiddlers
271 */
272#define	GET32(reg)	\
273	ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
274
275#define	PUT32(reg, val)	\
276	ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val))
277
278#define	SET32(reg, val)	PUT32(reg, GET32(reg) | ((uint32_t)(val)))
279
280#define	CLR32(reg, val)	PUT32(reg, GET32(reg) & ~((uint32_t)(val)))
281
282#define	IXP_INTS		(175)	/* default interrupt rate */
283#define	IXP_MIN_INTS		(24)	/* minimum interrupt rate */
284#define	IXP_MAX_INTS		(500)	/* maximum interrupt rate */
285
286#endif /* _AUDIOIXP_H_ */
287