audiohd.h revision 11942:7c085d34b43f
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25#ifndef _SYS_AUDIOHD_IMPL_H_ 26#define _SYS_AUDIOHD_IMPL_H_ 27 28#ifdef __cplusplus 29extern "C" { 30#endif 31 32/* 33 * vendor IDs of PCI audio controllers 34 */ 35#define AUDIOHD_VID_ATI 0x1002 36#define AUDIOHD_VID_CIRRUS 0x1013 37#define AUDIOHD_VID_NVIDIA 0x10de 38#define AUDIOHD_VID_REALTEK 0x10ec 39#define AUDIOHD_VID_CREATIVE 0x1102 40#define AUDIOHD_VID_IDT 0x111d 41#define AUDIOHD_VID_ANALOG 0x11d4 42#define AUDIOHD_VID_CONEXANT 0x14f1 43#define AUDIOHD_VID_SIGMATEL 0x8384 44#define AUDIOHD_VID_INTEL 0x8086 45 46/* 47 * specific audiohd controller device id 48 */ 49#define AUDIOHD_CONTROLLER_MCP51 0x10de026c 50 51/* 52 * codec special initial flags 53 */ 54#define NO_GPIO 0x00000001 55#define NO_MIXER 0x00000002 56#define NO_SPDIF 0x00000004 57#define EN_PIN_BEEP 0x00000008 58 59#define AUDIOHD_DEV_CONFIG "onboard1" 60#define AUDIOHD_DEV_VERSION "a" 61 62#define AUDIOHD_FMT_PCM 0x001 63/* 64 * Only for Intel hardware: 65 * PCI Express traffic class select register in PCI configure space 66 */ 67#define AUDIOHD_INTEL_PCI_TCSEL 0x44 68 69/* 70 * Only for ATI SB450: 71 * MISC control register 2 72 */ 73#define AUDIOHD_ATI_PCI_MISC2 0x42 74#define AUDIOHD_ATI_MISC2_SNOOP 0x02 75#define AUDIOHDC_NID(x) x 76#define AUDIOHDC_NULL_NODE -1 77#define AUDIOHD_NULL_CONN ((uint_t)(-1)) 78/* 79 * currently, only the format of 48K sample rate, 16-bit 80 * 2-channel is supported. 81 */ 82#define AUDIOHD_FMT_PCMOUT 0x0011 83#define AUDIOHD_FMT_PCMIN 0x0011 84 85#define AUDIOHD_EXT_AMP_MASK 0x00010000 86#define AUDIOHD_EXT_AMP_ENABLE 0x02 87/* NVIDIA snoop */ 88#define AUDIOHD_NVIDIA_SNOOP 0x0f 89 90/* Power On/Off */ 91#define AUDIOHD_PW_D0 0 92#define AUDIOHD_PW_D2 2 93 94#define AUDIOHD_INTEL_TCS_MASK 0xf8 95#define AUDIOHD_ATI_MISC2_MASK 0xf8 96 97/* Pin speaker On/Off */ 98#define AUDIOHD_SP_ON 1 99#define AUDIOHD_SP_OFF 0 100 101#define AUDIOHD_PORT_MAX 15 102#define AUDIOHD_CODEC_MAX 16 103#define AUDIOHD_MEMIO_LEN 0x4000 104 105#define AUDIOHD_RETRY_TIMES 60 106#define AUDIOHD_TEST_TIMES 500 107#define AUDIOHD_OUTSTR_NUM_OFF 12 108#define AUDIOHD_INSTR_NUM_OFF 8 109 110#define AUDIOHD_CORB_SIZE_OFF 0x4e 111 112#define AUDIOHD_URCAP_MASK 0x80 113#define AUDIOHD_DTCCAP_MASK 0x4 114#define AUDIOHD_UR_ENABLE_OFF 8 115#define AUDIOHD_UR_TAG_MASK 0x1f 116 117#define AUDIOHD_CIS_MASK 0x40000000 118 119#define AUDIOHD_RIRB_UR_MASK 0x10 120#define AUDIOHD_RIRB_CODEC_MASK 0xf 121#define AUDIOHD_RIRB_WID_OFF 27 122#define AUDIOHD_RIRB_INTRCNT 0x0 123#define AUDIOHD_RIRB_WPMASK 0xff 124 125#define AUDIOHD_FORM_MASK 0x0080 126#define AUDIOHD_LEN_MASK 0x007f 127#define AUDIOHD_PIN_CAP_MASK 0x00000010 128#define AUDIOHD_PIN_CONF_MASK 0xc0000000 129#define AUDIOHD_PIN_CON_MASK 3 130#define AUDIOHD_PIN_CON_STEP 30 131#define AUDIOHD_PIN_IO_MASK 0X0018 132#define AUDIOHD_PIN_SEQ_MASK 0x0000000f 133#define AUDIOHD_PIN_ASO_MASK 0x000000f0 134#define AUDIOHD_PIN_ASO_OFF 0x4 135#define AUDIOHD_PIN_DEV_MASK 0x00f00000 136#define AUDIOHD_PIN_DEV_OFF 20 137#define AUDIOHD_PIN_NUMS 6 138#define AUDIOHD_PIN_NO_CONN 0x40000000 139#define AUDIOHD_PIN_IN_ENABLE 0x20 140#define AUDIOHD_PIN_OUT_ENABLE 0x40 141#define AUDIOHD_PIN_PRES_OFF 0x20 142#define AUDIOHD_PIN_CONTP_OFF 0x1e 143#define AUDIOHD_PIN_CON_JACK 0 144#define AUDIOHD_PIN_CON_FIXED 0x2 145#define AUDIOHD_PIN_CONTP_MASK 0x3 146#define AUDIOHD_PIN_VREF_L1 0x20 147#define AUDIOHD_PIN_VREF_L2 0x10 148#define AUDIOHD_PIN_VREF_L3 0x04 149#define AUDIOHD_PIN_VREF_L4 0x02 150#define AUDIOHD_PIN_VREF_OFF 8 151#define AUDIOHD_PIN_VREF_MASK 0xff 152#define AUDIOHD_PIN_CLR_MASK 0xf 153#define AUDIOHD_PIN_CLR_OFF 12 154 155 156#define AUDIOHD_VERB_ADDR_OFF 28 157#define AUDIOHD_VERB_NID_OFF 20 158#define AUDIOHD_VERB_CMD_OFF 8 159#define AUDIOHD_VERB_CMD16_OFF 16 160 161#define AUDIOHD_RING_MAX_SIZE 0x00ff 162#define AUDIOHD_REC_TAG_OFF 4 163#define AUDIOHD_PLAY_TAG_OFF 4 164#define AUDIOHD_PLAY_CTL_OFF 2 165#define AUDIOHD_REC_CTL_OFF 2 166 167#define AUDIOHD_SPDIF_ON 1 168#define AUDIOHD_SPDIF_MASK 0x00ff 169 170#define AUDIOHD_GAIN_OFF 8 171 172#define AUDIOHD_CODEC_STR_OFF 16 173#define AUDIOHD_CODEC_STR_MASK 0x000000ff 174#define AUDIOHD_CODEC_NUM_MASK 0x000000ff 175#define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 176 177#define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 178#define AUDIOHD_BDLE_BUF_ALIGN 128 179#define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 180#define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 181#define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 182#define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 183 184#define AUDIOHD_PORT_UNMUTE (0xffffffff) 185 186/* 187 * Audio registers of high definition 188 */ 189#define AUDIOHD_REG_GCAP 0x00 190#define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 191#define AUDIOHDR_GCAP_INSTREAMS 0x0f00 192#define AUDIOHDR_GCAP_BSTREAMS 0x00f8 193#define AUDIOHDR_GCAP_NSDO 0x0006 194#define AUDIOHDR_GCAP_64OK 0x0001 195 196#define AUDIOHD_REG_VMIN 0x02 197#define AUDIOHD_REG_VMAJ 0x03 198#define AUDIOHD_REG_OUTPAY 0x04 199#define AUDIOHD_REG_INPAY 0x06 200#define AUDIOHD_REG_GCTL 0x08 201#define AUDIOHD_REG_WAKEEN 0x0C 202#define AUDIOHD_REG_STATESTS 0x0E 203#define AUDIOHD_STATESTS_BIT_SDINS 0x7F 204 205#define AUDIOHD_REG_GSTS 0x10 206#define AUDIOHD_REG_INTCTL 0x20 207#define AUDIOHD_INTCTL_BIT_GIE 0x80000000 208#define AUDIOHD_INTCTL_BIT_CIE 0x40000000 209#define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 210 211 212#define AUDIOHD_REG_INTSTS 0x24 213#define AUDIOHD_INTSTS_BIT_GIS 0x80000000 214#define AUDIOHD_INTSTS_BIT_CIS 0x40000000 215#define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 216 217#define AUDIOHD_REG_WALCLK 0x30 218#define AUDIOHD_REG_SYNC 0x38 219 220#define AUDIOHD_REG_CORBLBASE 0x40 221#define AUDIOHD_REG_CORBUBASE 0x44 222#define AUDIOHD_REG_CORBWP 0x48 223#define AUDIOHD_REG_CORBRP 0x4A 224#define AUDIOHD_REG_CORBCTL 0x4C 225#define AUDIOHD_REG_CORBST 0x4D 226#define AUDIOHD_REG_CORBSIZE 0x4E 227 228#define AUDIOHD_REG_RIRBLBASE 0x50 229#define AUDIOHD_REG_RIRBUBASE 0x54 230#define AUDIOHD_REG_RIRBWP 0x58 231#define AUDIOHD_REG_RINTCNT 0x5A 232#define AUDIOHD_REG_RIRBCTL 0x5C 233#define AUDIOHD_REG_RIRBSTS 0x5D 234#define AUDIOHD_REG_RIRBSIZE 0x5E 235 236#define AUDIOHD_REG_IC 0x60 237#define AUDIOHD_REG_IR 0x64 238#define AUDIOHD_REG_IRS 0x68 239#define AUDIOHD_REG_DPLBASE 0x70 240#define AUDIOHD_REG_DPUBASE 0x74 241 242#define AUDIOHD_REG_SD_BASE 0x80 243#define AUDIOHD_REG_SD_LEN 0x20 244 245/* 246 * Offset of Stream Descriptor Registers 247 */ 248#define AUDIOHD_SDREG_OFFSET_CTL 0x00 249#define AUDIOHD_SDREG_OFFSET_STS 0x03 250#define AUDIOHD_SDREG_OFFSET_LPIB 0x04 251#define AUDIOHD_SDREG_OFFSET_CBL 0x08 252#define AUDIOHD_SDREG_OFFSET_LVI 0x0c 253#define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 254#define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 255#define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 256#define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 257#define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 258 259/* bits for stream descriptor control reg */ 260#define AUDIOHDR_SD_CTL_DEIE 0x000010 261#define AUDIOHDR_SD_CTL_FEIE 0x000008 262#define AUDIOHDR_SD_CTL_IOCE 0x000004 263#define AUDIOHDR_SD_CTL_SRUN 0x000002 264#define AUDIOHDR_SD_CTL_SRST 0x000001 265 266/* bits for stream descriptor status register */ 267#define AUDIOHDR_SD_STS_BCIS 0x0004 268#define AUDIOHDR_SD_STS_FIFOE 0x0008 269#define AUDIOHDR_SD_STS_DESE 0x0010 270#define AUDIOHDR_SD_STS_FIFORY 0x0020 271#define AUDIOHDR_SD_STS_INTRS \ 272 (AUDIOHDR_SD_STS_BCIS | \ 273 AUDIOHDR_SD_STS_FIFOE | \ 274 AUDIOHDR_SD_STS_DESE) 275 276 277/* bits for GCTL register */ 278#define AUDIOHDR_GCTL_CRST 0x00000001 279#define AUDIOHDR_GCTL_URESPE 0x00000100 280 281/* bits for CORBRP register */ 282#define AUDIOHDR_CORBRP_RESET 0x8000 283#define AUDIOHDR_CORBRP_WPTR 0x00ff 284 285/* bits for CORBCTL register */ 286#define AUDIOHDR_CORBCTL_CMEIE 0x01 287#define AUDIOHDR_CORBCTL_DMARUN 0x02 288 289/* bits for CORB SIZE register */ 290#define AUDIOHDR_CORBSZ_8 0 291#define AUDIOHDR_CORBSZ_16 1 292#define AUDIOHDR_CORBSZ_256 2 293 294/* bits for RIRBCTL register */ 295#define AUDIOHDR_RIRBCTL_RINTCTL 0x01 296#define AUDIOHDR_RIRBCTL_DMARUN 0x02 297#define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 298#define AUDIOHDR_RIRBCTL_RSTINT 0xfe 299 300/* bits for RIRBWP register */ 301#define AUDIOHDR_RIRBWP_RESET 0x8000 302#define AUDIOHDR_RIRBWP_WPTR 0x00ff 303 304/* bits for RIRB SIZE register */ 305#define AUDIOHDR_RIRBSZ_8 0 306#define AUDIOHDR_RIRBSZ_16 1 307#define AUDIOHDR_RIRBSZ_256 2 308 309#define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 310#define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 311 312/* HD spec: ID of Root node is 0 */ 313#define AUDIOHDC_NODE_ROOT 0x00 314 315/* HD spec: ID of audio function group is "1" */ 316#define AUDIOHDC_AUDIO_FUNC_GROUP 1 317 318/* 319 * HD audio verbs can be either 12-bit or 4-bit in length. 320 */ 321#define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 322#define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 323 324#define AUDIOHDC_SAMPR48000 48000 325#define AUDIOHDC_MAX_BEEP_GEN 12000 326#define AUDIOHDC_MIX_BEEP_GEN 47 327#define AUDIOHDC_MUTE_BEEP_GEN 0x0 328 329/* 330 * 12-bit verbs 331 */ 332#define AUDIOHDC_VERB_GET_PARAM 0xf00 333 334#define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 335#define AUDIOHDC_VERB_SET_CONN_SEL 0x701 336 337#define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 338#define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 339#define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 340 341#define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 342#define AUDIOHDC_VERB_SET_POWER_STATE 0x705 343 344#define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 345#define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 346 347#define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 348#define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 349 350#define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 351 352#define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 353#define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 354 355#define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 356#define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 357 358#define AUDIOHDC_VERB_GET_EAPD 0xf0c 359#define AUDIOHDC_VERB_SET_EAPD 0x70c 360 361#define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 362#define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 363#define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 364 365#define AUDIOHDC_VERB_SET_URCTRL 0x708 366#define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 367 368#define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 369#define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 370 371#define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 372#define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 373 374#define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 375#define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 376 377#define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 378#define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 379 380#define AUDIOHDC_GPIO_ENABLE 0xff 381#define AUDIOHDC_GPIO_DIRECT 0xf1 382 383#define AUDIOHDC_GPIO_DATA_CTRL 0xff 384#define AUDIOHDC_GPIO_STCK_CTRL 0xff 385/* 386 * 4-bit verbs 387 */ 388#define AUDIOHDC_VERB_GET_CONV_FMT 0xa 389#define AUDIOHDC_VERB_SET_CONV_FMT 0x2 390 391#define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 392#define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 393#define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 394 395/* 396 * parameters of nodes 397 */ 398#define AUDIOHDC_PAR_VENDOR_ID 0x00 399#define AUDIOHDC_PAR_SUBSYS_ID 0x01 400#define AUDIOHDC_PAR_REV_ID 0x02 401#define AUDIOHDC_PAR_NODE_COUNT 0x04 402#define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 403#define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 404#define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 405#define AUDIOHDC_PAR_PCM 0x0a 406#define AUDIOHDC_PAR_STREAM 0x0b 407#define AUDIOHDC_PAR_PIN_CAP 0x0c 408#define AUDIOHDC_PAR_INAMP_CAP 0x0d 409#define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 410#define AUDIOHDC_PAR_POWER_STATE 0x0f 411#define AUDIOHDC_PAR_PROC_CAP 0x10 412#define AUDIOHDC_PAR_GPIO_CAP 0x11 413#define AUDIOHDC_PAR_OUTAMP_CAP 0x12 414 415/* 416 * bits for get/set amplifier gain/mute 417 */ 418#define AUDIOHDC_AMP_SET_OUTPUT 0x8000 419#define AUDIOHDC_AMP_SET_INPUT 0x4000 420#define AUDIOHDC_AMP_SET_LEFT 0x2000 421#define AUDIOHDC_AMP_SET_RIGHT 0x1000 422#define AUDIOHDC_AMP_SET_MUTE 0x0080 423#define AUDIOHDC_AMP_SET_LNR 0x3000 424#define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 425#define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 426#define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 427#define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 428#define AUDIOHDC_GAIN_MAX 0x7f 429#define AUDIOHDC_GAIN_BITS 7 430#define AUDIOHDC_GAIN_DEFAULT 0x0f 431 432#define AUDIOHDC_AMP_GET_OUTPUT 0x8000 433#define AUDIOHDC_AMP_GET_INPUT 0x0000 434 435/* value used to set max volume for left output */ 436#define AUDIOHDC_AMP_LOUT_MAX \ 437 (AUDIOHDC_AMP_SET_OUTPUT | \ 438 AUDIOHDC_AMP_SET_LEFT | \ 439 AUDIOHDC_GAIN_MAX) 440 441/* value used to set max volume for right output */ 442#define AUDIOHDC_AMP_ROUT_MAX \ 443 (AUDIOHDC_AMP_SET_OUTPUT | \ 444 AUDIOHDC_AMP_SET_RIGHT | \ 445 AUDIOHDC_GAIN_MAX) 446 447 448/* 449 * Bits for pin widget control verb 450 */ 451#define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 452#define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 453#define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 454 455/* 456 * Bits for Amplifier capabilities 457 */ 458#define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 459#define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 460#define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 461#define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 462 463 464/* 465 * Bits for Audio Widget Capabilities 466 */ 467#define AUDIOHD_WIDCAP_STEREO 0x00000001 468#define AUDIOHD_WIDCAP_INAMP 0x00000002 469#define AUDIOHD_WIDCAP_OUTAMP 0x00000004 470#define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 471#define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 472#define AUDIOHD_WIDCAP_STRIP 0x00000020 473#define AUDIOHD_WIDCAP_PROC_WID 0x00000040 474#define AUDIOHD_WIDCAP_UNSOL 0x00000080 475#define AUDIOHD_WIDCAP_CONNLIST 0x00000100 476#define AUDIOHD_WIDCAP_DIGIT 0x00000200 477#define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 478#define AUDIOHD_WIDCAP_LRSWAP 0x00000800 479#define AUDIOHD_WIDCAP_TYPE 0x00f00000 480#define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 481 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 482 483 484#define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 485 486/* 487 * buffer descriptor list entry of stream descriptor 488 */ 489typedef struct { 490 uint64_t sbde_addr; 491 uint32_t sbde_len; 492 uint32_t 493 sbde_ioc: 1, 494 reserved: 31; 495}sd_bdle_t; 496 497 498#define AUDIOHD_PLAY_STARTED 0x00000001 499#define AUDIOHD_PLAY_EMPTY 0x00000002 500#define AUDIOHD_PLAY_PAUSED 0x00000004 501#define AUDIOHD_RECORD_STARTED 0x00000008 502 503enum audiohda_widget_type { 504 WTYPE_AUDIO_OUT = 0, 505 WTYPE_AUDIO_IN, 506 WTYPE_AUDIO_MIX, 507 WTYPE_AUDIO_SEL, 508 WTYPE_PIN, 509 WTYPE_POWER, 510 WTYPE_VOL_KNOB, 511 WTYPE_BEEP, 512 WTYPE_VENDOR = 0xf 513}; 514 515enum audiohda_device_type { 516 DTYPE_LINEOUT = 0, 517 DTYPE_SPEAKER, 518 DTYPE_HP_OUT, 519 DTYPE_CD, 520 DTYPE_SPDIF_OUT, 521 DTYPE_DIGIT_OUT, 522 DTYPE_MODEM_SIDE, 523 DTYPE_MODEM_HNAD_SIDE, 524 DTYPE_LINE_IN, 525 DTYPE_AUX, 526 DTYPE_MIC_IN, 527 DTYPE_TEL, 528 DTYPE_SPDIF_IN, 529 DTYPE_DIGIT_IN, 530 DTYPE_OTHER = 0x0f, 531}; 532 533enum audiohd_pin_color { 534 AUDIOHD_PIN_UNKNOWN = 0, 535 AUDIOHD_PIN_BLACK, 536 AUDIOHD_PIN_GREY, 537 AUDIOHD_PIN_BLUE, 538 AUDIOHD_PIN_GREEN, 539 AUDIOHD_PIN_RED, 540 AUDIOHD_PIN_ORANGE, 541 AUDIOHD_PIN_YELLOW, 542 AUDIOHD_PIN_PURPLE, 543 AUDIOHD_PIN_PINK, 544 AUDIOHD_PIN_WHITE = 0xe, 545 AUDIOHD_PIN_OTHER = 0xf, 546}; 547 548/* values for audiohd_widget.path_flags */ 549#define AUDIOHD_PATH_DAC (1 << 0) 550#define AUDIOHD_PATH_ADC (1 << 1) 551#define AUDIOHD_PATH_MON (1 << 2) 552#define AUDIOHD_PATH_NOMON (1 << 3) 553#define AUDIOHD_PATH_BEEP (1 << 4) 554 555typedef struct audiohd_path audiohd_path_t; 556typedef struct audiohd_widget audiohd_widget_t; 557typedef struct audiohd_state audiohd_state_t; 558typedef struct audiohd_codec_info audiohd_codec_info_t; 559typedef struct audiohd_pin audiohd_pin_t; 560typedef struct hda_codec hda_codec_t; 561typedef uint32_t wid_t; /* id of widget */ 562typedef struct audiohd_entry_prop audiohd_entry_prop_t; 563typedef enum audiohda_device_type audiohda_device_type_t; 564typedef enum audiohd_pin_color audiohd_pin_color_t; 565 566#define AUDIOHD_MAX_WIDGET 128 567#define AUDIOHD_MAX_CONN 16 568#define AUDIOHD_MAX_PINS 16 569#define AUDIOHD_MAX_DEPTH 8 570 571struct audiohd_entry_prop { 572 uint32_t conn_len; 573 uint32_t mask_range; 574 uint32_t mask_wid; 575 wid_t input_wid; 576 int conns_per_entry; 577 int bits_per_conn; 578}; 579struct audiohd_widget { 580 wid_t wid_wid; 581 hda_codec_t *codec; 582 enum audiohda_widget_type type; 583 584 uint32_t widget_cap; 585 uint32_t pcm_format; 586 uint32_t inamp_cap; 587 uint32_t outamp_cap; 588 589 uint32_t path_flags; 590 591 int out_weight; 592 int in_weight; 593 int finish; 594 595 /* 596 * wid of possible & selected input connections 597 */ 598 wid_t avail_conn[AUDIOHD_MAX_CONN]; 599 wid_t selconn; 600 /* 601 * for monitor path 602 */ 603 wid_t selmon[AUDIOHD_MAX_CONN]; 604 uint16_t used; 605 606 /* 607 * available (input) connections. 0 means this widget 608 * has fixed connection 609 */ 610 int nconns; 611 612 /* 613 * pointer to struct depending on widget type: 614 * 1. DAC audiohd_ostream_t 615 * 2. ADC audiohd_istream_t 616 * 3. PIN audiohd_pin_t 617 */ 618 void *priv; 619}; 620 621#define AUDIOHD_FLAG_LINEOUT (1 << 0) 622#define AUDIOHD_FLAG_SPEAKER (1 << 1) 623#define AUDIOHD_FLAG_HP (1 << 2) 624#define AUDIOHD_FLAG_MONO (1 << 3) 625 626#define AUDIOHD_MAX_MIXER 5 627#define AUDIOHD_MAX_PIN 4 628 629#define PORT_DAC 0 630#define PORT_ADC 1 631#define PORT_MAX 2 632typedef enum { 633 PLAY = 0, 634 RECORD = 1, 635 BEEP = 2, 636} path_type_t; 637 638struct audiohd_path { 639 wid_t adda_wid; 640 wid_t beep_wid; 641 642 wid_t pin_wid[AUDIOHD_MAX_PINS]; 643 int sum_selconn[AUDIOHD_MAX_PINS]; 644 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 645 int pin_nums; 646 int maxmixer[AUDIOHD_MAX_PINS]; 647 648 path_type_t path_type; 649 650 wid_t mute_wid; 651 int mute_dir; 652 wid_t gain_wid; 653 int gain_dir; 654 uint32_t gain_bits; 655 656 uint32_t pin_outputs; 657 uint8_t tag; 658 659 hda_codec_t *codec; 660 661 wid_t sum_wid; 662 663 audiohd_state_t *statep; 664}; 665 666typedef struct audiohd_port 667{ 668 uint8_t nchan; 669 int index; 670 uint16_t regoff; 671 672 unsigned nframes; 673 size_t bufsize; 674 size_t fragsize; 675 uint64_t count; 676 int curpos; 677 678 uint_t format; 679 unsigned sync_dir; 680 681 ddi_dma_handle_t samp_dmah; 682 ddi_acc_handle_t samp_acch; 683 caddr_t samp_kaddr; 684 uint64_t samp_paddr; 685 686 ddi_dma_handle_t bdl_dmah; 687 ddi_acc_handle_t bdl_acch; 688 size_t bdl_size; 689 caddr_t bdl_kaddr; 690 uint64_t bdl_paddr; 691 692 audio_engine_t *engine; 693 audiohd_state_t *statep; 694}audiohd_port_t; 695 696enum { 697 CTL_VOLUME = 0, 698 CTL_FRONT, 699 CTL_SPEAKER, 700 CTL_HEADPHONE, 701 CTL_REAR, 702 CTL_CENTER, 703 CTL_SURROUND, 704 CTL_LFE, 705 CTL_IGAIN, 706 CTL_LINEIN, 707 CTL_MIC, 708 CTL_CD, 709 CTL_MONGAIN, 710 CTL_MONSRC, 711 CTL_RECSRC, 712 CTL_BEEP, 713 714 /* this one must be last */ 715 CTL_MAX 716}; 717 718typedef struct audiohd_ctrl 719{ 720 audiohd_state_t *statep; 721 audio_ctrl_t *ctrl; 722 int num; 723 uint64_t val; 724} audiohd_ctrl_t; 725 726struct audiohd_pin { 727 audiohd_pin_t *next; 728 wid_t wid; 729 wid_t mute_wid; /* node used to mute this pin */ 730 int mute_dir; /* 1: input, 2: output */ 731 wid_t gain_wid; /* node for gain control */ 732 int gain_dir; /* _OUTPUT/_INPUT */ 733 uint32_t gain_bits; 734 735 uint8_t vrefvalue; /* value of VRef */ 736 737 uint32_t cap; 738 uint32_t config; 739 uint32_t ctrl; 740 uint32_t assoc; 741 uint32_t seq; 742 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 743 wid_t beep_wid; 744 int no_phys_conn; 745 enum audiohda_device_type device; 746 747 /* 748 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 749 * widget wid. 750 */ 751 int mg_dir[AUDIOHD_MAX_CONN]; 752 int mg_gain[AUDIOHD_MAX_CONN]; 753 int mg_wid[AUDIOHD_MAX_CONN]; 754 int num; 755 int finish; 756 757}; 758 759typedef struct { 760 ddi_dma_handle_t ad_dmahdl; 761 ddi_acc_handle_t ad_acchdl; 762 caddr_t ad_vaddr; /* virtual addr */ 763 uint64_t ad_paddr; /* physical addr */ 764 size_t ad_req_sz; /* required size of memory */ 765 size_t ad_real_sz; /* real size of memory */ 766} audiohd_dma_t; 767 768struct hda_codec { 769 uint8_t index; /* codec address */ 770 uint32_t vid; /* vendor id and device id */ 771 uint32_t revid; /* revision id */ 772 wid_t wid_afg; /* id of AFG */ 773 wid_t first_wid; /* wid of 1st subnode of AFG */ 774 wid_t last_wid; /* wid of the last subnode of AFG */ 775 int nnodes; /* # of subnodes of AFG */ 776 uint8_t nistream; 777 778 uint32_t outamp_cap; 779 uint32_t inamp_cap; 780 uint32_t stream_format; 781 uint32_t pcm_format; 782 783 audiohd_state_t *soft_statep; 784 audiohd_codec_info_t *codec_info; 785 786 /* use wid as index to the array of widget pointers */ 787 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 788 789 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 790 uint8_t portnum; 791 audiohd_pin_t *first_pin; 792}; 793 794#define AUDIOHD_MAX_ASSOC 15 795struct audiohd_state { 796 dev_info_t *hda_dip; 797 kstat_t *hda_ksp; 798 kmutex_t hda_mutex; 799 uint32_t hda_flags; 800 801 boolean_t soft_volume; 802 803 caddr_t hda_reg_base; 804 ddi_acc_handle_t hda_pci_handle; 805 ddi_acc_handle_t hda_reg_handle; 806 807 ddi_intr_handle_t *htable; /* For array of interrupts */ 808 boolean_t intr_added; 809 int intr_type; /* What type of interrupt */ 810 int intr_rqst; /* # of request intrs count */ 811 int intr_cnt; /* # of intrs count returned */ 812 uint_t intr_pri; /* Interrupt priority */ 813 int intr_cap; /* Interrupt capabilities */ 814 boolean_t msi_enable; 815 816 audiohd_dma_t hda_dma_corb; 817 audiohd_dma_t hda_dma_rirb; 818 819 820 uint8_t hda_rirb_rp; /* read pointer for rirb */ 821 uint16_t hda_codec_mask; 822 823 824 audio_dev_t *adev; 825 uint32_t devid; 826 827 int hda_input_streams; /* # of input stream */ 828 int hda_output_streams; /* # of output stream */ 829 int hda_streams_nums; /* # of stream */ 830 831 uint_t hda_play_regbase; 832 uint_t hda_record_regbase; 833 834 uint_t hda_play_stag; /* tag of playback stream */ 835 uint_t hda_record_stag; /* tag of record stream */ 836 uint_t hda_play_lgain; /* left gain for playback */ 837 uint_t hda_play_rgain; /* right gain for playback */ 838 839 /* 840 * Now, for the time being, we add some fields 841 * for parsing codec topology 842 */ 843 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 844 /* 845 * Suspend/Resume used fields 846 */ 847 boolean_t suspended; 848 849 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 850 uint8_t pathnum; 851 audiohd_port_t *port[PORT_MAX]; 852 uint8_t pchan; 853 uint8_t rchan; 854 855 uint64_t inmask; 856 857 uint_t hda_out_ports; 858 uint_t in_port; 859 860 /* 861 * Controls 862 */ 863 audiohd_ctrl_t ctrls[CTL_MAX]; 864 boolean_t monitor_unsupported; 865 866 /* for multichannel */ 867 uint8_t chann[AUDIOHD_MAX_ASSOC]; 868 uint8_t assoc; 869 870}; 871 872struct audiohd_codec_info { 873 uint32_t devid; 874 const char *buf; 875 uint32_t flags; 876}; 877 878/* 879 * Operation for high definition audio control system bus 880 * interface registers 881 */ 882#define AUDIOHD_REG_GET8(reg) \ 883 ddi_get8(statep->hda_reg_handle, \ 884 (void *)((char *)statep->hda_reg_base + (reg))) 885 886#define AUDIOHD_REG_GET16(reg) \ 887 ddi_get16(statep->hda_reg_handle, \ 888 (void *)((char *)statep->hda_reg_base + (reg))) 889 890#define AUDIOHD_REG_GET32(reg) \ 891 ddi_get32(statep->hda_reg_handle, \ 892 (void *)((char *)statep->hda_reg_base + (reg))) 893 894#define AUDIOHD_REG_GET64(reg) \ 895 ddi_get64(statep->hda_reg_handle, \ 896 (void *)((char *)statep->hda_reg_base + (reg))) 897 898#define AUDIOHD_REG_SET8(reg, val) \ 899 ddi_put8(statep->hda_reg_handle, \ 900 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 901 902#define AUDIOHD_REG_SET16(reg, val) \ 903 ddi_put16(statep->hda_reg_handle, \ 904 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 905 906#define AUDIOHD_REG_SET32(reg, val) \ 907 ddi_put32(statep->hda_reg_handle, \ 908 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 909 910#define AUDIOHD_REG_SET64(reg, val) \ 911 ddi_put64(statep->hda_reg_handle, \ 912 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 913 914 915/* 916 * enable a pin widget to input 917 */ 918#define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 919{ \ 920 (void) audioha_codec_verb_get(statep, caddr, wid, \ 921 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 922} 923 924 925/* 926 * disable input pin 927 */ 928#define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 929{ \ 930 uint32_t lTmp; \ 931\ 932 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 933 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 934 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 935 return (DDI_FAILURE); \ 936 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 937 AUDIOHDC_VERB_SET_PIN_CTRL, \ 938 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 939 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 940 return (DDI_FAILURE); \ 941} 942 943/* 944 * unmute an output pin 945 */ 946#define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 947{ \ 948 if (audioha_codec_4bit_verb_get(statep, \ 949 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 950 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 951 AUDIOHD_CODEC_FAILURE) \ 952 return (DDI_FAILURE); \ 953} 954 955/* 956 * check volume adjust value of 2 channels control 957 */ 958#define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 959{ \ 960 if ((value) & ~0xffff) \ 961 return (EINVAL); \ 962 if ((((value) & 0xff00) >> 8) > 100 || \ 963 ((value) & 0xff) > 100) \ 964 return (EINVAL); \ 965} 966 967/* 968 * check volume adjust value of mono channel control 969 */ 970#define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 971{ \ 972 if ((value) & ~0xff) \ 973 return (EINVAL); \ 974 if (((value) & 0xff) > 100) \ 975 return (EINVAL); \ 976} 977 978#ifdef __cplusplus 979} 980#endif 981 982#endif /* _SYS_AUDIOHD_IMPL_H_ */ 983