audio1575.h revision 9484:fbd5ddc28e96
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef AUDIO1575_H 27#define AUDIO1575_H 28 29/* 30 * Header file for the audio1575 device driver 31 */ 32 33/* 34 * Values returned by the AUDIO_GETDEV ioctl() 35 */ 36#define M1575_DEV_NAME "SUNW,audio1575" 37#define M1575_DEV_CONFIG "onboard1" 38#define M1575_DEV_VERSION "a" 39 40/* 41 * Driver supported configuration information 42 */ 43#define M1575_NAME "audio1575" 44#define M1575_MOD_NAME "M1575 audio driver" 45 46#define M1575_INTS (175) /* default interrupt rate */ 47#define M1575_MIN_INTS (25) /* minimum interrupt rate */ 48#define M1575_MAX_INTS (5000) /* maximum interrupt rate */ 49 50/* 51 * Implementation specific header file for the audio1575 device driver. 52 */ 53 54/* Misc. defines */ 55#define M1575_CONFIG_DEVICE_ID M1575_IDNUM 56#define M1575_CONFIG_VENDOR_ID (0x10b9) 57#define M1575_CONFIG_SUBSYSTEM_ID M1575_IDNUM 58#define M1575_CONFIG_SUBSYSTEM_VENDOR_ID M1575_CONFIG_VENDOR_ID 59#define M1575_AUDIO_PCICFG_SPACE (0) 60#define M1575_AUDIO_IO_SPACE (1) 61#define M1575_AUDIO_MEM_SPACE (2) 62 63#define M1575_LOOP_CTR (100) 64 65/* Gain and attenuation shift values */ 66#define M1575_GAIN_SHIFT3 (3) 67#define M1575_GAIN_SHIFT4 (4) 68#define M1575_BYTE_SHIFT (8) 69 70/* audio direction */ 71#define M1575_PLAY (0) 72#define M1575_REC (1) 73 74#define M1575_DMA_PCM_IN (1) 75#define M1575_DMA_PCM_OUT (2) 76 77/* last AC97 saved register */ 78#define M1575_LAST_AC_REG (0x3a) 79 80/* Restore audio flags */ 81#define M1575_INIT_RESTORE (0) 82#define M1575_INIT_NO_RESTORE ~M1575_INIT_RESTORE 83 84/* AC97 codec shadow reg to index macro */ 85#define M1575_CODEC_REG(r) ((r) >> 1) 86 87/* play and record sample buffer counts */ 88#define M1575_PLAY_BUFS (2) 89#define M1575_PLAY_BUF_MSK (M1575_PLAY_BUFS - 1) 90#define M1575_REC_BUFS (4) 91#define M1575_REC_BUF_MSK (M1575_REC_BUFS - 1) 92 93/* Buffer Descriptor List defines */ 94#define M1575_BD_NUMS (32) 95#define M1575_NUM_PORTS (2) 96#define M1575_MOD_SIZE (16) 97 98/* default buffer size */ 99#define M1575_BSIZE (8*1024) 100#define M1575_MOD_SIZE (16) 101#define M1575_PLAY_BUF_SZ (1024) 102#define M1575_RECORD_BUF_SZ (1024) 103#define M1575_BUF_MIN (512) 104#define M1575_BUF_MAX (8192) 105 106/* kstat interrupt counter define */ 107#define M1575_KIOP(X) ((kstat_intr_t *)(X->ksp->ks_data)) 108#define M1575_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 109 110/* PCI CFG SPACE REGISTERS for Audio (Device 29, Function 0) */ 111#define M1575_PCIPMR_REG 0x42 /* Power Capabilities 16 */ 112#define M1575_PCIPMCSR_REG 0x44 /* Power Cmd & Status 16 */ 113#define M1575_PCISCCR_REG 0x48 /* System Cfg Cntrl 16 */ 114#define M1575_PCIAPMUCR1_REG 0x54 /* Add. PMU Cntrl Reg 8 */ 115#define M1575_PCISCRR_REG 0x57 /* Scratch Reg 8 */ 116#define M1575_PCIMISC_REG 0x58 /* Misc Reg 8 */ 117#define M1575_PCIGCC_REG 0x59 /* Global Clk Control 16 */ 118#define M1575_PCIACD_REG 0x5C /* AC97 Codec Detect 8 */ 119#define M1575_PCIMISC_REG 0x58 /* Misc Reg 8 */ 120#define M1575_PCIGCLK_REG 0x59 /* Misc Reg 8 */ 121#define M1575_PCIMSICTRL_REG 0x62 /* MSI Control Reg 16 */ 122#define M1575_PCIMSIADDR_REG 0x64 /* MSI Address Reg 32 */ 123#define M1575_PCIMSIDATA_REG 0x68 /* MSI Data Reg 16 */ 124#define M1575_PCIMSIMASK_REG 0x6C /* MSI Data Reg 32 */ 125#define M1575_PCIMSIPEND_REG 0x70 /* MSI Pend Reg 32 */ 126 127/* Bit definitions for PCI AC97 Clk detect Reg */ 128#define M1575_PCIACD_CLKDET 0x01 129#define M1575_PCIMISC_INTENB 0x40 130#define M1575_PCIINT_LINE 0x05 131 132/* Base Line Audio I/O Memory Registers */ 133#define M1575_SCR_REG 0x00 /* System Control Reg 32 */ 134#define M1575_SSR_REG 0x04 /* System System Reg 32 */ 135#define M1575_DMACR_REG 0x08 /* DMA Control Reg 32 */ 136#define M1575_FIFOCR1_REG 0x0C /* FIFO 1 Control Reg 32 */ 137#define M1575_INTFCR_REG 0x10 /* Interface Ctrl Reg 32 */ 138#define M1575_INTRCR_REG 0x14 /* Interrupt Ctrl Reg 32 */ 139#define M1575_INTRSR_REG 0x18 /* Interrupt Status Reg 32 */ 140#define M1575_FIFOCR2_REG 0x1C /* FIFO 2 Control Reg 32 */ 141#define M1575_CPR_REG 0x20 /* Cmd Port Reg 32 */ 142#define M1575_SPR_REG 0x24 /* Status Port Reg 32 */ 143#define M1575_FIFOCR3_REG 0x2C /* FIFO 3 Control Reg 32 */ 144#define M1575_TTSR_REG 0x30 /* Tx Tag Slot Reg 32 */ 145#define M1575_RTSR_REG 0x34 /* Rx Tag Slot Reg 32 */ 146#define M1575_CSPSR_REG 0x38 /* CSP Status Reg 32 */ 147#define M1575_CASR_REG 0x3C /* Codec Access Sem Reg 32 */ 148 149/* PCM IN Registers */ 150#define M1575_PCMIBDBAR_REG 0x40 /* 32 */ 151#define M1575_PCMICIV_REG 0x44 /* 8 */ 152#define M1575_PCMILVIV_REG 0x45 /* 8 */ 153#define M1575_PCMISR_REG 0x46 /* 16 */ 154#define M1575_PCMIPICB_REG 0x48 /* 16 */ 155#define M1575_PCMICR_REG 0x4B /* 8 */ 156 157/* PCM OUT Registers */ 158#define M1575_PCMOBDBAR_REG 0x50 /* 32 */ 159#define M1575_PCMOCIV_REG 0x54 /* 8 */ 160#define M1575_PCMOLVIV_REG 0x55 /* 8 */ 161#define M1575_PCMOSR_REG 0x56 /* 16 */ 162#define M1575_PCMOPICB_REG 0x58 /* 16 */ 163#define M1575_PCMOCR_REG 0x5B /* 8 */ 164 165/* MIC In Registers */ 166#define M1575_MICIBDBAR_REG 0x60 /* 32 */ 167#define M1575_MICICIV_REG 0x64 /* 8 */ 168#define M1575_MICILVIV_REG 0x65 /* 8 */ 169#define M1575_MICISR_REG 0x66 /* 16 */ 170#define M1575_MICIPICB_REG 0x68 /* 16 */ 171#define M1575_MICICR_REG 0x6B /* 8 */ 172 173/* SPIDOF Registers */ 174#define M1575_CSPOBDBAR_REG 0x70 /* 32 */ 175#define M1575_CSPOCIV_REG 0x74 /* 8 */ 176#define M1575_CSPOLVIV_REG 0x75 /* 8 */ 177#define M1575_CSPOSR_REG 0x76 /* 16 */ 178#define M1575_CSPOPICB_REG 0x78 /* 16 */ 179#define M1575_CSPOCR_REG 0x7B /* 8 */ 180 181/* PCM IN2 Registers */ 182#define M1575_PCMI2BDBAR_REG 0xd0 /* 32 */ 183#define M1575_PCMI2CIV_REG 0xd4 /* 8 */ 184#define M1575_PCMI2LVIV_REG 0xd5 /* 8 */ 185#define M1575_PCMI2SR_REG 0xd6 /* 16 */ 186#define M1575_PCMI2PICB_REG 0xd8 /* 16 */ 187#define M1575_PCMI2CR_REG 0xdB /* 8 */ 188 189/* MIC2 IN2 Registers */ 190#define M1575_MICI2BDBAR_REG 0xe0 /* 32 */ 191#define M1575_MICI2CIV_REG 0xe4 /* 8 */ 192#define M1575_MICI2LVIV_REG 0xe5 /* 8 */ 193#define M1575_MICI2SR_REG 0xe6 /* 16 */ 194#define M1575_MICI2PICB_REG 0xe8 /* 16 */ 195#define M1575_MICI2CR_REG 0xeB /* 8 */ 196 197/* Bits of FIFO Control Register1 */ 198#define M1575_FIFOCR1_CSPORST 0x80000000 /* SPDIF Out Reset */ 199#define M1575_FIFOCR1_MICIRST 0x00800000 /* MIC In Reset */ 200#define M1575_FIFOCR1_PCMORST 0x00008000 /* PCM Out Reset */ 201#define M1575_FIFOCR1_PCMIRST 0x00000080 /* PCM In Reset */ 202 203/* Bits of FIFO Control Register2 */ 204#define M1575_FIFOCR2_SPORST 0x80000000 /* SPDIF Out FIFO Reset */ 205#define M1575_FIFOCR2_SPIRST 0x00800000 /* SPDIF In FIFO Reset */ 206#define M1575_FIFOCR2_LFEORST 0x00008000 /* LFE Out FIFO Reset */ 207#define M1575_FIFOCR2_CENORST 0x00000080 /* CENTER Out Reset */ 208 209/* Bits of FIFO Control Register3 */ 210#define M1575_FIFOCR3_PCMI2RST 0x00800000 /* PCM In2 FIFO Reset */ 211#define M1575_FIFOCR3_MICI2RST 0x00008000 /* MIC In2 FIFO Reset */ 212#define M1575_FIFOCR3_I2SIRST 0x00000080 /* I2S In FIFO Reset */ 213 214/* Bits of DMA Control Register */ 215#define M1575_DMACR_PCMISTART 0x00000001 216#define M1575_DMACR_PCMOSTART 0x00000002 217#define M1575_DMACR_MICISTART 0x00000004 218#define M1575_DMACR_CSPOSTART 0x00000008 219#define M1575_DMACR_CENOSTART 0x00000010 220#define M1575_DMACR_LFEOSTART 0x00000020 221#define M1575_DMACR_SPISTART 0x00000040 222#define M1575_DMACR_SPOSTART 0x00000080 223#define M1575_DMACR_I2SISTART 0x00000100 224#define M1575_DMACR_PCMI2START 0x00000200 225#define M1575_DMACR_MICI2START 0x00000400 226#define M1575_DMACR_PCMIPAUSE 0x00010000 227#define M1575_DMACR_PCMOPAUSE 0x00020000 228#define M1575_DMACR_MICIPAUSE 0x00040000 229#define M1575_DMACR_CSPOPAUSE 0x00080000 230#define M1575_DMACR_CENOPAUSE 0x00100000 231#define M1575_DMACR_LFEOPAUSE 0x00200000 232#define M1575_DMACR_SPIPAUSE 0x00400000 233#define M1575_DMACR_SPOPAUSE 0x00800000 234#define M1575_DMACR_I2SIPAUSE 0x01000000 235#define M1575_DMACR_PCMI2PAUSE 0x02000000 236#define M1575_DMACR_MICI2PAUSE 0x04000000 237 238#define M1575_DMACR_PAUSE_ALL 0x07ff0000 239 240/* Bits of INTRSR Interrupt Status Register */ 241#define M1575_INTRSR_GPIOINTR 0x0000002 242#define M1575_INTRSR_SPRINTR 0x0000020 243#define M1575_INTRSR_CPRINTR 0x0000080 244#define M1575_INTRSR_PCMIINTR 0x0010000 245#define M1575_INTRSR_PCMOINTR 0x0020000 246#define M1575_INTRSR_MICIINTR 0x0040000 247#define M1575_INTRSR_CSPOINTR 0x0080000 248#define M1575_INTRSR_CENOINTR 0x0100000 249#define M1575_INTRSR_LFEOINTR 0x0200000 250#define M1575_INTRSR_SPIINTR 0x0400000 251#define M1575_INTRSR_SPOINTR 0x0800000 252#define M1575_INTRSR_I2SIINTR 0x1000000 253#define M1575_INTRSR_PCMI2INTR 0x2000000 254#define M1575_INTRSR_MICI2INTR 0x4000000 255 256#define M1575_INTR_MASK (M1575_INTRSR_GPIOINTR |\ 257 M1575_INTRSR_SPRINTR |\ 258 M1575_INTRSR_CPRINTR |\ 259 M1575_INTRSR_PCMIINTR |\ 260 M1575_INTRSR_PCMOINTR |\ 261 M1575_INTRSR_MICIINTR |\ 262 M1575_INTRSR_CSPOINTR |\ 263 M1575_INTRSR_CENOINTR |\ 264 M1575_INTRSR_LFEOINTR |\ 265 M1575_INTRSR_SPIINTR |\ 266 M1575_INTRSR_SPOINTR |\ 267 M1575_INTRSR_I2SIINTR |\ 268 M1575_INTRSR_PCMI2INTR|\ 269 M1575_INTRSR_MICI2INTR) 270 271#define M1575_UNUSED_INTR_MASK (M1575_INTRSR_GPIOINTR |\ 272 M1575_INTRSR_SPRINTR |\ 273 M1575_INTRSR_CPRINTR |\ 274 M1575_INTRSR_MICIINTR |\ 275 M1575_INTRSR_CSPOINTR |\ 276 M1575_INTRSR_CENOINTR |\ 277 M1575_INTRSR_LFEOINTR |\ 278 M1575_INTRSR_SPIINTR |\ 279 M1575_INTRSR_SPOINTR |\ 280 M1575_INTRSR_I2SIINTR |\ 281 M1575_INTRSR_PCMI2INTR|\ 282 M1575_INTRSR_MICI2INTR) 283 284/* Defines a generic clear for all MIC and PCM Status Registers */ 285#define M1575_SR_CLR 0x001e 286#define M1575_SR_DMACS 0x0001 287 288/* Defines a generic RESET for all MIC and PCM Control Registers */ 289#define M1575_CR_IOCE 0x10 290#define M1575_CR_RR 0x02 291 292/* Bits of PCM In Status Register */ 293#define M1575_PCMISR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 294#define M1575_PCMISR_CELV 0x02 295#define M1575_PCMISR_LVBCI 0x04 296#define M1575_PCMISR_BCIS 0x08 297#define M1575_PCMISR_FIFOE 0x10 298 299/* Bits in PCM In Control Register */ 300#define M1575_PCMICR_RR 0x02 /* Reset */ 301#define M1575_PCMICR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 302#define M1575_PCMICR_IOCE 0x10 /* Intr On Completion Enable */ 303 304/* Bits of PCM Out Status Register */ 305#define M1575_PCMOSR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 306#define M1575_PCMOSR_CELV 0x02 307#define M1575_PCMOSR_LVBCI 0x04 308#define M1575_PCMOSR_BCIS 0x08 309#define M1575_PCMOSR_FIFOE 0x10 310 311/* Bits in PCM Out Control Register */ 312#define M1575_PCMOCR_RR 0x02 /* Reset */ 313#define M1575_PCMOCR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 314#define M1575_PCMOCR_IOCE 0x10 /* Intr On Completion Enable */ 315 316/* Bits of MIC In Status Register */ 317#define M1575_MICISR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 318#define M1575_MICISR_CELV 0x02 319#define M1575_MICISR_LVBCI 0x04 320#define M1575_MICISR_BCIS 0x08 321#define M1575_MICISR_FIFOE 0x10 322 323/* Bits in PCM In Control Register */ 324#define M1575_MICICR_RR 0x02 /* Reset */ 325#define M1575_MICICR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 326#define M1575_MICICR_IOCE 0x10 /* Intr On Completion Enable */ 327 328/* Bits in System Control Register */ 329#define M1575_SCR_WARMRST 0x00000001 330#define M1575_SCR_COLDRST 0x00000002 331#define M1575_SCR_DRENT 0x40000000 332#define M1575_SCR_MSTRST 0x80000000 333 334/* Bits in System Status Register */ 335#define M1575_SSR_RSTBLK 0x00000002 336#define M1575_SSR_FACCS_MSK 0x00000018 337#define M1575_SSR_SCID 0x00000040 338 339/* Bits in Command Port Register */ 340#define M1575_CPR_ACSCS 0x0100 /* Audio Codec for cmd 1=codec 2 */ 341#define M1575_CPR_READ 0x0080 342 343/* Bits in Cmd Status Port Register */ 344#define M1575_CSPSR_SUCC 0x08 /* cmd successful */ 345#define M1575_CSPSR_RDRDY 0x02 /* ready for read cmd */ 346#define M1575_CSPSR_WRRDY 0x01 /* ready for write cmd */ 347#define M1575_PCMI2CR_RR 0x02 /* Reset */ 348#define M1575_MICI2CR_RR 0x02 /* Reset */ 349#define M1575_CSPOCR_RR 0x02 /* Reset */ 350 351/* Bits in Interface Control Register */ 352#define M1575_INTFCR_RSTREL 0x02000000 353#define M1575_INTFCR_RSTBLK 0x00200000 354#define M1575_INTFCR_MICENB 0x00100000 355#define M1575_INTFCR_PCMIENB 0x00080000 356#define M1575_INTFCR_MICI2ENB 0x00040000 357#define M1575_INTFCR_PCMI2ENB 0x00020000 358#define M1575_INTFCR_MICI2SEL 0x00008000 359#define M1575_INTFCR_MICISEL 0x00004000 360#define M1575_INTFCR_PCMOENB 0x00000002 361 362#define M1575_INTRCR_CPRINTR 0x00000080 363#define M1575_INTRCR_SPRINTR 0x00000020 364#define M1575_INTRCR_GPIOINTR 0x00000002 365 366/* Bits of Recv Tag Slot Register */ 367#define M1575_RTSR_SACRDY 0x20u /* 2nd Audio Codec Rdy */ 368#define M1575_RTSR_FACRDY 0x80u /* 1st Audio Codec Rdy */ 369 370/* Semaphore busy */ 371#define M1575_CASR_SEMBSY 0x80000000 372 373/* 374 * buffer descripter list entry, see M1575 datasheet 375 */ 376#define IOC 0x8000 377#define BUP 0x4000 378 379struct m1575_bd_entry { 380 uint32_t buf_base; /* the address of the buffer */ 381 uint16_t buf_len; /* the number of samples */ 382 uint16_t buf_cmd; 383}; 384typedef struct m1575_bd_entry m1575_bd_entry_t; 385 386struct audio1575_port { 387 struct audio1575_state *statep; 388 ddi_dma_handle_t samp_dmah; 389 ddi_acc_handle_t samp_acch; 390 size_t samp_size; 391 caddr_t samp_kaddr; 392 uint32_t samp_paddr; 393 394 ddi_dma_handle_t bdl_dmah; 395 ddi_acc_handle_t bdl_acch; 396 size_t bdl_size; 397 caddr_t bdl_kaddr; 398 uint32_t bdl_paddr; 399 400 int num; 401 unsigned intrs; 402 unsigned fragfr; 403 uint64_t count; 404 uint8_t nchan; 405 406 uint8_t civ; 407 uint16_t picb; 408 unsigned sync_dir; 409 410 boolean_t started; 411 412 audio_engine_t *engine; 413}; 414typedef struct audio1575_port audio1575_port_t; 415 416 417/* 418 * audio1575_state_t per instance state and operation data 419 */ 420struct audio1575_state { 421 kmutex_t lock; /* intr mutex */ 422 kmutex_t ac_lock; /* ac'97 mutex */ 423 dev_info_t *dip; /* dev instance ptr */ 424 audio_dev_t *adev; /* audio handle */ 425 ac97_t *ac97; /* ac'97 handle */ 426 audio1575_port_t *ports[2]; /* DMA engines */ 427 428 ddi_intr_handle_t ih; /* intr handle */ 429 430 ddi_acc_handle_t pcih; /* pci config space */ 431 432 ddi_acc_handle_t regsh; /* audio i/o regs */ 433 caddr_t regsp; /* base of i/o regs */ 434 435 kstat_t *ksp; /* kernel statistics */ 436 437 boolean_t suspended; /* if DDI_SUSPENDed */ 438}; 439typedef struct audio1575_state audio1575_state_t; 440 441/* audio i/o register macros */ 442#define GET8(reg) \ 443 ddi_get8(statep->regsh, (void *)(statep->regsp + (reg))) 444 445#define GET16(reg) \ 446 ddi_get16(statep->regsh, (void *)(statep->regsp + (reg))) 447 448#define GET32(reg) \ 449 ddi_get32(statep->regsh, (void *)(statep->regsp + (reg))) 450 451#define PUT8(reg, val) \ 452 ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 453 454#define PUT16(reg, val) \ 455 ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 456 457#define PUT32(reg, val) \ 458 ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 459 460#define SET8(reg, bit) PUT8(reg, GET8(reg) | (bit)) 461#define SET16(reg, bit) PUT16(reg, GET16(reg) | (bit)) 462#define SET32(reg, bit) PUT32(reg, GET32(reg) | (bit)) 463#define CLR8(reg, bit) PUT8(reg, GET8(reg) & ~(bit)) 464#define CLR16(reg, bit) PUT16(reg, GET16(reg) & ~(bit)) 465#define CLR32(reg, bit) PUT32(reg, GET32(reg) & ~(bit)) 466 467 468#endif /* AUDIO1575_H */ 469