proc64_id.h revision 6320:760e2394a4b5 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright (c) 2008, Intel Corporation
24 * All rights reserved.
25 */
26
27#ifndef	_PROC64_ID_H
28#define	_PROC64_ID_H
29
30#pragma ident	"%Z%%M%	%I%	%E% SMI"
31
32#include <sys/x86_archext.h>
33
34#ifdef	__cplusplus
35extern "C" {
36#endif
37
38/*
39 * Defines to determine what SSE instructions can be used for memops or strops.
40 */
41#define	NO_SSE		0x00	/* Default -- Don't use SSE instructions */
42#define	USE_SSE2	0x01	/* SSE2 */
43#define	USE_SSE3	0x02	/* SSE3 */
44#define	USE_SSSE3	0x04	/* Supplemental SSE3 */
45#define	USE_SSE4_1	0x08	/* SSE 4.1 */
46#define	USE_SSE4_2	0x10	/* SSE 4.2 */
47
48/*
49 * Cache size defaults for Core 2 Duo
50 */
51#define	INTEL_DFLT_L1_CACHE_SIZE	(32 * 1024)
52#define	INTEL_DFLT_L2_CACHE_SIZE	(4 * 1024 * 1024)
53#define	INTEL_DFLT_LARGEST_CACHE_SIZE	(4 * 1024 * 1024)
54
55/*
56 * Cache size defaults for AMD SledgeHammer
57 */
58#define	AMD_DFLT_L1_CACHE_SIZE		(64 * 1024)
59#define	AMD_DFLT_L1_HALF_CACHE_SIZE	(32 * 1024)
60#define	AMD_DFLT_L2_CACHE_SIZE		(1024 * 1024)
61#define	AMD_DFLT_L2_HALF_CACHE_SIZE	(512 * 1024)
62
63#ifdef _ASM
64	.extern .memops_method
65#else
66
67void __libc_get_cpuid(int cpuid_function, void *out_reg, int cache_index);
68void __intel_set_memops_method(long sse_level);
69void __intel_set_cache_sizes(long l1_cache_size, long l2_cache_size,
70    long largest_level_cache);
71
72#endif /* _ASM */
73
74#ifdef	__cplusplus
75}
76#endif
77
78#endif /* _PROC64_ID_H */
79