SUN4V.dict revision 4759:3a228be89946 
1#
2# Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
3# Use is subject to license terms.
4#
5# CDDL HEADER START
6#
7# The contents of this file are subject to the terms of the
8# Common Development and Distribution License (the "License").
9# You may not use this file except in compliance with the License.
10#
11# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
12# or http://www.opensolaris.org/os/licensing.
13# See the License for the specific language governing permissions
14# and limitations under the License.
15#
16# When distributing Covered Code, include this CDDL HEADER in each
17# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
18# If applicable, add the following below this CDDL HEADER, with the
19# fields enclosed by brackets "[]" replaced with your own identifying
20# information: Portions Copyright [yyyy] [name of copyright owner]
21#
22# CDDL HEADER END
23#
24#ident	"%Z%%M%	%I%	%E% SMI"
25#
26# DO NOT EDIT -- this file is generated by the Event Registry.
27#
28
29FMDICT: name=SUN4V version=1 maxkey=3 dictid=0x3456
30
31fault.cpu.ultraSPARC-T1.ireg=1
32fault.cpu.ultraSPARC-T1.freg=2
33fault.cpu.ultraSPARC-T1.itlb=3
34fault.cpu.ultraSPARC-T1.dtlb=4
35fault.cpu.ultraSPARC-T1.icache=5
36fault.cpu.ultraSPARC-T1.dcache=6
37fault.cpu.ultraSPARC-T1.mau=7
38fault.cpu.ultraSPARC-T1.l2cachedata=8
39fault.cpu.ultraSPARC-T1.l2cachetag=9
40fault.cpu.ultraSPARC-T1.l2cachectl=10
41fault.memory.page=11
42fault.memory.dimm=12
43fault.memory.bank=13
44fault.memory.link-c=14
45fault.cpu.ultraSPARC-T2.ireg=15
46fault.cpu.ultraSPARC-T2.freg=16
47fault.cpu.ultraSPARC-T2.misc_reg=17
48fault.cpu.ultraSPARC-T2.itlb=18
49fault.cpu.ultraSPARC-T2.dtlb=19
50fault.cpu.ultraSPARC-T2.icache=20
51fault.cpu.ultraSPARC-T2.dcache=21
52fault.cpu.ultraSPARC-T2.mau=22
53fault.cpu.ultraSPARC-T2.l2data-c=23
54fault.cpu.ultraSPARC-T2.l2cachetag=24
55fault.cpu.ultraSPARC-T2.l2cachectl=25
56fault.memory.link-u=26
57fault.cpu.ultraSPARC-T2.l2data-u=27
58fault.cpu.ultraSPARC-T1.l2data-c=28
59fault.cpu.ultraSPARC-T1.l2data-u=29
60fault.memory.datapath=30
61fault.io.n2.ncu=31
62fault.io.n2.dmu=32
63fault.io.n2.niu=33
64fault.io.n2.siu=34
65fault.io.n2.soc=35
66fault.io.n2.crossbar=36
67fault.io.fire.fw-epkt fault.io.fire.sw-epkt fault.io.fire.sw-fw-mismatch=37
68fault.io.vf.ncx=38
69fault.memory.link-f=39
70fault.cpu.ultraSPARC-T2plus.ireg=40
71fault.cpu.ultraSPARC-T2plus.freg=41
72fault.cpu.ultraSPARC-T2plus.misc_reg=42
73fault.cpu.ultraSPARC-T2plus.itlb=43
74fault.cpu.ultraSPARC-T2plus.dtlb=44
75fault.cpu.ultraSPARC-T2plus.icache=45
76fault.cpu.ultraSPARC-T2plus.dcache=46
77fault.cpu.ultraSPARC-T2plus.mau=47
78fault.cpu.ultraSPARC-T2plus.l2data-c=48
79fault.cpu.ultraSPARC-T2plus.l2cachetag=49
80fault.cpu.ultraSPARC-T2plus.l2cachectl=50
81fault.cpu.ultraSPARC-T2plus.l2data-u=51
82fault.cpu.ultraSPARC-T2plus.lfu-f=52
83fault.cpu.ultraSPARC-T2plus.lfu-p=53
84fault.cpu.ultraSPARC-T2plus.lfu-u=54
85