matcher.hpp revision 1274:2883969d09e7
1/* 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25class Compile; 26class Node; 27class MachNode; 28class MachTypeNode; 29class MachOper; 30 31//---------------------------Matcher------------------------------------------- 32class Matcher : public PhaseTransform { 33 friend class VMStructs; 34 // Private arena of State objects 35 ResourceArea _states_arena; 36 37 VectorSet _visited; // Visit bits 38 39 // Used to control the Label pass 40 VectorSet _shared; // Shared Ideal Node 41 VectorSet _dontcare; // Nothing the matcher cares about 42 43 // Private methods which perform the actual matching and reduction 44 // Walks the label tree, generating machine nodes 45 MachNode *ReduceInst( State *s, int rule, Node *&mem); 46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); 47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); 48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); 49 50 // If this node already matched using "rule", return the MachNode for it. 51 MachNode* find_shared_node(Node* n, uint rule); 52 53 // Convert a dense opcode number to an expanded rule number 54 const int *_reduceOp; 55 const int *_leftOp; 56 const int *_rightOp; 57 58 // Map dense opcode number to info on when rule is swallowed constant. 59 const bool *_swallowed; 60 61 // Map dense rule number to determine if this is an instruction chain rule 62 const uint _begin_inst_chain_rule; 63 const uint _end_inst_chain_rule; 64 65 // We want to clone constants and possible CmpI-variants. 66 // If we do not clone CmpI, then we can have many instances of 67 // condition codes alive at once. This is OK on some chips and 68 // bad on others. Hence the machine-dependent table lookup. 69 const char *_must_clone; 70 71 // Find shared Nodes, or Nodes that otherwise are Matcher roots 72 void find_shared( Node *n ); 73 74 // Debug and profile information for nodes in old space: 75 GrowableArray<Node_Notes*>* _old_node_note_array; 76 77 // Node labeling iterator for instruction selection 78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); 79 80 Node *transform( Node *dummy ); 81 82 Node_List &_proj_list; // For Machine nodes killing many values 83 84 Node_Array _shared_nodes; 85 86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots 87 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal 88 89 // Accessors for the inherited field PhaseTransform::_nodes: 90 void grow_new_node_array(uint idx_limit) { 91 _nodes.map(idx_limit-1, NULL); 92 } 93 bool has_new_node(const Node* n) const { 94 return _nodes.at(n->_idx) != NULL; 95 } 96 Node* new_node(const Node* n) const { 97 assert(has_new_node(n), "set before get"); 98 return _nodes.at(n->_idx); 99 } 100 void set_new_node(const Node* n, Node *nn) { 101 assert(!has_new_node(n), "set only once"); 102 _nodes.map(n->_idx, nn); 103 } 104 105#ifdef ASSERT 106 // Make sure only new nodes are reachable from this node 107 void verify_new_nodes_only(Node* root); 108 109 Node* _mem_node; // Ideal memory node consumed by mach node 110#endif 111 112 // Mach node for ConP #NULL 113 MachNode* _mach_null; 114 115public: 116 int LabelRootDepth; 117 static const int base2reg[]; // Map Types to machine register types 118 // Convert ideal machine register to a register mask for spill-loads 119 static const RegMask *idealreg2regmask[]; 120 RegMask *idealreg2spillmask [_last_machine_leaf]; 121 RegMask *idealreg2debugmask [_last_machine_leaf]; 122 RegMask *idealreg2mhdebugmask[_last_machine_leaf]; 123 void init_spill_mask( Node *ret ); 124 // Convert machine register number to register mask 125 static uint mreg2regmask_max; 126 static RegMask mreg2regmask[]; 127 static RegMask STACK_ONLY_mask; 128 129 MachNode* mach_null() const { return _mach_null; } 130 131 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } 132 void set_shared( Node *n ) { _shared.set(n->_idx); } 133 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } 134 void set_visited( Node *n ) { _visited.set(n->_idx); } 135 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } 136 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } 137 138 // Mode bit to tell DFA and expand rules whether we are running after 139 // (or during) register selection. Usually, the matcher runs before, 140 // but it will also get called to generate post-allocation spill code. 141 // In this situation, it is a deadly error to attempt to allocate more 142 // temporary registers. 143 bool _allocation_started; 144 145 // Machine register names 146 static const char *regName[]; 147 // Machine register encodings 148 static const unsigned char _regEncode[]; 149 // Machine Node names 150 const char **_ruleName; 151 // Rules that are cheaper to rematerialize than to spill 152 static const uint _begin_rematerialize; 153 static const uint _end_rematerialize; 154 155 // An array of chars, from 0 to _last_Mach_Reg. 156 // No Save = 'N' (for register windows) 157 // Save on Entry = 'E' 158 // Save on Call = 'C' 159 // Always Save = 'A' (same as SOE + SOC) 160 const char *_register_save_policy; 161 const char *_c_reg_save_policy; 162 // Convert a machine register to a machine register type, so-as to 163 // properly match spill code. 164 const int *_register_save_type; 165 // Maps from machine register to boolean; true if machine register can 166 // be holding a call argument in some signature. 167 static bool can_be_java_arg( int reg ); 168 // Maps from machine register to boolean; true if machine register holds 169 // a spillable argument. 170 static bool is_spillable_arg( int reg ); 171 172 // List of IfFalse or IfTrue Nodes that indicate a taken null test. 173 // List is valid in the post-matching space. 174 Node_List _null_check_tests; 175 void collect_null_checks( Node *proj, Node *orig_proj ); 176 void validate_null_checks( ); 177 178 Matcher( Node_List &proj_list ); 179 180 // Select instructions for entire method 181 void match( ); 182 // Helper for match 183 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); 184 185 // Transform, then walk. Does implicit DCE while walking. 186 // Name changed from "transform" to avoid it being virtual. 187 Node *xform( Node *old_space_node, int Nodes ); 188 189 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. 190 MachNode *match_tree( const Node *n ); 191 MachNode *match_sfpt( SafePointNode *sfpt ); 192 // Helper for match_sfpt 193 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); 194 195 // Initialize first stack mask and related masks. 196 void init_first_stack_mask(); 197 198 // If we should save-on-entry this register 199 bool is_save_on_entry( int reg ); 200 201 // Fixup the save-on-entry registers 202 void Fixup_Save_On_Entry( ); 203 204 // --- Frame handling --- 205 206 // Register number of the stack slot corresponding to the incoming SP. 207 // Per the Big Picture in the AD file, it is: 208 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. 209 OptoReg::Name _old_SP; 210 211 // Register number of the stack slot corresponding to the highest incoming 212 // argument on the stack. Per the Big Picture in the AD file, it is: 213 // _old_SP + out_preserve_stack_slots + incoming argument size. 214 OptoReg::Name _in_arg_limit; 215 216 // Register number of the stack slot corresponding to the new SP. 217 // Per the Big Picture in the AD file, it is: 218 // _in_arg_limit + pad0 219 OptoReg::Name _new_SP; 220 221 // Register number of the stack slot corresponding to the highest outgoing 222 // argument on the stack. Per the Big Picture in the AD file, it is: 223 // _new_SP + max outgoing arguments of all calls 224 OptoReg::Name _out_arg_limit; 225 226 OptoRegPair *_parm_regs; // Array of machine registers per argument 227 RegMask *_calling_convention_mask; // Array of RegMasks per argument 228 229 // Does matcher have a match rule for this ideal node? 230 static const bool has_match_rule(int opcode); 231 static const bool _hasMatchRule[_last_opcode]; 232 233 // Does matcher have a match rule for this ideal node and is the 234 // predicate (if there is one) true? 235 // NOTE: If this function is used more commonly in the future, ADLC 236 // should generate this one. 237 static const bool match_rule_supported(int opcode); 238 239 // Used to determine if we have fast l2f conversion 240 // USII has it, USIII doesn't 241 static const bool convL2FSupported(void); 242 243 // Vector width in bytes 244 static const uint vector_width_in_bytes(void); 245 246 // Vector ideal reg 247 static const uint vector_ideal_reg(void); 248 249 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) 250 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). 251 // Depends on the details of 64-bit constant generation on the CPU. 252 static const bool isSimpleConstant64(jlong con); 253 254 // These calls are all generated by the ADLC 255 256 // TRUE - grows up, FALSE - grows down (Intel) 257 virtual bool stack_direction() const; 258 259 // Java-Java calling convention 260 // (what you use when Java calls Java) 261 262 // Alignment of stack in bytes, standard Intel word alignment is 4. 263 // Sparc probably wants at least double-word (8). 264 static uint stack_alignment_in_bytes(); 265 // Alignment of stack, measured in stack slots. 266 // The size of stack slots is defined by VMRegImpl::stack_slot_size. 267 static uint stack_alignment_in_slots() { 268 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); 269 } 270 271 // Array mapping arguments to registers. Argument 0 is usually the 'this' 272 // pointer. Registers can include stack-slots and regular registers. 273 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); 274 275 // Convert a sig into a calling convention register layout 276 // and find interesting things about it. 277 static OptoReg::Name find_receiver( bool is_outgoing ); 278 // Return address register. On Intel it is a stack-slot. On PowerPC 279 // it is the Link register. On Sparc it is r31? 280 virtual OptoReg::Name return_addr() const; 281 RegMask _return_addr_mask; 282 // Return value register. On Intel it is EAX. On Sparc i0/o0. 283 static OptoRegPair return_value(int ideal_reg, bool is_outgoing); 284 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); 285 RegMask _return_value_mask; 286 // Inline Cache Register 287 static OptoReg::Name inline_cache_reg(); 288 static const RegMask &inline_cache_reg_mask(); 289 static int inline_cache_reg_encode(); 290 291 // Register for DIVI projection of divmodI 292 static RegMask divI_proj_mask(); 293 // Register for MODI projection of divmodI 294 static RegMask modI_proj_mask(); 295 296 // Register for DIVL projection of divmodL 297 static RegMask divL_proj_mask(); 298 // Register for MODL projection of divmodL 299 static RegMask modL_proj_mask(); 300 301 static const RegMask method_handle_invoke_SP_save_mask(); 302 303 // Java-Interpreter calling convention 304 // (what you use when calling between compiled-Java and Interpreted-Java 305 306 // Number of callee-save + always-save registers 307 // Ignores frame pointer and "special" registers 308 static int number_of_saved_registers(); 309 310 // The Method-klass-holder may be passed in the inline_cache_reg 311 // and then expanded into the inline_cache_reg and a method_oop register 312 313 static OptoReg::Name interpreter_method_oop_reg(); 314 static const RegMask &interpreter_method_oop_reg_mask(); 315 static int interpreter_method_oop_reg_encode(); 316 317 static OptoReg::Name compiler_method_oop_reg(); 318 static const RegMask &compiler_method_oop_reg_mask(); 319 static int compiler_method_oop_reg_encode(); 320 321 // Interpreter's Frame Pointer Register 322 static OptoReg::Name interpreter_frame_pointer_reg(); 323 static const RegMask &interpreter_frame_pointer_reg_mask(); 324 325 // Java-Native calling convention 326 // (what you use when intercalling between Java and C++ code) 327 328 // Array mapping arguments to registers. Argument 0 is usually the 'this' 329 // pointer. Registers can include stack-slots and regular registers. 330 static void c_calling_convention( BasicType*, VMRegPair *, uint ); 331 // Frame pointer. The frame pointer is kept at the base of the stack 332 // and so is probably the stack pointer for most machines. On Intel 333 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. 334 OptoReg::Name c_frame_pointer() const; 335 static RegMask c_frame_ptr_mask; 336 337 // !!!!! Special stuff for building ScopeDescs 338 virtual int regnum_to_fpu_offset(int regnum); 339 340 // Is this branch offset small enough to be addressed by a short branch? 341 bool is_short_branch_offset(int rule, int offset); 342 343 // Optional scaling for the parameter to the ClearArray/CopyArray node. 344 static const bool init_array_count_is_in_bytes; 345 346 // Threshold small size (in bytes) for a ClearArray/CopyArray node. 347 // Anything this size or smaller may get converted to discrete scalar stores. 348 static const int init_array_short_size; 349 350 // Should the Matcher clone shifts on addressing modes, expecting them to 351 // be subsumed into complex addressing expressions or compute them into 352 // registers? True for Intel but false for most RISCs 353 static const bool clone_shift_expressions; 354 355 // Is it better to copy float constants, or load them directly from memory? 356 // Intel can load a float constant from a direct address, requiring no 357 // extra registers. Most RISCs will have to materialize an address into a 358 // register first, so they may as well materialize the constant immediately. 359 static const bool rematerialize_float_constants; 360 361 // If CPU can load and store mis-aligned doubles directly then no fixup is 362 // needed. Else we split the double into 2 integer pieces and move it 363 // piece-by-piece. Only happens when passing doubles into C code or when 364 // calling i2c adapters as the Java calling convention forces doubles to be 365 // aligned. 366 static const bool misaligned_doubles_ok; 367 368 // Perform a platform dependent implicit null fixup. This is needed 369 // on windows95 to take care of some unusual register constraints. 370 void pd_implicit_null_fixup(MachNode *load, uint idx); 371 372 // Advertise here if the CPU requires explicit rounding operations 373 // to implement the UseStrictFP mode. 374 static const bool strict_fp_requires_explicit_rounding; 375 376 // Are floats conerted to double when stored to stack during deoptimization? 377 static bool float_in_double(); 378 // Do ints take an entire long register or just half? 379 static const bool int_in_long; 380 381 // This routine is run whenever a graph fails to match. 382 // If it returns, the compiler should bailout to interpreter without error. 383 // In non-product mode, SoftMatchFailure is false to detect non-canonical 384 // graphs. Print a message and exit. 385 static void soft_match_failure() { 386 if( SoftMatchFailure ) return; 387 else { fatal("SoftMatchFailure is not allowed except in product"); } 388 } 389 390 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock 391 // acting as an Acquire and thus we don't need an Acquire here. We 392 // retain the Node to act as a compiler ordering barrier. 393 static bool prior_fast_lock( const Node *acq ); 394 395 // Used by the DFA in dfa_sparc.cpp. Check for a following 396 // FastUnLock acting as a Release and thus we don't need a Release 397 // here. We retain the Node to act as a compiler ordering barrier. 398 static bool post_fast_unlock( const Node *rel ); 399 400 // Check for a following volatile memory barrier without an 401 // intervening load and thus we don't need a barrier here. We 402 // retain the Node to act as a compiler ordering barrier. 403 static bool post_store_load_barrier(const Node* mb); 404 405 406#ifdef ASSERT 407 void dump_old2new_map(); // machine-independent to machine-dependent 408 409 Node* find_old_node(Node* new_node) { 410 return _new2old_map[new_node->_idx]; 411 } 412#endif 413}; 414