matcher.cpp revision 5947:f4f6ae481e1a
1/* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "memory/allocation.inline.hpp" 27#include "opto/addnode.hpp" 28#include "opto/callnode.hpp" 29#include "opto/connode.hpp" 30#include "opto/idealGraphPrinter.hpp" 31#include "opto/matcher.hpp" 32#include "opto/memnode.hpp" 33#include "opto/opcodes.hpp" 34#include "opto/regmask.hpp" 35#include "opto/rootnode.hpp" 36#include "opto/runtime.hpp" 37#include "opto/type.hpp" 38#include "opto/vectornode.hpp" 39#include "runtime/atomic.hpp" 40#include "runtime/os.hpp" 41#ifdef TARGET_ARCH_MODEL_x86_32 42# include "adfiles/ad_x86_32.hpp" 43#endif 44#ifdef TARGET_ARCH_MODEL_x86_64 45# include "adfiles/ad_x86_64.hpp" 46#endif 47#ifdef TARGET_ARCH_MODEL_sparc 48# include "adfiles/ad_sparc.hpp" 49#endif 50#ifdef TARGET_ARCH_MODEL_zero 51# include "adfiles/ad_zero.hpp" 52#endif 53#ifdef TARGET_ARCH_MODEL_arm 54# include "adfiles/ad_arm.hpp" 55#endif 56#ifdef TARGET_ARCH_MODEL_ppc_32 57# include "adfiles/ad_ppc_32.hpp" 58#endif 59#ifdef TARGET_ARCH_MODEL_ppc_64 60# include "adfiles/ad_ppc_64.hpp" 61#endif 62 63OptoReg::Name OptoReg::c_frame_pointer; 64 65const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 66RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 67RegMask Matcher::STACK_ONLY_mask; 68RegMask Matcher::c_frame_ptr_mask; 69const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 70const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 71 72//---------------------------Matcher------------------------------------------- 73Matcher::Matcher( Node_List &proj_list ) : 74 PhaseTransform( Phase::Ins_Select ), 75#ifdef ASSERT 76 _old2new_map(C->comp_arena()), 77 _new2old_map(C->comp_arena()), 78#endif 79 _shared_nodes(C->comp_arena()), 80 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 81 _swallowed(swallowed), 82 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 83 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 84 _must_clone(must_clone), _proj_list(proj_list), 85 _register_save_policy(register_save_policy), 86 _c_reg_save_policy(c_reg_save_policy), 87 _register_save_type(register_save_type), 88 _ruleName(ruleName), 89 _allocation_started(false), 90 _states_arena(Chunk::medium_size), 91 _visited(&_states_arena), 92 _shared(&_states_arena), 93 _dontcare(&_states_arena) { 94 C->set_matcher(this); 95 96 idealreg2spillmask [Op_RegI] = NULL; 97 idealreg2spillmask [Op_RegN] = NULL; 98 idealreg2spillmask [Op_RegL] = NULL; 99 idealreg2spillmask [Op_RegF] = NULL; 100 idealreg2spillmask [Op_RegD] = NULL; 101 idealreg2spillmask [Op_RegP] = NULL; 102 idealreg2spillmask [Op_VecS] = NULL; 103 idealreg2spillmask [Op_VecD] = NULL; 104 idealreg2spillmask [Op_VecX] = NULL; 105 idealreg2spillmask [Op_VecY] = NULL; 106 107 idealreg2debugmask [Op_RegI] = NULL; 108 idealreg2debugmask [Op_RegN] = NULL; 109 idealreg2debugmask [Op_RegL] = NULL; 110 idealreg2debugmask [Op_RegF] = NULL; 111 idealreg2debugmask [Op_RegD] = NULL; 112 idealreg2debugmask [Op_RegP] = NULL; 113 idealreg2debugmask [Op_VecS] = NULL; 114 idealreg2debugmask [Op_VecD] = NULL; 115 idealreg2debugmask [Op_VecX] = NULL; 116 idealreg2debugmask [Op_VecY] = NULL; 117 118 idealreg2mhdebugmask[Op_RegI] = NULL; 119 idealreg2mhdebugmask[Op_RegN] = NULL; 120 idealreg2mhdebugmask[Op_RegL] = NULL; 121 idealreg2mhdebugmask[Op_RegF] = NULL; 122 idealreg2mhdebugmask[Op_RegD] = NULL; 123 idealreg2mhdebugmask[Op_RegP] = NULL; 124 idealreg2mhdebugmask[Op_VecS] = NULL; 125 idealreg2mhdebugmask[Op_VecD] = NULL; 126 idealreg2mhdebugmask[Op_VecX] = NULL; 127 idealreg2mhdebugmask[Op_VecY] = NULL; 128 129 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 130} 131 132//------------------------------warp_incoming_stk_arg------------------------ 133// This warps a VMReg into an OptoReg::Name 134OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 135 OptoReg::Name warped; 136 if( reg->is_stack() ) { // Stack slot argument? 137 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 138 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 139 if( warped >= _in_arg_limit ) 140 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 141 if (!RegMask::can_represent_arg(warped)) { 142 // the compiler cannot represent this method's calling sequence 143 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence"); 144 return OptoReg::Bad; 145 } 146 return warped; 147 } 148 return OptoReg::as_OptoReg(reg); 149} 150 151//---------------------------compute_old_SP------------------------------------ 152OptoReg::Name Compile::compute_old_SP() { 153 int fixed = fixed_slots(); 154 int preserve = in_preserve_stack_slots(); 155 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots())); 156} 157 158 159 160#ifdef ASSERT 161void Matcher::verify_new_nodes_only(Node* xroot) { 162 // Make sure that the new graph only references new nodes 163 ResourceMark rm; 164 Unique_Node_List worklist; 165 VectorSet visited(Thread::current()->resource_area()); 166 worklist.push(xroot); 167 while (worklist.size() > 0) { 168 Node* n = worklist.pop(); 169 visited <<= n->_idx; 170 assert(C->node_arena()->contains(n), "dead node"); 171 for (uint j = 0; j < n->req(); j++) { 172 Node* in = n->in(j); 173 if (in != NULL) { 174 assert(C->node_arena()->contains(in), "dead node"); 175 if (!visited.test(in->_idx)) { 176 worklist.push(in); 177 } 178 } 179 } 180 } 181} 182#endif 183 184 185//---------------------------match--------------------------------------------- 186void Matcher::match( ) { 187 if( MaxLabelRootDepth < 100 ) { // Too small? 188 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 189 MaxLabelRootDepth = 100; 190 } 191 // One-time initialization of some register masks. 192 init_spill_mask( C->root()->in(1) ); 193 _return_addr_mask = return_addr(); 194#ifdef _LP64 195 // Pointers take 2 slots in 64-bit land 196 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 197#endif 198 199 // Map a Java-signature return type into return register-value 200 // machine registers for 0, 1 and 2 returned values. 201 const TypeTuple *range = C->tf()->range(); 202 if( range->cnt() > TypeFunc::Parms ) { // If not a void function 203 // Get ideal-register return type 204 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 205 // Get machine return register 206 uint sop = C->start()->Opcode(); 207 OptoRegPair regs = return_value(ireg, false); 208 209 // And mask for same 210 _return_value_mask = RegMask(regs.first()); 211 if( OptoReg::is_valid(regs.second()) ) 212 _return_value_mask.Insert(regs.second()); 213 } 214 215 // --------------- 216 // Frame Layout 217 218 // Need the method signature to determine the incoming argument types, 219 // because the types determine which registers the incoming arguments are 220 // in, and this affects the matched code. 221 const TypeTuple *domain = C->tf()->domain(); 222 uint argcnt = domain->cnt() - TypeFunc::Parms; 223 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 224 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 225 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 226 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 227 uint i; 228 for( i = 0; i<argcnt; i++ ) { 229 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 230 } 231 232 // Pass array of ideal registers and length to USER code (from the AD file) 233 // that will convert this to an array of register numbers. 234 const StartNode *start = C->start(); 235 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 236#ifdef ASSERT 237 // Sanity check users' calling convention. Real handy while trying to 238 // get the initial port correct. 239 { for (uint i = 0; i<argcnt; i++) { 240 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 241 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 242 _parm_regs[i].set_bad(); 243 continue; 244 } 245 VMReg parm_reg = vm_parm_regs[i].first(); 246 assert(parm_reg->is_valid(), "invalid arg?"); 247 if (parm_reg->is_reg()) { 248 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 249 assert(can_be_java_arg(opto_parm_reg) || 250 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 251 opto_parm_reg == inline_cache_reg(), 252 "parameters in register must be preserved by runtime stubs"); 253 } 254 for (uint j = 0; j < i; j++) { 255 assert(parm_reg != vm_parm_regs[j].first(), 256 "calling conv. must produce distinct regs"); 257 } 258 } 259 } 260#endif 261 262 // Do some initial frame layout. 263 264 // Compute the old incoming SP (may be called FP) as 265 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 266 _old_SP = C->compute_old_SP(); 267 assert( is_even(_old_SP), "must be even" ); 268 269 // Compute highest incoming stack argument as 270 // _old_SP + out_preserve_stack_slots + incoming argument size. 271 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 272 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 273 for( i = 0; i < argcnt; i++ ) { 274 // Permit args to have no register 275 _calling_convention_mask[i].Clear(); 276 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 277 continue; 278 } 279 // calling_convention returns stack arguments as a count of 280 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 281 // the allocators point of view, taking into account all the 282 // preserve area, locks & pad2. 283 284 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 285 if( OptoReg::is_valid(reg1)) 286 _calling_convention_mask[i].Insert(reg1); 287 288 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 289 if( OptoReg::is_valid(reg2)) 290 _calling_convention_mask[i].Insert(reg2); 291 292 // Saved biased stack-slot register number 293 _parm_regs[i].set_pair(reg2, reg1); 294 } 295 296 // Finally, make sure the incoming arguments take up an even number of 297 // words, in case the arguments or locals need to contain doubleword stack 298 // slots. The rest of the system assumes that stack slot pairs (in 299 // particular, in the spill area) which look aligned will in fact be 300 // aligned relative to the stack pointer in the target machine. Double 301 // stack slots will always be allocated aligned. 302 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong)); 303 304 // Compute highest outgoing stack argument as 305 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 306 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 307 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 308 309 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 310 // the compiler cannot represent this method's calling sequence 311 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 312 } 313 314 if (C->failing()) return; // bailed out on incoming arg failure 315 316 // --------------- 317 // Collect roots of matcher trees. Every node for which 318 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 319 // can be a valid interior of some tree. 320 find_shared( C->root() ); 321 find_shared( C->top() ); 322 323 C->print_method(PHASE_BEFORE_MATCHING); 324 325 // Create new ideal node ConP #NULL even if it does exist in old space 326 // to avoid false sharing if the corresponding mach node is not used. 327 // The corresponding mach node is only used in rare cases for derived 328 // pointers. 329 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR); 330 331 // Swap out to old-space; emptying new-space 332 Arena *old = C->node_arena()->move_contents(C->old_arena()); 333 334 // Save debug and profile information for nodes in old space: 335 _old_node_note_array = C->node_note_array(); 336 if (_old_node_note_array != NULL) { 337 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 338 (C->comp_arena(), _old_node_note_array->length(), 339 0, NULL)); 340 } 341 342 // Pre-size the new_node table to avoid the need for range checks. 343 grow_new_node_array(C->unique()); 344 345 // Reset node counter so MachNodes start with _idx at 0 346 int nodes = C->unique(); // save value 347 C->set_unique(0); 348 C->reset_dead_node_list(); 349 350 // Recursively match trees from old space into new space. 351 // Correct leaves of new-space Nodes; they point to old-space. 352 _visited.Clear(); // Clear visit bits for xform call 353 C->set_cached_top_node(xform( C->top(), nodes )); 354 if (!C->failing()) { 355 Node* xroot = xform( C->root(), 1 ); 356 if (xroot == NULL) { 357 Matcher::soft_match_failure(); // recursive matching process failed 358 C->record_method_not_compilable("instruction match failed"); 359 } else { 360 // During matching shared constants were attached to C->root() 361 // because xroot wasn't available yet, so transfer the uses to 362 // the xroot. 363 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 364 Node* n = C->root()->fast_out(j); 365 if (C->node_arena()->contains(n)) { 366 assert(n->in(0) == C->root(), "should be control user"); 367 n->set_req(0, xroot); 368 --j; 369 --jmax; 370 } 371 } 372 373 // Generate new mach node for ConP #NULL 374 assert(new_ideal_null != NULL, "sanity"); 375 _mach_null = match_tree(new_ideal_null); 376 // Don't set control, it will confuse GCM since there are no uses. 377 // The control will be set when this node is used first time 378 // in find_base_for_derived(). 379 assert(_mach_null != NULL, ""); 380 381 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 382 383#ifdef ASSERT 384 verify_new_nodes_only(xroot); 385#endif 386 } 387 } 388 if (C->top() == NULL || C->root() == NULL) { 389 C->record_method_not_compilable("graph lost"); // %%% cannot happen? 390 } 391 if (C->failing()) { 392 // delete old; 393 old->destruct_contents(); 394 return; 395 } 396 assert( C->top(), "" ); 397 assert( C->root(), "" ); 398 validate_null_checks(); 399 400 // Now smoke old-space 401 NOT_DEBUG( old->destruct_contents() ); 402 403 // ------------------------ 404 // Set up save-on-entry registers 405 Fixup_Save_On_Entry( ); 406} 407 408 409//------------------------------Fixup_Save_On_Entry---------------------------- 410// The stated purpose of this routine is to take care of save-on-entry 411// registers. However, the overall goal of the Match phase is to convert into 412// machine-specific instructions which have RegMasks to guide allocation. 413// So what this procedure really does is put a valid RegMask on each input 414// to the machine-specific variations of all Return, TailCall and Halt 415// instructions. It also adds edgs to define the save-on-entry values (and of 416// course gives them a mask). 417 418static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 419 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 420 // Do all the pre-defined register masks 421 rms[TypeFunc::Control ] = RegMask::Empty; 422 rms[TypeFunc::I_O ] = RegMask::Empty; 423 rms[TypeFunc::Memory ] = RegMask::Empty; 424 rms[TypeFunc::ReturnAdr] = ret_adr; 425 rms[TypeFunc::FramePtr ] = fp; 426 return rms; 427} 428 429//---------------------------init_first_stack_mask----------------------------- 430// Create the initial stack mask used by values spilling to the stack. 431// Disallow any debug info in outgoing argument areas by setting the 432// initial mask accordingly. 433void Matcher::init_first_stack_mask() { 434 435 // Allocate storage for spill masks as masks for the appropriate load type. 436 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4)); 437 438 idealreg2spillmask [Op_RegN] = &rms[0]; 439 idealreg2spillmask [Op_RegI] = &rms[1]; 440 idealreg2spillmask [Op_RegL] = &rms[2]; 441 idealreg2spillmask [Op_RegF] = &rms[3]; 442 idealreg2spillmask [Op_RegD] = &rms[4]; 443 idealreg2spillmask [Op_RegP] = &rms[5]; 444 445 idealreg2debugmask [Op_RegN] = &rms[6]; 446 idealreg2debugmask [Op_RegI] = &rms[7]; 447 idealreg2debugmask [Op_RegL] = &rms[8]; 448 idealreg2debugmask [Op_RegF] = &rms[9]; 449 idealreg2debugmask [Op_RegD] = &rms[10]; 450 idealreg2debugmask [Op_RegP] = &rms[11]; 451 452 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 453 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 454 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 455 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 456 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 457 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 458 459 idealreg2spillmask [Op_VecS] = &rms[18]; 460 idealreg2spillmask [Op_VecD] = &rms[19]; 461 idealreg2spillmask [Op_VecX] = &rms[20]; 462 idealreg2spillmask [Op_VecY] = &rms[21]; 463 464 OptoReg::Name i; 465 466 // At first, start with the empty mask 467 C->FIRST_STACK_mask().Clear(); 468 469 // Add in the incoming argument area 470 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 471 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1)) 472 C->FIRST_STACK_mask().Insert(i); 473 474 // Add in all bits past the outgoing argument area 475 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 476 "must be able to represent all call arguments in reg mask"); 477 init = _out_arg_limit; 478 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 479 C->FIRST_STACK_mask().Insert(i); 480 481 // Finally, set the "infinite stack" bit. 482 C->FIRST_STACK_mask().set_AllStack(); 483 484 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 485 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 486 // Keep spill masks aligned. 487 aligned_stack_mask.clear_to_pairs(); 488 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 489 490 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 491#ifdef _LP64 492 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 493 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 494 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 495#else 496 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 497#endif 498 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 499 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 500 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 501 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 502 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 503 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 504 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 505 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 506 507 if (Matcher::vector_size_supported(T_BYTE,4)) { 508 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 509 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 510 } 511 if (Matcher::vector_size_supported(T_FLOAT,2)) { 512 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 513 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 514 } 515 if (Matcher::vector_size_supported(T_FLOAT,4)) { 516 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 517 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 518 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 519 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 520 } 521 if (Matcher::vector_size_supported(T_FLOAT,8)) { 522 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 523 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 524 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 525 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 526 } 527 if (UseFPUForSpilling) { 528 // This mask logic assumes that the spill operations are 529 // symmetric and that the registers involved are the same size. 530 // On sparc for instance we may have to use 64 bit moves will 531 // kill 2 registers when used with F0-F31. 532 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 533 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 534#ifdef _LP64 535 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 536 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 537 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 538 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 539#else 540 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 541#ifdef ARM 542 // ARM has support for moving 64bit values between a pair of 543 // integer registers and a double register 544 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 545 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 546#endif 547#endif 548 } 549 550 // Make up debug masks. Any spill slot plus callee-save registers. 551 // Caller-save registers are assumed to be trashable by the various 552 // inline-cache fixup routines. 553 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 554 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 555 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 556 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 557 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 558 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 559 560 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 561 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 562 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 563 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 564 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 565 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 566 567 // Prevent stub compilations from attempting to reference 568 // callee-saved registers from debug info 569 bool exclude_soe = !Compile::current()->is_method_compilation(); 570 571 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 572 // registers the caller has to save do not work 573 if( _register_save_policy[i] == 'C' || 574 _register_save_policy[i] == 'A' || 575 (_register_save_policy[i] == 'E' && exclude_soe) ) { 576 idealreg2debugmask [Op_RegN]->Remove(i); 577 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 578 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 579 idealreg2debugmask [Op_RegF]->Remove(i); // masks 580 idealreg2debugmask [Op_RegD]->Remove(i); 581 idealreg2debugmask [Op_RegP]->Remove(i); 582 583 idealreg2mhdebugmask[Op_RegN]->Remove(i); 584 idealreg2mhdebugmask[Op_RegI]->Remove(i); 585 idealreg2mhdebugmask[Op_RegL]->Remove(i); 586 idealreg2mhdebugmask[Op_RegF]->Remove(i); 587 idealreg2mhdebugmask[Op_RegD]->Remove(i); 588 idealreg2mhdebugmask[Op_RegP]->Remove(i); 589 } 590 } 591 592 // Subtract the register we use to save the SP for MethodHandle 593 // invokes to from the debug mask. 594 const RegMask save_mask = method_handle_invoke_SP_save_mask(); 595 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 596 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 597 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 598 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 599 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 600 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 601} 602 603//---------------------------is_save_on_entry---------------------------------- 604bool Matcher::is_save_on_entry( int reg ) { 605 return 606 _register_save_policy[reg] == 'E' || 607 _register_save_policy[reg] == 'A' || // Save-on-entry register? 608 // Also save argument registers in the trampolining stubs 609 (C->save_argument_registers() && is_spillable_arg(reg)); 610} 611 612//---------------------------Fixup_Save_On_Entry------------------------------- 613void Matcher::Fixup_Save_On_Entry( ) { 614 init_first_stack_mask(); 615 616 Node *root = C->root(); // Short name for root 617 // Count number of save-on-entry registers. 618 uint soe_cnt = number_of_saved_registers(); 619 uint i; 620 621 // Find the procedure Start Node 622 StartNode *start = C->start(); 623 assert( start, "Expect a start node" ); 624 625 // Save argument registers in the trampolining stubs 626 if( C->save_argument_registers() ) 627 for( i = 0; i < _last_Mach_Reg; i++ ) 628 if( is_spillable_arg(i) ) 629 soe_cnt++; 630 631 // Input RegMask array shared by all Returns. 632 // The type for doubles and longs has a count of 2, but 633 // there is only 1 returned value 634 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 635 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 636 // Returns have 0 or 1 returned values depending on call signature. 637 // Return register is specified by return_value in the AD file. 638 if (ret_edge_cnt > TypeFunc::Parms) 639 ret_rms[TypeFunc::Parms+0] = _return_value_mask; 640 641 // Input RegMask array shared by all Rethrows. 642 uint reth_edge_cnt = TypeFunc::Parms+1; 643 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 644 // Rethrow takes exception oop only, but in the argument 0 slot. 645 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)]; 646#ifdef _LP64 647 // Need two slots for ptrs in 64-bit land 648 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1)); 649#endif 650 651 // Input RegMask array shared by all TailCalls 652 uint tail_call_edge_cnt = TypeFunc::Parms+2; 653 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 654 655 // Input RegMask array shared by all TailJumps 656 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 657 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 658 659 // TailCalls have 2 returned values (target & moop), whose masks come 660 // from the usual MachNode/MachOper mechanism. Find a sample 661 // TailCall to extract these masks and put the correct masks into 662 // the tail_call_rms array. 663 for( i=1; i < root->req(); i++ ) { 664 MachReturnNode *m = root->in(i)->as_MachReturn(); 665 if( m->ideal_Opcode() == Op_TailCall ) { 666 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 667 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 668 break; 669 } 670 } 671 672 // TailJumps have 2 returned values (target & ex_oop), whose masks come 673 // from the usual MachNode/MachOper mechanism. Find a sample 674 // TailJump to extract these masks and put the correct masks into 675 // the tail_jump_rms array. 676 for( i=1; i < root->req(); i++ ) { 677 MachReturnNode *m = root->in(i)->as_MachReturn(); 678 if( m->ideal_Opcode() == Op_TailJump ) { 679 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 680 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 681 break; 682 } 683 } 684 685 // Input RegMask array shared by all Halts 686 uint halt_edge_cnt = TypeFunc::Parms; 687 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 688 689 // Capture the return input masks into each exit flavor 690 for( i=1; i < root->req(); i++ ) { 691 MachReturnNode *exit = root->in(i)->as_MachReturn(); 692 switch( exit->ideal_Opcode() ) { 693 case Op_Return : exit->_in_rms = ret_rms; break; 694 case Op_Rethrow : exit->_in_rms = reth_rms; break; 695 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 696 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 697 case Op_Halt : exit->_in_rms = halt_rms; break; 698 default : ShouldNotReachHere(); 699 } 700 } 701 702 // Next unused projection number from Start. 703 int proj_cnt = C->tf()->domain()->cnt(); 704 705 // Do all the save-on-entry registers. Make projections from Start for 706 // them, and give them a use at the exit points. To the allocator, they 707 // look like incoming register arguments. 708 for( i = 0; i < _last_Mach_Reg; i++ ) { 709 if( is_save_on_entry(i) ) { 710 711 // Add the save-on-entry to the mask array 712 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 713 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 714 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 715 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 716 // Halts need the SOE registers, but only in the stack as debug info. 717 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 718 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 719 720 Node *mproj; 721 722 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 723 // into a single RegD. 724 if( (i&1) == 0 && 725 _register_save_type[i ] == Op_RegF && 726 _register_save_type[i+1] == Op_RegF && 727 is_save_on_entry(i+1) ) { 728 // Add other bit for double 729 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 730 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 731 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 732 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 733 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 734 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 735 proj_cnt += 2; // Skip 2 for doubles 736 } 737 else if( (i&1) == 1 && // Else check for high half of double 738 _register_save_type[i-1] == Op_RegF && 739 _register_save_type[i ] == Op_RegF && 740 is_save_on_entry(i-1) ) { 741 ret_rms [ ret_edge_cnt] = RegMask::Empty; 742 reth_rms [ reth_edge_cnt] = RegMask::Empty; 743 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 744 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 745 halt_rms [ halt_edge_cnt] = RegMask::Empty; 746 mproj = C->top(); 747 } 748 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 749 // into a single RegL. 750 else if( (i&1) == 0 && 751 _register_save_type[i ] == Op_RegI && 752 _register_save_type[i+1] == Op_RegI && 753 is_save_on_entry(i+1) ) { 754 // Add other bit for long 755 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 756 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 757 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 758 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 759 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 760 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 761 proj_cnt += 2; // Skip 2 for longs 762 } 763 else if( (i&1) == 1 && // Else check for high half of long 764 _register_save_type[i-1] == Op_RegI && 765 _register_save_type[i ] == Op_RegI && 766 is_save_on_entry(i-1) ) { 767 ret_rms [ ret_edge_cnt] = RegMask::Empty; 768 reth_rms [ reth_edge_cnt] = RegMask::Empty; 769 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 770 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 771 halt_rms [ halt_edge_cnt] = RegMask::Empty; 772 mproj = C->top(); 773 } else { 774 // Make a projection for it off the Start 775 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 776 } 777 778 ret_edge_cnt ++; 779 reth_edge_cnt ++; 780 tail_call_edge_cnt ++; 781 tail_jump_edge_cnt ++; 782 halt_edge_cnt ++; 783 784 // Add a use of the SOE register to all exit paths 785 for( uint j=1; j < root->req(); j++ ) 786 root->in(j)->add_req(mproj); 787 } // End of if a save-on-entry register 788 } // End of for all machine registers 789} 790 791//------------------------------init_spill_mask-------------------------------- 792void Matcher::init_spill_mask( Node *ret ) { 793 if( idealreg2regmask[Op_RegI] ) return; // One time only init 794 795 OptoReg::c_frame_pointer = c_frame_pointer(); 796 c_frame_ptr_mask = c_frame_pointer(); 797#ifdef _LP64 798 // pointers are twice as big 799 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 800#endif 801 802 // Start at OptoReg::stack0() 803 STACK_ONLY_mask.Clear(); 804 OptoReg::Name init = OptoReg::stack2reg(0); 805 // STACK_ONLY_mask is all stack bits 806 OptoReg::Name i; 807 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 808 STACK_ONLY_mask.Insert(i); 809 // Also set the "infinite stack" bit. 810 STACK_ONLY_mask.set_AllStack(); 811 812 // Copy the register names over into the shared world 813 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 814 // SharedInfo::regName[i] = regName[i]; 815 // Handy RegMasks per machine register 816 mreg2regmask[i].Insert(i); 817 } 818 819 // Grab the Frame Pointer 820 Node *fp = ret->in(TypeFunc::FramePtr); 821 Node *mem = ret->in(TypeFunc::Memory); 822 const TypePtr* atp = TypePtr::BOTTOM; 823 // Share frame pointer while making spill ops 824 set_shared(fp); 825 826 // Compute generic short-offset Loads 827#ifdef _LP64 828 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); 829#endif 830 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp)); 831 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp)); 832 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp)); 833 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp)); 834 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); 835 assert(spillI != NULL && spillL != NULL && spillF != NULL && 836 spillD != NULL && spillP != NULL, ""); 837 838 // Get the ADLC notion of the right regmask, for each basic type. 839#ifdef _LP64 840 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 841#endif 842 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 843 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 844 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 845 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 846 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 847 848 // Vector regmasks. 849 if (Matcher::vector_size_supported(T_BYTE,4)) { 850 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 851 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 852 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 853 } 854 if (Matcher::vector_size_supported(T_FLOAT,2)) { 855 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 856 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 857 } 858 if (Matcher::vector_size_supported(T_FLOAT,4)) { 859 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 860 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 861 } 862 if (Matcher::vector_size_supported(T_FLOAT,8)) { 863 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 864 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 865 } 866} 867 868#ifdef ASSERT 869static void match_alias_type(Compile* C, Node* n, Node* m) { 870 if (!VerifyAliases) return; // do not go looking for trouble by default 871 const TypePtr* nat = n->adr_type(); 872 const TypePtr* mat = m->adr_type(); 873 int nidx = C->get_alias_index(nat); 874 int midx = C->get_alias_index(mat); 875 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 876 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 877 for (uint i = 1; i < n->req(); i++) { 878 Node* n1 = n->in(i); 879 const TypePtr* n1at = n1->adr_type(); 880 if (n1at != NULL) { 881 nat = n1at; 882 nidx = C->get_alias_index(n1at); 883 } 884 } 885 } 886 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 887 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 888 switch (n->Opcode()) { 889 case Op_PrefetchRead: 890 case Op_PrefetchWrite: 891 case Op_PrefetchAllocation: 892 nidx = Compile::AliasIdxRaw; 893 nat = TypeRawPtr::BOTTOM; 894 break; 895 } 896 } 897 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 898 switch (n->Opcode()) { 899 case Op_ClearArray: 900 midx = Compile::AliasIdxRaw; 901 mat = TypeRawPtr::BOTTOM; 902 break; 903 } 904 } 905 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 906 switch (n->Opcode()) { 907 case Op_Return: 908 case Op_Rethrow: 909 case Op_Halt: 910 case Op_TailCall: 911 case Op_TailJump: 912 nidx = Compile::AliasIdxBot; 913 nat = TypePtr::BOTTOM; 914 break; 915 } 916 } 917 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 918 switch (n->Opcode()) { 919 case Op_StrComp: 920 case Op_StrEquals: 921 case Op_StrIndexOf: 922 case Op_AryEq: 923 case Op_MemBarVolatile: 924 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 925 case Op_EncodeISOArray: 926 nidx = Compile::AliasIdxTop; 927 nat = NULL; 928 break; 929 } 930 } 931 if (nidx != midx) { 932 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 933 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 934 n->dump(); 935 m->dump(); 936 } 937 assert(C->subsume_loads() && C->must_alias(nat, midx), 938 "must not lose alias info when matching"); 939 } 940} 941#endif 942 943 944//------------------------------MStack----------------------------------------- 945// State and MStack class used in xform() and find_shared() iterative methods. 946enum Node_State { Pre_Visit, // node has to be pre-visited 947 Visit, // visit node 948 Post_Visit, // post-visit node 949 Alt_Post_Visit // alternative post-visit path 950 }; 951 952class MStack: public Node_Stack { 953 public: 954 MStack(int size) : Node_Stack(size) { } 955 956 void push(Node *n, Node_State ns) { 957 Node_Stack::push(n, (uint)ns); 958 } 959 void push(Node *n, Node_State ns, Node *parent, int indx) { 960 ++_inode_top; 961 if ((_inode_top + 1) >= _inode_max) grow(); 962 _inode_top->node = parent; 963 _inode_top->indx = (uint)indx; 964 ++_inode_top; 965 _inode_top->node = n; 966 _inode_top->indx = (uint)ns; 967 } 968 Node *parent() { 969 pop(); 970 return node(); 971 } 972 Node_State state() const { 973 return (Node_State)index(); 974 } 975 void set_state(Node_State ns) { 976 set_index((uint)ns); 977 } 978}; 979 980 981//------------------------------xform------------------------------------------ 982// Given a Node in old-space, Match him (Label/Reduce) to produce a machine 983// Node in new-space. Given a new-space Node, recursively walk his children. 984Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 985Node *Matcher::xform( Node *n, int max_stack ) { 986 // Use one stack to keep both: child's node/state and parent's node/index 987 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2 988 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 989 990 while (mstack.is_nonempty()) { 991 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 992 if (C->failing()) return NULL; 993 n = mstack.node(); // Leave node on stack 994 Node_State nstate = mstack.state(); 995 if (nstate == Visit) { 996 mstack.set_state(Post_Visit); 997 Node *oldn = n; 998 // Old-space or new-space check 999 if (!C->node_arena()->contains(n)) { 1000 // Old space! 1001 Node* m; 1002 if (has_new_node(n)) { // Not yet Label/Reduced 1003 m = new_node(n); 1004 } else { 1005 if (!is_dontcare(n)) { // Matcher can match this guy 1006 // Calls match special. They match alone with no children. 1007 // Their children, the incoming arguments, match normally. 1008 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 1009 if (C->failing()) return NULL; 1010 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1011 } else { // Nothing the matcher cares about 1012 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections? 1013 // Convert to machine-dependent projection 1014 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1015#ifdef ASSERT 1016 _new2old_map.map(m->_idx, n); 1017#endif 1018 if (m->in(0) != NULL) // m might be top 1019 collect_null_checks(m, n); 1020 } else { // Else just a regular 'ol guy 1021 m = n->clone(); // So just clone into new-space 1022#ifdef ASSERT 1023 _new2old_map.map(m->_idx, n); 1024#endif 1025 // Def-Use edges will be added incrementally as Uses 1026 // of this node are matched. 1027 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1028 } 1029 } 1030 1031 set_new_node(n, m); // Map old to new 1032 if (_old_node_note_array != NULL) { 1033 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1034 n->_idx); 1035 C->set_node_notes_at(m->_idx, nn); 1036 } 1037 debug_only(match_alias_type(C, n, m)); 1038 } 1039 n = m; // n is now a new-space node 1040 mstack.set_node(n); 1041 } 1042 1043 // New space! 1044 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1045 1046 int i; 1047 // Put precedence edges on stack first (match them last). 1048 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1049 Node *m = oldn->in(i); 1050 if (m == NULL) break; 1051 // set -1 to call add_prec() instead of set_req() during Step1 1052 mstack.push(m, Visit, n, -1); 1053 } 1054 1055 // For constant debug info, I'd rather have unmatched constants. 1056 int cnt = n->req(); 1057 JVMState* jvms = n->jvms(); 1058 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1059 1060 // Now do only debug info. Clone constants rather than matching. 1061 // Constants are represented directly in the debug info without 1062 // the need for executable machine instructions. 1063 // Monitor boxes are also represented directly. 1064 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1065 Node *m = n->in(i); // Get input 1066 int op = m->Opcode(); 1067 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1068 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1069 op == Op_ConF || op == Op_ConD || op == Op_ConL 1070 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1071 ) { 1072 m = m->clone(); 1073#ifdef ASSERT 1074 _new2old_map.map(m->_idx, n); 1075#endif 1076 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1077 mstack.push(m->in(0), Visit, m, 0); 1078 } else { 1079 mstack.push(m, Visit, n, i); 1080 } 1081 } 1082 1083 // And now walk his children, and convert his inputs to new-space. 1084 for( ; i >= 0; --i ) { // For all normal inputs do 1085 Node *m = n->in(i); // Get input 1086 if(m != NULL) 1087 mstack.push(m, Visit, n, i); 1088 } 1089 1090 } 1091 else if (nstate == Post_Visit) { 1092 // Set xformed input 1093 Node *p = mstack.parent(); 1094 if (p != NULL) { // root doesn't have parent 1095 int i = (int)mstack.index(); 1096 if (i >= 0) 1097 p->set_req(i, n); // required input 1098 else if (i == -1) 1099 p->add_prec(n); // precedence input 1100 else 1101 ShouldNotReachHere(); 1102 } 1103 mstack.pop(); // remove processed node from stack 1104 } 1105 else { 1106 ShouldNotReachHere(); 1107 } 1108 } // while (mstack.is_nonempty()) 1109 return n; // Return new-space Node 1110} 1111 1112//------------------------------warp_outgoing_stk_arg------------------------ 1113OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1114 // Convert outgoing argument location to a pre-biased stack offset 1115 if (reg->is_stack()) { 1116 OptoReg::Name warped = reg->reg2stack(); 1117 // Adjust the stack slot offset to be the register number used 1118 // by the allocator. 1119 warped = OptoReg::add(begin_out_arg_area, warped); 1120 // Keep track of the largest numbered stack slot used for an arg. 1121 // Largest used slot per call-site indicates the amount of stack 1122 // that is killed by the call. 1123 if( warped >= out_arg_limit_per_call ) 1124 out_arg_limit_per_call = OptoReg::add(warped,1); 1125 if (!RegMask::can_represent_arg(warped)) { 1126 C->record_method_not_compilable_all_tiers("unsupported calling sequence"); 1127 return OptoReg::Bad; 1128 } 1129 return warped; 1130 } 1131 return OptoReg::as_OptoReg(reg); 1132} 1133 1134 1135//------------------------------match_sfpt------------------------------------- 1136// Helper function to match call instructions. Calls match special. 1137// They match alone with no children. Their children, the incoming 1138// arguments, match normally. 1139MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1140 MachSafePointNode *msfpt = NULL; 1141 MachCallNode *mcall = NULL; 1142 uint cnt; 1143 // Split out case for SafePoint vs Call 1144 CallNode *call; 1145 const TypeTuple *domain; 1146 ciMethod* method = NULL; 1147 bool is_method_handle_invoke = false; // for special kill effects 1148 if( sfpt->is_Call() ) { 1149 call = sfpt->as_Call(); 1150 domain = call->tf()->domain(); 1151 cnt = domain->cnt(); 1152 1153 // Match just the call, nothing else 1154 MachNode *m = match_tree(call); 1155 if (C->failing()) return NULL; 1156 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1157 1158 // Copy data from the Ideal SafePoint to the machine version 1159 mcall = m->as_MachCall(); 1160 1161 mcall->set_tf( call->tf()); 1162 mcall->set_entry_point(call->entry_point()); 1163 mcall->set_cnt( call->cnt()); 1164 1165 if( mcall->is_MachCallJava() ) { 1166 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1167 const CallJavaNode *call_java = call->as_CallJava(); 1168 method = call_java->method(); 1169 mcall_java->_method = method; 1170 mcall_java->_bci = call_java->_bci; 1171 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1172 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1173 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1174 if (is_method_handle_invoke) { 1175 C->set_has_method_handle_invokes(true); 1176 } 1177 if( mcall_java->is_MachCallStaticJava() ) 1178 mcall_java->as_MachCallStaticJava()->_name = 1179 call_java->as_CallStaticJava()->_name; 1180 if( mcall_java->is_MachCallDynamicJava() ) 1181 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1182 call_java->as_CallDynamicJava()->_vtable_index; 1183 } 1184 else if( mcall->is_MachCallRuntime() ) { 1185 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1186 } 1187 msfpt = mcall; 1188 } 1189 // This is a non-call safepoint 1190 else { 1191 call = NULL; 1192 domain = NULL; 1193 MachNode *mn = match_tree(sfpt); 1194 if (C->failing()) return NULL; 1195 msfpt = mn->as_MachSafePoint(); 1196 cnt = TypeFunc::Parms; 1197 } 1198 1199 // Advertise the correct memory effects (for anti-dependence computation). 1200 msfpt->set_adr_type(sfpt->adr_type()); 1201 1202 // Allocate a private array of RegMasks. These RegMasks are not shared. 1203 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1204 // Empty them all. 1205 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); 1206 1207 // Do all the pre-defined non-Empty register masks 1208 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1209 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1210 1211 // Place first outgoing argument can possibly be put. 1212 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1213 assert( is_even(begin_out_arg_area), "" ); 1214 // Compute max outgoing register number per call site. 1215 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1216 // Calls to C may hammer extra stack slots above and beyond any arguments. 1217 // These are usually backing store for register arguments for varargs. 1218 if( call != NULL && call->is_CallRuntime() ) 1219 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1220 1221 1222 // Do the normal argument list (parameters) register masks 1223 int argcnt = cnt - TypeFunc::Parms; 1224 if( argcnt > 0 ) { // Skip it all if we have no args 1225 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1226 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1227 int i; 1228 for( i = 0; i < argcnt; i++ ) { 1229 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1230 } 1231 // V-call to pick proper calling convention 1232 call->calling_convention( sig_bt, parm_regs, argcnt ); 1233 1234#ifdef ASSERT 1235 // Sanity check users' calling convention. Really handy during 1236 // the initial porting effort. Fairly expensive otherwise. 1237 { for (int i = 0; i<argcnt; i++) { 1238 if( !parm_regs[i].first()->is_valid() && 1239 !parm_regs[i].second()->is_valid() ) continue; 1240 VMReg reg1 = parm_regs[i].first(); 1241 VMReg reg2 = parm_regs[i].second(); 1242 for (int j = 0; j < i; j++) { 1243 if( !parm_regs[j].first()->is_valid() && 1244 !parm_regs[j].second()->is_valid() ) continue; 1245 VMReg reg3 = parm_regs[j].first(); 1246 VMReg reg4 = parm_regs[j].second(); 1247 if( !reg1->is_valid() ) { 1248 assert( !reg2->is_valid(), "valid halvsies" ); 1249 } else if( !reg3->is_valid() ) { 1250 assert( !reg4->is_valid(), "valid halvsies" ); 1251 } else { 1252 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1253 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1254 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1255 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1256 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1257 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1258 } 1259 } 1260 } 1261 } 1262#endif 1263 1264 // Visit each argument. Compute its outgoing register mask. 1265 // Return results now can have 2 bits returned. 1266 // Compute max over all outgoing arguments both per call-site 1267 // and over the entire method. 1268 for( i = 0; i < argcnt; i++ ) { 1269 // Address of incoming argument mask to fill in 1270 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1271 if( !parm_regs[i].first()->is_valid() && 1272 !parm_regs[i].second()->is_valid() ) { 1273 continue; // Avoid Halves 1274 } 1275 // Grab first register, adjust stack slots and insert in mask. 1276 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1277 if (OptoReg::is_valid(reg1)) 1278 rm->Insert( reg1 ); 1279 // Grab second register (if any), adjust stack slots and insert in mask. 1280 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1281 if (OptoReg::is_valid(reg2)) 1282 rm->Insert( reg2 ); 1283 } // End of for all arguments 1284 1285 // Compute number of stack slots needed to restore stack in case of 1286 // Pascal-style argument popping. 1287 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1288 } 1289 1290 // Compute the max stack slot killed by any call. These will not be 1291 // available for debug info, and will be used to adjust FIRST_STACK_mask 1292 // after all call sites have been visited. 1293 if( _out_arg_limit < out_arg_limit_per_call) 1294 _out_arg_limit = out_arg_limit_per_call; 1295 1296 if (mcall) { 1297 // Kill the outgoing argument area, including any non-argument holes and 1298 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1299 // Since the max-per-method covers the max-per-call-site and debug info 1300 // is excluded on the max-per-method basis, debug info cannot land in 1301 // this killed area. 1302 uint r_cnt = mcall->tf()->range()->cnt(); 1303 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1304 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1305 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence"); 1306 } else { 1307 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1308 proj->_rout.Insert(OptoReg::Name(i)); 1309 } 1310 if( proj->_rout.is_NotEmpty() ) 1311 _proj_list.push(proj); 1312 } 1313 // Transfer the safepoint information from the call to the mcall 1314 // Move the JVMState list 1315 msfpt->set_jvms(sfpt->jvms()); 1316 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1317 jvms->set_map(sfpt); 1318 } 1319 1320 // Debug inputs begin just after the last incoming parameter 1321 assert( (mcall == NULL) || (mcall->jvms() == NULL) || 1322 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" ); 1323 1324 // Move the OopMap 1325 msfpt->_oop_map = sfpt->_oop_map; 1326 1327 // Registers killed by the call are set in the local scheduling pass 1328 // of Global Code Motion. 1329 return msfpt; 1330} 1331 1332//---------------------------match_tree---------------------------------------- 1333// Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1334// of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1335// making GotoNodes while building the CFG and in init_spill_mask() to identify 1336// a Load's result RegMask for memoization in idealreg2regmask[] 1337MachNode *Matcher::match_tree( const Node *n ) { 1338 assert( n->Opcode() != Op_Phi, "cannot match" ); 1339 assert( !n->is_block_start(), "cannot match" ); 1340 // Set the mark for all locally allocated State objects. 1341 // When this call returns, the _states_arena arena will be reset 1342 // freeing all State objects. 1343 ResourceMark rm( &_states_arena ); 1344 1345 LabelRootDepth = 0; 1346 1347 // StoreNodes require their Memory input to match any LoadNodes 1348 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1349#ifdef ASSERT 1350 Node* save_mem_node = _mem_node; 1351 _mem_node = n->is_Store() ? (Node*)n : NULL; 1352#endif 1353 // State object for root node of match tree 1354 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1355 State *s = new (&_states_arena) State; 1356 s->_kids[0] = NULL; 1357 s->_kids[1] = NULL; 1358 s->_leaf = (Node*)n; 1359 // Label the input tree, allocating labels from top-level arena 1360 Label_Root( n, s, n->in(0), mem ); 1361 if (C->failing()) return NULL; 1362 1363 // The minimum cost match for the whole tree is found at the root State 1364 uint mincost = max_juint; 1365 uint cost = max_juint; 1366 uint i; 1367 for( i = 0; i < NUM_OPERANDS; i++ ) { 1368 if( s->valid(i) && // valid entry and 1369 s->_cost[i] < cost && // low cost and 1370 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1371 cost = s->_cost[mincost=i]; 1372 } 1373 if (mincost == max_juint) { 1374#ifndef PRODUCT 1375 tty->print("No matching rule for:"); 1376 s->dump(); 1377#endif 1378 Matcher::soft_match_failure(); 1379 return NULL; 1380 } 1381 // Reduce input tree based upon the state labels to machine Nodes 1382 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1383#ifdef ASSERT 1384 _old2new_map.map(n->_idx, m); 1385 _new2old_map.map(m->_idx, (Node*)n); 1386#endif 1387 1388 // Add any Matcher-ignored edges 1389 uint cnt = n->req(); 1390 uint start = 1; 1391 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1392 if( n->is_AddP() ) { 1393 assert( mem == (Node*)1, "" ); 1394 start = AddPNode::Base+1; 1395 } 1396 for( i = start; i < cnt; i++ ) { 1397 if( !n->match_edge(i) ) { 1398 if( i < m->req() ) 1399 m->ins_req( i, n->in(i) ); 1400 else 1401 m->add_req( n->in(i) ); 1402 } 1403 } 1404 1405 debug_only( _mem_node = save_mem_node; ) 1406 return m; 1407} 1408 1409 1410//------------------------------match_into_reg--------------------------------- 1411// Choose to either match this Node in a register or part of the current 1412// match tree. Return true for requiring a register and false for matching 1413// as part of the current match tree. 1414static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1415 1416 const Type *t = m->bottom_type(); 1417 1418 if (t->singleton()) { 1419 // Never force constants into registers. Allow them to match as 1420 // constants or registers. Copies of the same value will share 1421 // the same register. See find_shared_node. 1422 return false; 1423 } else { // Not a constant 1424 // Stop recursion if they have different Controls. 1425 Node* m_control = m->in(0); 1426 // Control of load's memory can post-dominates load's control. 1427 // So use it since load can't float above its memory. 1428 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1429 if (control && m_control && control != m_control && control != mem_control) { 1430 1431 // Actually, we can live with the most conservative control we 1432 // find, if it post-dominates the others. This allows us to 1433 // pick up load/op/store trees where the load can float a little 1434 // above the store. 1435 Node *x = control; 1436 const uint max_scan = 6; // Arbitrary scan cutoff 1437 uint j; 1438 for (j=0; j<max_scan; j++) { 1439 if (x->is_Region()) // Bail out at merge points 1440 return true; 1441 x = x->in(0); 1442 if (x == m_control) // Does 'control' post-dominate 1443 break; // m->in(0)? If so, we can use it 1444 if (x == mem_control) // Does 'control' post-dominate 1445 break; // mem_control? If so, we can use it 1446 } 1447 if (j == max_scan) // No post-domination before scan end? 1448 return true; // Then break the match tree up 1449 } 1450 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1451 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1452 // These are commonly used in address expressions and can 1453 // efficiently fold into them on X64 in some cases. 1454 return false; 1455 } 1456 } 1457 1458 // Not forceable cloning. If shared, put it into a register. 1459 return shared; 1460} 1461 1462 1463//------------------------------Instruction Selection-------------------------- 1464// Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1465// ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1466// things the Matcher does not match (e.g., Memory), and things with different 1467// Controls (hence forced into different blocks). We pass in the Control 1468// selected for this entire State tree. 1469 1470// The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1471// Store and the Load must have identical Memories (as well as identical 1472// pointers). Since the Matcher does not have anything for Memory (and 1473// does not handle DAGs), I have to match the Memory input myself. If the 1474// Tree root is a Store, I require all Loads to have the identical memory. 1475Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1476 // Since Label_Root is a recursive function, its possible that we might run 1477 // out of stack space. See bugs 6272980 & 6227033 for more info. 1478 LabelRootDepth++; 1479 if (LabelRootDepth > MaxLabelRootDepth) { 1480 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth"); 1481 return NULL; 1482 } 1483 uint care = 0; // Edges matcher cares about 1484 uint cnt = n->req(); 1485 uint i = 0; 1486 1487 // Examine children for memory state 1488 // Can only subsume a child into your match-tree if that child's memory state 1489 // is not modified along the path to another input. 1490 // It is unsafe even if the other inputs are separate roots. 1491 Node *input_mem = NULL; 1492 for( i = 1; i < cnt; i++ ) { 1493 if( !n->match_edge(i) ) continue; 1494 Node *m = n->in(i); // Get ith input 1495 assert( m, "expect non-null children" ); 1496 if( m->is_Load() ) { 1497 if( input_mem == NULL ) { 1498 input_mem = m->in(MemNode::Memory); 1499 } else if( input_mem != m->in(MemNode::Memory) ) { 1500 input_mem = NodeSentinel; 1501 } 1502 } 1503 } 1504 1505 for( i = 1; i < cnt; i++ ){// For my children 1506 if( !n->match_edge(i) ) continue; 1507 Node *m = n->in(i); // Get ith input 1508 // Allocate states out of a private arena 1509 State *s = new (&_states_arena) State; 1510 svec->_kids[care++] = s; 1511 assert( care <= 2, "binary only for now" ); 1512 1513 // Recursively label the State tree. 1514 s->_kids[0] = NULL; 1515 s->_kids[1] = NULL; 1516 s->_leaf = m; 1517 1518 // Check for leaves of the State Tree; things that cannot be a part of 1519 // the current tree. If it finds any, that value is matched as a 1520 // register operand. If not, then the normal matching is used. 1521 if( match_into_reg(n, m, control, i, is_shared(m)) || 1522 // 1523 // Stop recursion if this is LoadNode and the root of this tree is a 1524 // StoreNode and the load & store have different memories. 1525 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1526 // Can NOT include the match of a subtree when its memory state 1527 // is used by any of the other subtrees 1528 (input_mem == NodeSentinel) ) { 1529#ifndef PRODUCT 1530 // Print when we exclude matching due to different memory states at input-loads 1531 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1532 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) { 1533 tty->print_cr("invalid input_mem"); 1534 } 1535#endif 1536 // Switch to a register-only opcode; this value must be in a register 1537 // and cannot be subsumed as part of a larger instruction. 1538 s->DFA( m->ideal_reg(), m ); 1539 1540 } else { 1541 // If match tree has no control and we do, adopt it for entire tree 1542 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1543 control = m->in(0); // Pick up control 1544 // Else match as a normal part of the match tree. 1545 control = Label_Root(m,s,control,mem); 1546 if (C->failing()) return NULL; 1547 } 1548 } 1549 1550 1551 // Call DFA to match this node, and return 1552 svec->DFA( n->Opcode(), n ); 1553 1554#ifdef ASSERT 1555 uint x; 1556 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1557 if( svec->valid(x) ) 1558 break; 1559 1560 if (x >= _LAST_MACH_OPER) { 1561 n->dump(); 1562 svec->dump(); 1563 assert( false, "bad AD file" ); 1564 } 1565#endif 1566 return control; 1567} 1568 1569 1570// Con nodes reduced using the same rule can share their MachNode 1571// which reduces the number of copies of a constant in the final 1572// program. The register allocator is free to split uses later to 1573// split live ranges. 1574MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1575 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; 1576 1577 // See if this Con has already been reduced using this rule. 1578 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1579 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1580 if (last != NULL && rule == last->rule()) { 1581 // Don't expect control change for DecodeN 1582 if (leaf->is_DecodeNarrowPtr()) 1583 return last; 1584 // Get the new space root. 1585 Node* xroot = new_node(C->root()); 1586 if (xroot == NULL) { 1587 // This shouldn't happen give the order of matching. 1588 return NULL; 1589 } 1590 1591 // Shared constants need to have their control be root so they 1592 // can be scheduled properly. 1593 Node* control = last->in(0); 1594 if (control != xroot) { 1595 if (control == NULL || control == C->root()) { 1596 last->set_req(0, xroot); 1597 } else { 1598 assert(false, "unexpected control"); 1599 return NULL; 1600 } 1601 } 1602 return last; 1603 } 1604 return NULL; 1605} 1606 1607 1608//------------------------------ReduceInst------------------------------------- 1609// Reduce a State tree (with given Control) into a tree of MachNodes. 1610// This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1611// complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1612// Each MachNode has a number of complicated MachOper operands; each 1613// MachOper also covers a further tree of Ideal Nodes. 1614 1615// The root of the Ideal match tree is always an instruction, so we enter 1616// the recursion here. After building the MachNode, we need to recurse 1617// the tree checking for these cases: 1618// (1) Child is an instruction - 1619// Build the instruction (recursively), add it as an edge. 1620// Build a simple operand (register) to hold the result of the instruction. 1621// (2) Child is an interior part of an instruction - 1622// Skip over it (do nothing) 1623// (3) Child is the start of a operand - 1624// Build the operand, place it inside the instruction 1625// Call ReduceOper. 1626MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1627 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1628 1629 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1630 if (shared_node != NULL) { 1631 return shared_node; 1632 } 1633 1634 // Build the object to represent this state & prepare for recursive calls 1635 MachNode *mach = s->MachNodeGenerator( rule, C ); 1636 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C ); 1637 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1638 Node *leaf = s->_leaf; 1639 // Check for instruction or instruction chain rule 1640 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1641 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1642 "duplicating node that's already been matched"); 1643 // Instruction 1644 mach->add_req( leaf->in(0) ); // Set initial control 1645 // Reduce interior of complex instruction 1646 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1647 } else { 1648 // Instruction chain rules are data-dependent on their inputs 1649 mach->add_req(0); // Set initial control to none 1650 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1651 } 1652 1653 // If a Memory was used, insert a Memory edge 1654 if( mem != (Node*)1 ) { 1655 mach->ins_req(MemNode::Memory,mem); 1656#ifdef ASSERT 1657 // Verify adr type after matching memory operation 1658 const MachOper* oper = mach->memory_operand(); 1659 if (oper != NULL && oper != (MachOper*)-1) { 1660 // It has a unique memory operand. Find corresponding ideal mem node. 1661 Node* m = NULL; 1662 if (leaf->is_Mem()) { 1663 m = leaf; 1664 } else { 1665 m = _mem_node; 1666 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1667 } 1668 const Type* mach_at = mach->adr_type(); 1669 // DecodeN node consumed by an address may have different type 1670 // then its input. Don't compare types for such case. 1671 if (m->adr_type() != mach_at && 1672 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1673 m->in(MemNode::Address)->is_AddP() && 1674 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() || 1675 m->in(MemNode::Address)->is_AddP() && 1676 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1677 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) { 1678 mach_at = m->adr_type(); 1679 } 1680 if (m->adr_type() != mach_at) { 1681 m->dump(); 1682 tty->print_cr("mach:"); 1683 mach->dump(1); 1684 } 1685 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1686 } 1687#endif 1688 } 1689 1690 // If the _leaf is an AddP, insert the base edge 1691 if( leaf->is_AddP() ) 1692 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1693 1694 uint num_proj = _proj_list.size(); 1695 1696 // Perform any 1-to-many expansions required 1697 MachNode *ex = mach->Expand(s,_proj_list, mem); 1698 if( ex != mach ) { 1699 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1700 if( ex->in(1)->is_Con() ) 1701 ex->in(1)->set_req(0, C->root()); 1702 // Remove old node from the graph 1703 for( uint i=0; i<mach->req(); i++ ) { 1704 mach->set_req(i,NULL); 1705 } 1706#ifdef ASSERT 1707 _new2old_map.map(ex->_idx, s->_leaf); 1708#endif 1709 } 1710 1711 // PhaseChaitin::fixup_spills will sometimes generate spill code 1712 // via the matcher. By the time, nodes have been wired into the CFG, 1713 // and any further nodes generated by expand rules will be left hanging 1714 // in space, and will not get emitted as output code. Catch this. 1715 // Also, catch any new register allocation constraints ("projections") 1716 // generated belatedly during spill code generation. 1717 if (_allocation_started) { 1718 guarantee(ex == mach, "no expand rules during spill generation"); 1719 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation"); 1720 } 1721 1722 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1723 // Record the con for sharing 1724 _shared_nodes.map(leaf->_idx, ex); 1725 } 1726 1727 return ex; 1728} 1729 1730void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1731 // 'op' is what I am expecting to receive 1732 int op = _leftOp[rule]; 1733 // Operand type to catch childs result 1734 // This is what my child will give me. 1735 int opnd_class_instance = s->_rule[op]; 1736 // Choose between operand class or not. 1737 // This is what I will receive. 1738 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1739 // New rule for child. Chase operand classes to get the actual rule. 1740 int newrule = s->_rule[catch_op]; 1741 1742 if( newrule < NUM_OPERANDS ) { 1743 // Chain from operand or operand class, may be output of shared node 1744 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1745 "Bad AD file: Instruction chain rule must chain from operand"); 1746 // Insert operand into array of operands for this instruction 1747 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C ); 1748 1749 ReduceOper( s, newrule, mem, mach ); 1750 } else { 1751 // Chain from the result of an instruction 1752 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1753 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C ); 1754 Node *mem1 = (Node*)1; 1755 debug_only(Node *save_mem_node = _mem_node;) 1756 mach->add_req( ReduceInst(s, newrule, mem1) ); 1757 debug_only(_mem_node = save_mem_node;) 1758 } 1759 return; 1760} 1761 1762 1763uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1764 if( s->_leaf->is_Load() ) { 1765 Node *mem2 = s->_leaf->in(MemNode::Memory); 1766 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1767 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1768 mem = mem2; 1769 } 1770 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1771 if( mach->in(0) == NULL ) 1772 mach->set_req(0, s->_leaf->in(0)); 1773 } 1774 1775 // Now recursively walk the state tree & add operand list. 1776 for( uint i=0; i<2; i++ ) { // binary tree 1777 State *newstate = s->_kids[i]; 1778 if( newstate == NULL ) break; // Might only have 1 child 1779 // 'op' is what I am expecting to receive 1780 int op; 1781 if( i == 0 ) { 1782 op = _leftOp[rule]; 1783 } else { 1784 op = _rightOp[rule]; 1785 } 1786 // Operand type to catch childs result 1787 // This is what my child will give me. 1788 int opnd_class_instance = newstate->_rule[op]; 1789 // Choose between operand class or not. 1790 // This is what I will receive. 1791 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1792 // New rule for child. Chase operand classes to get the actual rule. 1793 int newrule = newstate->_rule[catch_op]; 1794 1795 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1796 // Operand/operandClass 1797 // Insert operand into array of operands for this instruction 1798 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C ); 1799 ReduceOper( newstate, newrule, mem, mach ); 1800 1801 } else { // Child is internal operand or new instruction 1802 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1803 // internal operand --> call ReduceInst_Interior 1804 // Interior of complex instruction. Do nothing but recurse. 1805 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1806 } else { 1807 // instruction --> call build operand( ) to catch result 1808 // --> ReduceInst( newrule ) 1809 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C ); 1810 Node *mem1 = (Node*)1; 1811 debug_only(Node *save_mem_node = _mem_node;) 1812 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1813 debug_only(_mem_node = save_mem_node;) 1814 } 1815 } 1816 assert( mach->_opnds[num_opnds-1], "" ); 1817 } 1818 return num_opnds; 1819} 1820 1821// This routine walks the interior of possible complex operands. 1822// At each point we check our children in the match tree: 1823// (1) No children - 1824// We are a leaf; add _leaf field as an input to the MachNode 1825// (2) Child is an internal operand - 1826// Skip over it ( do nothing ) 1827// (3) Child is an instruction - 1828// Call ReduceInst recursively and 1829// and instruction as an input to the MachNode 1830void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1831 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1832 State *kid = s->_kids[0]; 1833 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1834 1835 // Leaf? And not subsumed? 1836 if( kid == NULL && !_swallowed[rule] ) { 1837 mach->add_req( s->_leaf ); // Add leaf pointer 1838 return; // Bail out 1839 } 1840 1841 if( s->_leaf->is_Load() ) { 1842 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1843 mem = s->_leaf->in(MemNode::Memory); 1844 debug_only(_mem_node = s->_leaf;) 1845 } 1846 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1847 if( !mach->in(0) ) 1848 mach->set_req(0,s->_leaf->in(0)); 1849 else { 1850 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1851 } 1852 } 1853 1854 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1855 int newrule; 1856 if( i == 0) 1857 newrule = kid->_rule[_leftOp[rule]]; 1858 else 1859 newrule = kid->_rule[_rightOp[rule]]; 1860 1861 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1862 // Internal operand; recurse but do nothing else 1863 ReduceOper( kid, newrule, mem, mach ); 1864 1865 } else { // Child is a new instruction 1866 // Reduce the instruction, and add a direct pointer from this 1867 // machine instruction to the newly reduced one. 1868 Node *mem1 = (Node*)1; 1869 debug_only(Node *save_mem_node = _mem_node;) 1870 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1871 debug_only(_mem_node = save_mem_node;) 1872 } 1873 } 1874} 1875 1876 1877// ------------------------------------------------------------------------- 1878// Java-Java calling convention 1879// (what you use when Java calls Java) 1880 1881//------------------------------find_receiver---------------------------------- 1882// For a given signature, return the OptoReg for parameter 0. 1883OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1884 VMRegPair regs; 1885 BasicType sig_bt = T_OBJECT; 1886 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1887 // Return argument 0 register. In the LP64 build pointers 1888 // take 2 registers, but the VM wants only the 'main' name. 1889 return OptoReg::as_OptoReg(regs.first()); 1890} 1891 1892// A method-klass-holder may be passed in the inline_cache_reg 1893// and then expanded into the inline_cache_reg and a method_oop register 1894// defined in ad_<arch>.cpp 1895 1896 1897//------------------------------find_shared------------------------------------ 1898// Set bits if Node is shared or otherwise a root 1899void Matcher::find_shared( Node *n ) { 1900 // Allocate stack of size C->unique() * 2 to avoid frequent realloc 1901 MStack mstack(C->unique() * 2); 1902 // Mark nodes as address_visited if they are inputs to an address expression 1903 VectorSet address_visited(Thread::current()->resource_area()); 1904 mstack.push(n, Visit); // Don't need to pre-visit root node 1905 while (mstack.is_nonempty()) { 1906 n = mstack.node(); // Leave node on stack 1907 Node_State nstate = mstack.state(); 1908 uint nop = n->Opcode(); 1909 if (nstate == Pre_Visit) { 1910 if (address_visited.test(n->_idx)) { // Visited in address already? 1911 // Flag as visited and shared now. 1912 set_visited(n); 1913 } 1914 if (is_visited(n)) { // Visited already? 1915 // Node is shared and has no reason to clone. Flag it as shared. 1916 // This causes it to match into a register for the sharing. 1917 set_shared(n); // Flag as shared and 1918 mstack.pop(); // remove node from stack 1919 continue; 1920 } 1921 nstate = Visit; // Not already visited; so visit now 1922 } 1923 if (nstate == Visit) { 1924 mstack.set_state(Post_Visit); 1925 set_visited(n); // Flag as visited now 1926 bool mem_op = false; 1927 1928 switch( nop ) { // Handle some opcodes special 1929 case Op_Phi: // Treat Phis as shared roots 1930 case Op_Parm: 1931 case Op_Proj: // All handled specially during matching 1932 case Op_SafePointScalarObject: 1933 set_shared(n); 1934 set_dontcare(n); 1935 break; 1936 case Op_If: 1937 case Op_CountedLoopEnd: 1938 mstack.set_state(Alt_Post_Visit); // Alternative way 1939 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 1940 // with matching cmp/branch in 1 instruction. The Matcher needs the 1941 // Bool and CmpX side-by-side, because it can only get at constants 1942 // that are at the leaves of Match trees, and the Bool's condition acts 1943 // as a constant here. 1944 mstack.push(n->in(1), Visit); // Clone the Bool 1945 mstack.push(n->in(0), Pre_Visit); // Visit control input 1946 continue; // while (mstack.is_nonempty()) 1947 case Op_ConvI2D: // These forms efficiently match with a prior 1948 case Op_ConvI2F: // Load but not a following Store 1949 if( n->in(1)->is_Load() && // Prior load 1950 n->outcnt() == 1 && // Not already shared 1951 n->unique_out()->is_Store() ) // Following store 1952 set_shared(n); // Force it to be a root 1953 break; 1954 case Op_ReverseBytesI: 1955 case Op_ReverseBytesL: 1956 if( n->in(1)->is_Load() && // Prior load 1957 n->outcnt() == 1 ) // Not already shared 1958 set_shared(n); // Force it to be a root 1959 break; 1960 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 1961 case Op_IfFalse: 1962 case Op_IfTrue: 1963 case Op_MachProj: 1964 case Op_MergeMem: 1965 case Op_Catch: 1966 case Op_CatchProj: 1967 case Op_CProj: 1968 case Op_JumpProj: 1969 case Op_JProj: 1970 case Op_NeverBranch: 1971 set_dontcare(n); 1972 break; 1973 case Op_Jump: 1974 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 1975 mstack.push(n->in(0), Pre_Visit); // Visit Control input 1976 continue; // while (mstack.is_nonempty()) 1977 case Op_StrComp: 1978 case Op_StrEquals: 1979 case Op_StrIndexOf: 1980 case Op_AryEq: 1981 case Op_EncodeISOArray: 1982 set_shared(n); // Force result into register (it will be anyways) 1983 break; 1984 case Op_ConP: { // Convert pointers above the centerline to NUL 1985 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 1986 const TypePtr* tp = tn->type()->is_ptr(); 1987 if (tp->_ptr == TypePtr::AnyNull) { 1988 tn->set_type(TypePtr::NULL_PTR); 1989 } 1990 break; 1991 } 1992 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 1993 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 1994 const TypePtr* tp = tn->type()->make_ptr(); 1995 if (tp && tp->_ptr == TypePtr::AnyNull) { 1996 tn->set_type(TypeNarrowOop::NULL_PTR); 1997 } 1998 break; 1999 } 2000 case Op_Binary: // These are introduced in the Post_Visit state. 2001 ShouldNotReachHere(); 2002 break; 2003 case Op_ClearArray: 2004 case Op_SafePoint: 2005 mem_op = true; 2006 break; 2007 default: 2008 if( n->is_Store() ) { 2009 // Do match stores, despite no ideal reg 2010 mem_op = true; 2011 break; 2012 } 2013 if( n->is_Mem() ) { // Loads and LoadStores 2014 mem_op = true; 2015 // Loads must be root of match tree due to prior load conflict 2016 if( C->subsume_loads() == false ) 2017 set_shared(n); 2018 } 2019 // Fall into default case 2020 if( !n->ideal_reg() ) 2021 set_dontcare(n); // Unmatchable Nodes 2022 } // end_switch 2023 2024 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2025 Node *m = n->in(i); // Get ith input 2026 if (m == NULL) continue; // Ignore NULLs 2027 uint mop = m->Opcode(); 2028 2029 // Must clone all producers of flags, or we will not match correctly. 2030 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2031 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2032 // are also there, so we may match a float-branch to int-flags and 2033 // expect the allocator to haul the flags from the int-side to the 2034 // fp-side. No can do. 2035 if( _must_clone[mop] ) { 2036 mstack.push(m, Visit); 2037 continue; // for(int i = ...) 2038 } 2039 2040 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) { 2041 // Bases used in addresses must be shared but since 2042 // they are shared through a DecodeN they may appear 2043 // to have a single use so force sharing here. 2044 set_shared(m->in(AddPNode::Base)->in(1)); 2045 } 2046 2047 // Clone addressing expressions as they are "free" in memory access instructions 2048 if( mem_op && i == MemNode::Address && mop == Op_AddP ) { 2049 // Some inputs for address expression are not put on stack 2050 // to avoid marking them as shared and forcing them into register 2051 // if they are used only in address expressions. 2052 // But they should be marked as shared if there are other uses 2053 // besides address expressions. 2054 2055 Node *off = m->in(AddPNode::Offset); 2056 if( off->is_Con() && 2057 // When there are other uses besides address expressions 2058 // put it on stack and mark as shared. 2059 !is_visited(m) ) { 2060 address_visited.test_set(m->_idx); // Flag as address_visited 2061 Node *adr = m->in(AddPNode::Address); 2062 2063 // Intel, ARM and friends can handle 2 adds in addressing mode 2064 if( clone_shift_expressions && adr->is_AddP() && 2065 // AtomicAdd is not an addressing expression. 2066 // Cheap to find it by looking for screwy base. 2067 !adr->in(AddPNode::Base)->is_top() && 2068 // Are there other uses besides address expressions? 2069 !is_visited(adr) ) { 2070 address_visited.set(adr->_idx); // Flag as address_visited 2071 Node *shift = adr->in(AddPNode::Offset); 2072 // Check for shift by small constant as well 2073 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() && 2074 shift->in(2)->get_int() <= 3 && 2075 // Are there other uses besides address expressions? 2076 !is_visited(shift) ) { 2077 address_visited.set(shift->_idx); // Flag as address_visited 2078 mstack.push(shift->in(2), Visit); 2079 Node *conv = shift->in(1); 2080#ifdef _LP64 2081 // Allow Matcher to match the rule which bypass 2082 // ConvI2L operation for an array index on LP64 2083 // if the index value is positive. 2084 if( conv->Opcode() == Op_ConvI2L && 2085 conv->as_Type()->type()->is_long()->_lo >= 0 && 2086 // Are there other uses besides address expressions? 2087 !is_visited(conv) ) { 2088 address_visited.set(conv->_idx); // Flag as address_visited 2089 mstack.push(conv->in(1), Pre_Visit); 2090 } else 2091#endif 2092 mstack.push(conv, Pre_Visit); 2093 } else { 2094 mstack.push(shift, Pre_Visit); 2095 } 2096 mstack.push(adr->in(AddPNode::Address), Pre_Visit); 2097 mstack.push(adr->in(AddPNode::Base), Pre_Visit); 2098 } else { // Sparc, Alpha, PPC and friends 2099 mstack.push(adr, Pre_Visit); 2100 } 2101 2102 // Clone X+offset as it also folds into most addressing expressions 2103 mstack.push(off, Visit); 2104 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2105 continue; // for(int i = ...) 2106 } // if( off->is_Con() ) 2107 } // if( mem_op && 2108 mstack.push(m, Pre_Visit); 2109 } // for(int i = ...) 2110 } 2111 else if (nstate == Alt_Post_Visit) { 2112 mstack.pop(); // Remove node from stack 2113 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2114 // shared and all users of the Bool need to move the Cmp in parallel. 2115 // This leaves both the Bool and the If pointing at the Cmp. To 2116 // prevent the Matcher from trying to Match the Cmp along both paths 2117 // BoolNode::match_edge always returns a zero. 2118 2119 // We reorder the Op_If in a pre-order manner, so we can visit without 2120 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2121 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2122 } 2123 else if (nstate == Post_Visit) { 2124 mstack.pop(); // Remove node from stack 2125 2126 // Now hack a few special opcodes 2127 switch( n->Opcode() ) { // Handle some opcodes special 2128 case Op_StorePConditional: 2129 case Op_StoreIConditional: 2130 case Op_StoreLConditional: 2131 case Op_CompareAndSwapI: 2132 case Op_CompareAndSwapL: 2133 case Op_CompareAndSwapP: 2134 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2135 Node *newval = n->in(MemNode::ValueIn ); 2136 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2137 Node *pair = new (C) BinaryNode( oldval, newval ); 2138 n->set_req(MemNode::ValueIn,pair); 2139 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2140 break; 2141 } 2142 case Op_CMoveD: // Convert trinary to binary-tree 2143 case Op_CMoveF: 2144 case Op_CMoveI: 2145 case Op_CMoveL: 2146 case Op_CMoveN: 2147 case Op_CMoveP: { 2148 // Restructure into a binary tree for Matching. It's possible that 2149 // we could move this code up next to the graph reshaping for IfNodes 2150 // or vice-versa, but I do not want to debug this for Ladybird. 2151 // 10/2/2000 CNC. 2152 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1)); 2153 n->set_req(1,pair1); 2154 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3)); 2155 n->set_req(2,pair2); 2156 n->del_req(3); 2157 break; 2158 } 2159 case Op_LoopLimit: { 2160 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2)); 2161 n->set_req(1,pair1); 2162 n->set_req(2,n->in(3)); 2163 n->del_req(3); 2164 break; 2165 } 2166 case Op_StrEquals: { 2167 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3)); 2168 n->set_req(2,pair1); 2169 n->set_req(3,n->in(4)); 2170 n->del_req(4); 2171 break; 2172 } 2173 case Op_StrComp: 2174 case Op_StrIndexOf: { 2175 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3)); 2176 n->set_req(2,pair1); 2177 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5)); 2178 n->set_req(3,pair2); 2179 n->del_req(5); 2180 n->del_req(4); 2181 break; 2182 } 2183 case Op_EncodeISOArray: { 2184 // Restructure into a binary tree for Matching. 2185 Node* pair = new (C) BinaryNode(n->in(3), n->in(4)); 2186 n->set_req(3, pair); 2187 n->del_req(4); 2188 break; 2189 } 2190 default: 2191 break; 2192 } 2193 } 2194 else { 2195 ShouldNotReachHere(); 2196 } 2197 } // end of while (mstack.is_nonempty()) 2198} 2199 2200#ifdef ASSERT 2201// machine-independent root to machine-dependent root 2202void Matcher::dump_old2new_map() { 2203 _old2new_map.dump(); 2204} 2205#endif 2206 2207//---------------------------collect_null_checks------------------------------- 2208// Find null checks in the ideal graph; write a machine-specific node for 2209// it. Used by later implicit-null-check handling. Actually collects 2210// either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2211// value being tested. 2212void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2213 Node *iff = proj->in(0); 2214 if( iff->Opcode() == Op_If ) { 2215 // During matching If's have Bool & Cmp side-by-side 2216 BoolNode *b = iff->in(1)->as_Bool(); 2217 Node *cmp = iff->in(2); 2218 int opc = cmp->Opcode(); 2219 if (opc != Op_CmpP && opc != Op_CmpN) return; 2220 2221 const Type* ct = cmp->in(2)->bottom_type(); 2222 if (ct == TypePtr::NULL_PTR || 2223 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2224 2225 bool push_it = false; 2226 if( proj->Opcode() == Op_IfTrue ) { 2227 extern int all_null_checks_found; 2228 all_null_checks_found++; 2229 if( b->_test._test == BoolTest::ne ) { 2230 push_it = true; 2231 } 2232 } else { 2233 assert( proj->Opcode() == Op_IfFalse, "" ); 2234 if( b->_test._test == BoolTest::eq ) { 2235 push_it = true; 2236 } 2237 } 2238 if( push_it ) { 2239 _null_check_tests.push(proj); 2240 Node* val = cmp->in(1); 2241#ifdef _LP64 2242 if (val->bottom_type()->isa_narrowoop() && 2243 !Matcher::narrow_oop_use_complex_address()) { 2244 // 2245 // Look for DecodeN node which should be pinned to orig_proj. 2246 // On platforms (Sparc) which can not handle 2 adds 2247 // in addressing mode we have to keep a DecodeN node and 2248 // use it to do implicit NULL check in address. 2249 // 2250 // DecodeN node was pinned to non-null path (orig_proj) during 2251 // CastPP transformation in final_graph_reshaping_impl(). 2252 // 2253 uint cnt = orig_proj->outcnt(); 2254 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2255 Node* d = orig_proj->raw_out(i); 2256 if (d->is_DecodeN() && d->in(1) == val) { 2257 val = d; 2258 val->set_req(0, NULL); // Unpin now. 2259 // Mark this as special case to distinguish from 2260 // a regular case: CmpP(DecodeN, NULL). 2261 val = (Node*)(((intptr_t)val) | 1); 2262 break; 2263 } 2264 } 2265 } 2266#endif 2267 _null_check_tests.push(val); 2268 } 2269 } 2270 } 2271} 2272 2273//---------------------------validate_null_checks------------------------------ 2274// Its possible that the value being NULL checked is not the root of a match 2275// tree. If so, I cannot use the value in an implicit null check. 2276void Matcher::validate_null_checks( ) { 2277 uint cnt = _null_check_tests.size(); 2278 for( uint i=0; i < cnt; i+=2 ) { 2279 Node *test = _null_check_tests[i]; 2280 Node *val = _null_check_tests[i+1]; 2281 bool is_decoden = ((intptr_t)val) & 1; 2282 val = (Node*)(((intptr_t)val) & ~1); 2283 if (has_new_node(val)) { 2284 Node* new_val = new_node(val); 2285 if (is_decoden) { 2286 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); 2287 // Note: new_val may have a control edge if 2288 // the original ideal node DecodeN was matched before 2289 // it was unpinned in Matcher::collect_null_checks(). 2290 // Unpin the mach node and mark it. 2291 new_val->set_req(0, NULL); 2292 new_val = (Node*)(((intptr_t)new_val) | 1); 2293 } 2294 // Is a match-tree root, so replace with the matched value 2295 _null_check_tests.map(i+1, new_val); 2296 } else { 2297 // Yank from candidate list 2298 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2299 _null_check_tests.map(i,_null_check_tests[--cnt]); 2300 _null_check_tests.pop(); 2301 _null_check_tests.pop(); 2302 i-=2; 2303 } 2304 } 2305} 2306 2307// Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2308// atomic instruction acting as a store_load barrier without any 2309// intervening volatile load, and thus we don't need a barrier here. 2310// We retain the Node to act as a compiler ordering barrier. 2311bool Matcher::post_store_load_barrier(const Node *vmb) { 2312 Compile *C = Compile::current(); 2313 assert( vmb->is_MemBar(), "" ); 2314 assert( vmb->Opcode() != Op_MemBarAcquire, "" ); 2315 const MemBarNode *mem = (const MemBarNode*)vmb; 2316 2317 // Get the Proj node, ctrl, that can be used to iterate forward 2318 Node *ctrl = NULL; 2319 DUIterator_Fast imax, i = mem->fast_outs(imax); 2320 while( true ) { 2321 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found 2322 assert( ctrl->is_Proj(), "only projections here" ); 2323 ProjNode *proj = (ProjNode*)ctrl; 2324 if( proj->_con == TypeFunc::Control && 2325 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only 2326 break; 2327 i++; 2328 } 2329 2330 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) { 2331 Node *x = ctrl->fast_out(j); 2332 int xop = x->Opcode(); 2333 2334 // We don't need current barrier if we see another or a lock 2335 // before seeing volatile load. 2336 // 2337 // Op_Fastunlock previously appeared in the Op_* list below. 2338 // With the advent of 1-0 lock operations we're no longer guaranteed 2339 // that a monitor exit operation contains a serializing instruction. 2340 2341 if (xop == Op_MemBarVolatile || 2342 xop == Op_FastLock || 2343 xop == Op_CompareAndSwapL || 2344 xop == Op_CompareAndSwapP || 2345 xop == Op_CompareAndSwapN || 2346 xop == Op_CompareAndSwapI) 2347 return true; 2348 2349 if (x->is_MemBar()) { 2350 // We must retain this membar if there is an upcoming volatile 2351 // load, which will be preceded by acquire membar. 2352 if (xop == Op_MemBarAcquire) 2353 return false; 2354 // For other kinds of barriers, check by pretending we 2355 // are them, and seeing if we can be removed. 2356 else 2357 return post_store_load_barrier((const MemBarNode*)x); 2358 } 2359 2360 // Delicate code to detect case of an upcoming fastlock block 2361 if( x->is_If() && x->req() > 1 && 2362 !C->node_arena()->contains(x) ) { // Unmatched old-space only 2363 Node *iff = x; 2364 Node *bol = iff->in(1); 2365 // The iff might be some random subclass of If or bol might be Con-Top 2366 if (!bol->is_Bool()) return false; 2367 assert( bol->req() > 1, "" ); 2368 return (bol->in(1)->Opcode() == Op_FastUnlock); 2369 } 2370 // probably not necessary to check for these 2371 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) 2372 return false; 2373 } 2374 return false; 2375} 2376 2377//============================================================================= 2378//---------------------------State--------------------------------------------- 2379State::State(void) { 2380#ifdef ASSERT 2381 _id = 0; 2382 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2383 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2384 //memset(_cost, -1, sizeof(_cost)); 2385 //memset(_rule, -1, sizeof(_rule)); 2386#endif 2387 memset(_valid, 0, sizeof(_valid)); 2388} 2389 2390#ifdef ASSERT 2391State::~State() { 2392 _id = 99; 2393 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2394 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2395 memset(_cost, -3, sizeof(_cost)); 2396 memset(_rule, -3, sizeof(_rule)); 2397} 2398#endif 2399 2400#ifndef PRODUCT 2401//---------------------------dump---------------------------------------------- 2402void State::dump() { 2403 tty->print("\n"); 2404 dump(0); 2405} 2406 2407void State::dump(int depth) { 2408 for( int j = 0; j < depth; j++ ) 2409 tty->print(" "); 2410 tty->print("--N: "); 2411 _leaf->dump(); 2412 uint i; 2413 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2414 // Check for valid entry 2415 if( valid(i) ) { 2416 for( int j = 0; j < depth; j++ ) 2417 tty->print(" "); 2418 assert(_cost[i] != max_juint, "cost must be a valid value"); 2419 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2420 tty->print_cr("%s %d %s", 2421 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2422 } 2423 tty->print_cr(""); 2424 2425 for( i=0; i<2; i++ ) 2426 if( _kids[i] ) 2427 _kids[i]->dump(depth+1); 2428} 2429#endif 2430