c1_LIR.cpp revision 1472:c18cbe5936b8
1/* 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25# include "incls/_precompiled.incl" 26# include "incls/_c1_LIR.cpp.incl" 27 28Register LIR_OprDesc::as_register() const { 29 return FrameMap::cpu_rnr2reg(cpu_regnr()); 30} 31 32Register LIR_OprDesc::as_register_lo() const { 33 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 34} 35 36Register LIR_OprDesc::as_register_hi() const { 37 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 38} 39 40#if defined(X86) 41 42XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 43 return FrameMap::nr2xmmreg(xmm_regnr()); 44} 45 46XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 47 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 48 return FrameMap::nr2xmmreg(xmm_regnrLo()); 49} 50 51#endif // X86 52 53 54#ifdef SPARC 55 56FloatRegister LIR_OprDesc::as_float_reg() const { 57 return FrameMap::nr2floatreg(fpu_regnr()); 58} 59 60FloatRegister LIR_OprDesc::as_double_reg() const { 61 return FrameMap::nr2floatreg(fpu_regnrHi()); 62} 63 64#endif 65 66LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 67 68LIR_Opr LIR_OprFact::value_type(ValueType* type) { 69 ValueTag tag = type->tag(); 70 switch (tag) { 71 case objectTag : { 72 ClassConstant* c = type->as_ClassConstant(); 73 if (c != NULL && !c->value()->is_loaded()) { 74 return LIR_OprFact::oopConst(NULL); 75 } else { 76 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 77 } 78 } 79 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 80 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 81 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 82 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 83 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 84 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 85 } 86} 87 88 89LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 90 switch (type->tag()) { 91 case objectTag: return LIR_OprFact::oopConst(NULL); 92 case addressTag:return LIR_OprFact::addressConst(0); 93 case intTag: return LIR_OprFact::intConst(0); 94 case floatTag: return LIR_OprFact::floatConst(0.0); 95 case longTag: return LIR_OprFact::longConst(0); 96 case doubleTag: return LIR_OprFact::doubleConst(0.0); 97 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 98 } 99 return illegalOpr; 100} 101 102 103 104//--------------------------------------------------- 105 106 107LIR_Address::Scale LIR_Address::scale(BasicType type) { 108 int elem_size = type2aelembytes(type); 109 switch (elem_size) { 110 case 1: return LIR_Address::times_1; 111 case 2: return LIR_Address::times_2; 112 case 4: return LIR_Address::times_4; 113 case 8: return LIR_Address::times_8; 114 } 115 ShouldNotReachHere(); 116 return LIR_Address::times_1; 117} 118 119 120#ifndef PRODUCT 121void LIR_Address::verify() const { 122#ifdef SPARC 123 assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used"); 124 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 125#endif 126#ifdef _LP64 127 assert(base()->is_cpu_register(), "wrong base operand"); 128 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 129 assert(base()->type() == T_OBJECT || base()->type() == T_LONG, 130 "wrong type for addresses"); 131#else 132 assert(base()->is_single_cpu(), "wrong base operand"); 133 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 134 assert(base()->type() == T_OBJECT || base()->type() == T_INT, 135 "wrong type for addresses"); 136#endif 137} 138#endif 139 140 141//--------------------------------------------------- 142 143char LIR_OprDesc::type_char(BasicType t) { 144 switch (t) { 145 case T_ARRAY: 146 t = T_OBJECT; 147 case T_BOOLEAN: 148 case T_CHAR: 149 case T_FLOAT: 150 case T_DOUBLE: 151 case T_BYTE: 152 case T_SHORT: 153 case T_INT: 154 case T_LONG: 155 case T_OBJECT: 156 case T_ADDRESS: 157 case T_VOID: 158 return ::type2char(t); 159 160 case T_ILLEGAL: 161 return '?'; 162 163 default: 164 ShouldNotReachHere(); 165 return '?'; 166 } 167} 168 169#ifndef PRODUCT 170void LIR_OprDesc::validate_type() const { 171 172#ifdef ASSERT 173 if (!is_pointer() && !is_illegal()) { 174 switch (as_BasicType(type_field())) { 175 case T_LONG: 176 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == double_size, "must match"); 177 break; 178 case T_FLOAT: 179 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == single_size, "must match"); 180 break; 181 case T_DOUBLE: 182 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == double_size, "must match"); 183 break; 184 case T_BOOLEAN: 185 case T_CHAR: 186 case T_BYTE: 187 case T_SHORT: 188 case T_INT: 189 case T_OBJECT: 190 case T_ARRAY: 191 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == single_size, "must match"); 192 break; 193 194 case T_ILLEGAL: 195 // XXX TKR also means unknown right now 196 // assert(is_illegal(), "must match"); 197 break; 198 199 default: 200 ShouldNotReachHere(); 201 } 202 } 203#endif 204 205} 206#endif // PRODUCT 207 208 209bool LIR_OprDesc::is_oop() const { 210 if (is_pointer()) { 211 return pointer()->is_oop_pointer(); 212 } else { 213 OprType t= type_field(); 214 assert(t != unknown_type, "not set"); 215 return t == object_type; 216 } 217} 218 219 220 221void LIR_Op2::verify() const { 222#ifdef ASSERT 223 switch (code()) { 224 case lir_cmove: 225 break; 226 227 default: 228 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 229 "can't produce oops from arith"); 230 } 231 232 if (TwoOperandLIRForm) { 233 switch (code()) { 234 case lir_add: 235 case lir_sub: 236 case lir_mul: 237 case lir_mul_strictfp: 238 case lir_div: 239 case lir_div_strictfp: 240 case lir_rem: 241 case lir_logic_and: 242 case lir_logic_or: 243 case lir_logic_xor: 244 case lir_shl: 245 case lir_shr: 246 assert(in_opr1() == result_opr(), "opr1 and result must match"); 247 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 248 break; 249 250 // special handling for lir_ushr because of write barriers 251 case lir_ushr: 252 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 253 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 254 break; 255 256 } 257 } 258#endif 259} 260 261 262LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 263 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 264 , _cond(cond) 265 , _type(type) 266 , _label(block->label()) 267 , _block(block) 268 , _ublock(NULL) 269 , _stub(NULL) { 270} 271 272LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 273 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 274 , _cond(cond) 275 , _type(type) 276 , _label(stub->entry()) 277 , _block(NULL) 278 , _ublock(NULL) 279 , _stub(stub) { 280} 281 282LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 283 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 284 , _cond(cond) 285 , _type(type) 286 , _label(block->label()) 287 , _block(block) 288 , _ublock(ublock) 289 , _stub(NULL) 290{ 291} 292 293void LIR_OpBranch::change_block(BlockBegin* b) { 294 assert(_block != NULL, "must have old block"); 295 assert(_block->label() == label(), "must be equal"); 296 297 _block = b; 298 _label = b->label(); 299} 300 301void LIR_OpBranch::change_ublock(BlockBegin* b) { 302 assert(_ublock != NULL, "must have old block"); 303 _ublock = b; 304} 305 306void LIR_OpBranch::negate_cond() { 307 switch (_cond) { 308 case lir_cond_equal: _cond = lir_cond_notEqual; break; 309 case lir_cond_notEqual: _cond = lir_cond_equal; break; 310 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 311 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 312 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 313 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 314 default: ShouldNotReachHere(); 315 } 316} 317 318 319LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 320 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 321 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 322 CodeStub* stub, 323 ciMethod* profiled_method, 324 int profiled_bci) 325 : LIR_Op(code, result, NULL) 326 , _object(object) 327 , _array(LIR_OprFact::illegalOpr) 328 , _klass(klass) 329 , _tmp1(tmp1) 330 , _tmp2(tmp2) 331 , _tmp3(tmp3) 332 , _fast_check(fast_check) 333 , _stub(stub) 334 , _info_for_patch(info_for_patch) 335 , _info_for_exception(info_for_exception) 336 , _profiled_method(profiled_method) 337 , _profiled_bci(profiled_bci) { 338 if (code == lir_checkcast) { 339 assert(info_for_exception != NULL, "checkcast throws exceptions"); 340 } else if (code == lir_instanceof) { 341 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 342 } else { 343 ShouldNotReachHere(); 344 } 345} 346 347 348 349LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) 350 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 351 , _object(object) 352 , _array(array) 353 , _klass(NULL) 354 , _tmp1(tmp1) 355 , _tmp2(tmp2) 356 , _tmp3(tmp3) 357 , _fast_check(false) 358 , _stub(NULL) 359 , _info_for_patch(NULL) 360 , _info_for_exception(info_for_exception) 361 , _profiled_method(profiled_method) 362 , _profiled_bci(profiled_bci) { 363 if (code == lir_store_check) { 364 _stub = new ArrayStoreExceptionStub(info_for_exception); 365 assert(info_for_exception != NULL, "store_check throws exceptions"); 366 } else { 367 ShouldNotReachHere(); 368 } 369} 370 371 372LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 373 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 374 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 375 , _tmp(tmp) 376 , _src(src) 377 , _src_pos(src_pos) 378 , _dst(dst) 379 , _dst_pos(dst_pos) 380 , _flags(flags) 381 , _expected_type(expected_type) 382 , _length(length) { 383 _stub = new ArrayCopyStub(this); 384} 385 386 387//-------------------verify-------------------------- 388 389void LIR_Op1::verify() const { 390 switch(code()) { 391 case lir_move: 392 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 393 break; 394 case lir_null_check: 395 assert(in_opr()->is_register(), "must be"); 396 break; 397 case lir_return: 398 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 399 break; 400 } 401} 402 403void LIR_OpRTCall::verify() const { 404 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 405} 406 407//-------------------visits-------------------------- 408 409// complete rework of LIR instruction visitor. 410// The virtual calls for each instruction type is replaced by a big 411// switch that adds the operands for each instruction 412 413void LIR_OpVisitState::visit(LIR_Op* op) { 414 // copy information from the LIR_Op 415 reset(); 416 set_op(op); 417 418 switch (op->code()) { 419 420// LIR_Op0 421 case lir_word_align: // result and info always invalid 422 case lir_backwardbranch_target: // result and info always invalid 423 case lir_build_frame: // result and info always invalid 424 case lir_fpop_raw: // result and info always invalid 425 case lir_24bit_FPU: // result and info always invalid 426 case lir_reset_FPU: // result and info always invalid 427 case lir_breakpoint: // result and info always invalid 428 case lir_membar: // result and info always invalid 429 case lir_membar_acquire: // result and info always invalid 430 case lir_membar_release: // result and info always invalid 431 { 432 assert(op->as_Op0() != NULL, "must be"); 433 assert(op->_info == NULL, "info not used by this instruction"); 434 assert(op->_result->is_illegal(), "not used"); 435 break; 436 } 437 438 case lir_nop: // may have info, result always invalid 439 case lir_std_entry: // may have result, info always invalid 440 case lir_osr_entry: // may have result, info always invalid 441 case lir_get_thread: // may have result, info always invalid 442 { 443 assert(op->as_Op0() != NULL, "must be"); 444 if (op->_info != NULL) do_info(op->_info); 445 if (op->_result->is_valid()) do_output(op->_result); 446 break; 447 } 448 449 450// LIR_OpLabel 451 case lir_label: // result and info always invalid 452 { 453 assert(op->as_OpLabel() != NULL, "must be"); 454 assert(op->_info == NULL, "info not used by this instruction"); 455 assert(op->_result->is_illegal(), "not used"); 456 break; 457 } 458 459 460// LIR_Op1 461 case lir_fxch: // input always valid, result and info always invalid 462 case lir_fld: // input always valid, result and info always invalid 463 case lir_ffree: // input always valid, result and info always invalid 464 case lir_push: // input always valid, result and info always invalid 465 case lir_pop: // input always valid, result and info always invalid 466 case lir_return: // input always valid, result and info always invalid 467 case lir_leal: // input and result always valid, info always invalid 468 case lir_neg: // input and result always valid, info always invalid 469 case lir_monaddr: // input and result always valid, info always invalid 470 case lir_null_check: // input and info always valid, result always invalid 471 case lir_move: // input and result always valid, may have info 472 case lir_prefetchr: // input always valid, result and info always invalid 473 case lir_prefetchw: // input always valid, result and info always invalid 474 { 475 assert(op->as_Op1() != NULL, "must be"); 476 LIR_Op1* op1 = (LIR_Op1*)op; 477 478 if (op1->_info) do_info(op1->_info); 479 if (op1->_opr->is_valid()) do_input(op1->_opr); 480 if (op1->_result->is_valid()) do_output(op1->_result); 481 482 break; 483 } 484 485 case lir_safepoint: 486 { 487 assert(op->as_Op1() != NULL, "must be"); 488 LIR_Op1* op1 = (LIR_Op1*)op; 489 490 assert(op1->_info != NULL, ""); do_info(op1->_info); 491 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 492 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 493 494 break; 495 } 496 497// LIR_OpConvert; 498 case lir_convert: // input and result always valid, info always invalid 499 { 500 assert(op->as_OpConvert() != NULL, "must be"); 501 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 502 503 assert(opConvert->_info == NULL, "must be"); 504 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 505 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 506 do_stub(opConvert->_stub); 507 508 break; 509 } 510 511// LIR_OpBranch; 512 case lir_branch: // may have info, input and result register always invalid 513 case lir_cond_float_branch: // may have info, input and result register always invalid 514 { 515 assert(op->as_OpBranch() != NULL, "must be"); 516 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 517 518 if (opBranch->_info != NULL) do_info(opBranch->_info); 519 assert(opBranch->_result->is_illegal(), "not used"); 520 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 521 522 break; 523 } 524 525 526// LIR_OpAllocObj 527 case lir_alloc_object: 528 { 529 assert(op->as_OpAllocObj() != NULL, "must be"); 530 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 531 532 if (opAllocObj->_info) do_info(opAllocObj->_info); 533 if (opAllocObj->_opr->is_valid()) do_input(opAllocObj->_opr); 534 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 535 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 536 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 537 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 538 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 539 do_stub(opAllocObj->_stub); 540 break; 541 } 542 543 544// LIR_OpRoundFP; 545 case lir_roundfp: { 546 assert(op->as_OpRoundFP() != NULL, "must be"); 547 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 548 549 assert(op->_info == NULL, "info not used by this instruction"); 550 assert(opRoundFP->_tmp->is_illegal(), "not used"); 551 do_input(opRoundFP->_opr); 552 do_output(opRoundFP->_result); 553 554 break; 555 } 556 557 558// LIR_Op2 559 case lir_cmp: 560 case lir_cmp_l2i: 561 case lir_ucmp_fd2i: 562 case lir_cmp_fd2i: 563 case lir_add: 564 case lir_sub: 565 case lir_mul: 566 case lir_div: 567 case lir_rem: 568 case lir_sqrt: 569 case lir_abs: 570 case lir_logic_and: 571 case lir_logic_or: 572 case lir_logic_xor: 573 case lir_shl: 574 case lir_shr: 575 case lir_ushr: 576 { 577 assert(op->as_Op2() != NULL, "must be"); 578 LIR_Op2* op2 = (LIR_Op2*)op; 579 580 if (op2->_info) do_info(op2->_info); 581 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 582 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 583 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); 584 if (op2->_result->is_valid()) do_output(op2->_result); 585 586 break; 587 } 588 589 // special handling for cmove: right input operand must not be equal 590 // to the result operand, otherwise the backend fails 591 case lir_cmove: 592 { 593 assert(op->as_Op2() != NULL, "must be"); 594 LIR_Op2* op2 = (LIR_Op2*)op; 595 596 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used"); 597 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 598 599 do_input(op2->_opr1); 600 do_input(op2->_opr2); 601 do_temp(op2->_opr2); 602 do_output(op2->_result); 603 604 break; 605 } 606 607 // vspecial handling for strict operations: register input operands 608 // as temp to guarantee that they do not overlap with other 609 // registers 610 case lir_mul_strictfp: 611 case lir_div_strictfp: 612 { 613 assert(op->as_Op2() != NULL, "must be"); 614 LIR_Op2* op2 = (LIR_Op2*)op; 615 616 assert(op2->_info == NULL, "not used"); 617 assert(op2->_opr1->is_valid(), "used"); 618 assert(op2->_opr2->is_valid(), "used"); 619 assert(op2->_result->is_valid(), "used"); 620 621 do_input(op2->_opr1); do_temp(op2->_opr1); 622 do_input(op2->_opr2); do_temp(op2->_opr2); 623 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); 624 do_output(op2->_result); 625 626 break; 627 } 628 629 case lir_throw: { 630 assert(op->as_Op2() != NULL, "must be"); 631 LIR_Op2* op2 = (LIR_Op2*)op; 632 633 if (op2->_info) do_info(op2->_info); 634 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 635 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 636 assert(op2->_result->is_illegal(), "no result"); 637 638 break; 639 } 640 641 case lir_unwind: { 642 assert(op->as_Op1() != NULL, "must be"); 643 LIR_Op1* op1 = (LIR_Op1*)op; 644 645 assert(op1->_info == NULL, "no info"); 646 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 647 assert(op1->_result->is_illegal(), "no result"); 648 649 break; 650 } 651 652 653 case lir_tan: 654 case lir_sin: 655 case lir_cos: 656 case lir_log: 657 case lir_log10: { 658 assert(op->as_Op2() != NULL, "must be"); 659 LIR_Op2* op2 = (LIR_Op2*)op; 660 661 // On x86 tan/sin/cos need two temporary fpu stack slots and 662 // log/log10 need one so handle opr2 and tmp as temp inputs. 663 // Register input operand as temp to guarantee that it doesn't 664 // overlap with the input. 665 assert(op2->_info == NULL, "not used"); 666 assert(op2->_opr1->is_valid(), "used"); 667 do_input(op2->_opr1); do_temp(op2->_opr1); 668 669 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 670 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); 671 if (op2->_result->is_valid()) do_output(op2->_result); 672 673 break; 674 } 675 676 677// LIR_Op3 678 case lir_idiv: 679 case lir_irem: { 680 assert(op->as_Op3() != NULL, "must be"); 681 LIR_Op3* op3= (LIR_Op3*)op; 682 683 if (op3->_info) do_info(op3->_info); 684 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 685 686 // second operand is input and temp, so ensure that second operand 687 // and third operand get not the same register 688 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 689 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 690 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 691 692 if (op3->_result->is_valid()) do_output(op3->_result); 693 694 break; 695 } 696 697 698// LIR_OpJavaCall 699 case lir_static_call: 700 case lir_optvirtual_call: 701 case lir_icvirtual_call: 702 case lir_virtual_call: 703 case lir_dynamic_call: { 704 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 705 assert(opJavaCall != NULL, "must be"); 706 707 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 708 709 // only visit register parameters 710 int n = opJavaCall->_arguments->length(); 711 for (int i = 0; i < n; i++) { 712 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 713 do_input(*opJavaCall->_arguments->adr_at(i)); 714 } 715 } 716 717 if (opJavaCall->_info) do_info(opJavaCall->_info); 718 if (opJavaCall->is_method_handle_invoke()) do_temp(FrameMap::method_handle_invoke_SP_save_opr()); 719 do_call(); 720 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 721 722 break; 723 } 724 725 726// LIR_OpRTCall 727 case lir_rtcall: { 728 assert(op->as_OpRTCall() != NULL, "must be"); 729 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 730 731 // only visit register parameters 732 int n = opRTCall->_arguments->length(); 733 for (int i = 0; i < n; i++) { 734 if (!opRTCall->_arguments->at(i)->is_pointer()) { 735 do_input(*opRTCall->_arguments->adr_at(i)); 736 } 737 } 738 if (opRTCall->_info) do_info(opRTCall->_info); 739 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 740 do_call(); 741 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 742 743 break; 744 } 745 746 747// LIR_OpArrayCopy 748 case lir_arraycopy: { 749 assert(op->as_OpArrayCopy() != NULL, "must be"); 750 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 751 752 assert(opArrayCopy->_result->is_illegal(), "unused"); 753 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 754 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 755 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 756 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 757 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 758 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 759 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 760 761 // the implementation of arraycopy always has a call into the runtime 762 do_call(); 763 764 break; 765 } 766 767 768// LIR_OpLock 769 case lir_lock: 770 case lir_unlock: { 771 assert(op->as_OpLock() != NULL, "must be"); 772 LIR_OpLock* opLock = (LIR_OpLock*)op; 773 774 if (opLock->_info) do_info(opLock->_info); 775 776 // TODO: check if these operands really have to be temp 777 // (or if input is sufficient). This may have influence on the oop map! 778 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 779 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 780 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 781 782 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 783 assert(opLock->_result->is_illegal(), "unused"); 784 785 do_stub(opLock->_stub); 786 787 break; 788 } 789 790 791// LIR_OpDelay 792 case lir_delay_slot: { 793 assert(op->as_OpDelay() != NULL, "must be"); 794 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 795 796 visit(opDelay->delay_op()); 797 break; 798 } 799 800// LIR_OpTypeCheck 801 case lir_instanceof: 802 case lir_checkcast: 803 case lir_store_check: { 804 assert(op->as_OpTypeCheck() != NULL, "must be"); 805 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 806 807 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 808 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 809 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 810 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 811 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 812 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 813 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 814 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 815 do_stub(opTypeCheck->_stub); 816 break; 817 } 818 819// LIR_OpCompareAndSwap 820 case lir_cas_long: 821 case lir_cas_obj: 822 case lir_cas_int: { 823 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 824 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 825 826 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 827 if (opCompareAndSwap->_addr->is_valid()) do_input(opCompareAndSwap->_addr); 828 if (opCompareAndSwap->_cmp_value->is_valid()) do_input(opCompareAndSwap->_cmp_value); 829 if (opCompareAndSwap->_new_value->is_valid()) do_input(opCompareAndSwap->_new_value); 830 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 831 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 832 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 833 834 break; 835 } 836 837 838// LIR_OpAllocArray; 839 case lir_alloc_array: { 840 assert(op->as_OpAllocArray() != NULL, "must be"); 841 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 842 843 if (opAllocArray->_info) do_info(opAllocArray->_info); 844 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 845 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 846 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 847 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 848 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 849 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 850 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 851 do_stub(opAllocArray->_stub); 852 break; 853 } 854 855// LIR_OpProfileCall: 856 case lir_profile_call: { 857 assert(op->as_OpProfileCall() != NULL, "must be"); 858 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 859 860 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 861 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 862 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 863 break; 864 } 865 866 default: 867 ShouldNotReachHere(); 868 } 869} 870 871 872void LIR_OpVisitState::do_stub(CodeStub* stub) { 873 if (stub != NULL) { 874 stub->visit(this); 875 } 876} 877 878XHandlers* LIR_OpVisitState::all_xhandler() { 879 XHandlers* result = NULL; 880 881 int i; 882 for (i = 0; i < info_count(); i++) { 883 if (info_at(i)->exception_handlers() != NULL) { 884 result = info_at(i)->exception_handlers(); 885 break; 886 } 887 } 888 889#ifdef ASSERT 890 for (i = 0; i < info_count(); i++) { 891 assert(info_at(i)->exception_handlers() == NULL || 892 info_at(i)->exception_handlers() == result, 893 "only one xhandler list allowed per LIR-operation"); 894 } 895#endif 896 897 if (result != NULL) { 898 return result; 899 } else { 900 return new XHandlers(); 901 } 902 903 return result; 904} 905 906 907#ifdef ASSERT 908bool LIR_OpVisitState::no_operands(LIR_Op* op) { 909 visit(op); 910 911 return opr_count(inputMode) == 0 && 912 opr_count(outputMode) == 0 && 913 opr_count(tempMode) == 0 && 914 info_count() == 0 && 915 !has_call() && 916 !has_slow_case(); 917} 918#endif 919 920//--------------------------------------------------- 921 922 923void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 924 masm->emit_call(this); 925} 926 927void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 928 masm->emit_rtcall(this); 929} 930 931void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 932 masm->emit_opLabel(this); 933} 934 935void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 936 masm->emit_arraycopy(this); 937 masm->emit_code_stub(stub()); 938} 939 940void LIR_Op0::emit_code(LIR_Assembler* masm) { 941 masm->emit_op0(this); 942} 943 944void LIR_Op1::emit_code(LIR_Assembler* masm) { 945 masm->emit_op1(this); 946} 947 948void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 949 masm->emit_alloc_obj(this); 950 masm->emit_code_stub(stub()); 951} 952 953void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 954 masm->emit_opBranch(this); 955 if (stub()) { 956 masm->emit_code_stub(stub()); 957 } 958} 959 960void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 961 masm->emit_opConvert(this); 962 if (stub() != NULL) { 963 masm->emit_code_stub(stub()); 964 } 965} 966 967void LIR_Op2::emit_code(LIR_Assembler* masm) { 968 masm->emit_op2(this); 969} 970 971void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 972 masm->emit_alloc_array(this); 973 masm->emit_code_stub(stub()); 974} 975 976void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 977 masm->emit_opTypeCheck(this); 978 if (stub()) { 979 masm->emit_code_stub(stub()); 980 } 981} 982 983void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 984 masm->emit_compare_and_swap(this); 985} 986 987void LIR_Op3::emit_code(LIR_Assembler* masm) { 988 masm->emit_op3(this); 989} 990 991void LIR_OpLock::emit_code(LIR_Assembler* masm) { 992 masm->emit_lock(this); 993 if (stub()) { 994 masm->emit_code_stub(stub()); 995 } 996} 997 998 999void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1000 masm->emit_delay(this); 1001} 1002 1003 1004void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1005 masm->emit_profile_call(this); 1006} 1007 1008 1009// LIR_List 1010LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1011 : _operations(8) 1012 , _compilation(compilation) 1013#ifndef PRODUCT 1014 , _block(block) 1015#endif 1016#ifdef ASSERT 1017 , _file(NULL) 1018 , _line(0) 1019#endif 1020{ } 1021 1022 1023#ifdef ASSERT 1024void LIR_List::set_file_and_line(const char * file, int line) { 1025 const char * f = strrchr(file, '/'); 1026 if (f == NULL) f = strrchr(file, '\\'); 1027 if (f == NULL) { 1028 f = file; 1029 } else { 1030 f++; 1031 } 1032 _file = f; 1033 _line = line; 1034} 1035#endif 1036 1037 1038void LIR_List::append(LIR_InsertionBuffer* buffer) { 1039 assert(this == buffer->lir_list(), "wrong lir list"); 1040 const int n = _operations.length(); 1041 1042 if (buffer->number_of_ops() > 0) { 1043 // increase size of instructions list 1044 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1045 // insert ops from buffer into instructions list 1046 int op_index = buffer->number_of_ops() - 1; 1047 int ip_index = buffer->number_of_insertion_points() - 1; 1048 int from_index = n - 1; 1049 int to_index = _operations.length() - 1; 1050 for (; ip_index >= 0; ip_index --) { 1051 int index = buffer->index_at(ip_index); 1052 // make room after insertion point 1053 while (index < from_index) { 1054 _operations.at_put(to_index --, _operations.at(from_index --)); 1055 } 1056 // insert ops from buffer 1057 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1058 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1059 } 1060 } 1061 } 1062 1063 buffer->finish(); 1064} 1065 1066 1067void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1068 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1069} 1070 1071 1072void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1073 append(new LIR_Op1( 1074 lir_move, 1075 LIR_OprFact::address(addr), 1076 src, 1077 addr->type(), 1078 patch_code, 1079 info)); 1080} 1081 1082 1083void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1084 append(new LIR_Op1( 1085 lir_move, 1086 LIR_OprFact::address(address), 1087 dst, 1088 address->type(), 1089 patch_code, 1090 info, lir_move_volatile)); 1091} 1092 1093void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1094 append(new LIR_Op1( 1095 lir_move, 1096 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1097 dst, 1098 type, 1099 patch_code, 1100 info, lir_move_volatile)); 1101} 1102 1103 1104void LIR_List::prefetch(LIR_Address* addr, bool is_store) { 1105 append(new LIR_Op1( 1106 is_store ? lir_prefetchw : lir_prefetchr, 1107 LIR_OprFact::address(addr))); 1108} 1109 1110 1111void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1112 append(new LIR_Op1( 1113 lir_move, 1114 LIR_OprFact::intConst(v), 1115 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1116 type, 1117 patch_code, 1118 info)); 1119} 1120 1121 1122void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1123 append(new LIR_Op1( 1124 lir_move, 1125 LIR_OprFact::oopConst(o), 1126 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1127 type, 1128 patch_code, 1129 info)); 1130} 1131 1132 1133void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1134 append(new LIR_Op1( 1135 lir_move, 1136 src, 1137 LIR_OprFact::address(addr), 1138 addr->type(), 1139 patch_code, 1140 info)); 1141} 1142 1143 1144void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1145 append(new LIR_Op1( 1146 lir_move, 1147 src, 1148 LIR_OprFact::address(addr), 1149 addr->type(), 1150 patch_code, 1151 info, 1152 lir_move_volatile)); 1153} 1154 1155void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1156 append(new LIR_Op1( 1157 lir_move, 1158 src, 1159 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1160 type, 1161 patch_code, 1162 info, lir_move_volatile)); 1163} 1164 1165 1166void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1167 append(new LIR_Op3( 1168 lir_idiv, 1169 left, 1170 right, 1171 tmp, 1172 res, 1173 info)); 1174} 1175 1176 1177void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1178 append(new LIR_Op3( 1179 lir_idiv, 1180 left, 1181 LIR_OprFact::intConst(right), 1182 tmp, 1183 res, 1184 info)); 1185} 1186 1187 1188void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1189 append(new LIR_Op3( 1190 lir_irem, 1191 left, 1192 right, 1193 tmp, 1194 res, 1195 info)); 1196} 1197 1198 1199void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1200 append(new LIR_Op3( 1201 lir_irem, 1202 left, 1203 LIR_OprFact::intConst(right), 1204 tmp, 1205 res, 1206 info)); 1207} 1208 1209 1210void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1211 append(new LIR_Op2( 1212 lir_cmp, 1213 condition, 1214 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1215 LIR_OprFact::intConst(c), 1216 info)); 1217} 1218 1219 1220void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1221 append(new LIR_Op2( 1222 lir_cmp, 1223 condition, 1224 reg, 1225 LIR_OprFact::address(addr), 1226 info)); 1227} 1228 1229void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1230 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1231 append(new LIR_OpAllocObj( 1232 klass, 1233 dst, 1234 t1, 1235 t2, 1236 t3, 1237 t4, 1238 header_size, 1239 object_size, 1240 init_check, 1241 stub)); 1242} 1243 1244void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1245 append(new LIR_OpAllocArray( 1246 klass, 1247 len, 1248 dst, 1249 t1, 1250 t2, 1251 t3, 1252 t4, 1253 type, 1254 stub)); 1255} 1256 1257void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1258 append(new LIR_Op2( 1259 lir_shl, 1260 value, 1261 count, 1262 dst, 1263 tmp)); 1264} 1265 1266void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1267 append(new LIR_Op2( 1268 lir_shr, 1269 value, 1270 count, 1271 dst, 1272 tmp)); 1273} 1274 1275 1276void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1277 append(new LIR_Op2( 1278 lir_ushr, 1279 value, 1280 count, 1281 dst, 1282 tmp)); 1283} 1284 1285void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1286 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1287 left, 1288 right, 1289 dst)); 1290} 1291 1292void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1293 append(new LIR_OpLock( 1294 lir_lock, 1295 hdr, 1296 obj, 1297 lock, 1298 scratch, 1299 stub, 1300 info)); 1301} 1302 1303void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, CodeStub* stub) { 1304 append(new LIR_OpLock( 1305 lir_unlock, 1306 hdr, 1307 obj, 1308 lock, 1309 LIR_OprFact::illegalOpr, 1310 stub, 1311 NULL)); 1312} 1313 1314 1315void check_LIR() { 1316 // cannot do the proper checking as PRODUCT and other modes return different results 1317 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1318} 1319 1320 1321 1322void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1323 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1324 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1325 ciMethod* profiled_method, int profiled_bci) { 1326 append(new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1327 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub, 1328 profiled_method, profiled_bci)); 1329} 1330 1331 1332void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch) { 1333 append(new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL, NULL, 0)); 1334} 1335 1336 1337void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) { 1338 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception, NULL, 0)); 1339} 1340 1341 1342void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) { 1343 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, 1344 // implying successful swap of new_value into addr 1345 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2)); 1346} 1347 1348void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) { 1349 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, 1350 // implying successful swap of new_value into addr 1351 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2)); 1352} 1353 1354void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) { 1355 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, 1356 // implying successful swap of new_value into addr 1357 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2)); 1358} 1359 1360 1361#ifdef PRODUCT 1362 1363void print_LIR(BlockList* blocks) { 1364} 1365 1366#else 1367// LIR_OprDesc 1368void LIR_OprDesc::print() const { 1369 print(tty); 1370} 1371 1372void LIR_OprDesc::print(outputStream* out) const { 1373 if (is_illegal()) { 1374 return; 1375 } 1376 1377 out->print("["); 1378 if (is_pointer()) { 1379 pointer()->print_value_on(out); 1380 } else if (is_single_stack()) { 1381 out->print("stack:%d", single_stack_ix()); 1382 } else if (is_double_stack()) { 1383 out->print("dbl_stack:%d",double_stack_ix()); 1384 } else if (is_virtual()) { 1385 out->print("R%d", vreg_number()); 1386 } else if (is_single_cpu()) { 1387 out->print(as_register()->name()); 1388 } else if (is_double_cpu()) { 1389 out->print(as_register_hi()->name()); 1390 out->print(as_register_lo()->name()); 1391#if defined(X86) 1392 } else if (is_single_xmm()) { 1393 out->print(as_xmm_float_reg()->name()); 1394 } else if (is_double_xmm()) { 1395 out->print(as_xmm_double_reg()->name()); 1396 } else if (is_single_fpu()) { 1397 out->print("fpu%d", fpu_regnr()); 1398 } else if (is_double_fpu()) { 1399 out->print("fpu%d", fpu_regnrLo()); 1400#else 1401 } else if (is_single_fpu()) { 1402 out->print(as_float_reg()->name()); 1403 } else if (is_double_fpu()) { 1404 out->print(as_double_reg()->name()); 1405#endif 1406 1407 } else if (is_illegal()) { 1408 out->print("-"); 1409 } else { 1410 out->print("Unknown Operand"); 1411 } 1412 if (!is_illegal()) { 1413 out->print("|%c", type_char()); 1414 } 1415 if (is_register() && is_last_use()) { 1416 out->print("(last_use)"); 1417 } 1418 out->print("]"); 1419} 1420 1421 1422// LIR_Address 1423void LIR_Const::print_value_on(outputStream* out) const { 1424 switch (type()) { 1425 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1426 case T_INT: out->print("int:%d", as_jint()); break; 1427 case T_LONG: out->print("lng:%lld", as_jlong()); break; 1428 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1429 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1430 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break; 1431 default: out->print("%3d:0x%x",type(), as_jdouble()); break; 1432 } 1433} 1434 1435// LIR_Address 1436void LIR_Address::print_value_on(outputStream* out) const { 1437 out->print("Base:"); _base->print(out); 1438 if (!_index->is_illegal()) { 1439 out->print(" Index:"); _index->print(out); 1440 switch (scale()) { 1441 case times_1: break; 1442 case times_2: out->print(" * 2"); break; 1443 case times_4: out->print(" * 4"); break; 1444 case times_8: out->print(" * 8"); break; 1445 } 1446 } 1447 out->print(" Disp: %d", _disp); 1448} 1449 1450// debug output of block header without InstructionPrinter 1451// (because phi functions are not necessary for LIR) 1452static void print_block(BlockBegin* x) { 1453 // print block id 1454 BlockEnd* end = x->end(); 1455 tty->print("B%d ", x->block_id()); 1456 1457 // print flags 1458 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1459 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1460 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1461 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1462 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1463 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1464 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1465 1466 // print block bci range 1467 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->bci())); 1468 1469 // print predecessors and successors 1470 if (x->number_of_preds() > 0) { 1471 tty->print("preds: "); 1472 for (int i = 0; i < x->number_of_preds(); i ++) { 1473 tty->print("B%d ", x->pred_at(i)->block_id()); 1474 } 1475 } 1476 1477 if (x->number_of_sux() > 0) { 1478 tty->print("sux: "); 1479 for (int i = 0; i < x->number_of_sux(); i ++) { 1480 tty->print("B%d ", x->sux_at(i)->block_id()); 1481 } 1482 } 1483 1484 // print exception handlers 1485 if (x->number_of_exception_handlers() > 0) { 1486 tty->print("xhandler: "); 1487 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1488 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1489 } 1490 } 1491 1492 tty->cr(); 1493} 1494 1495void print_LIR(BlockList* blocks) { 1496 tty->print_cr("LIR:"); 1497 int i; 1498 for (i = 0; i < blocks->length(); i++) { 1499 BlockBegin* bb = blocks->at(i); 1500 print_block(bb); 1501 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1502 bb->lir()->print_instructions(); 1503 } 1504} 1505 1506void LIR_List::print_instructions() { 1507 for (int i = 0; i < _operations.length(); i++) { 1508 _operations.at(i)->print(); tty->cr(); 1509 } 1510 tty->cr(); 1511} 1512 1513// LIR_Ops printing routines 1514// LIR_Op 1515void LIR_Op::print_on(outputStream* out) const { 1516 if (id() != -1 || PrintCFGToFile) { 1517 out->print("%4d ", id()); 1518 } else { 1519 out->print(" "); 1520 } 1521 out->print(name()); out->print(" "); 1522 print_instr(out); 1523 if (info() != NULL) out->print(" [bci:%d]", info()->bci()); 1524#ifdef ASSERT 1525 if (Verbose && _file != NULL) { 1526 out->print(" (%s:%d)", _file, _line); 1527 } 1528#endif 1529} 1530 1531const char * LIR_Op::name() const { 1532 const char* s = NULL; 1533 switch(code()) { 1534 // LIR_Op0 1535 case lir_membar: s = "membar"; break; 1536 case lir_membar_acquire: s = "membar_acquire"; break; 1537 case lir_membar_release: s = "membar_release"; break; 1538 case lir_word_align: s = "word_align"; break; 1539 case lir_label: s = "label"; break; 1540 case lir_nop: s = "nop"; break; 1541 case lir_backwardbranch_target: s = "backbranch"; break; 1542 case lir_std_entry: s = "std_entry"; break; 1543 case lir_osr_entry: s = "osr_entry"; break; 1544 case lir_build_frame: s = "build_frm"; break; 1545 case lir_fpop_raw: s = "fpop_raw"; break; 1546 case lir_24bit_FPU: s = "24bit_FPU"; break; 1547 case lir_reset_FPU: s = "reset_FPU"; break; 1548 case lir_breakpoint: s = "breakpoint"; break; 1549 case lir_get_thread: s = "get_thread"; break; 1550 // LIR_Op1 1551 case lir_fxch: s = "fxch"; break; 1552 case lir_fld: s = "fld"; break; 1553 case lir_ffree: s = "ffree"; break; 1554 case lir_push: s = "push"; break; 1555 case lir_pop: s = "pop"; break; 1556 case lir_null_check: s = "null_check"; break; 1557 case lir_return: s = "return"; break; 1558 case lir_safepoint: s = "safepoint"; break; 1559 case lir_neg: s = "neg"; break; 1560 case lir_leal: s = "leal"; break; 1561 case lir_branch: s = "branch"; break; 1562 case lir_cond_float_branch: s = "flt_cond_br"; break; 1563 case lir_move: s = "move"; break; 1564 case lir_roundfp: s = "roundfp"; break; 1565 case lir_rtcall: s = "rtcall"; break; 1566 case lir_throw: s = "throw"; break; 1567 case lir_unwind: s = "unwind"; break; 1568 case lir_convert: s = "convert"; break; 1569 case lir_alloc_object: s = "alloc_obj"; break; 1570 case lir_monaddr: s = "mon_addr"; break; 1571 // LIR_Op2 1572 case lir_cmp: s = "cmp"; break; 1573 case lir_cmp_l2i: s = "cmp_l2i"; break; 1574 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1575 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1576 case lir_cmove: s = "cmove"; break; 1577 case lir_add: s = "add"; break; 1578 case lir_sub: s = "sub"; break; 1579 case lir_mul: s = "mul"; break; 1580 case lir_mul_strictfp: s = "mul_strictfp"; break; 1581 case lir_div: s = "div"; break; 1582 case lir_div_strictfp: s = "div_strictfp"; break; 1583 case lir_rem: s = "rem"; break; 1584 case lir_abs: s = "abs"; break; 1585 case lir_sqrt: s = "sqrt"; break; 1586 case lir_sin: s = "sin"; break; 1587 case lir_cos: s = "cos"; break; 1588 case lir_tan: s = "tan"; break; 1589 case lir_log: s = "log"; break; 1590 case lir_log10: s = "log10"; break; 1591 case lir_logic_and: s = "logic_and"; break; 1592 case lir_logic_or: s = "logic_or"; break; 1593 case lir_logic_xor: s = "logic_xor"; break; 1594 case lir_shl: s = "shift_left"; break; 1595 case lir_shr: s = "shift_right"; break; 1596 case lir_ushr: s = "ushift_right"; break; 1597 case lir_alloc_array: s = "alloc_array"; break; 1598 // LIR_Op3 1599 case lir_idiv: s = "idiv"; break; 1600 case lir_irem: s = "irem"; break; 1601 // LIR_OpJavaCall 1602 case lir_static_call: s = "static"; break; 1603 case lir_optvirtual_call: s = "optvirtual"; break; 1604 case lir_icvirtual_call: s = "icvirtual"; break; 1605 case lir_virtual_call: s = "virtual"; break; 1606 case lir_dynamic_call: s = "dynamic"; break; 1607 // LIR_OpArrayCopy 1608 case lir_arraycopy: s = "arraycopy"; break; 1609 // LIR_OpLock 1610 case lir_lock: s = "lock"; break; 1611 case lir_unlock: s = "unlock"; break; 1612 // LIR_OpDelay 1613 case lir_delay_slot: s = "delay"; break; 1614 // LIR_OpTypeCheck 1615 case lir_instanceof: s = "instanceof"; break; 1616 case lir_checkcast: s = "checkcast"; break; 1617 case lir_store_check: s = "store_check"; break; 1618 // LIR_OpCompareAndSwap 1619 case lir_cas_long: s = "cas_long"; break; 1620 case lir_cas_obj: s = "cas_obj"; break; 1621 case lir_cas_int: s = "cas_int"; break; 1622 // LIR_OpProfileCall 1623 case lir_profile_call: s = "profile_call"; break; 1624 1625 case lir_none: ShouldNotReachHere();break; 1626 default: s = "illegal_op"; break; 1627 } 1628 return s; 1629} 1630 1631// LIR_OpJavaCall 1632void LIR_OpJavaCall::print_instr(outputStream* out) const { 1633 out->print("call: "); 1634 out->print("[addr: 0x%x]", address()); 1635 if (receiver()->is_valid()) { 1636 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1637 } 1638 if (result_opr()->is_valid()) { 1639 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1640 } 1641} 1642 1643// LIR_OpLabel 1644void LIR_OpLabel::print_instr(outputStream* out) const { 1645 out->print("[label:0x%x]", _label); 1646} 1647 1648// LIR_OpArrayCopy 1649void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1650 src()->print(out); out->print(" "); 1651 src_pos()->print(out); out->print(" "); 1652 dst()->print(out); out->print(" "); 1653 dst_pos()->print(out); out->print(" "); 1654 length()->print(out); out->print(" "); 1655 tmp()->print(out); out->print(" "); 1656} 1657 1658// LIR_OpCompareAndSwap 1659void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1660 addr()->print(out); out->print(" "); 1661 cmp_value()->print(out); out->print(" "); 1662 new_value()->print(out); out->print(" "); 1663 tmp1()->print(out); out->print(" "); 1664 tmp2()->print(out); out->print(" "); 1665 1666} 1667 1668// LIR_Op0 1669void LIR_Op0::print_instr(outputStream* out) const { 1670 result_opr()->print(out); 1671} 1672 1673// LIR_Op1 1674const char * LIR_Op1::name() const { 1675 if (code() == lir_move) { 1676 switch (move_kind()) { 1677 case lir_move_normal: 1678 return "move"; 1679 case lir_move_unaligned: 1680 return "unaligned move"; 1681 case lir_move_volatile: 1682 return "volatile_move"; 1683 default: 1684 ShouldNotReachHere(); 1685 return "illegal_op"; 1686 } 1687 } else { 1688 return LIR_Op::name(); 1689 } 1690} 1691 1692 1693void LIR_Op1::print_instr(outputStream* out) const { 1694 _opr->print(out); out->print(" "); 1695 result_opr()->print(out); out->print(" "); 1696 print_patch_code(out, patch_code()); 1697} 1698 1699 1700// LIR_Op1 1701void LIR_OpRTCall::print_instr(outputStream* out) const { 1702 intx a = (intx)addr(); 1703 out->print(Runtime1::name_for_address(addr())); 1704 out->print(" "); 1705 tmp()->print(out); 1706} 1707 1708void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1709 switch(code) { 1710 case lir_patch_none: break; 1711 case lir_patch_low: out->print("[patch_low]"); break; 1712 case lir_patch_high: out->print("[patch_high]"); break; 1713 case lir_patch_normal: out->print("[patch_normal]"); break; 1714 default: ShouldNotReachHere(); 1715 } 1716} 1717 1718// LIR_OpBranch 1719void LIR_OpBranch::print_instr(outputStream* out) const { 1720 print_condition(out, cond()); out->print(" "); 1721 if (block() != NULL) { 1722 out->print("[B%d] ", block()->block_id()); 1723 } else if (stub() != NULL) { 1724 out->print("["); 1725 stub()->print_name(out); 1726 out->print(": 0x%x]", stub()); 1727 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->bci()); 1728 } else { 1729 out->print("[label:0x%x] ", label()); 1730 } 1731 if (ublock() != NULL) { 1732 out->print("unordered: [B%d] ", ublock()->block_id()); 1733 } 1734} 1735 1736void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1737 switch(cond) { 1738 case lir_cond_equal: out->print("[EQ]"); break; 1739 case lir_cond_notEqual: out->print("[NE]"); break; 1740 case lir_cond_less: out->print("[LT]"); break; 1741 case lir_cond_lessEqual: out->print("[LE]"); break; 1742 case lir_cond_greaterEqual: out->print("[GE]"); break; 1743 case lir_cond_greater: out->print("[GT]"); break; 1744 case lir_cond_belowEqual: out->print("[BE]"); break; 1745 case lir_cond_aboveEqual: out->print("[AE]"); break; 1746 case lir_cond_always: out->print("[AL]"); break; 1747 default: out->print("[%d]",cond); break; 1748 } 1749} 1750 1751// LIR_OpConvert 1752void LIR_OpConvert::print_instr(outputStream* out) const { 1753 print_bytecode(out, bytecode()); 1754 in_opr()->print(out); out->print(" "); 1755 result_opr()->print(out); out->print(" "); 1756} 1757 1758void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1759 switch(code) { 1760 case Bytecodes::_d2f: out->print("[d2f] "); break; 1761 case Bytecodes::_d2i: out->print("[d2i] "); break; 1762 case Bytecodes::_d2l: out->print("[d2l] "); break; 1763 case Bytecodes::_f2d: out->print("[f2d] "); break; 1764 case Bytecodes::_f2i: out->print("[f2i] "); break; 1765 case Bytecodes::_f2l: out->print("[f2l] "); break; 1766 case Bytecodes::_i2b: out->print("[i2b] "); break; 1767 case Bytecodes::_i2c: out->print("[i2c] "); break; 1768 case Bytecodes::_i2d: out->print("[i2d] "); break; 1769 case Bytecodes::_i2f: out->print("[i2f] "); break; 1770 case Bytecodes::_i2l: out->print("[i2l] "); break; 1771 case Bytecodes::_i2s: out->print("[i2s] "); break; 1772 case Bytecodes::_l2i: out->print("[l2i] "); break; 1773 case Bytecodes::_l2f: out->print("[l2f] "); break; 1774 case Bytecodes::_l2d: out->print("[l2d] "); break; 1775 default: 1776 out->print("[?%d]",code); 1777 break; 1778 } 1779} 1780 1781void LIR_OpAllocObj::print_instr(outputStream* out) const { 1782 klass()->print(out); out->print(" "); 1783 obj()->print(out); out->print(" "); 1784 tmp1()->print(out); out->print(" "); 1785 tmp2()->print(out); out->print(" "); 1786 tmp3()->print(out); out->print(" "); 1787 tmp4()->print(out); out->print(" "); 1788 out->print("[hdr:%d]", header_size()); out->print(" "); 1789 out->print("[obj:%d]", object_size()); out->print(" "); 1790 out->print("[lbl:0x%x]", stub()->entry()); 1791} 1792 1793void LIR_OpRoundFP::print_instr(outputStream* out) const { 1794 _opr->print(out); out->print(" "); 1795 tmp()->print(out); out->print(" "); 1796 result_opr()->print(out); out->print(" "); 1797} 1798 1799// LIR_Op2 1800void LIR_Op2::print_instr(outputStream* out) const { 1801 if (code() == lir_cmove) { 1802 print_condition(out, condition()); out->print(" "); 1803 } 1804 in_opr1()->print(out); out->print(" "); 1805 in_opr2()->print(out); out->print(" "); 1806 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); } 1807 result_opr()->print(out); 1808} 1809 1810void LIR_OpAllocArray::print_instr(outputStream* out) const { 1811 klass()->print(out); out->print(" "); 1812 len()->print(out); out->print(" "); 1813 obj()->print(out); out->print(" "); 1814 tmp1()->print(out); out->print(" "); 1815 tmp2()->print(out); out->print(" "); 1816 tmp3()->print(out); out->print(" "); 1817 tmp4()->print(out); out->print(" "); 1818 out->print("[type:0x%x]", type()); out->print(" "); 1819 out->print("[label:0x%x]", stub()->entry()); 1820} 1821 1822 1823void LIR_OpTypeCheck::print_instr(outputStream* out) const { 1824 object()->print(out); out->print(" "); 1825 if (code() == lir_store_check) { 1826 array()->print(out); out->print(" "); 1827 } 1828 if (code() != lir_store_check) { 1829 klass()->print_name_on(out); out->print(" "); 1830 if (fast_check()) out->print("fast_check "); 1831 } 1832 tmp1()->print(out); out->print(" "); 1833 tmp2()->print(out); out->print(" "); 1834 tmp3()->print(out); out->print(" "); 1835 result_opr()->print(out); out->print(" "); 1836 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->bci()); 1837} 1838 1839 1840// LIR_Op3 1841void LIR_Op3::print_instr(outputStream* out) const { 1842 in_opr1()->print(out); out->print(" "); 1843 in_opr2()->print(out); out->print(" "); 1844 in_opr3()->print(out); out->print(" "); 1845 result_opr()->print(out); 1846} 1847 1848 1849void LIR_OpLock::print_instr(outputStream* out) const { 1850 hdr_opr()->print(out); out->print(" "); 1851 obj_opr()->print(out); out->print(" "); 1852 lock_opr()->print(out); out->print(" "); 1853 if (_scratch->is_valid()) { 1854 _scratch->print(out); out->print(" "); 1855 } 1856 out->print("[lbl:0x%x]", stub()->entry()); 1857} 1858 1859 1860void LIR_OpDelay::print_instr(outputStream* out) const { 1861 _op->print_on(out); 1862} 1863 1864 1865// LIR_OpProfileCall 1866void LIR_OpProfileCall::print_instr(outputStream* out) const { 1867 profiled_method()->name()->print_symbol_on(out); 1868 out->print("."); 1869 profiled_method()->holder()->name()->print_symbol_on(out); 1870 out->print(" @ %d ", profiled_bci()); 1871 mdo()->print(out); out->print(" "); 1872 recv()->print(out); out->print(" "); 1873 tmp1()->print(out); out->print(" "); 1874} 1875 1876 1877#endif // PRODUCT 1878 1879// Implementation of LIR_InsertionBuffer 1880 1881void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 1882 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 1883 1884 int i = number_of_insertion_points() - 1; 1885 if (i < 0 || index_at(i) < index) { 1886 append_new(index, 1); 1887 } else { 1888 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 1889 assert(count_at(i) > 0, "check"); 1890 set_count_at(i, count_at(i) + 1); 1891 } 1892 _ops.push(op); 1893 1894 DEBUG_ONLY(verify()); 1895} 1896 1897#ifdef ASSERT 1898void LIR_InsertionBuffer::verify() { 1899 int sum = 0; 1900 int prev_idx = -1; 1901 1902 for (int i = 0; i < number_of_insertion_points(); i++) { 1903 assert(prev_idx < index_at(i), "index must be ordered ascending"); 1904 sum += count_at(i); 1905 } 1906 assert(sum == number_of_ops(), "wrong total sum"); 1907} 1908#endif 1909