solaris_sparc.s revision 1472:c18cbe5936b8 
1!!
2!! Copyright (c) 2005, 2008 Oracle and/or its affiliates. All rights reserved.
3!! DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4!!
5!! This code is free software; you can redistribute it and/or modify it
6!! under the terms of the GNU General Public License version 2 only, as
7!! published by the Free Software Foundation.
8!!
9!! This code is distributed in the hope that it will be useful, but WITHOUT
10!! ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11!! FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12!! version 2 for more details (a copy is included in the LICENSE file that
13!! accompanied this code).
14!!
15!! You should have received a copy of the GNU General Public License version
16!! 2 along with this work; if not, write to the Free Software Foundation,
17!! Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18!!
19!! Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20!! or visit www.oracle.com if you need additional information or have any
21!! questions.
22!!
23
24    !! Prototype: int SafeFetch32 (int * adr, int ErrValue)
25    !! The "ld" at Fetch32 is potentially faulting instruction.
26    !! If the instruction traps the trap handler will arrange
27    !! for control to resume at Fetch32Resume.
28    !! By convention with the trap handler we ensure there is a non-CTI
29    !! instruction in the trap shadow.
30    !!
31    !! The reader might be tempted to move this service to .il.
32    !! Don't.  Sun's CC back-end reads and optimize code emitted
33    !! by the .il "call", in some cases optimizing the code, completely eliding it,
34    !! or by moving the code from the "call site".
35
36     !! ASM better know we may use G6 for our own purposes
37    .register %g6, #ignore
38
39    .globl  SafeFetch32
40    .align  32
41    .global Fetch32PFI, Fetch32Resume
42SafeFetch32:
43    mov     %o0, %g1
44    mov     %o1, %o0
45Fetch32PFI:
46    ld      [%g1], %o0          !! <-- Potentially faulting instruction
47Fetch32Resume:
48    nop
49    retl
50    nop
51
52    .globl  SafeFetchN
53    .align  32
54    .globl  FetchNPFI, FetchNResume
55SafeFetchN:
56    mov     %o0, %g1
57    mov     %o1, %o0
58FetchNPFI:
59    ldn     [%g1], %o0
60FetchNResume:
61    nop
62    retl
63    nop
64
65    !! Possibilities:
66    !! -- membar
67    !! -- CAS (SP + BIAS, G0, G0)
68    !! -- wr %g0, %asi
69
70    .global SpinPause
71    .align  32
72SpinPause:
73    retl
74    mov %g0, %o0
75
76
77
78    .globl _Copy_conjoint_jlongs_atomic
79    .align 32
80    .global   _Copy_conjoint_jlongs_atomic
81 _Copy_conjoint_jlongs_atomic:
82         cmp     %o0, %o1
83         bleu    4f
84         sll     %o2, 3, %o4
85         ba      2f
86    1:
87         subcc   %o4, 8, %o4
88         std     %o2, [%o1]
89         add     %o0, 8, %o0
90         add     %o1, 8, %o1
91    2:
92         bge,a   1b
93         ldd     [%o0], %o2
94         ba      5f
95         nop
96    3:
97         std     %o2, [%o1+%o4]
98    4:
99         subcc   %o4, 8, %o4
100         bge,a   3b
101         ldd     [%o0+%o4], %o2
102    5:
103         retl
104         nop
105
106
107
108    .globl _raw_thread_id
109    .align 32
110 _raw_thread_id:
111    .register %g7, #scratch
112        retl
113        mov     %g7, %o0
114
115
116    .globl _flush_reg_windows
117    .align 32
118 _flush_reg_windows:
119        ta 0x03
120        retl
121        mov     %fp, %o0
122
123
124