AMD64SignExtendOp.java revision 12651:6ef01bd40ce2 
1/*
2 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23package org.graalvm.compiler.lir.amd64;
24
25import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.DWORD;
26import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.QWORD;
27import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
28import static jdk.vm.ci.code.ValueUtil.asRegister;
29
30import org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize;
31import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
32import org.graalvm.compiler.core.common.LIRKind;
33import org.graalvm.compiler.lir.LIRInstructionClass;
34import org.graalvm.compiler.lir.Opcode;
35import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
36
37import jdk.vm.ci.amd64.AMD64;
38import jdk.vm.ci.meta.AllocatableValue;
39
40@Opcode("CDQ")
41public class AMD64SignExtendOp extends AMD64LIRInstruction {
42    public static final LIRInstructionClass<AMD64SignExtendOp> TYPE = LIRInstructionClass.create(AMD64SignExtendOp.class);
43
44    private final OperandSize size;
45
46    @Def({REG}) protected AllocatableValue highResult;
47    @Def({REG}) protected AllocatableValue lowResult;
48
49    @Use({REG}) protected AllocatableValue input;
50
51    public AMD64SignExtendOp(OperandSize size, LIRKind resultKind, AllocatableValue input) {
52        super(TYPE);
53        this.size = size;
54
55        this.highResult = AMD64.rdx.asValue(resultKind);
56        this.lowResult = AMD64.rax.asValue(resultKind);
57        this.input = input;
58    }
59
60    public AllocatableValue getHighResult() {
61        return highResult;
62    }
63
64    public AllocatableValue getLowResult() {
65        return lowResult;
66    }
67
68    @Override
69    public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
70        if (size == DWORD) {
71            masm.cdql();
72        } else {
73            assert size == QWORD;
74            masm.cdqq();
75        }
76    }
77
78    @Override
79    public void verify() {
80        assert asRegister(highResult).equals(AMD64.rdx);
81        assert asRegister(lowResult).equals(AMD64.rax);
82        assert asRegister(input).equals(AMD64.rax);
83    }
84}
85