register_x86.hpp revision 1472:c18cbe5936b8
1/* 2 * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25class VMRegImpl; 26typedef VMRegImpl* VMReg; 27 28// Use Register as shortcut 29class RegisterImpl; 30typedef RegisterImpl* Register; 31 32 33// The implementation of integer registers for the ia32 architecture 34inline Register as_Register(int encoding) { 35 return (Register)(intptr_t) encoding; 36} 37 38class RegisterImpl: public AbstractRegisterImpl { 39 public: 40 enum { 41#ifndef AMD64 42 number_of_registers = 8, 43 number_of_byte_registers = 4 44#else 45 number_of_registers = 16, 46 number_of_byte_registers = 16 47#endif // AMD64 48 }; 49 50 // derived registers, offsets, and addresses 51 Register successor() const { return as_Register(encoding() + 1); } 52 53 // construction 54 inline friend Register as_Register(int encoding); 55 56 VMReg as_VMReg(); 57 58 // accessors 59 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 60 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 61 bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; } 62 const char* name() const; 63}; 64 65// The integer registers of the ia32/amd64 architecture 66 67CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); 68 69 70CONSTANT_REGISTER_DECLARATION(Register, rax, (0)); 71CONSTANT_REGISTER_DECLARATION(Register, rcx, (1)); 72CONSTANT_REGISTER_DECLARATION(Register, rdx, (2)); 73CONSTANT_REGISTER_DECLARATION(Register, rbx, (3)); 74CONSTANT_REGISTER_DECLARATION(Register, rsp, (4)); 75CONSTANT_REGISTER_DECLARATION(Register, rbp, (5)); 76CONSTANT_REGISTER_DECLARATION(Register, rsi, (6)); 77CONSTANT_REGISTER_DECLARATION(Register, rdi, (7)); 78#ifdef AMD64 79CONSTANT_REGISTER_DECLARATION(Register, r8, (8)); 80CONSTANT_REGISTER_DECLARATION(Register, r9, (9)); 81CONSTANT_REGISTER_DECLARATION(Register, r10, (10)); 82CONSTANT_REGISTER_DECLARATION(Register, r11, (11)); 83CONSTANT_REGISTER_DECLARATION(Register, r12, (12)); 84CONSTANT_REGISTER_DECLARATION(Register, r13, (13)); 85CONSTANT_REGISTER_DECLARATION(Register, r14, (14)); 86CONSTANT_REGISTER_DECLARATION(Register, r15, (15)); 87#endif // AMD64 88 89// Use FloatRegister as shortcut 90class FloatRegisterImpl; 91typedef FloatRegisterImpl* FloatRegister; 92 93inline FloatRegister as_FloatRegister(int encoding) { 94 return (FloatRegister)(intptr_t) encoding; 95} 96 97// The implementation of floating point registers for the ia32 architecture 98class FloatRegisterImpl: public AbstractRegisterImpl { 99 public: 100 enum { 101 number_of_registers = 8 102 }; 103 104 // construction 105 inline friend FloatRegister as_FloatRegister(int encoding); 106 107 VMReg as_VMReg(); 108 109 // derived registers, offsets, and addresses 110 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } 111 112 // accessors 113 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 114 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 115 const char* name() const; 116 117}; 118 119// Use XMMRegister as shortcut 120class XMMRegisterImpl; 121typedef XMMRegisterImpl* XMMRegister; 122 123// Use MMXRegister as shortcut 124class MMXRegisterImpl; 125typedef MMXRegisterImpl* MMXRegister; 126 127inline XMMRegister as_XMMRegister(int encoding) { 128 return (XMMRegister)(intptr_t)encoding; 129} 130 131inline MMXRegister as_MMXRegister(int encoding) { 132 return (MMXRegister)(intptr_t)encoding; 133} 134 135// The implementation of XMM registers for the IA32 architecture 136class XMMRegisterImpl: public AbstractRegisterImpl { 137 public: 138 enum { 139#ifndef AMD64 140 number_of_registers = 8 141#else 142 number_of_registers = 16 143#endif // AMD64 144 }; 145 146 // construction 147 friend XMMRegister as_XMMRegister(int encoding); 148 149 VMReg as_VMReg(); 150 151 // derived registers, offsets, and addresses 152 XMMRegister successor() const { return as_XMMRegister(encoding() + 1); } 153 154 // accessors 155 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 156 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 157 const char* name() const; 158}; 159 160 161// The XMM registers, for P3 and up chips 162CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1)); 163CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0)); 164CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1)); 165CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2)); 166CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3)); 167CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4)); 168CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5)); 169CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6)); 170CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7)); 171#ifdef AMD64 172CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8)); 173CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9)); 174CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10)); 175CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11)); 176CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12, (12)); 177CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13, (13)); 178CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14, (14)); 179CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15, (15)); 180#endif // AMD64 181 182// Only used by the 32bit stubGenerator. These can't be described by vmreg and hence 183// can't be described in oopMaps and therefore can't be used by the compilers (at least 184// were deopt might wan't to see them). 185 186// The MMX registers, for P3 and up chips 187CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1)); 188CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0)); 189CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1)); 190CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2)); 191CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3)); 192CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4)); 193CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5)); 194CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6)); 195CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7)); 196 197 198// Need to know the total number of registers of all sorts for SharedInfo. 199// Define a class that exports it. 200class ConcreteRegisterImpl : public AbstractRegisterImpl { 201 public: 202 enum { 203 // A big enough number for C2: all the registers plus flags 204 // This number must be large enough to cover REG_COUNT (defined by c2) registers. 205 // There is no requirement that any ordering here matches any ordering c2 gives 206 // it's optoregs. 207 208 number_of_registers = RegisterImpl::number_of_registers + 209#ifdef AMD64 210 RegisterImpl::number_of_registers + // "H" half of a 64bit register 211#endif // AMD64 212 2 * FloatRegisterImpl::number_of_registers + 213 2 * XMMRegisterImpl::number_of_registers + 214 1 // eflags 215 }; 216 217 static const int max_gpr; 218 static const int max_fpr; 219 static const int max_xmm; 220 221}; 222