icache_x86.hpp revision 1472:c18cbe5936b8 
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24
25// Interface for updating the instruction cache.  Whenever the VM modifies
26// code, part of the processor instruction cache potentially has to be flushed.
27
28// On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
29// after the next jump, and the VM never modifies instructions directly ahead
30// of the instruction fetch path.
31
32// [phh] It's not clear that the above comment is correct, because on an MP
33// system where the dcaches are not snooped, only the thread doing the invalidate
34// will see the update.  Even in the snooped case, a memory fence would be
35// necessary if stores weren't ordered.  Fortunately, they are on all known
36// x86 implementations.
37
38class ICache : public AbstractICache {
39 public:
40#ifdef AMD64
41  enum {
42    stub_size      = 64, // Size of the icache flush stub in bytes
43    line_size      = 32, // Icache line size in bytes
44    log2_line_size = 5   // log2(line_size)
45  };
46
47  // Use default implementation
48#else
49  enum {
50    stub_size      = 16,                 // Size of the icache flush stub in bytes
51    line_size      = BytesPerWord,      // conservative
52    log2_line_size = LogBytesPerWord    // log2(line_size)
53  };
54#endif // AMD64
55};
56