globals_x86.hpp revision 12253:59da89afe788 
1/*
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
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12 * version 2 for more details (a copy is included in the LICENSE file that
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24
25#ifndef CPU_X86_VM_GLOBALS_X86_HPP
26#define CPU_X86_VM_GLOBALS_X86_HPP
27
28#include "utilities/globalDefinitions.hpp"
29#include "utilities/macros.hpp"
30
31// Sets the default values for platform dependent flags used by the runtime system.
32// (see globals.hpp)
33
34define_pd_global(bool, ShareVtableStubs,         true);
35define_pd_global(bool, NeedsDeoptSuspend,        false); // only register window machines need this
36
37define_pd_global(bool, ImplicitNullChecks,       true);  // Generate code for implicit null checks
38define_pd_global(bool, TrapBasedNullChecks,      false); // Not needed on x86.
39define_pd_global(bool, UncommonNullCast,         true);  // Uncommon-trap NULLs passed to check cast
40
41define_pd_global(uintx, CodeCacheSegmentSize,    64 TIERED_ONLY(+64)); // Tiered compilation has large code-entry alignment.
42// See 4827828 for this change. There is no globals_core_i486.hpp. I can't
43// assign a different value for C2 without touching a number of files. Use
44// #ifdef to minimize the change as it's late in Mantis. -- FIXME.
45// c1 doesn't have this problem because the fix to 4858033 assures us
46// the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
47// the uep and the vep doesn't get real alignment but just slops on by
48// only assured that the entry instruction meets the 5 byte size requirement.
49#if defined(COMPILER2) || INCLUDE_JVMCI
50define_pd_global(intx, CodeEntryAlignment,       32);
51#else
52define_pd_global(intx, CodeEntryAlignment,       16);
53#endif // COMPILER2
54define_pd_global(intx, OptoLoopAlignment,        16);
55define_pd_global(intx, InlineFrequencyCount,     100);
56define_pd_global(intx, InlineSmallCode,          1000);
57
58#define DEFAULT_STACK_YELLOW_PAGES (NOT_WINDOWS(2) WINDOWS_ONLY(3))
59#define DEFAULT_STACK_RED_PAGES (1)
60#define DEFAULT_STACK_RESERVED_PAGES (NOT_WINDOWS(1) WINDOWS_ONLY(0))
61
62#define MIN_STACK_YELLOW_PAGES DEFAULT_STACK_YELLOW_PAGES
63#define MIN_STACK_RED_PAGES DEFAULT_STACK_RED_PAGES
64#define MIN_STACK_RESERVED_PAGES (0)
65
66#ifdef AMD64
67// Very large C++ stack frames using solaris-amd64 optimized builds
68// due to lack of optimization caused by C++ compiler bugs
69#define DEFAULT_STACK_SHADOW_PAGES (NOT_WIN64(20) WIN64_ONLY(7) DEBUG_ONLY(+2))
70// For those clients that do not use write socket, we allow
71// the min range value to be below that of the default
72#define MIN_STACK_SHADOW_PAGES (NOT_WIN64(10) WIN64_ONLY(7) DEBUG_ONLY(+2))
73#else
74#define DEFAULT_STACK_SHADOW_PAGES (4 DEBUG_ONLY(+5))
75#define MIN_STACK_SHADOW_PAGES DEFAULT_STACK_SHADOW_PAGES
76#endif // AMD64
77
78define_pd_global(intx, StackYellowPages, DEFAULT_STACK_YELLOW_PAGES);
79define_pd_global(intx, StackRedPages, DEFAULT_STACK_RED_PAGES);
80define_pd_global(intx, StackShadowPages, DEFAULT_STACK_SHADOW_PAGES);
81define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGES);
82
83define_pd_global(bool, RewriteBytecodes,     true);
84define_pd_global(bool, RewriteFrequentPairs, true);
85
86#ifdef _ALLBSD_SOURCE
87define_pd_global(bool, UseMembar,            true);
88#else
89define_pd_global(bool, UseMembar,            false);
90#endif
91
92// GC Ergo Flags
93define_pd_global(size_t, CMSYoungGenPerWorker, 64*M);  // default max size of CMS young gen, per GC worker thread
94
95define_pd_global(uintx, TypeProfileLevel, 111);
96
97define_pd_global(bool, CompactStrings, true);
98
99define_pd_global(bool, PreserveFramePointer, false);
100
101define_pd_global(intx, InitArrayShortSize, 8*BytesPerLong);
102
103#define ARCH_FLAGS(develop, \
104                   product, \
105                   diagnostic, \
106                   experimental, \
107                   notproduct, \
108                   range, \
109                   constraint, \
110                   writeable) \
111                                                                            \
112  develop(bool, IEEEPrecision, true,                                        \
113          "Enables IEEE precision (for INTEL only)")                        \
114                                                                            \
115  product(bool, UseStoreImmI16, true,                                       \
116          "Use store immediate 16-bits value instruction on x86")           \
117                                                                            \
118  product(intx, UseAVX, 99,                                                 \
119          "Highest supported AVX instructions set on x86/x64")              \
120          range(0, 99)                                                      \
121                                                                            \
122  product(bool, UseCLMUL, false,                                            \
123          "Control whether CLMUL instructions can be used on x86/x64")      \
124                                                                            \
125  diagnostic(bool, UseIncDec, true,                                         \
126          "Use INC, DEC instructions on x86")                               \
127                                                                            \
128  product(bool, UseNewLongLShift, false,                                    \
129          "Use optimized bitwise shift left")                               \
130                                                                            \
131  product(bool, UseAddressNop, false,                                       \
132          "Use '0F 1F [addr]' NOP instructions on x86 cpus")                \
133                                                                            \
134  product(bool, UseXmmLoadAndClearUpper, true,                              \
135          "Load low part of XMM register and clear upper part")             \
136                                                                            \
137  product(bool, UseXmmRegToRegMoveAll, false,                               \
138          "Copy all XMM register bits when moving value between registers") \
139                                                                            \
140  product(bool, UseXmmI2D, false,                                           \
141          "Use SSE2 CVTDQ2PD instruction to convert Integer to Double")     \
142                                                                            \
143  product(bool, UseXmmI2F, false,                                           \
144          "Use SSE2 CVTDQ2PS instruction to convert Integer to Float")      \
145                                                                            \
146  product(bool, UseUnalignedLoadStores, false,                              \
147          "Use SSE2 MOVDQU instruction for Arraycopy")                      \
148                                                                            \
149  product(bool, UseFastStosb, false,                                        \
150          "Use fast-string operation for zeroing: rep stosb")               \
151                                                                            \
152  /* Use Restricted Transactional Memory for lock eliding */                \
153  product(bool, UseRTMLocking, false,                                       \
154          "Enable RTM lock eliding for inflated locks in compiled code")    \
155                                                                            \
156  experimental(bool, UseRTMForStackLocks, false,                            \
157          "Enable RTM lock eliding for stack locks in compiled code")       \
158                                                                            \
159  product(bool, UseRTMDeopt, false,                                         \
160          "Perform deopt and recompilation based on RTM abort ratio")       \
161                                                                            \
162  product(uintx, RTMRetryCount, 5,                                          \
163          "Number of RTM retries on lock abort or busy")                    \
164          range(0, max_uintx)                                               \
165                                                                            \
166  experimental(intx, RTMSpinLoopCount, 100,                                 \
167          "Spin count for lock to become free before RTM retry")            \
168                                                                            \
169  experimental(intx, RTMAbortThreshold, 1000,                               \
170          "Calculate abort ratio after this number of aborts")              \
171                                                                            \
172  experimental(intx, RTMLockingThreshold, 10000,                            \
173          "Lock count at which to do RTM lock eliding without "             \
174          "abort ratio calculation")                                        \
175                                                                            \
176  experimental(intx, RTMAbortRatio, 50,                                     \
177          "Lock abort ratio at which to stop use RTM lock eliding")         \
178                                                                            \
179  experimental(intx, RTMTotalCountIncrRate, 64,                             \
180          "Increment total RTM attempted lock count once every n times")    \
181                                                                            \
182  experimental(intx, RTMLockingCalculationDelay, 0,                         \
183          "Number of milliseconds to wait before start calculating aborts " \
184          "for RTM locking")                                                \
185                                                                            \
186  experimental(bool, UseRTMXendForLockBusy, true,                           \
187          "Use RTM Xend instead of Xabort when lock busy")                  \
188                                                                            \
189  /* assembler */                                                           \
190  product(bool, UseCountLeadingZerosInstruction, false,                     \
191          "Use count leading zeros instruction")                            \
192                                                                            \
193  product(bool, UseCountTrailingZerosInstruction, false,                    \
194          "Use count trailing zeros instruction")                           \
195                                                                            \
196  product(bool, UseSSE42Intrinsics, false,                                  \
197          "SSE4.2 versions of intrinsics")                                  \
198                                                                            \
199  product(bool, UseBMI1Instructions, false,                                 \
200          "Use BMI1 instructions")                                          \
201                                                                            \
202  product(bool, UseBMI2Instructions, false,                                 \
203          "Use BMI2 instructions")                                          \
204                                                                            \
205  diagnostic(bool, UseLibmIntrinsic, true,                                  \
206          "Use Libm Intrinsics")
207#endif // CPU_X86_VM_GLOBALS_X86_HPP
208