c1_Defs_x86.hpp revision 1472:c18cbe5936b8
1/* 2 * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25// native word offsets from memory address (little endian) 26enum { 27 pd_lo_word_offset_in_bytes = 0, 28 pd_hi_word_offset_in_bytes = BytesPerWord 29}; 30 31// explicit rounding operations are required to implement the strictFP mode 32enum { 33 pd_strict_fp_requires_explicit_rounding = true 34}; 35 36 37// registers 38enum { 39 pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission 40 pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission 41 pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission 42 43#ifdef _LP64 44 #define UNALLOCATED 4 // rsp, rbp, r15, r10 45#else 46 #define UNALLOCATED 2 // rsp, rbp 47#endif // LP64 48 49 pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls 50 pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls 51 pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls 52 53 pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator 54 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator 55 56 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan 57 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan 58 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan 59 pd_first_cpu_reg = 0, 60 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11), 61 pd_first_byte_reg = 2, 62 pd_last_byte_reg = 5, 63 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, 64 pd_last_fpu_reg = pd_first_fpu_reg + 7, 65 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, 66 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1 67}; 68 69 70// encoding of float value in debug info: 71enum { 72 pd_float_saved_as_double = true 73}; 74