sparc.ad revision 235:9c2ecc2ffb12
1// 2// Copyright 1998-2008 Sun Microsystems, Inc. All Rights Reserved. 3// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4// 5// This code is free software; you can redistribute it and/or modify it 6// under the terms of the GNU General Public License version 2 only, as 7// published by the Free Software Foundation. 8// 9// This code is distributed in the hope that it will be useful, but WITHOUT 10// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12// version 2 for more details (a copy is included in the LICENSE file that 13// accompanied this code). 14// 15// You should have received a copy of the GNU General Public License version 16// 2 along with this work; if not, write to the Free Software Foundation, 17// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18// 19// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20// CA 95054 USA or visit www.sun.com if you need additional information or 21// have any questions. 22// 23// 24 25// SPARC Architecture Description File 26 27//----------REGISTER DEFINITION BLOCK------------------------------------------ 28// This information is used by the matcher and the register allocator to 29// describe individual registers and classes of registers within the target 30// archtecture. 31register %{ 32//----------Architecture Description Register Definitions---------------------- 33// General Registers 34// "reg_def" name ( register save type, C convention save type, 35// ideal register type, encoding, vm name ); 36// Register Save Types: 37// 38// NS = No-Save: The register allocator assumes that these registers 39// can be used without saving upon entry to the method, & 40// that they do not need to be saved at call sites. 41// 42// SOC = Save-On-Call: The register allocator assumes that these registers 43// can be used without saving upon entry to the method, 44// but that they must be saved at call sites. 45// 46// SOE = Save-On-Entry: The register allocator assumes that these registers 47// must be saved before using them upon entry to the 48// method, but they do not need to be saved at call 49// sites. 50// 51// AS = Always-Save: The register allocator assumes that these registers 52// must be saved before using them upon entry to the 53// method, & that they must be saved at call sites. 54// 55// Ideal Register Type is used to determine how to save & restore a 56// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58// 59// The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62// ---------------------------- 63// Integer/Long Registers 64// ---------------------------- 65 66// Need to expose the hi/lo aspect of 64-bit registers 67// This register set is used for both the 64-bit build and 68// the 32-bit build with 1-register longs. 69 70// Global Registers 0-7 71reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88// Output Registers 0-7 89reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106// Local Registers 0-7 107reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124// Input Registers 0-7 125reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142// ---------------------------- 143// Float/Double Registers 144// ---------------------------- 145 146// Float Registers 147reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180// Double Registers 181// The rules of ADL require that double registers be defined in pairs. 182// Each pair must be two 32-bit values, but not necessarily a pair of 183// single float registers. In each pair, ADLC-assigned register numbers 184// must be adjacent, with the lower number even. Finally, when the 185// CPU stores such a register pair to memory, the word associated with 186// the lower ADLC-assigned number must be stored to the lower address. 187 188// These definitions specify the actual bit encodings of the sparc 189// double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190// wants 0-63, so we have to convert every time we want to use fp regs 191// with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192// 255 is a flag meaning 'dont go here'. 193// I believe we can't handle callee-save doubles D32 and up until 194// the place in the sparc stack crawler that asserts on the 255 is 195// fixed up. 196reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()); 197reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next()); 198reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()); 199reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next()); 200reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()); 201reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next()); 202reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()); 203reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next()); 204reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()); 205reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next()); 206reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()); 207reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next()); 208reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()); 209reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next()); 210reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()); 211reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next()); 212reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()); 213reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next()); 214reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()); 215reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next()); 216reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()); 217reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next()); 218reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()); 219reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next()); 220reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()); 221reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next()); 222reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()); 223reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next()); 224reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()); 225reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next()); 226reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()); 227reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next()); 228 229 230// ---------------------------- 231// Special Registers 232// Condition Codes Flag Registers 233// I tried to break out ICC and XCC but it's not very pretty. 234// Every Sparc instruction which defs/kills one also kills the other. 235// Hence every compare instruction which defs one kind of flags ends 236// up needing a kill of the other. 237reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244// ---------------------------- 245// Specify the enum values for the registers. These enums are only used by the 246// OptoReg "class". We can convert these enum values at will to VMReg when needed 247// for visibility to the rest of the vm. The order of this enum influences the 248// register allocator so having the freedom to set this order and not be stuck 249// with the order that is natural for the rest of the vm is worth it. 250alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256// Note that a register is not allocatable unless it is also mentioned 257// in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277//----------Architecture Description Register Classes-------------------------- 278// Several register classes are automatically defined based upon information in 279// this architecture description. 280// 1) reg_class inline_cache_reg ( as defined in frame section ) 281// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283// 284 285// G0 is not included in integer class since it has special meaning. 286reg_class g0_reg(R_G0); 287 288// ---------------------------- 289// Integer Register Classes 290// ---------------------------- 291// Exclusions from i_reg: 292// R_G0: hardwired zero 293// R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294// R_G6: reserved by Solaris ABI to tools 295// R_G7: reserved by Solaris ABI to libthread 296// R_O7: Used as a temp in many encodings 297reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299// Class for all integer registers, except the G registers. This is used for 300// encodings which use G registers as temps. The regular inputs to such 301// instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302// will not put an input into a temp register. 303reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305reg_class g1_regI(R_G1); 306reg_class g3_regI(R_G3); 307reg_class g4_regI(R_G4); 308reg_class o0_regI(R_O0); 309reg_class o7_regI(R_O7); 310 311// ---------------------------- 312// Pointer Register Classes 313// ---------------------------- 314#ifdef _LP64 315// 64-bit build means 64-bit pointers means hi/lo pairs 316reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320// Lock encodings use G3 and G4 internally 321reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325// Special class for storeP instructions, which can store SP or RPC to TLS. 326// It is also used for memory addressing, allowing direct TLS addressing. 327reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331// R_L7 is the lowest-priority callee-save (i.e., NS) register 332// We use it to save R_G2 across calls out of Java. 333reg_class l7_regP(R_L7H,R_L7); 334 335// Other special pointer regs 336reg_class g1_regP(R_G1H,R_G1); 337reg_class g2_regP(R_G2H,R_G2); 338reg_class g3_regP(R_G3H,R_G3); 339reg_class g4_regP(R_G4H,R_G4); 340reg_class g5_regP(R_G5H,R_G5); 341reg_class i0_regP(R_I0H,R_I0); 342reg_class o0_regP(R_O0H,R_O0); 343reg_class o1_regP(R_O1H,R_O1); 344reg_class o2_regP(R_O2H,R_O2); 345reg_class o7_regP(R_O7H,R_O7); 346 347#else // _LP64 348// 32-bit build means 32-bit pointers means 1 register. 349reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353// Lock encodings use G3 and G4 internally 354reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358// Special class for storeP instructions, which can store SP or RPC to TLS. 359// It is also used for memory addressing, allowing direct TLS addressing. 360reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364// R_L7 is the lowest-priority callee-save (i.e., NS) register 365// We use it to save R_G2 across calls out of Java. 366reg_class l7_regP(R_L7); 367 368// Other special pointer regs 369reg_class g1_regP(R_G1); 370reg_class g2_regP(R_G2); 371reg_class g3_regP(R_G3); 372reg_class g4_regP(R_G4); 373reg_class g5_regP(R_G5); 374reg_class i0_regP(R_I0); 375reg_class o0_regP(R_O0); 376reg_class o1_regP(R_O1); 377reg_class o2_regP(R_O2); 378reg_class o7_regP(R_O7); 379#endif // _LP64 380 381 382// ---------------------------- 383// Long Register Classes 384// ---------------------------- 385// Longs in 1 register. Aligned adjacent hi/lo pairs. 386// Note: O7 is never in this class; it is sometimes used as an encoding temp. 387reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389#ifdef _LP64 390// 64-bit, longs in 1 register: use all 64-bit integer registers 391// 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394#endif // _LP64 395 ); 396 397reg_class g1_regL(R_G1H,R_G1); 398reg_class o2_regL(R_O2H,R_O2); 399reg_class o7_regL(R_O7H,R_O7); 400 401// ---------------------------- 402// Special Class for Condition Code Flags Register 403reg_class int_flags(CCR); 404reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 405reg_class float_flag0(FCC0); 406 407 408// ---------------------------- 409// Float Point Register Classes 410// ---------------------------- 411// Skip F30/F31, they are reserved for mem-mem copies 412reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 413 414// Paired floating point registers--they show up in the same order as the floats, 415// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 416reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 417 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 418 /* Use extra V9 double registers; this AD file does not support V8 */ 419 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 420 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 421 ); 422 423// Paired floating point registers--they show up in the same order as the floats, 424// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 425// This class is usable for mis-aligned loads as happen in I2C adapters. 426reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 427 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); 428%} 429 430//----------DEFINITION BLOCK--------------------------------------------------- 431// Define name --> value mappings to inform the ADLC of an integer valued name 432// Current support includes integer values in the range [0, 0x7FFFFFFF] 433// Format: 434// int_def <name> ( <int_value>, <expression>); 435// Generated Code in ad_<arch>.hpp 436// #define <name> (<expression>) 437// // value == <int_value> 438// Generated code in ad_<arch>.cpp adlc_verification() 439// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 440// 441definitions %{ 442// The default cost (of an ALU instruction). 443 int_def DEFAULT_COST ( 100, 100); 444 int_def HUGE_COST (1000000, 1000000); 445 446// Memory refs are twice as expensive as run-of-the-mill. 447 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 448 449// Branches are even more expensive. 450 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 451 int_def CALL_COST ( 300, DEFAULT_COST * 3); 452%} 453 454 455//----------SOURCE BLOCK------------------------------------------------------- 456// This is a block of C++ code which provides values, functions, and 457// definitions necessary in the rest of the architecture description 458source_hpp %{ 459// Must be visible to the DFA in dfa_sparc.cpp 460extern bool can_branch_register( Node *bol, Node *cmp ); 461 462// Macros to extract hi & lo halves from a long pair. 463// G0 is not part of any long pair, so assert on that. 464// Prevents accidently using G1 instead of G0. 465#define LONG_HI_REG(x) (x) 466#define LONG_LO_REG(x) (x) 467 468%} 469 470source %{ 471#define __ _masm. 472 473// tertiary op of a LoadP or StoreP encoding 474#define REGP_OP true 475 476static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 477static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 478static Register reg_to_register_object(int register_encoding); 479 480// Used by the DFA in dfa_sparc.cpp. 481// Check for being able to use a V9 branch-on-register. Requires a 482// compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 483// extended. Doesn't work following an integer ADD, for example, because of 484// overflow (-1 incremented yields 0 plus a carry in the high-order word). On 485// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 486// replace them with zero, which could become sign-extension in a different OS 487// release. There's no obvious reason why an interrupt will ever fill these 488// bits with non-zero junk (the registers are reloaded with standard LD 489// instructions which either zero-fill or sign-fill). 490bool can_branch_register( Node *bol, Node *cmp ) { 491 if( !BranchOnRegister ) return false; 492#ifdef _LP64 493 if( cmp->Opcode() == Op_CmpP ) 494 return true; // No problems with pointer compares 495#endif 496 if( cmp->Opcode() == Op_CmpL ) 497 return true; // No problems with long compares 498 499 if( !SparcV9RegsHiBitsZero ) return false; 500 if( bol->as_Bool()->_test._test != BoolTest::ne && 501 bol->as_Bool()->_test._test != BoolTest::eq ) 502 return false; 503 504 // Check for comparing against a 'safe' value. Any operation which 505 // clears out the high word is safe. Thus, loads and certain shifts 506 // are safe, as are non-negative constants. Any operation which 507 // preserves zero bits in the high word is safe as long as each of its 508 // inputs are safe. Thus, phis and bitwise booleans are safe if their 509 // inputs are safe. At present, the only important case to recognize 510 // seems to be loads. Constants should fold away, and shifts & 511 // logicals can use the 'cc' forms. 512 Node *x = cmp->in(1); 513 if( x->is_Load() ) return true; 514 if( x->is_Phi() ) { 515 for( uint i = 1; i < x->req(); i++ ) 516 if( !x->in(i)->is_Load() ) 517 return false; 518 return true; 519 } 520 return false; 521} 522 523// **************************************************************************** 524 525// REQUIRED FUNCTIONALITY 526 527// !!!!! Special hack to get all type of calls to specify the byte offset 528// from the start of the call to the point where the return address 529// will point. 530// The "return address" is the address of the call instruction, plus 8. 531 532int MachCallStaticJavaNode::ret_addr_offset() { 533 return NativeCall::instruction_size; // call; delay slot 534} 535 536int MachCallDynamicJavaNode::ret_addr_offset() { 537 int vtable_index = this->_vtable_index; 538 if (vtable_index < 0) { 539 // must be invalid_vtable_index, not nonvirtual_vtable_index 540 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 541 return (NativeMovConstReg::instruction_size + 542 NativeCall::instruction_size); // sethi; setlo; call; delay slot 543 } else { 544 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 545 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 546 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 547 int klass_load_size; 548 if (UseCompressedOops) { 549 klass_load_size = 3*BytesPerInstWord; // see MacroAssembler::load_klass() 550 } else { 551 klass_load_size = 1*BytesPerInstWord; 552 } 553 if( Assembler::is_simm13(v_off) ) { 554 return klass_load_size + 555 (2*BytesPerInstWord + // ld_ptr, ld_ptr 556 NativeCall::instruction_size); // call; delay slot 557 } else { 558 return klass_load_size + 559 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 560 NativeCall::instruction_size); // call; delay slot 561 } 562 } 563} 564 565int MachCallRuntimeNode::ret_addr_offset() { 566#ifdef _LP64 567 return NativeFarCall::instruction_size; // farcall; delay slot 568#else 569 return NativeCall::instruction_size; // call; delay slot 570#endif 571} 572 573// Indicate if the safepoint node needs the polling page as an input. 574// Since Sparc does not have absolute addressing, it does. 575bool SafePointNode::needs_polling_address_input() { 576 return true; 577} 578 579// emit an interrupt that is caught by the debugger (for debugging compiler) 580void emit_break(CodeBuffer &cbuf) { 581 MacroAssembler _masm(&cbuf); 582 __ breakpoint_trap(); 583} 584 585#ifndef PRODUCT 586void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 587 st->print("TA"); 588} 589#endif 590 591void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 592 emit_break(cbuf); 593} 594 595uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 596 return MachNode::size(ra_); 597} 598 599// Traceable jump 600void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 601 MacroAssembler _masm(&cbuf); 602 Register rdest = reg_to_register_object(jump_target); 603 __ JMP(rdest, 0); 604 __ delayed()->nop(); 605} 606 607// Traceable jump and set exception pc 608void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 609 MacroAssembler _masm(&cbuf); 610 Register rdest = reg_to_register_object(jump_target); 611 __ JMP(rdest, 0); 612 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 613} 614 615void emit_nop(CodeBuffer &cbuf) { 616 MacroAssembler _masm(&cbuf); 617 __ nop(); 618} 619 620void emit_illtrap(CodeBuffer &cbuf) { 621 MacroAssembler _masm(&cbuf); 622 __ illtrap(0); 623} 624 625 626intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 627 assert(n->rule() != loadUB_rule, ""); 628 629 intptr_t offset = 0; 630 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 631 const Node* addr = n->get_base_and_disp(offset, adr_type); 632 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 633 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 634 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 635 atype = atype->add_offset(offset); 636 assert(disp32 == offset, "wrong disp32"); 637 return atype->_offset; 638} 639 640 641intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 642 assert(n->rule() != loadUB_rule, ""); 643 644 intptr_t offset = 0; 645 Node* addr = n->in(2); 646 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 647 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 648 Node* a = addr->in(2/*AddPNode::Address*/); 649 Node* o = addr->in(3/*AddPNode::Offset*/); 650 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 651 atype = a->bottom_type()->is_ptr()->add_offset(offset); 652 assert(atype->isa_oop_ptr(), "still an oop"); 653 } 654 offset = atype->is_ptr()->_offset; 655 if (offset != Type::OffsetBot) offset += disp32; 656 return offset; 657} 658 659// Standard Sparc opcode form2 field breakdown 660static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 661 f0 &= (1<<19)-1; // Mask displacement to 19 bits 662 int op = (f30 << 30) | 663 (f29 << 29) | 664 (f25 << 25) | 665 (f22 << 22) | 666 (f20 << 20) | 667 (f19 << 19) | 668 (f0 << 0); 669 *((int*)(cbuf.code_end())) = op; 670 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 671} 672 673// Standard Sparc opcode form2 field breakdown 674static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 675 f0 >>= 10; // Drop 10 bits 676 f0 &= (1<<22)-1; // Mask displacement to 22 bits 677 int op = (f30 << 30) | 678 (f25 << 25) | 679 (f22 << 22) | 680 (f0 << 0); 681 *((int*)(cbuf.code_end())) = op; 682 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 683} 684 685// Standard Sparc opcode form3 field breakdown 686static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 687 int op = (f30 << 30) | 688 (f25 << 25) | 689 (f19 << 19) | 690 (f14 << 14) | 691 (f5 << 5) | 692 (f0 << 0); 693 *((int*)(cbuf.code_end())) = op; 694 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 695} 696 697// Standard Sparc opcode form3 field breakdown 698static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 699 simm13 &= (1<<13)-1; // Mask to 13 bits 700 int op = (f30 << 30) | 701 (f25 << 25) | 702 (f19 << 19) | 703 (f14 << 14) | 704 (1 << 13) | // bit to indicate immediate-mode 705 (simm13<<0); 706 *((int*)(cbuf.code_end())) = op; 707 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 708} 709 710static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 711 simm10 &= (1<<10)-1; // Mask to 10 bits 712 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 713} 714 715#ifdef ASSERT 716// Helper function for VerifyOops in emit_form3_mem_reg 717void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 718 warning("VerifyOops encountered unexpected instruction:"); 719 n->dump(2); 720 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 721} 722#endif 723 724 725void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 726 int src1_enc, int disp32, int src2_enc, int dst_enc) { 727 728#ifdef ASSERT 729 // The following code implements the +VerifyOops feature. 730 // It verifies oop values which are loaded into or stored out of 731 // the current method activation. +VerifyOops complements techniques 732 // like ScavengeALot, because it eagerly inspects oops in transit, 733 // as they enter or leave the stack, as opposed to ScavengeALot, 734 // which inspects oops "at rest", in the stack or heap, at safepoints. 735 // For this reason, +VerifyOops can sometimes detect bugs very close 736 // to their point of creation. It can also serve as a cross-check 737 // on the validity of oop maps, when used toegether with ScavengeALot. 738 739 // It would be good to verify oops at other points, especially 740 // when an oop is used as a base pointer for a load or store. 741 // This is presently difficult, because it is hard to know when 742 // a base address is biased or not. (If we had such information, 743 // it would be easy and useful to make a two-argument version of 744 // verify_oop which unbiases the base, and performs verification.) 745 746 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 747 bool is_verified_oop_base = false; 748 bool is_verified_oop_load = false; 749 bool is_verified_oop_store = false; 750 int tmp_enc = -1; 751 if (VerifyOops && src1_enc != R_SP_enc) { 752 // classify the op, mainly for an assert check 753 int st_op = 0, ld_op = 0; 754 switch (primary) { 755 case Assembler::stb_op3: st_op = Op_StoreB; break; 756 case Assembler::sth_op3: st_op = Op_StoreC; break; 757 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 758 case Assembler::stw_op3: st_op = Op_StoreI; break; 759 case Assembler::std_op3: st_op = Op_StoreL; break; 760 case Assembler::stf_op3: st_op = Op_StoreF; break; 761 case Assembler::stdf_op3: st_op = Op_StoreD; break; 762 763 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 764 case Assembler::lduh_op3: ld_op = Op_LoadC; break; 765 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 766 case Assembler::ldx_op3: // may become LoadP or stay LoadI 767 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 768 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 769 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 770 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 771 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 772 case Assembler::ldub_op3: ld_op = Op_LoadB; break; 773 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 774 775 default: ShouldNotReachHere(); 776 } 777 if (tertiary == REGP_OP) { 778 if (st_op == Op_StoreI) st_op = Op_StoreP; 779 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 780 else ShouldNotReachHere(); 781 if (st_op) { 782 // a store 783 // inputs are (0:control, 1:memory, 2:address, 3:value) 784 Node* n2 = n->in(3); 785 if (n2 != NULL) { 786 const Type* t = n2->bottom_type(); 787 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 788 } 789 } else { 790 // a load 791 const Type* t = n->bottom_type(); 792 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 793 } 794 } 795 796 if (ld_op) { 797 // a Load 798 // inputs are (0:control, 1:memory, 2:address) 799 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 800 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 801 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 802 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 803 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 804 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 805 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 806 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 807 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 808 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 809 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 810 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 811 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 812 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 813 !(n->rule() == loadUB_rule)) { 814 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 815 } 816 } else if (st_op) { 817 // a Store 818 // inputs are (0:control, 1:memory, 2:address, 3:value) 819 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 820 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 821 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 822 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 823 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 824 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 825 verify_oops_warning(n, n->ideal_Opcode(), st_op); 826 } 827 } 828 829 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 830 Node* addr = n->in(2); 831 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 832 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 833 if (atype != NULL) { 834 intptr_t offset = get_offset_from_base(n, atype, disp32); 835 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 836 if (offset != offset_2) { 837 get_offset_from_base(n, atype, disp32); 838 get_offset_from_base_2(n, atype, disp32); 839 } 840 assert(offset == offset_2, "different offsets"); 841 if (offset == disp32) { 842 // we now know that src1 is a true oop pointer 843 is_verified_oop_base = true; 844 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 845 if( primary == Assembler::ldd_op3 ) { 846 is_verified_oop_base = false; // Cannot 'ldd' into O7 847 } else { 848 tmp_enc = dst_enc; 849 dst_enc = R_O7_enc; // Load into O7; preserve source oop 850 assert(src1_enc != dst_enc, ""); 851 } 852 } 853 } 854 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 855 || offset == oopDesc::mark_offset_in_bytes())) { 856 // loading the mark should not be allowed either, but 857 // we don't check this since it conflicts with InlineObjectHash 858 // usage of LoadINode to get the mark. We could keep the 859 // check if we create a new LoadMarkNode 860 // but do not verify the object before its header is initialized 861 ShouldNotReachHere(); 862 } 863 } 864 } 865 } 866 } 867#endif 868 869 uint instr; 870 instr = (Assembler::ldst_op << 30) 871 | (dst_enc << 25) 872 | (primary << 19) 873 | (src1_enc << 14); 874 875 uint index = src2_enc; 876 int disp = disp32; 877 878 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 879 disp += STACK_BIAS; 880 881 // We should have a compiler bailout here rather than a guarantee. 882 // Better yet would be some mechanism to handle variable-size matches correctly. 883 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 884 885 if( disp == 0 ) { 886 // use reg-reg form 887 // bit 13 is already zero 888 instr |= index; 889 } else { 890 // use reg-imm form 891 instr |= 0x00002000; // set bit 13 to one 892 instr |= disp & 0x1FFF; 893 } 894 895 uint *code = (uint*)cbuf.code_end(); 896 *code = instr; 897 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 898 899#ifdef ASSERT 900 { 901 MacroAssembler _masm(&cbuf); 902 if (is_verified_oop_base) { 903 __ verify_oop(reg_to_register_object(src1_enc)); 904 } 905 if (is_verified_oop_store) { 906 __ verify_oop(reg_to_register_object(dst_enc)); 907 } 908 if (tmp_enc != -1) { 909 __ mov(O7, reg_to_register_object(tmp_enc)); 910 } 911 if (is_verified_oop_load) { 912 __ verify_oop(reg_to_register_object(dst_enc)); 913 } 914 } 915#endif 916} 917 918void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 919 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { 920 921 uint instr; 922 instr = (Assembler::ldst_op << 30) 923 | (dst_enc << 25) 924 | (primary << 19) 925 | (src1_enc << 14); 926 927 int disp = disp32; 928 int index = src2_enc; 929 930 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 931 disp += STACK_BIAS; 932 933 // We should have a compiler bailout here rather than a guarantee. 934 // Better yet would be some mechanism to handle variable-size matches correctly. 935 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 936 937 if( disp != 0 ) { 938 // use reg-reg form 939 // set src2=R_O7 contains offset 940 index = R_O7_enc; 941 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); 942 } 943 instr |= (asi << 5); 944 instr |= index; 945 uint *code = (uint*)cbuf.code_end(); 946 *code = instr; 947 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 948} 949 950void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { 951 // The method which records debug information at every safepoint 952 // expects the call to be the first instruction in the snippet as 953 // it creates a PcDesc structure which tracks the offset of a call 954 // from the start of the codeBlob. This offset is computed as 955 // code_end() - code_begin() of the code which has been emitted 956 // so far. 957 // In this particular case we have skirted around the problem by 958 // putting the "mov" instruction in the delay slot but the problem 959 // may bite us again at some other point and a cleaner/generic 960 // solution using relocations would be needed. 961 MacroAssembler _masm(&cbuf); 962 __ set_inst_mark(); 963 964 // We flush the current window just so that there is a valid stack copy 965 // the fact that the current window becomes active again instantly is 966 // not a problem there is nothing live in it. 967 968#ifdef ASSERT 969 int startpos = __ offset(); 970#endif /* ASSERT */ 971 972#ifdef _LP64 973 // Calls to the runtime or native may not be reachable from compiled code, 974 // so we generate the far call sequence on 64 bit sparc. 975 // This code sequence is relocatable to any address, even on LP64. 976 if ( force_far_call ) { 977 __ relocate(rtype); 978 Address dest(O7, (address)entry_point); 979 __ jumpl_to(dest, O7); 980 } 981 else 982#endif 983 { 984 __ call((address)entry_point, rtype); 985 } 986 987 if (preserve_g2) __ delayed()->mov(G2, L7); 988 else __ delayed()->nop(); 989 990 if (preserve_g2) __ mov(L7, G2); 991 992#ifdef ASSERT 993 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 994#ifdef _LP64 995 // Trash argument dump slots. 996 __ set(0xb0b8ac0db0b8ac0d, G1); 997 __ mov(G1, G5); 998 __ stx(G1, SP, STACK_BIAS + 0x80); 999 __ stx(G1, SP, STACK_BIAS + 0x88); 1000 __ stx(G1, SP, STACK_BIAS + 0x90); 1001 __ stx(G1, SP, STACK_BIAS + 0x98); 1002 __ stx(G1, SP, STACK_BIAS + 0xA0); 1003 __ stx(G1, SP, STACK_BIAS + 0xA8); 1004#else // _LP64 1005 // this is also a native call, so smash the first 7 stack locations, 1006 // and the various registers 1007 1008 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1009 // while [SP+0x44..0x58] are the argument dump slots. 1010 __ set((intptr_t)0xbaadf00d, G1); 1011 __ mov(G1, G5); 1012 __ sllx(G1, 32, G1); 1013 __ or3(G1, G5, G1); 1014 __ mov(G1, G5); 1015 __ stx(G1, SP, 0x40); 1016 __ stx(G1, SP, 0x48); 1017 __ stx(G1, SP, 0x50); 1018 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1019#endif // _LP64 1020 } 1021#endif /*ASSERT*/ 1022} 1023 1024//============================================================================= 1025// REQUIRED FUNCTIONALITY for encoding 1026void emit_lo(CodeBuffer &cbuf, int val) { } 1027void emit_hi(CodeBuffer &cbuf, int val) { } 1028 1029void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) { 1030 MacroAssembler _masm(&cbuf); 1031 if (ForceRelocatable) { 1032 Address addr(reg, (address)val); 1033 __ sethi(addr, ForceRelocatable); 1034 __ add(addr, reg); 1035 } else { 1036 __ set(val, reg); 1037 } 1038} 1039 1040 1041//============================================================================= 1042 1043#ifndef PRODUCT 1044void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1045 Compile* C = ra_->C; 1046 1047 for (int i = 0; i < OptoPrologueNops; i++) { 1048 st->print_cr("NOP"); st->print("\t"); 1049 } 1050 1051 if( VerifyThread ) { 1052 st->print_cr("Verify_Thread"); st->print("\t"); 1053 } 1054 1055 size_t framesize = C->frame_slots() << LogBytesPerInt; 1056 1057 // Calls to C2R adapters often do not accept exceptional returns. 1058 // We require that their callers must bang for them. But be careful, because 1059 // some VM calls (such as call site linkage) can use several kilobytes of 1060 // stack. But the stack safety zone should account for that. 1061 // See bugs 4446381, 4468289, 4497237. 1062 if (C->need_stack_bang(framesize)) { 1063 st->print_cr("! stack bang"); st->print("\t"); 1064 } 1065 1066 if (Assembler::is_simm13(-framesize)) { 1067 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1068 } else { 1069 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1070 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1071 st->print ("SAVE R_SP,R_G3,R_SP"); 1072 } 1073 1074} 1075#endif 1076 1077void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1078 Compile* C = ra_->C; 1079 MacroAssembler _masm(&cbuf); 1080 1081 for (int i = 0; i < OptoPrologueNops; i++) { 1082 __ nop(); 1083 } 1084 1085 __ verify_thread(); 1086 1087 size_t framesize = C->frame_slots() << LogBytesPerInt; 1088 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1089 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1090 1091 // Calls to C2R adapters often do not accept exceptional returns. 1092 // We require that their callers must bang for them. But be careful, because 1093 // some VM calls (such as call site linkage) can use several kilobytes of 1094 // stack. But the stack safety zone should account for that. 1095 // See bugs 4446381, 4468289, 4497237. 1096 if (C->need_stack_bang(framesize)) { 1097 __ generate_stack_overflow_check(framesize); 1098 } 1099 1100 if (Assembler::is_simm13(-framesize)) { 1101 __ save(SP, -framesize, SP); 1102 } else { 1103 __ sethi(-framesize & ~0x3ff, G3); 1104 __ add(G3, -framesize & 0x3ff, G3); 1105 __ save(SP, G3, SP); 1106 } 1107 C->set_frame_complete( __ offset() ); 1108} 1109 1110uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1111 return MachNode::size(ra_); 1112} 1113 1114int MachPrologNode::reloc() const { 1115 return 10; // a large enough number 1116} 1117 1118//============================================================================= 1119#ifndef PRODUCT 1120void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1121 Compile* C = ra_->C; 1122 1123 if( do_polling() && ra_->C->is_method_compilation() ) { 1124 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1125#ifdef _LP64 1126 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1127#else 1128 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1129#endif 1130 } 1131 1132 if( do_polling() ) 1133 st->print("RET\n\t"); 1134 1135 st->print("RESTORE"); 1136} 1137#endif 1138 1139void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1140 MacroAssembler _masm(&cbuf); 1141 Compile* C = ra_->C; 1142 1143 __ verify_thread(); 1144 1145 // If this does safepoint polling, then do it here 1146 if( do_polling() && ra_->C->is_method_compilation() ) { 1147 Address polling_page(L0, (address)os::get_polling_page()); 1148 __ sethi(polling_page, false); 1149 __ relocate(relocInfo::poll_return_type); 1150 __ ld_ptr( L0, 0, G0 ); 1151 } 1152 1153 // If this is a return, then stuff the restore in the delay slot 1154 if( do_polling() ) { 1155 __ ret(); 1156 __ delayed()->restore(); 1157 } else { 1158 __ restore(); 1159 } 1160} 1161 1162uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1163 return MachNode::size(ra_); 1164} 1165 1166int MachEpilogNode::reloc() const { 1167 return 16; // a large enough number 1168} 1169 1170const Pipeline * MachEpilogNode::pipeline() const { 1171 return MachNode::pipeline_class(); 1172} 1173 1174int MachEpilogNode::safepoint_offset() const { 1175 assert( do_polling(), "no return for this epilog node"); 1176 return MacroAssembler::size_of_sethi(os::get_polling_page()); 1177} 1178 1179//============================================================================= 1180 1181// Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1182enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1183static enum RC rc_class( OptoReg::Name reg ) { 1184 if( !OptoReg::is_valid(reg) ) return rc_bad; 1185 if (OptoReg::is_stack(reg)) return rc_stack; 1186 VMReg r = OptoReg::as_VMReg(reg); 1187 if (r->is_Register()) return rc_int; 1188 assert(r->is_FloatRegister(), "must be"); 1189 return rc_float; 1190} 1191 1192static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1193 if( cbuf ) { 1194 // Better yet would be some mechanism to handle variable-size matches correctly 1195 if (!Assembler::is_simm13(offset + STACK_BIAS)) { 1196 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 1197 } else { 1198 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1199 } 1200 } 1201#ifndef PRODUCT 1202 else if( !do_size ) { 1203 if( size != 0 ) st->print("\n\t"); 1204 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1205 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1206 } 1207#endif 1208 return size+4; 1209} 1210 1211static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1212 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1213#ifndef PRODUCT 1214 else if( !do_size ) { 1215 if( size != 0 ) st->print("\n\t"); 1216 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1217 } 1218#endif 1219 return size+4; 1220} 1221 1222uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1223 PhaseRegAlloc *ra_, 1224 bool do_size, 1225 outputStream* st ) const { 1226 // Get registers to move 1227 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1228 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1229 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1230 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1231 1232 enum RC src_second_rc = rc_class(src_second); 1233 enum RC src_first_rc = rc_class(src_first); 1234 enum RC dst_second_rc = rc_class(dst_second); 1235 enum RC dst_first_rc = rc_class(dst_first); 1236 1237 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1238 1239 // Generate spill code! 1240 int size = 0; 1241 1242 if( src_first == dst_first && src_second == dst_second ) 1243 return size; // Self copy, no move 1244 1245 // -------------------------------------- 1246 // Check for mem-mem move. Load into unused float registers and fall into 1247 // the float-store case. 1248 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1249 int offset = ra_->reg2offset(src_first); 1250 // Further check for aligned-adjacent pair, so we can use a double load 1251 if( (src_first&1)==0 && src_first+1 == src_second ) { 1252 src_second = OptoReg::Name(R_F31_num); 1253 src_second_rc = rc_float; 1254 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1255 } else { 1256 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1257 } 1258 src_first = OptoReg::Name(R_F30_num); 1259 src_first_rc = rc_float; 1260 } 1261 1262 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1263 int offset = ra_->reg2offset(src_second); 1264 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1265 src_second = OptoReg::Name(R_F31_num); 1266 src_second_rc = rc_float; 1267 } 1268 1269 // -------------------------------------- 1270 // Check for float->int copy; requires a trip through memory 1271 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { 1272 int offset = frame::register_save_words*wordSize; 1273 if( cbuf ) { 1274 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1275 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1276 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1277 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1278 } 1279#ifndef PRODUCT 1280 else if( !do_size ) { 1281 if( size != 0 ) st->print("\n\t"); 1282 st->print( "SUB R_SP,16,R_SP\n"); 1283 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1284 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1285 st->print("\tADD R_SP,16,R_SP\n"); 1286 } 1287#endif 1288 size += 16; 1289 } 1290 1291 // -------------------------------------- 1292 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1293 // In such cases, I have to do the big-endian swap. For aligned targets, the 1294 // hardware does the flop for me. Doubles are always aligned, so no problem 1295 // there. Misaligned sources only come from native-long-returns (handled 1296 // special below). 1297#ifndef _LP64 1298 if( src_first_rc == rc_int && // source is already big-endian 1299 src_second_rc != rc_bad && // 64-bit move 1300 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1301 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1302 // Do the big-endian flop. 1303 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1304 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1305 } 1306#endif 1307 1308 // -------------------------------------- 1309 // Check for integer reg-reg copy 1310 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1311#ifndef _LP64 1312 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1313 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1314 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1315 // operand contains the least significant word of the 64-bit value and vice versa. 1316 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1317 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1318 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1319 if( cbuf ) { 1320 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1321 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1322 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1323#ifndef PRODUCT 1324 } else if( !do_size ) { 1325 if( size != 0 ) st->print("\n\t"); 1326 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1327 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1328 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1329#endif 1330 } 1331 return size+12; 1332 } 1333 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1334 // returning a long value in I0/I1 1335 // a SpillCopy must be able to target a return instruction's reg_class 1336 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1337 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1338 // operand contains the least significant word of the 64-bit value and vice versa. 1339 OptoReg::Name tdest = dst_first; 1340 1341 if (src_first == dst_first) { 1342 tdest = OptoReg::Name(R_O7_num); 1343 size += 4; 1344 } 1345 1346 if( cbuf ) { 1347 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1348 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1349 // ShrL_reg_imm6 1350 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1351 // ShrR_reg_imm6 src, 0, dst 1352 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1353 if (tdest != dst_first) { 1354 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1355 } 1356 } 1357#ifndef PRODUCT 1358 else if( !do_size ) { 1359 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1360 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1361 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1362 if (tdest != dst_first) { 1363 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1364 } 1365 } 1366#endif // PRODUCT 1367 return size+8; 1368 } 1369#endif // !_LP64 1370 // Else normal reg-reg copy 1371 assert( src_second != dst_first, "smashed second before evacuating it" ); 1372 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1373 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1374 // This moves an aligned adjacent pair. 1375 // See if we are done. 1376 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1377 return size; 1378 } 1379 1380 // Check for integer store 1381 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1382 int offset = ra_->reg2offset(dst_first); 1383 // Further check for aligned-adjacent pair, so we can use a double store 1384 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1385 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1386 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1387 } 1388 1389 // Check for integer load 1390 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1391 int offset = ra_->reg2offset(src_first); 1392 // Further check for aligned-adjacent pair, so we can use a double load 1393 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1394 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1395 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1396 } 1397 1398 // Check for float reg-reg copy 1399 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1400 // Further check for aligned-adjacent pair, so we can use a double move 1401 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1402 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1403 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1404 } 1405 1406 // Check for float store 1407 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1408 int offset = ra_->reg2offset(dst_first); 1409 // Further check for aligned-adjacent pair, so we can use a double store 1410 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1411 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1412 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1413 } 1414 1415 // Check for float load 1416 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1417 int offset = ra_->reg2offset(src_first); 1418 // Further check for aligned-adjacent pair, so we can use a double load 1419 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1420 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1421 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1422 } 1423 1424 // -------------------------------------------------------------------- 1425 // Check for hi bits still needing moving. Only happens for misaligned 1426 // arguments to native calls. 1427 if( src_second == dst_second ) 1428 return size; // Self copy; no move 1429 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1430 1431#ifndef _LP64 1432 // In the LP64 build, all registers can be moved as aligned/adjacent 1433 // pairs, so there's never any need to move the high bits seperately. 1434 // The 32-bit builds have to deal with the 32-bit ABI which can force 1435 // all sorts of silly alignment problems. 1436 1437 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1438 // 32-bits of a 64-bit register, but are needed in low bits of another 1439 // register (else it's a hi-bits-to-hi-bits copy which should have 1440 // happened already as part of a 64-bit move) 1441 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1442 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1443 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1444 // Shift src_second down to dst_second's low bits. 1445 if( cbuf ) { 1446 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1447#ifndef PRODUCT 1448 } else if( !do_size ) { 1449 if( size != 0 ) st->print("\n\t"); 1450 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1451#endif 1452 } 1453 return size+4; 1454 } 1455 1456 // Check for high word integer store. Must down-shift the hi bits 1457 // into a temp register, then fall into the case of storing int bits. 1458 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1459 // Shift src_second down to dst_second's low bits. 1460 if( cbuf ) { 1461 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1462#ifndef PRODUCT 1463 } else if( !do_size ) { 1464 if( size != 0 ) st->print("\n\t"); 1465 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1466#endif 1467 } 1468 size+=4; 1469 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1470 } 1471 1472 // Check for high word integer load 1473 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1474 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1475 1476 // Check for high word integer store 1477 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1478 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1479 1480 // Check for high word float store 1481 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1482 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1483 1484#endif // !_LP64 1485 1486 Unimplemented(); 1487} 1488 1489#ifndef PRODUCT 1490void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1491 implementation( NULL, ra_, false, st ); 1492} 1493#endif 1494 1495void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1496 implementation( &cbuf, ra_, false, NULL ); 1497} 1498 1499uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1500 return implementation( NULL, ra_, true, NULL ); 1501} 1502 1503//============================================================================= 1504#ifndef PRODUCT 1505void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1506 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1507} 1508#endif 1509 1510void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1511 MacroAssembler _masm(&cbuf); 1512 for(int i = 0; i < _count; i += 1) { 1513 __ nop(); 1514 } 1515} 1516 1517uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1518 return 4 * _count; 1519} 1520 1521 1522//============================================================================= 1523#ifndef PRODUCT 1524void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1526 int reg = ra_->get_reg_first(this); 1527 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1528} 1529#endif 1530 1531void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1532 MacroAssembler _masm(&cbuf); 1533 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1534 int reg = ra_->get_encode(this); 1535 1536 if (Assembler::is_simm13(offset)) { 1537 __ add(SP, offset, reg_to_register_object(reg)); 1538 } else { 1539 __ set(offset, O7); 1540 __ add(SP, O7, reg_to_register_object(reg)); 1541 } 1542} 1543 1544uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1545 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1546 assert(ra_ == ra_->C->regalloc(), "sanity"); 1547 return ra_->C->scratch_emit_size(this); 1548} 1549 1550//============================================================================= 1551 1552// emit call stub, compiled java to interpretor 1553void emit_java_to_interp(CodeBuffer &cbuf ) { 1554 1555 // Stub is fixed up when the corresponding call is converted from calling 1556 // compiled code to calling interpreted code. 1557 // set (empty), G5 1558 // jmp -1 1559 1560 address mark = cbuf.inst_mark(); // get mark within main instrs section 1561 1562 MacroAssembler _masm(&cbuf); 1563 1564 address base = 1565 __ start_a_stub(Compile::MAX_stubs_size); 1566 if (base == NULL) return; // CodeBuffer::expand failed 1567 1568 // static stub relocation stores the instruction address of the call 1569 __ relocate(static_stub_Relocation::spec(mark)); 1570 1571 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1572 1573 __ set_inst_mark(); 1574 Address a(G3, (address)-1); 1575 __ JUMP(a, 0); 1576 1577 __ delayed()->nop(); 1578 1579 // Update current stubs pointer and restore code_end. 1580 __ end_a_stub(); 1581} 1582 1583// size of call stub, compiled java to interpretor 1584uint size_java_to_interp() { 1585 // This doesn't need to be accurate but it must be larger or equal to 1586 // the real size of the stub. 1587 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1588 NativeJump::instruction_size + // sethi; jmp; nop 1589 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1590} 1591// relocation entries for call stub, compiled java to interpretor 1592uint reloc_java_to_interp() { 1593 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1594} 1595 1596 1597//============================================================================= 1598#ifndef PRODUCT 1599void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1600 st->print_cr("\nUEP:"); 1601#ifdef _LP64 1602 if (UseCompressedOops) { 1603 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1604 st->print_cr("\tSLL R_G5,3,R_G5"); 1605 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1606 } else { 1607 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1608 } 1609 st->print_cr("\tCMP R_G5,R_G3" ); 1610 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1611#else // _LP64 1612 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1613 st->print_cr("\tCMP R_G5,R_G3" ); 1614 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1615#endif // _LP64 1616} 1617#endif 1618 1619void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1620 MacroAssembler _masm(&cbuf); 1621 Label L; 1622 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1623 Register temp_reg = G3; 1624 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1625 1626 // Load klass from reciever 1627 __ load_klass(O0, temp_reg); 1628 // Compare against expected klass 1629 __ cmp(temp_reg, G5_ic_reg); 1630 // Branch to miss code, checks xcc or icc depending 1631 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1632} 1633 1634uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1635 return MachNode::size(ra_); 1636} 1637 1638 1639//============================================================================= 1640 1641uint size_exception_handler() { 1642 if (TraceJumps) { 1643 return (400); // just a guess 1644 } 1645 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1646} 1647 1648uint size_deopt_handler() { 1649 if (TraceJumps) { 1650 return (400); // just a guess 1651 } 1652 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1653} 1654 1655// Emit exception handler code. 1656int emit_exception_handler(CodeBuffer& cbuf) { 1657 Register temp_reg = G3; 1658 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin()); 1659 MacroAssembler _masm(&cbuf); 1660 1661 address base = 1662 __ start_a_stub(size_exception_handler()); 1663 if (base == NULL) return 0; // CodeBuffer::expand failed 1664 1665 int offset = __ offset(); 1666 1667 __ JUMP(exception_blob, 0); // sethi;jmp 1668 __ delayed()->nop(); 1669 1670 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1671 1672 __ end_a_stub(); 1673 1674 return offset; 1675} 1676 1677int emit_deopt_handler(CodeBuffer& cbuf) { 1678 // Can't use any of the current frame's registers as we may have deopted 1679 // at a poll and everything (including G3) can be live. 1680 Register temp_reg = L0; 1681 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack()); 1682 MacroAssembler _masm(&cbuf); 1683 1684 address base = 1685 __ start_a_stub(size_deopt_handler()); 1686 if (base == NULL) return 0; // CodeBuffer::expand failed 1687 1688 int offset = __ offset(); 1689 __ save_frame(0); 1690 __ JUMP(deopt_blob, 0); // sethi;jmp 1691 __ delayed()->restore(); 1692 1693 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1694 1695 __ end_a_stub(); 1696 return offset; 1697 1698} 1699 1700// Given a register encoding, produce a Integer Register object 1701static Register reg_to_register_object(int register_encoding) { 1702 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1703 return as_Register(register_encoding); 1704} 1705 1706// Given a register encoding, produce a single-precision Float Register object 1707static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1708 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1709 return as_SingleFloatRegister(register_encoding); 1710} 1711 1712// Given a register encoding, produce a double-precision Float Register object 1713static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1714 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1715 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1716 return as_DoubleFloatRegister(register_encoding); 1717} 1718 1719int Matcher::regnum_to_fpu_offset(int regnum) { 1720 return regnum - 32; // The FP registers are in the second chunk 1721} 1722 1723#ifdef ASSERT 1724address last_rethrow = NULL; // debugging aid for Rethrow encoding 1725#endif 1726 1727// Vector width in bytes 1728const uint Matcher::vector_width_in_bytes(void) { 1729 return 8; 1730} 1731 1732// Vector ideal reg 1733const uint Matcher::vector_ideal_reg(void) { 1734 return Op_RegD; 1735} 1736 1737// USII supports fxtof through the whole range of number, USIII doesn't 1738const bool Matcher::convL2FSupported(void) { 1739 return VM_Version::has_fast_fxtof(); 1740} 1741 1742// Is this branch offset short enough that a short branch can be used? 1743// 1744// NOTE: If the platform does not provide any short branch variants, then 1745// this method should return false for offset 0. 1746bool Matcher::is_short_branch_offset(int offset) { 1747 return false; 1748} 1749 1750const bool Matcher::isSimpleConstant64(jlong value) { 1751 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1752 // Depends on optimizations in MacroAssembler::setx. 1753 int hi = (int)(value >> 32); 1754 int lo = (int)(value & ~0); 1755 return (hi == 0) || (hi == -1) || (lo == 0); 1756} 1757 1758// No scaling for the parameter the ClearArray node. 1759const bool Matcher::init_array_count_is_in_bytes = true; 1760 1761// Threshold size for cleararray. 1762const int Matcher::init_array_short_size = 8 * BytesPerLong; 1763 1764// Should the Matcher clone shifts on addressing modes, expecting them to 1765// be subsumed into complex addressing expressions or compute them into 1766// registers? True for Intel but false for most RISCs 1767const bool Matcher::clone_shift_expressions = false; 1768 1769// Is it better to copy float constants, or load them directly from memory? 1770// Intel can load a float constant from a direct address, requiring no 1771// extra registers. Most RISCs will have to materialize an address into a 1772// register first, so they would do better to copy the constant from stack. 1773const bool Matcher::rematerialize_float_constants = false; 1774 1775// If CPU can load and store mis-aligned doubles directly then no fixup is 1776// needed. Else we split the double into 2 integer pieces and move it 1777// piece-by-piece. Only happens when passing doubles into C code as the 1778// Java calling convention forces doubles to be aligned. 1779#ifdef _LP64 1780const bool Matcher::misaligned_doubles_ok = true; 1781#else 1782const bool Matcher::misaligned_doubles_ok = false; 1783#endif 1784 1785// No-op on SPARC. 1786void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1787} 1788 1789// Advertise here if the CPU requires explicit rounding operations 1790// to implement the UseStrictFP mode. 1791const bool Matcher::strict_fp_requires_explicit_rounding = false; 1792 1793// Do floats take an entire double register or just half? 1794const bool Matcher::float_in_double = false; 1795 1796// Do ints take an entire long register or just half? 1797// Note that we if-def off of _LP64. 1798// The relevant question is how the int is callee-saved. In _LP64 1799// the whole long is written but de-opt'ing will have to extract 1800// the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1801#ifdef _LP64 1802const bool Matcher::int_in_long = true; 1803#else 1804const bool Matcher::int_in_long = false; 1805#endif 1806 1807// Return whether or not this register is ever used as an argument. This 1808// function is used on startup to build the trampoline stubs in generateOptoStub. 1809// Registers not mentioned will be killed by the VM call in the trampoline, and 1810// arguments in those registers not be available to the callee. 1811bool Matcher::can_be_java_arg( int reg ) { 1812 // Standard sparc 6 args in registers 1813 if( reg == R_I0_num || 1814 reg == R_I1_num || 1815 reg == R_I2_num || 1816 reg == R_I3_num || 1817 reg == R_I4_num || 1818 reg == R_I5_num ) return true; 1819#ifdef _LP64 1820 // 64-bit builds can pass 64-bit pointers and longs in 1821 // the high I registers 1822 if( reg == R_I0H_num || 1823 reg == R_I1H_num || 1824 reg == R_I2H_num || 1825 reg == R_I3H_num || 1826 reg == R_I4H_num || 1827 reg == R_I5H_num ) return true; 1828 1829 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1830 return true; 1831 } 1832 1833#else 1834 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1835 // Longs cannot be passed in O regs, because O regs become I regs 1836 // after a 'save' and I regs get their high bits chopped off on 1837 // interrupt. 1838 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1839 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1840#endif 1841 // A few float args in registers 1842 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1843 1844 return false; 1845} 1846 1847bool Matcher::is_spillable_arg( int reg ) { 1848 return can_be_java_arg(reg); 1849} 1850 1851// Register for DIVI projection of divmodI 1852RegMask Matcher::divI_proj_mask() { 1853 ShouldNotReachHere(); 1854 return RegMask(); 1855} 1856 1857// Register for MODI projection of divmodI 1858RegMask Matcher::modI_proj_mask() { 1859 ShouldNotReachHere(); 1860 return RegMask(); 1861} 1862 1863// Register for DIVL projection of divmodL 1864RegMask Matcher::divL_proj_mask() { 1865 ShouldNotReachHere(); 1866 return RegMask(); 1867} 1868 1869// Register for MODL projection of divmodL 1870RegMask Matcher::modL_proj_mask() { 1871 ShouldNotReachHere(); 1872 return RegMask(); 1873} 1874 1875%} 1876 1877 1878// The intptr_t operand types, defined by textual substitution. 1879// (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1880#ifdef _LP64 1881#define immX immL 1882#define immX13 immL13 1883#define iRegX iRegL 1884#define g1RegX g1RegL 1885#else 1886#define immX immI 1887#define immX13 immI13 1888#define iRegX iRegI 1889#define g1RegX g1RegI 1890#endif 1891 1892//----------ENCODING BLOCK----------------------------------------------------- 1893// This block specifies the encoding classes used by the compiler to output 1894// byte streams. Encoding classes are parameterized macros used by 1895// Machine Instruction Nodes in order to generate the bit encoding of the 1896// instruction. Operands specify their base encoding interface with the 1897// interface keyword. There are currently supported four interfaces, 1898// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1899// operand to generate a function which returns its register number when 1900// queried. CONST_INTER causes an operand to generate a function which 1901// returns the value of the constant when queried. MEMORY_INTER causes an 1902// operand to generate four functions which return the Base Register, the 1903// Index Register, the Scale Value, and the Offset Value of the operand when 1904// queried. COND_INTER causes an operand to generate six functions which 1905// return the encoding code (ie - encoding bits for the instruction) 1906// associated with each basic boolean condition for a conditional instruction. 1907// 1908// Instructions specify two basic values for encoding. Again, a function 1909// is available to check if the constant displacement is an oop. They use the 1910// ins_encode keyword to specify their encoding classes (which must be 1911// a sequence of enc_class names, and their parameters, specified in 1912// the encoding block), and they use the 1913// opcode keyword to specify, in order, their primary, secondary, and 1914// tertiary opcode. Only the opcode sections which a particular instruction 1915// needs for encoding need to be specified. 1916encode %{ 1917 enc_class enc_untested %{ 1918#ifdef ASSERT 1919 MacroAssembler _masm(&cbuf); 1920 __ untested("encoding"); 1921#endif 1922 %} 1923 1924 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1925 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1926 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1927 %} 1928 1929 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ 1930 emit_form3_mem_reg_asi(cbuf, this, $primary, $tertiary, 1931 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); 1932 %} 1933 1934 enc_class form3_mem_prefetch_read( memory mem ) %{ 1935 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1936 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 1937 %} 1938 1939 enc_class form3_mem_prefetch_write( memory mem ) %{ 1940 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1941 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 1942 %} 1943 1944 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 1945 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1946 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1947 guarantee($mem$$index == R_G0_enc, "double index?"); 1948 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 1949 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 1950 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 1951 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 1952 %} 1953 1954 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 1955 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1956 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1957 guarantee($mem$$index == R_G0_enc, "double index?"); 1958 // Load long with 2 instructions 1959 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 1960 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 1961 %} 1962 1963 //%%% form3_mem_plus_4_reg is a hack--get rid of it 1964 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 1965 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 1966 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 1967 %} 1968 1969 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 1970 // Encode a reg-reg copy. If it is useless, then empty encoding. 1971 if( $rs2$$reg != $rd$$reg ) 1972 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 1973 %} 1974 1975 // Target lo half of long 1976 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 1977 // Encode a reg-reg copy. If it is useless, then empty encoding. 1978 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 1979 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 1980 %} 1981 1982 // Source lo half of long 1983 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 1984 // Encode a reg-reg copy. If it is useless, then empty encoding. 1985 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 1986 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 1987 %} 1988 1989 // Target hi half of long 1990 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 1991 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 1992 %} 1993 1994 // Source lo half of long, and leave it sign extended. 1995 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 1996 // Sign extend low half 1997 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 1998 %} 1999 2000 // Source hi half of long, and leave it sign extended. 2001 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2002 // Shift high half to low half 2003 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2004 %} 2005 2006 // Source hi half of long 2007 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2008 // Encode a reg-reg copy. If it is useless, then empty encoding. 2009 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2010 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2011 %} 2012 2013 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2014 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2015 %} 2016 2017 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2018 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2019 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2020 %} 2021 2022 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2023 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2024 // clear if nothing else is happening 2025 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2026 // blt,a,pn done 2027 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2028 // mov dst,-1 in delay slot 2029 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2030 %} 2031 2032 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2033 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2034 %} 2035 2036 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2037 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2038 %} 2039 2040 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2041 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2042 %} 2043 2044 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2045 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2046 %} 2047 2048 enc_class move_return_pc_to_o1() %{ 2049 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2050 %} 2051 2052#ifdef _LP64 2053 /* %%% merge with enc_to_bool */ 2054 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2055 MacroAssembler _masm(&cbuf); 2056 2057 Register src_reg = reg_to_register_object($src$$reg); 2058 Register dst_reg = reg_to_register_object($dst$$reg); 2059 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2060 %} 2061#endif 2062 2063 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2064 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2065 MacroAssembler _masm(&cbuf); 2066 2067 Register p_reg = reg_to_register_object($p$$reg); 2068 Register q_reg = reg_to_register_object($q$$reg); 2069 Register y_reg = reg_to_register_object($y$$reg); 2070 Register tmp_reg = reg_to_register_object($tmp$$reg); 2071 2072 __ subcc( p_reg, q_reg, p_reg ); 2073 __ add ( p_reg, y_reg, tmp_reg ); 2074 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2075 %} 2076 2077 enc_class form_d2i_helper(regD src, regF dst) %{ 2078 // fcmp %fcc0,$src,$src 2079 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2080 // branch %fcc0 not-nan, predict taken 2081 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2082 // fdtoi $src,$dst 2083 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2084 // fitos $dst,$dst (if nan) 2085 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2086 // clear $dst (if nan) 2087 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2088 // carry on here... 2089 %} 2090 2091 enc_class form_d2l_helper(regD src, regD dst) %{ 2092 // fcmp %fcc0,$src,$src check for NAN 2093 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2094 // branch %fcc0 not-nan, predict taken 2095 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2096 // fdtox $src,$dst convert in delay slot 2097 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2098 // fxtod $dst,$dst (if nan) 2099 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2100 // clear $dst (if nan) 2101 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2102 // carry on here... 2103 %} 2104 2105 enc_class form_f2i_helper(regF src, regF dst) %{ 2106 // fcmps %fcc0,$src,$src 2107 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2108 // branch %fcc0 not-nan, predict taken 2109 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2110 // fstoi $src,$dst 2111 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2112 // fitos $dst,$dst (if nan) 2113 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2114 // clear $dst (if nan) 2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2116 // carry on here... 2117 %} 2118 2119 enc_class form_f2l_helper(regF src, regD dst) %{ 2120 // fcmps %fcc0,$src,$src 2121 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2122 // branch %fcc0 not-nan, predict taken 2123 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2124 // fstox $src,$dst 2125 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2126 // fxtod $dst,$dst (if nan) 2127 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2128 // clear $dst (if nan) 2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2130 // carry on here... 2131 %} 2132 2133 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2134 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2135 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2136 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2137 2138 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2139 2140 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2141 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2142 2143 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2144 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2145 %} 2146 2147 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2148 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2149 %} 2150 2151 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2152 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2153 %} 2154 2155 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2156 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2157 %} 2158 2159 enc_class form3_convI2F(regF rs2, regF rd) %{ 2160 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2161 %} 2162 2163 // Encloding class for traceable jumps 2164 enc_class form_jmpl(g3RegP dest) %{ 2165 emit_jmpl(cbuf, $dest$$reg); 2166 %} 2167 2168 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2169 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2170 %} 2171 2172 enc_class form2_nop() %{ 2173 emit_nop(cbuf); 2174 %} 2175 2176 enc_class form2_illtrap() %{ 2177 emit_illtrap(cbuf); 2178 %} 2179 2180 2181 // Compare longs and convert into -1, 0, 1. 2182 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2183 // CMP $src1,$src2 2184 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2185 // blt,a,pn done 2186 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2187 // mov dst,-1 in delay slot 2188 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2189 // bgt,a,pn done 2190 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2191 // mov dst,1 in delay slot 2192 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2193 // CLR $dst 2194 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2195 %} 2196 2197 enc_class enc_PartialSubtypeCheck() %{ 2198 MacroAssembler _masm(&cbuf); 2199 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2200 __ delayed()->nop(); 2201 %} 2202 2203 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ 2204 MacroAssembler _masm(&cbuf); 2205 Label &L = *($labl$$label); 2206 Assembler::Predict predict_taken = 2207 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2208 2209 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); 2210 __ delayed()->nop(); 2211 %} 2212 2213 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ 2214 MacroAssembler _masm(&cbuf); 2215 Label &L = *($labl$$label); 2216 Assembler::Predict predict_taken = 2217 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2218 2219 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); 2220 __ delayed()->nop(); 2221 %} 2222 2223 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ 2224 MacroAssembler _masm(&cbuf); 2225 Label &L = *($labl$$label); 2226 Assembler::Predict predict_taken = 2227 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2228 2229 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); 2230 __ delayed()->nop(); 2231 %} 2232 2233 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ 2234 MacroAssembler _masm(&cbuf); 2235 Label &L = *($labl$$label); 2236 Assembler::Predict predict_taken = 2237 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2238 2239 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); 2240 __ delayed()->nop(); 2241 %} 2242 2243 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ 2244 MacroAssembler _masm(&cbuf); 2245 2246 Register switch_reg = as_Register($switch_val$$reg); 2247 Register table_reg = O7; 2248 2249 address table_base = __ address_table_constant(_index2label); 2250 RelocationHolder rspec = internal_word_Relocation::spec(table_base); 2251 2252 // Load table address 2253 Address the_pc(table_reg, table_base, rspec); 2254 __ load_address(the_pc); 2255 2256 // Jump to base address + switch value 2257 __ ld_ptr(table_reg, switch_reg, table_reg); 2258 __ jmp(table_reg, G0); 2259 __ delayed()->nop(); 2260 2261 %} 2262 2263 enc_class enc_ba( Label labl ) %{ 2264 MacroAssembler _masm(&cbuf); 2265 Label &L = *($labl$$label); 2266 __ ba(false, L); 2267 __ delayed()->nop(); 2268 %} 2269 2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2271 MacroAssembler _masm(&cbuf); 2272 Label &L = *$labl$$label; 2273 Assembler::Predict predict_taken = 2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2275 2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); 2277 __ delayed()->nop(); 2278 %} 2279 2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2281 int op = (Assembler::arith_op << 30) | 2282 ($dst$$reg << 25) | 2283 (Assembler::movcc_op3 << 19) | 2284 (1 << 18) | // cc2 bit for 'icc' 2285 ($cmp$$cmpcode << 14) | 2286 (0 << 13) | // select register move 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2288 ($src$$reg << 0); 2289 *((int*)(cbuf.code_end())) = op; 2290 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2291 %} 2292 2293 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2294 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2295 int op = (Assembler::arith_op << 30) | 2296 ($dst$$reg << 25) | 2297 (Assembler::movcc_op3 << 19) | 2298 (1 << 18) | // cc2 bit for 'icc' 2299 ($cmp$$cmpcode << 14) | 2300 (1 << 13) | // select immediate move 2301 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2302 (simm11 << 0); 2303 *((int*)(cbuf.code_end())) = op; 2304 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2305 %} 2306 2307 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2308 int op = (Assembler::arith_op << 30) | 2309 ($dst$$reg << 25) | 2310 (Assembler::movcc_op3 << 19) | 2311 (0 << 18) | // cc2 bit for 'fccX' 2312 ($cmp$$cmpcode << 14) | 2313 (0 << 13) | // select register move 2314 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2315 ($src$$reg << 0); 2316 *((int*)(cbuf.code_end())) = op; 2317 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2318 %} 2319 2320 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2321 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2322 int op = (Assembler::arith_op << 30) | 2323 ($dst$$reg << 25) | 2324 (Assembler::movcc_op3 << 19) | 2325 (0 << 18) | // cc2 bit for 'fccX' 2326 ($cmp$$cmpcode << 14) | 2327 (1 << 13) | // select immediate move 2328 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2329 (simm11 << 0); 2330 *((int*)(cbuf.code_end())) = op; 2331 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2332 %} 2333 2334 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2335 int op = (Assembler::arith_op << 30) | 2336 ($dst$$reg << 25) | 2337 (Assembler::fpop2_op3 << 19) | 2338 (0 << 18) | 2339 ($cmp$$cmpcode << 14) | 2340 (1 << 13) | // select register move 2341 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2342 ($primary << 5) | // select single, double or quad 2343 ($src$$reg << 0); 2344 *((int*)(cbuf.code_end())) = op; 2345 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2346 %} 2347 2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2349 int op = (Assembler::arith_op << 30) | 2350 ($dst$$reg << 25) | 2351 (Assembler::fpop2_op3 << 19) | 2352 (0 << 18) | 2353 ($cmp$$cmpcode << 14) | 2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2355 ($primary << 5) | // select single, double or quad 2356 ($src$$reg << 0); 2357 *((int*)(cbuf.code_end())) = op; 2358 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2359 %} 2360 2361 // Used by the MIN/MAX encodings. Same as a CMOV, but 2362 // the condition comes from opcode-field instead of an argument. 2363 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2364 int op = (Assembler::arith_op << 30) | 2365 ($dst$$reg << 25) | 2366 (Assembler::movcc_op3 << 19) | 2367 (1 << 18) | // cc2 bit for 'icc' 2368 ($primary << 14) | 2369 (0 << 13) | // select register move 2370 (0 << 11) | // cc1, cc0 bits for 'icc' 2371 ($src$$reg << 0); 2372 *((int*)(cbuf.code_end())) = op; 2373 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2374 %} 2375 2376 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2377 int op = (Assembler::arith_op << 30) | 2378 ($dst$$reg << 25) | 2379 (Assembler::movcc_op3 << 19) | 2380 (6 << 16) | // cc2 bit for 'xcc' 2381 ($primary << 14) | 2382 (0 << 13) | // select register move 2383 (0 << 11) | // cc1, cc0 bits for 'icc' 2384 ($src$$reg << 0); 2385 *((int*)(cbuf.code_end())) = op; 2386 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 2387 %} 2388 2389 // Utility encoding for loading a 64 bit Pointer into a register 2390 // The 64 bit pointer is stored in the generated code stream 2391 enc_class SetPtr( immP src, iRegP rd ) %{ 2392 Register dest = reg_to_register_object($rd$$reg); 2393 // [RGV] This next line should be generated from ADLC 2394 if ( _opnds[1]->constant_is_oop() ) { 2395 intptr_t val = $src$$constant; 2396 MacroAssembler _masm(&cbuf); 2397 __ set_oop_constant((jobject)val, dest); 2398 } else { // non-oop pointers, e.g. card mark base, heap top 2399 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false); 2400 } 2401 %} 2402 2403 enc_class Set13( immI13 src, iRegI rd ) %{ 2404 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2405 %} 2406 2407 enc_class SetHi22( immI src, iRegI rd ) %{ 2408 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2409 %} 2410 2411 enc_class Set32( immI src, iRegI rd ) %{ 2412 MacroAssembler _masm(&cbuf); 2413 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2414 %} 2415 2416 enc_class SetNull( iRegI rd ) %{ 2417 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); 2418 %} 2419 2420 enc_class call_epilog %{ 2421 if( VerifyStackAtCalls ) { 2422 MacroAssembler _masm(&cbuf); 2423 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2424 Register temp_reg = G3; 2425 __ add(SP, framesize, temp_reg); 2426 __ cmp(temp_reg, FP); 2427 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2428 } 2429 %} 2430 2431 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2432 // to G1 so the register allocator will not have to deal with the misaligned register 2433 // pair. 2434 enc_class adjust_long_from_native_call %{ 2435#ifndef _LP64 2436 if (returns_long()) { 2437 // sllx O0,32,O0 2438 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2439 // srl O1,0,O1 2440 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2441 // or O0,O1,G1 2442 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2443 } 2444#endif 2445 %} 2446 2447 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2448 // CALL directly to the runtime 2449 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2450 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2451 /*preserve_g2=*/true, /*force far call*/true); 2452 %} 2453 2454 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2455 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2456 // who we intended to call. 2457 if ( !_method ) { 2458 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2459 } else if (_optimized_virtual) { 2460 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2461 } else { 2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2463 } 2464 if( _method ) { // Emit stub for static call 2465 emit_java_to_interp(cbuf); 2466 } 2467 %} 2468 2469 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2470 MacroAssembler _masm(&cbuf); 2471 __ set_inst_mark(); 2472 int vtable_index = this->_vtable_index; 2473 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2474 if (vtable_index < 0) { 2475 // must be invalid_vtable_index, not nonvirtual_vtable_index 2476 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2477 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2478 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2479 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2480 // !!!!! 2481 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2482 // emit_call_dynamic_prologue( cbuf ); 2483 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2484 2485 address virtual_call_oop_addr = __ inst_mark(); 2486 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2487 // who we intended to call. 2488 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2489 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2490 } else { 2491 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2492 // Just go thru the vtable 2493 // get receiver klass (receiver already checked for non-null) 2494 // If we end up going thru a c2i adapter interpreter expects method in G5 2495 int off = __ offset(); 2496 __ load_klass(O0, G3_scratch); 2497 int klass_load_size; 2498 if (UseCompressedOops) { 2499 klass_load_size = 3*BytesPerInstWord; 2500 } else { 2501 klass_load_size = 1*BytesPerInstWord; 2502 } 2503 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2504 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2505 if( __ is_simm13(v_off) ) { 2506 __ ld_ptr(G3, v_off, G5_method); 2507 } else { 2508 // Generate 2 instructions 2509 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2510 __ or3(G5_method, v_off & 0x3ff, G5_method); 2511 // ld_ptr, set_hi, set 2512 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2513 "Unexpected instruction size(s)"); 2514 __ ld_ptr(G3, G5_method, G5_method); 2515 } 2516 // NOTE: for vtable dispatches, the vtable entry will never be null. 2517 // However it may very well end up in handle_wrong_method if the 2518 // method is abstract for the particular class. 2519 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2520 // jump to target (either compiled code or c2iadapter) 2521 __ jmpl(G3_scratch, G0, O7); 2522 __ delayed()->nop(); 2523 } 2524 %} 2525 2526 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2527 MacroAssembler _masm(&cbuf); 2528 2529 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2530 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2531 // we might be calling a C2I adapter which needs it. 2532 2533 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2534 // Load nmethod 2535 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2536 2537 // CALL to compiled java, indirect the contents of G3 2538 __ set_inst_mark(); 2539 __ callr(temp_reg, G0); 2540 __ delayed()->nop(); 2541 %} 2542 2543enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2544 MacroAssembler _masm(&cbuf); 2545 Register Rdividend = reg_to_register_object($src1$$reg); 2546 Register Rdivisor = reg_to_register_object($src2$$reg); 2547 Register Rresult = reg_to_register_object($dst$$reg); 2548 2549 __ sra(Rdivisor, 0, Rdivisor); 2550 __ sra(Rdividend, 0, Rdividend); 2551 __ sdivx(Rdividend, Rdivisor, Rresult); 2552%} 2553 2554enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2555 MacroAssembler _masm(&cbuf); 2556 2557 Register Rdividend = reg_to_register_object($src1$$reg); 2558 int divisor = $imm$$constant; 2559 Register Rresult = reg_to_register_object($dst$$reg); 2560 2561 __ sra(Rdividend, 0, Rdividend); 2562 __ sdivx(Rdividend, divisor, Rresult); 2563%} 2564 2565enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2566 MacroAssembler _masm(&cbuf); 2567 Register Rsrc1 = reg_to_register_object($src1$$reg); 2568 Register Rsrc2 = reg_to_register_object($src2$$reg); 2569 Register Rdst = reg_to_register_object($dst$$reg); 2570 2571 __ sra( Rsrc1, 0, Rsrc1 ); 2572 __ sra( Rsrc2, 0, Rsrc2 ); 2573 __ mulx( Rsrc1, Rsrc2, Rdst ); 2574 __ srlx( Rdst, 32, Rdst ); 2575%} 2576 2577enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2578 MacroAssembler _masm(&cbuf); 2579 Register Rdividend = reg_to_register_object($src1$$reg); 2580 Register Rdivisor = reg_to_register_object($src2$$reg); 2581 Register Rresult = reg_to_register_object($dst$$reg); 2582 Register Rscratch = reg_to_register_object($scratch$$reg); 2583 2584 assert(Rdividend != Rscratch, ""); 2585 assert(Rdivisor != Rscratch, ""); 2586 2587 __ sra(Rdividend, 0, Rdividend); 2588 __ sra(Rdivisor, 0, Rdivisor); 2589 __ sdivx(Rdividend, Rdivisor, Rscratch); 2590 __ mulx(Rscratch, Rdivisor, Rscratch); 2591 __ sub(Rdividend, Rscratch, Rresult); 2592%} 2593 2594enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2595 MacroAssembler _masm(&cbuf); 2596 2597 Register Rdividend = reg_to_register_object($src1$$reg); 2598 int divisor = $imm$$constant; 2599 Register Rresult = reg_to_register_object($dst$$reg); 2600 Register Rscratch = reg_to_register_object($scratch$$reg); 2601 2602 assert(Rdividend != Rscratch, ""); 2603 2604 __ sra(Rdividend, 0, Rdividend); 2605 __ sdivx(Rdividend, divisor, Rscratch); 2606 __ mulx(Rscratch, divisor, Rscratch); 2607 __ sub(Rdividend, Rscratch, Rresult); 2608%} 2609 2610enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2611 MacroAssembler _masm(&cbuf); 2612 2613 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2614 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2615 2616 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2617%} 2618 2619enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2620 MacroAssembler _masm(&cbuf); 2621 2622 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2623 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2624 2625 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2626%} 2627 2628enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2629 MacroAssembler _masm(&cbuf); 2630 2631 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2632 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2633 2634 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2635%} 2636 2637enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2638 MacroAssembler _masm(&cbuf); 2639 2640 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2641 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2642 2643 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2644%} 2645 2646enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2647 MacroAssembler _masm(&cbuf); 2648 2649 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2650 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2651 2652 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2653%} 2654 2655enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2656 MacroAssembler _masm(&cbuf); 2657 2658 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2659 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2660 2661 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2662%} 2663 2664enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2665 MacroAssembler _masm(&cbuf); 2666 2667 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2668 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2669 2670 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2671%} 2672 2673enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2674 MacroAssembler _masm(&cbuf); 2675 2676 Register Roop = reg_to_register_object($oop$$reg); 2677 Register Rbox = reg_to_register_object($box$$reg); 2678 Register Rscratch = reg_to_register_object($scratch$$reg); 2679 Register Rmark = reg_to_register_object($scratch2$$reg); 2680 2681 assert(Roop != Rscratch, ""); 2682 assert(Roop != Rmark, ""); 2683 assert(Rbox != Rscratch, ""); 2684 assert(Rbox != Rmark, ""); 2685 2686 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters); 2687%} 2688 2689enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2690 MacroAssembler _masm(&cbuf); 2691 2692 Register Roop = reg_to_register_object($oop$$reg); 2693 Register Rbox = reg_to_register_object($box$$reg); 2694 Register Rscratch = reg_to_register_object($scratch$$reg); 2695 Register Rmark = reg_to_register_object($scratch2$$reg); 2696 2697 assert(Roop != Rscratch, ""); 2698 assert(Roop != Rmark, ""); 2699 assert(Rbox != Rscratch, ""); 2700 assert(Rbox != Rmark, ""); 2701 2702 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch); 2703 %} 2704 2705 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2706 MacroAssembler _masm(&cbuf); 2707 Register Rmem = reg_to_register_object($mem$$reg); 2708 Register Rold = reg_to_register_object($old$$reg); 2709 Register Rnew = reg_to_register_object($new$$reg); 2710 2711 // casx_under_lock picks 1 of 3 encodings: 2712 // For 32-bit pointers you get a 32-bit CAS 2713 // For 64-bit pointers you get a 64-bit CASX 2714 __ casx_under_lock(Rmem, Rold, Rnew, // Swap(*Rmem,Rnew) if *Rmem == Rold 2715 (address) StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2716 __ cmp( Rold, Rnew ); 2717 %} 2718 2719 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2720 Register Rmem = reg_to_register_object($mem$$reg); 2721 Register Rold = reg_to_register_object($old$$reg); 2722 Register Rnew = reg_to_register_object($new$$reg); 2723 2724 MacroAssembler _masm(&cbuf); 2725 __ mov(Rnew, O7); 2726 __ casx(Rmem, Rold, O7); 2727 __ cmp( Rold, O7 ); 2728 %} 2729 2730 // raw int cas, used for compareAndSwap 2731 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2732 Register Rmem = reg_to_register_object($mem$$reg); 2733 Register Rold = reg_to_register_object($old$$reg); 2734 Register Rnew = reg_to_register_object($new$$reg); 2735 2736 MacroAssembler _masm(&cbuf); 2737 __ mov(Rnew, O7); 2738 __ cas(Rmem, Rold, O7); 2739 __ cmp( Rold, O7 ); 2740 %} 2741 2742 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2743 Register Rres = reg_to_register_object($res$$reg); 2744 2745 MacroAssembler _masm(&cbuf); 2746 __ mov(1, Rres); 2747 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2748 %} 2749 2750 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2751 Register Rres = reg_to_register_object($res$$reg); 2752 2753 MacroAssembler _masm(&cbuf); 2754 __ mov(1, Rres); 2755 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2756 %} 2757 2758 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2759 MacroAssembler _masm(&cbuf); 2760 Register Rdst = reg_to_register_object($dst$$reg); 2761 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2762 : reg_to_DoubleFloatRegister_object($src1$$reg); 2763 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2764 : reg_to_DoubleFloatRegister_object($src2$$reg); 2765 2766 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2767 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2768 %} 2769 2770 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate 2771 MacroAssembler _masm(&cbuf); 2772 Register dest = reg_to_register_object($dst$$reg); 2773 Register temp = reg_to_register_object($tmp$$reg); 2774 __ set64( $src$$constant, dest, temp ); 2775 %} 2776 2777 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate 2778 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant); 2779 RelocationHolder rspec = internal_word_Relocation::spec(float_address); 2780#ifdef _LP64 2781 Register tmp_reg = reg_to_register_object($tmp$$reg); 2782 cbuf.relocate(cbuf.code_end(), rspec, 0); 2783 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true); 2784 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 ); 2785#else // _LP64 2786 uint *code; 2787 int tmp_reg = $tmp$$reg; 2788 2789 cbuf.relocate(cbuf.code_end(), rspec, 0); 2790 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address ); 2791 2792 cbuf.relocate(cbuf.code_end(), rspec, 0); 2793 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address ); 2794#endif // _LP64 2795 %} 2796 2797 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate 2798 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant); 2799 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2800#ifdef _LP64 2801 Register tmp_reg = reg_to_register_object($tmp$$reg); 2802 cbuf.relocate(cbuf.code_end(), rspec, 0); 2803 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); 2804 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 ); 2805#else // _LP64 2806 uint *code; 2807 int tmp_reg = $tmp$$reg; 2808 2809 cbuf.relocate(cbuf.code_end(), rspec, 0); 2810 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address ); 2811 2812 cbuf.relocate(cbuf.code_end(), rspec, 0); 2813 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address ); 2814#endif // _LP64 2815 %} 2816 2817 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ 2818 // Load a constant replicated "count" times with width "width" 2819 int bit_width = $width$$constant * 8; 2820 jlong elt_val = $src$$constant; 2821 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits 2822 jlong val = elt_val; 2823 for (int i = 0; i < $count$$constant - 1; i++) { 2824 val <<= bit_width; 2825 val |= elt_val; 2826 } 2827 jdouble dval = *(jdouble*)&val; // coerce to double type 2828 address double_address = MacroAssembler(&cbuf).double_constant(dval); 2829 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2830#ifdef _LP64 2831 Register tmp_reg = reg_to_register_object($tmp$$reg); 2832 cbuf.relocate(cbuf.code_end(), rspec, 0); 2833 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); 2834 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 ); 2835#else // _LP64 2836 uint *code; 2837 int tmp_reg = $tmp$$reg; 2838 2839 cbuf.relocate(cbuf.code_end(), rspec, 0); 2840 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address ); 2841 2842 cbuf.relocate(cbuf.code_end(), rspec, 0); 2843 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address ); 2844#endif // _LP64 2845 %} 2846 2847 2848 enc_class ShouldNotEncodeThis ( ) %{ 2849 ShouldNotCallThis(); 2850 %} 2851 2852 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2853 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2854 MacroAssembler _masm(&cbuf); 2855 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2856 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2857 Register base_pointer_arg = reg_to_register_object($base$$reg); 2858 2859 Label loop; 2860 __ mov(nof_bytes_arg, nof_bytes_tmp); 2861 2862 // Loop and clear, walking backwards through the array. 2863 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2864 __ bind(loop); 2865 __ deccc(nof_bytes_tmp, 8); 2866 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2867 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2868 // %%%% this mini-loop must not cross a cache boundary! 2869 %} 2870 2871 2872 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ 2873 Label Ldone, Lloop; 2874 MacroAssembler _masm(&cbuf); 2875 2876 Register str1_reg = reg_to_register_object($str1$$reg); 2877 Register str2_reg = reg_to_register_object($str2$$reg); 2878 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2879 Register tmp2_reg = reg_to_register_object($tmp2$$reg); 2880 Register result_reg = reg_to_register_object($result$$reg); 2881 2882 // Get the first character position in both strings 2883 // [8] char array, [12] offset, [16] count 2884 int value_offset = java_lang_String:: value_offset_in_bytes(); 2885 int offset_offset = java_lang_String::offset_offset_in_bytes(); 2886 int count_offset = java_lang_String:: count_offset_in_bytes(); 2887 2888 // load str1 (jchar*) base address into tmp1_reg 2889 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg); 2890 __ ld(Address(str1_reg, 0, offset_offset), result_reg); 2891 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); 2892 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted 2893 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2894 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted 2895 __ add(result_reg, tmp1_reg, tmp1_reg); 2896 2897 // load str2 (jchar*) base address into tmp2_reg 2898 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted 2899 __ ld(Address(str2_reg, 0, offset_offset), result_reg); 2900 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); 2901 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted 2902 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); 2903 __ subcc(str1_reg, str2_reg, O7); // hoisted 2904 __ add(result_reg, tmp2_reg, tmp2_reg); 2905 2906 // Compute the minimum of the string lengths(str1_reg) and the 2907 // difference of the string lengths (stack) 2908 2909 // discard string base pointers, after loading up the lengths 2910 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted 2911 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted 2912 2913 // See if the lengths are different, and calculate min in str1_reg. 2914 // Stash diff in O7 in case we need it for a tie-breaker. 2915 Label Lskip; 2916 // __ subcc(str1_reg, str2_reg, O7); // hoisted 2917 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit 2918 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2919 // str2 is shorter, so use its count: 2920 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit 2921 __ bind(Lskip); 2922 2923 // reallocate str1_reg, str2_reg, result_reg 2924 // Note: limit_reg holds the string length pre-scaled by 2 2925 Register limit_reg = str1_reg; 2926 Register chr2_reg = str2_reg; 2927 Register chr1_reg = result_reg; 2928 // tmp{12} are the base pointers 2929 2930 // Is the minimum length zero? 2931 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2932 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2933 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2934 2935 // Load first characters 2936 __ lduh(tmp1_reg, 0, chr1_reg); 2937 __ lduh(tmp2_reg, 0, chr2_reg); 2938 2939 // Compare first characters 2940 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2941 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2942 assert(chr1_reg == result_reg, "result must be pre-placed"); 2943 __ delayed()->nop(); 2944 2945 { 2946 // Check after comparing first character to see if strings are equivalent 2947 Label LSkip2; 2948 // Check if the strings start at same location 2949 __ cmp(tmp1_reg, tmp2_reg); 2950 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2951 __ delayed()->nop(); 2952 2953 // Check if the length difference is zero (in O7) 2954 __ cmp(G0, O7); 2955 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2956 __ delayed()->mov(G0, result_reg); // result is zero 2957 2958 // Strings might not be equal 2959 __ bind(LSkip2); 2960 } 2961 2962 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2963 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2964 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2965 2966 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit 2967 __ add(tmp1_reg, limit_reg, tmp1_reg); 2968 __ add(tmp2_reg, limit_reg, tmp2_reg); 2969 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2970 2971 // Compare the rest of the characters 2972 __ lduh(tmp1_reg, limit_reg, chr1_reg); 2973 __ bind(Lloop); 2974 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 2975 __ lduh(tmp2_reg, limit_reg, chr2_reg); 2976 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2977 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2978 assert(chr1_reg == result_reg, "result must be pre-placed"); 2979 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2980 // annul LDUH if branch is not taken to prevent access past end of string 2981 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2982 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted 2983 2984 // If strings are equal up to min length, return the length difference. 2985 __ mov(O7, result_reg); 2986 2987 // Otherwise, return the difference between the first mismatched chars. 2988 __ bind(Ldone); 2989 %} 2990 2991 enc_class enc_rethrow() %{ 2992 cbuf.set_inst_mark(); 2993 Register temp_reg = G3; 2994 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub()); 2995 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 2996 MacroAssembler _masm(&cbuf); 2997#ifdef ASSERT 2998 __ save_frame(0); 2999 Address last_rethrow_addr(L1, (address)&last_rethrow); 3000 __ sethi(last_rethrow_addr); 3001 __ get_pc(L2); 3002 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3003 __ st_ptr(L2, last_rethrow_addr); 3004 __ restore(); 3005#endif 3006 __ JUMP(rethrow_stub, 0); // sethi;jmp 3007 __ delayed()->nop(); 3008 %} 3009 3010 enc_class emit_mem_nop() %{ 3011 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3012 unsigned int *code = (unsigned int*)cbuf.code_end(); 3013 *code = (unsigned int)0xc0839040; 3014 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3015 %} 3016 3017 enc_class emit_fadd_nop() %{ 3018 // Generates the instruction FMOVS f31,f31 3019 unsigned int *code = (unsigned int*)cbuf.code_end(); 3020 *code = (unsigned int)0xbfa0003f; 3021 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3022 %} 3023 3024 enc_class emit_br_nop() %{ 3025 // Generates the instruction BPN,PN . 3026 unsigned int *code = (unsigned int*)cbuf.code_end(); 3027 *code = (unsigned int)0x00400000; 3028 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); 3029 %} 3030 3031 enc_class enc_membar_acquire %{ 3032 MacroAssembler _masm(&cbuf); 3033 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3034 %} 3035 3036 enc_class enc_membar_release %{ 3037 MacroAssembler _masm(&cbuf); 3038 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3039 %} 3040 3041 enc_class enc_membar_volatile %{ 3042 MacroAssembler _masm(&cbuf); 3043 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3044 %} 3045 3046 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3047 MacroAssembler _masm(&cbuf); 3048 Register src_reg = reg_to_register_object($src$$reg); 3049 Register dst_reg = reg_to_register_object($dst$$reg); 3050 __ sllx(src_reg, 56, dst_reg); 3051 __ srlx(dst_reg, 8, O7); 3052 __ or3 (dst_reg, O7, dst_reg); 3053 __ srlx(dst_reg, 16, O7); 3054 __ or3 (dst_reg, O7, dst_reg); 3055 __ srlx(dst_reg, 32, O7); 3056 __ or3 (dst_reg, O7, dst_reg); 3057 %} 3058 3059 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3060 MacroAssembler _masm(&cbuf); 3061 Register src_reg = reg_to_register_object($src$$reg); 3062 Register dst_reg = reg_to_register_object($dst$$reg); 3063 __ sll(src_reg, 24, dst_reg); 3064 __ srl(dst_reg, 8, O7); 3065 __ or3(dst_reg, O7, dst_reg); 3066 __ srl(dst_reg, 16, O7); 3067 __ or3(dst_reg, O7, dst_reg); 3068 %} 3069 3070 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3071 MacroAssembler _masm(&cbuf); 3072 Register src_reg = reg_to_register_object($src$$reg); 3073 Register dst_reg = reg_to_register_object($dst$$reg); 3074 __ sllx(src_reg, 48, dst_reg); 3075 __ srlx(dst_reg, 16, O7); 3076 __ or3 (dst_reg, O7, dst_reg); 3077 __ srlx(dst_reg, 32, O7); 3078 __ or3 (dst_reg, O7, dst_reg); 3079 %} 3080 3081 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3082 MacroAssembler _masm(&cbuf); 3083 Register src_reg = reg_to_register_object($src$$reg); 3084 Register dst_reg = reg_to_register_object($dst$$reg); 3085 __ sllx(src_reg, 32, dst_reg); 3086 __ srlx(dst_reg, 32, O7); 3087 __ or3 (dst_reg, O7, dst_reg); 3088 %} 3089 3090%} 3091 3092//----------FRAME-------------------------------------------------------------- 3093// Definition of frame structure and management information. 3094// 3095// S T A C K L A Y O U T Allocators stack-slot number 3096// | (to get allocators register number 3097// G Owned by | | v add VMRegImpl::stack0) 3098// r CALLER | | 3099// o | +--------+ pad to even-align allocators stack-slot 3100// w V | pad0 | numbers; owned by CALLER 3101// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3102// h ^ | in | 5 3103// | | args | 4 Holes in incoming args owned by SELF 3104// | | | | 3 3105// | | +--------+ 3106// V | | old out| Empty on Intel, window on Sparc 3107// | old |preserve| Must be even aligned. 3108// | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3109// | | in | 3 area for Intel ret address 3110// Owned by |preserve| Empty on Sparc. 3111// SELF +--------+ 3112// | | pad2 | 2 pad to align old SP 3113// | +--------+ 1 3114// | | locks | 0 3115// | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3116// | | pad1 | 11 pad to align new SP 3117// | +--------+ 3118// | | | 10 3119// | | spills | 9 spills 3120// V | | 8 (pad0 slot for callee) 3121// -----------+--------+----> Matcher::_out_arg_limit, unaligned 3122// ^ | out | 7 3123// | | args | 6 Holes in outgoing args owned by CALLEE 3124// Owned by +--------+ 3125// CALLEE | new out| 6 Empty on Intel, window on Sparc 3126// | new |preserve| Must be even-aligned. 3127// | SP-+--------+----> Matcher::_new_SP, even aligned 3128// | | | 3129// 3130// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3131// known from SELF's arguments and the Java calling convention. 3132// Region 6-7 is determined per call site. 3133// Note 2: If the calling convention leaves holes in the incoming argument 3134// area, those holes are owned by SELF. Holes in the outgoing area 3135// are owned by the CALLEE. Holes should not be nessecary in the 3136// incoming area, as the Java calling convention is completely under 3137// the control of the AD file. Doubles can be sorted and packed to 3138// avoid holes. Holes in the outgoing arguments may be nessecary for 3139// varargs C calling conventions. 3140// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3141// even aligned with pad0 as needed. 3142// Region 6 is even aligned. Region 6-7 is NOT even aligned; 3143// region 6-11 is even aligned; it may be padded out more so that 3144// the region from SP to FP meets the minimum stack alignment. 3145 3146frame %{ 3147 // What direction does stack grow in (assumed to be same for native & Java) 3148 stack_direction(TOWARDS_LOW); 3149 3150 // These two registers define part of the calling convention 3151 // between compiled code and the interpreter. 3152 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3153 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3154 3155 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3156 cisc_spilling_operand_name(indOffset); 3157 3158 // Number of stack slots consumed by a Monitor enter 3159#ifdef _LP64 3160 sync_stack_slots(2); 3161#else 3162 sync_stack_slots(1); 3163#endif 3164 3165 // Compiled code's Frame Pointer 3166 frame_pointer(R_SP); 3167 3168 // Stack alignment requirement 3169 stack_alignment(StackAlignmentInBytes); 3170 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3171 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3172 3173 // Number of stack slots between incoming argument block and the start of 3174 // a new frame. The PROLOG must add this many slots to the stack. The 3175 // EPILOG must remove this many slots. 3176 in_preserve_stack_slots(0); 3177 3178 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3179 // for calls to C. Supports the var-args backing area for register parms. 3180 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3181#ifdef _LP64 3182 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3183 varargs_C_out_slots_killed(12); 3184#else 3185 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3186 varargs_C_out_slots_killed( 7); 3187#endif 3188 3189 // The after-PROLOG location of the return address. Location of 3190 // return address specifies a type (REG or STACK) and a number 3191 // representing the register number (i.e. - use a register name) or 3192 // stack slot. 3193 return_addr(REG R_I7); // Ret Addr is in register I7 3194 3195 // Body of function which returns an OptoRegs array locating 3196 // arguments either in registers or in stack slots for calling 3197 // java 3198 calling_convention %{ 3199 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3200 3201 %} 3202 3203 // Body of function which returns an OptoRegs array locating 3204 // arguments either in registers or in stack slots for callin 3205 // C. 3206 c_calling_convention %{ 3207 // This is obviously always outgoing 3208 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3209 %} 3210 3211 // Location of native (C/C++) and interpreter return values. This is specified to 3212 // be the same as Java. In the 32-bit VM, long values are actually returned from 3213 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3214 // to and from the register pairs is done by the appropriate call and epilog 3215 // opcodes. This simplifies the register allocator. 3216 c_return_value %{ 3217 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3218#ifdef _LP64 3219 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3220 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3221 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3222 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3223#else // !_LP64 3224 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3225 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3226 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3227 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3228#endif 3229 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3230 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3231 %} 3232 3233 // Location of compiled Java return values. Same as C 3234 return_value %{ 3235 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3236#ifdef _LP64 3237 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3238 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3239 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3240 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3241#else // !_LP64 3242 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3243 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3244 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3245 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3246#endif 3247 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3248 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3249 %} 3250 3251%} 3252 3253 3254//----------ATTRIBUTES--------------------------------------------------------- 3255//----------Operand Attributes------------------------------------------------- 3256op_attrib op_cost(1); // Required cost attribute 3257 3258//----------Instruction Attributes--------------------------------------------- 3259ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3260ins_attrib ins_size(32); // Required size attribute (in bits) 3261ins_attrib ins_pc_relative(0); // Required PC Relative flag 3262ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3263 // non-matching short branch variant of some 3264 // long branch? 3265 3266//----------OPERANDS----------------------------------------------------------- 3267// Operand definitions must precede instruction definitions for correct parsing 3268// in the ADLC because operands constitute user defined types which are used in 3269// instruction definitions. 3270 3271//----------Simple Operands---------------------------------------------------- 3272// Immediate Operands 3273// Integer Immediate: 32-bit 3274operand immI() %{ 3275 match(ConI); 3276 3277 op_cost(0); 3278 // formats are generated automatically for constants and base registers 3279 format %{ %} 3280 interface(CONST_INTER); 3281%} 3282 3283// Integer Immediate: 13-bit 3284operand immI13() %{ 3285 predicate(Assembler::is_simm13(n->get_int())); 3286 match(ConI); 3287 op_cost(0); 3288 3289 format %{ %} 3290 interface(CONST_INTER); 3291%} 3292 3293// Unsigned (positive) Integer Immediate: 13-bit 3294operand immU13() %{ 3295 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3296 match(ConI); 3297 op_cost(0); 3298 3299 format %{ %} 3300 interface(CONST_INTER); 3301%} 3302 3303// Integer Immediate: 6-bit 3304operand immU6() %{ 3305 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3306 match(ConI); 3307 op_cost(0); 3308 format %{ %} 3309 interface(CONST_INTER); 3310%} 3311 3312// Integer Immediate: 11-bit 3313operand immI11() %{ 3314 predicate(Assembler::is_simm(n->get_int(),11)); 3315 match(ConI); 3316 op_cost(0); 3317 format %{ %} 3318 interface(CONST_INTER); 3319%} 3320 3321// Integer Immediate: 0-bit 3322operand immI0() %{ 3323 predicate(n->get_int() == 0); 3324 match(ConI); 3325 op_cost(0); 3326 3327 format %{ %} 3328 interface(CONST_INTER); 3329%} 3330 3331// Integer Immediate: the value 10 3332operand immI10() %{ 3333 predicate(n->get_int() == 10); 3334 match(ConI); 3335 op_cost(0); 3336 3337 format %{ %} 3338 interface(CONST_INTER); 3339%} 3340 3341// Integer Immediate: the values 0-31 3342operand immU5() %{ 3343 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3344 match(ConI); 3345 op_cost(0); 3346 3347 format %{ %} 3348 interface(CONST_INTER); 3349%} 3350 3351// Integer Immediate: the values 1-31 3352operand immI_1_31() %{ 3353 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3354 match(ConI); 3355 op_cost(0); 3356 3357 format %{ %} 3358 interface(CONST_INTER); 3359%} 3360 3361// Integer Immediate: the values 32-63 3362operand immI_32_63() %{ 3363 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3364 match(ConI); 3365 op_cost(0); 3366 3367 format %{ %} 3368 interface(CONST_INTER); 3369%} 3370 3371// Integer Immediate: the value 255 3372operand immI_255() %{ 3373 predicate( n->get_int() == 255 ); 3374 match(ConI); 3375 op_cost(0); 3376 3377 format %{ %} 3378 interface(CONST_INTER); 3379%} 3380 3381// Long Immediate: the value FF 3382operand immL_FF() %{ 3383 predicate( n->get_long() == 0xFFL ); 3384 match(ConL); 3385 op_cost(0); 3386 3387 format %{ %} 3388 interface(CONST_INTER); 3389%} 3390 3391// Long Immediate: the value FFFF 3392operand immL_FFFF() %{ 3393 predicate( n->get_long() == 0xFFFFL ); 3394 match(ConL); 3395 op_cost(0); 3396 3397 format %{ %} 3398 interface(CONST_INTER); 3399%} 3400 3401// Pointer Immediate: 32 or 64-bit 3402operand immP() %{ 3403 match(ConP); 3404 3405 op_cost(5); 3406 // formats are generated automatically for constants and base registers 3407 format %{ %} 3408 interface(CONST_INTER); 3409%} 3410 3411operand immP13() %{ 3412 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3413 match(ConP); 3414 op_cost(0); 3415 3416 format %{ %} 3417 interface(CONST_INTER); 3418%} 3419 3420operand immP0() %{ 3421 predicate(n->get_ptr() == 0); 3422 match(ConP); 3423 op_cost(0); 3424 3425 format %{ %} 3426 interface(CONST_INTER); 3427%} 3428 3429operand immP_poll() %{ 3430 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3431 match(ConP); 3432 3433 // formats are generated automatically for constants and base registers 3434 format %{ %} 3435 interface(CONST_INTER); 3436%} 3437 3438// Pointer Immediate 3439operand immN() 3440%{ 3441 match(ConN); 3442 3443 op_cost(10); 3444 format %{ %} 3445 interface(CONST_INTER); 3446%} 3447 3448// NULL Pointer Immediate 3449operand immN0() 3450%{ 3451 predicate(n->get_narrowcon() == 0); 3452 match(ConN); 3453 3454 op_cost(0); 3455 format %{ %} 3456 interface(CONST_INTER); 3457%} 3458 3459operand immL() %{ 3460 match(ConL); 3461 op_cost(40); 3462 // formats are generated automatically for constants and base registers 3463 format %{ %} 3464 interface(CONST_INTER); 3465%} 3466 3467operand immL0() %{ 3468 predicate(n->get_long() == 0L); 3469 match(ConL); 3470 op_cost(0); 3471 // formats are generated automatically for constants and base registers 3472 format %{ %} 3473 interface(CONST_INTER); 3474%} 3475 3476// Long Immediate: 13-bit 3477operand immL13() %{ 3478 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3479 match(ConL); 3480 op_cost(0); 3481 3482 format %{ %} 3483 interface(CONST_INTER); 3484%} 3485 3486// Long Immediate: low 32-bit mask 3487operand immL_32bits() %{ 3488 predicate(n->get_long() == 0xFFFFFFFFL); 3489 match(ConL); 3490 op_cost(0); 3491 3492 format %{ %} 3493 interface(CONST_INTER); 3494%} 3495 3496// Double Immediate 3497operand immD() %{ 3498 match(ConD); 3499 3500 op_cost(40); 3501 format %{ %} 3502 interface(CONST_INTER); 3503%} 3504 3505operand immD0() %{ 3506#ifdef _LP64 3507 // on 64-bit architectures this comparision is faster 3508 predicate(jlong_cast(n->getd()) == 0); 3509#else 3510 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3511#endif 3512 match(ConD); 3513 3514 op_cost(0); 3515 format %{ %} 3516 interface(CONST_INTER); 3517%} 3518 3519// Float Immediate 3520operand immF() %{ 3521 match(ConF); 3522 3523 op_cost(20); 3524 format %{ %} 3525 interface(CONST_INTER); 3526%} 3527 3528// Float Immediate: 0 3529operand immF0() %{ 3530 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3531 match(ConF); 3532 3533 op_cost(0); 3534 format %{ %} 3535 interface(CONST_INTER); 3536%} 3537 3538// Integer Register Operands 3539// Integer Register 3540operand iRegI() %{ 3541 constraint(ALLOC_IN_RC(int_reg)); 3542 match(RegI); 3543 3544 match(notemp_iRegI); 3545 match(g1RegI); 3546 match(o0RegI); 3547 match(iRegIsafe); 3548 3549 format %{ %} 3550 interface(REG_INTER); 3551%} 3552 3553operand notemp_iRegI() %{ 3554 constraint(ALLOC_IN_RC(notemp_int_reg)); 3555 match(RegI); 3556 3557 match(o0RegI); 3558 3559 format %{ %} 3560 interface(REG_INTER); 3561%} 3562 3563operand o0RegI() %{ 3564 constraint(ALLOC_IN_RC(o0_regI)); 3565 match(iRegI); 3566 3567 format %{ %} 3568 interface(REG_INTER); 3569%} 3570 3571// Pointer Register 3572operand iRegP() %{ 3573 constraint(ALLOC_IN_RC(ptr_reg)); 3574 match(RegP); 3575 3576 match(lock_ptr_RegP); 3577 match(g1RegP); 3578 match(g2RegP); 3579 match(g3RegP); 3580 match(g4RegP); 3581 match(i0RegP); 3582 match(o0RegP); 3583 match(o1RegP); 3584 match(l7RegP); 3585 3586 format %{ %} 3587 interface(REG_INTER); 3588%} 3589 3590operand sp_ptr_RegP() %{ 3591 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3592 match(RegP); 3593 match(iRegP); 3594 3595 format %{ %} 3596 interface(REG_INTER); 3597%} 3598 3599operand lock_ptr_RegP() %{ 3600 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3601 match(RegP); 3602 match(i0RegP); 3603 match(o0RegP); 3604 match(o1RegP); 3605 match(l7RegP); 3606 3607 format %{ %} 3608 interface(REG_INTER); 3609%} 3610 3611operand g1RegP() %{ 3612 constraint(ALLOC_IN_RC(g1_regP)); 3613 match(iRegP); 3614 3615 format %{ %} 3616 interface(REG_INTER); 3617%} 3618 3619operand g2RegP() %{ 3620 constraint(ALLOC_IN_RC(g2_regP)); 3621 match(iRegP); 3622 3623 format %{ %} 3624 interface(REG_INTER); 3625%} 3626 3627operand g3RegP() %{ 3628 constraint(ALLOC_IN_RC(g3_regP)); 3629 match(iRegP); 3630 3631 format %{ %} 3632 interface(REG_INTER); 3633%} 3634 3635operand g1RegI() %{ 3636 constraint(ALLOC_IN_RC(g1_regI)); 3637 match(iRegI); 3638 3639 format %{ %} 3640 interface(REG_INTER); 3641%} 3642 3643operand g3RegI() %{ 3644 constraint(ALLOC_IN_RC(g3_regI)); 3645 match(iRegI); 3646 3647 format %{ %} 3648 interface(REG_INTER); 3649%} 3650 3651operand g4RegI() %{ 3652 constraint(ALLOC_IN_RC(g4_regI)); 3653 match(iRegI); 3654 3655 format %{ %} 3656 interface(REG_INTER); 3657%} 3658 3659operand g4RegP() %{ 3660 constraint(ALLOC_IN_RC(g4_regP)); 3661 match(iRegP); 3662 3663 format %{ %} 3664 interface(REG_INTER); 3665%} 3666 3667operand i0RegP() %{ 3668 constraint(ALLOC_IN_RC(i0_regP)); 3669 match(iRegP); 3670 3671 format %{ %} 3672 interface(REG_INTER); 3673%} 3674 3675operand o0RegP() %{ 3676 constraint(ALLOC_IN_RC(o0_regP)); 3677 match(iRegP); 3678 3679 format %{ %} 3680 interface(REG_INTER); 3681%} 3682 3683operand o1RegP() %{ 3684 constraint(ALLOC_IN_RC(o1_regP)); 3685 match(iRegP); 3686 3687 format %{ %} 3688 interface(REG_INTER); 3689%} 3690 3691operand o2RegP() %{ 3692 constraint(ALLOC_IN_RC(o2_regP)); 3693 match(iRegP); 3694 3695 format %{ %} 3696 interface(REG_INTER); 3697%} 3698 3699operand o7RegP() %{ 3700 constraint(ALLOC_IN_RC(o7_regP)); 3701 match(iRegP); 3702 3703 format %{ %} 3704 interface(REG_INTER); 3705%} 3706 3707operand l7RegP() %{ 3708 constraint(ALLOC_IN_RC(l7_regP)); 3709 match(iRegP); 3710 3711 format %{ %} 3712 interface(REG_INTER); 3713%} 3714 3715operand o7RegI() %{ 3716 constraint(ALLOC_IN_RC(o7_regI)); 3717 match(iRegI); 3718 3719 format %{ %} 3720 interface(REG_INTER); 3721%} 3722 3723operand iRegN() %{ 3724 constraint(ALLOC_IN_RC(int_reg)); 3725 match(RegN); 3726 3727 format %{ %} 3728 interface(REG_INTER); 3729%} 3730 3731// Long Register 3732operand iRegL() %{ 3733 constraint(ALLOC_IN_RC(long_reg)); 3734 match(RegL); 3735 3736 format %{ %} 3737 interface(REG_INTER); 3738%} 3739 3740operand o2RegL() %{ 3741 constraint(ALLOC_IN_RC(o2_regL)); 3742 match(iRegL); 3743 3744 format %{ %} 3745 interface(REG_INTER); 3746%} 3747 3748operand o7RegL() %{ 3749 constraint(ALLOC_IN_RC(o7_regL)); 3750 match(iRegL); 3751 3752 format %{ %} 3753 interface(REG_INTER); 3754%} 3755 3756operand g1RegL() %{ 3757 constraint(ALLOC_IN_RC(g1_regL)); 3758 match(iRegL); 3759 3760 format %{ %} 3761 interface(REG_INTER); 3762%} 3763 3764// Int Register safe 3765// This is 64bit safe 3766operand iRegIsafe() %{ 3767 constraint(ALLOC_IN_RC(long_reg)); 3768 3769 match(iRegI); 3770 3771 format %{ %} 3772 interface(REG_INTER); 3773%} 3774 3775// Condition Code Flag Register 3776operand flagsReg() %{ 3777 constraint(ALLOC_IN_RC(int_flags)); 3778 match(RegFlags); 3779 3780 format %{ "ccr" %} // both ICC and XCC 3781 interface(REG_INTER); 3782%} 3783 3784// Condition Code Register, unsigned comparisons. 3785operand flagsRegU() %{ 3786 constraint(ALLOC_IN_RC(int_flags)); 3787 match(RegFlags); 3788 3789 format %{ "icc_U" %} 3790 interface(REG_INTER); 3791%} 3792 3793// Condition Code Register, pointer comparisons. 3794operand flagsRegP() %{ 3795 constraint(ALLOC_IN_RC(int_flags)); 3796 match(RegFlags); 3797 3798#ifdef _LP64 3799 format %{ "xcc_P" %} 3800#else 3801 format %{ "icc_P" %} 3802#endif 3803 interface(REG_INTER); 3804%} 3805 3806// Condition Code Register, long comparisons. 3807operand flagsRegL() %{ 3808 constraint(ALLOC_IN_RC(int_flags)); 3809 match(RegFlags); 3810 3811 format %{ "xcc_L" %} 3812 interface(REG_INTER); 3813%} 3814 3815// Condition Code Register, floating comparisons, unordered same as "less". 3816operand flagsRegF() %{ 3817 constraint(ALLOC_IN_RC(float_flags)); 3818 match(RegFlags); 3819 match(flagsRegF0); 3820 3821 format %{ %} 3822 interface(REG_INTER); 3823%} 3824 3825operand flagsRegF0() %{ 3826 constraint(ALLOC_IN_RC(float_flag0)); 3827 match(RegFlags); 3828 3829 format %{ %} 3830 interface(REG_INTER); 3831%} 3832 3833 3834// Condition Code Flag Register used by long compare 3835operand flagsReg_long_LTGE() %{ 3836 constraint(ALLOC_IN_RC(int_flags)); 3837 match(RegFlags); 3838 format %{ "icc_LTGE" %} 3839 interface(REG_INTER); 3840%} 3841operand flagsReg_long_EQNE() %{ 3842 constraint(ALLOC_IN_RC(int_flags)); 3843 match(RegFlags); 3844 format %{ "icc_EQNE" %} 3845 interface(REG_INTER); 3846%} 3847operand flagsReg_long_LEGT() %{ 3848 constraint(ALLOC_IN_RC(int_flags)); 3849 match(RegFlags); 3850 format %{ "icc_LEGT" %} 3851 interface(REG_INTER); 3852%} 3853 3854 3855operand regD() %{ 3856 constraint(ALLOC_IN_RC(dflt_reg)); 3857 match(RegD); 3858 3859 format %{ %} 3860 interface(REG_INTER); 3861%} 3862 3863operand regF() %{ 3864 constraint(ALLOC_IN_RC(sflt_reg)); 3865 match(RegF); 3866 3867 format %{ %} 3868 interface(REG_INTER); 3869%} 3870 3871operand regD_low() %{ 3872 constraint(ALLOC_IN_RC(dflt_low_reg)); 3873 match(RegD); 3874 3875 format %{ %} 3876 interface(REG_INTER); 3877%} 3878 3879// Special Registers 3880 3881// Method Register 3882operand inline_cache_regP(iRegP reg) %{ 3883 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 3884 match(reg); 3885 format %{ %} 3886 interface(REG_INTER); 3887%} 3888 3889operand interpreter_method_oop_regP(iRegP reg) %{ 3890 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 3891 match(reg); 3892 format %{ %} 3893 interface(REG_INTER); 3894%} 3895 3896 3897//----------Complex Operands--------------------------------------------------- 3898// Indirect Memory Reference 3899operand indirect(sp_ptr_RegP reg) %{ 3900 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3901 match(reg); 3902 3903 op_cost(100); 3904 format %{ "[$reg]" %} 3905 interface(MEMORY_INTER) %{ 3906 base($reg); 3907 index(0x0); 3908 scale(0x0); 3909 disp(0x0); 3910 %} 3911%} 3912 3913// Indirect with Offset 3914operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 3915 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3916 match(AddP reg offset); 3917 3918 op_cost(100); 3919 format %{ "[$reg + $offset]" %} 3920 interface(MEMORY_INTER) %{ 3921 base($reg); 3922 index(0x0); 3923 scale(0x0); 3924 disp($offset); 3925 %} 3926%} 3927 3928// Note: Intel has a swapped version also, like this: 3929//operand indOffsetX(iRegI reg, immP offset) %{ 3930// constraint(ALLOC_IN_RC(int_reg)); 3931// match(AddP offset reg); 3932// 3933// op_cost(100); 3934// format %{ "[$reg + $offset]" %} 3935// interface(MEMORY_INTER) %{ 3936// base($reg); 3937// index(0x0); 3938// scale(0x0); 3939// disp($offset); 3940// %} 3941//%} 3942//// However, it doesn't make sense for SPARC, since 3943// we have no particularly good way to embed oops in 3944// single instructions. 3945 3946// Indirect with Register Index 3947operand indIndex(iRegP addr, iRegX index) %{ 3948 constraint(ALLOC_IN_RC(ptr_reg)); 3949 match(AddP addr index); 3950 3951 op_cost(100); 3952 format %{ "[$addr + $index]" %} 3953 interface(MEMORY_INTER) %{ 3954 base($addr); 3955 index($index); 3956 scale(0x0); 3957 disp(0x0); 3958 %} 3959%} 3960 3961//----------Special Memory Operands-------------------------------------------- 3962// Stack Slot Operand - This operand is used for loading and storing temporary 3963// values on the stack where a match requires a value to 3964// flow through memory. 3965operand stackSlotI(sRegI reg) %{ 3966 constraint(ALLOC_IN_RC(stack_slots)); 3967 op_cost(100); 3968 //match(RegI); 3969 format %{ "[$reg]" %} 3970 interface(MEMORY_INTER) %{ 3971 base(0xE); // R_SP 3972 index(0x0); 3973 scale(0x0); 3974 disp($reg); // Stack Offset 3975 %} 3976%} 3977 3978operand stackSlotP(sRegP reg) %{ 3979 constraint(ALLOC_IN_RC(stack_slots)); 3980 op_cost(100); 3981 //match(RegP); 3982 format %{ "[$reg]" %} 3983 interface(MEMORY_INTER) %{ 3984 base(0xE); // R_SP 3985 index(0x0); 3986 scale(0x0); 3987 disp($reg); // Stack Offset 3988 %} 3989%} 3990 3991operand stackSlotF(sRegF reg) %{ 3992 constraint(ALLOC_IN_RC(stack_slots)); 3993 op_cost(100); 3994 //match(RegF); 3995 format %{ "[$reg]" %} 3996 interface(MEMORY_INTER) %{ 3997 base(0xE); // R_SP 3998 index(0x0); 3999 scale(0x0); 4000 disp($reg); // Stack Offset 4001 %} 4002%} 4003operand stackSlotD(sRegD reg) %{ 4004 constraint(ALLOC_IN_RC(stack_slots)); 4005 op_cost(100); 4006 //match(RegD); 4007 format %{ "[$reg]" %} 4008 interface(MEMORY_INTER) %{ 4009 base(0xE); // R_SP 4010 index(0x0); 4011 scale(0x0); 4012 disp($reg); // Stack Offset 4013 %} 4014%} 4015operand stackSlotL(sRegL reg) %{ 4016 constraint(ALLOC_IN_RC(stack_slots)); 4017 op_cost(100); 4018 //match(RegL); 4019 format %{ "[$reg]" %} 4020 interface(MEMORY_INTER) %{ 4021 base(0xE); // R_SP 4022 index(0x0); 4023 scale(0x0); 4024 disp($reg); // Stack Offset 4025 %} 4026%} 4027 4028// Operands for expressing Control Flow 4029// NOTE: Label is a predefined operand which should not be redefined in 4030// the AD file. It is generically handled within the ADLC. 4031 4032//----------Conditional Branch Operands---------------------------------------- 4033// Comparison Op - This is the operation of the comparison, and is limited to 4034// the following set of codes: 4035// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4036// 4037// Other attributes of the comparison, such as unsignedness, are specified 4038// by the comparison instruction that sets a condition code flags register. 4039// That result is represented by a flags operand whose subtype is appropriate 4040// to the unsignedness (etc.) of the comparison. 4041// 4042// Later, the instruction which matches both the Comparison Op (a Bool) and 4043// the flags (produced by the Cmp) specifies the coding of the comparison op 4044// by matching a specific subtype of Bool operand below, such as cmpOpU. 4045 4046operand cmpOp() %{ 4047 match(Bool); 4048 4049 format %{ "" %} 4050 interface(COND_INTER) %{ 4051 equal(0x1); 4052 not_equal(0x9); 4053 less(0x3); 4054 greater_equal(0xB); 4055 less_equal(0x2); 4056 greater(0xA); 4057 %} 4058%} 4059 4060// Comparison Op, unsigned 4061operand cmpOpU() %{ 4062 match(Bool); 4063 4064 format %{ "u" %} 4065 interface(COND_INTER) %{ 4066 equal(0x1); 4067 not_equal(0x9); 4068 less(0x5); 4069 greater_equal(0xD); 4070 less_equal(0x4); 4071 greater(0xC); 4072 %} 4073%} 4074 4075// Comparison Op, pointer (same as unsigned) 4076operand cmpOpP() %{ 4077 match(Bool); 4078 4079 format %{ "p" %} 4080 interface(COND_INTER) %{ 4081 equal(0x1); 4082 not_equal(0x9); 4083 less(0x5); 4084 greater_equal(0xD); 4085 less_equal(0x4); 4086 greater(0xC); 4087 %} 4088%} 4089 4090// Comparison Op, branch-register encoding 4091operand cmpOp_reg() %{ 4092 match(Bool); 4093 4094 format %{ "" %} 4095 interface(COND_INTER) %{ 4096 equal (0x1); 4097 not_equal (0x5); 4098 less (0x3); 4099 greater_equal(0x7); 4100 less_equal (0x2); 4101 greater (0x6); 4102 %} 4103%} 4104 4105// Comparison Code, floating, unordered same as less 4106operand cmpOpF() %{ 4107 match(Bool); 4108 4109 format %{ "fl" %} 4110 interface(COND_INTER) %{ 4111 equal(0x9); 4112 not_equal(0x1); 4113 less(0x3); 4114 greater_equal(0xB); 4115 less_equal(0xE); 4116 greater(0x6); 4117 %} 4118%} 4119 4120// Used by long compare 4121operand cmpOp_commute() %{ 4122 match(Bool); 4123 4124 format %{ "" %} 4125 interface(COND_INTER) %{ 4126 equal(0x1); 4127 not_equal(0x9); 4128 less(0xA); 4129 greater_equal(0x2); 4130 less_equal(0xB); 4131 greater(0x3); 4132 %} 4133%} 4134 4135//----------OPERAND CLASSES---------------------------------------------------- 4136// Operand Classes are groups of operands that are used to simplify 4137// instruction definitions by not requiring the AD writer to specify seperate 4138// instructions for every form of operand when the instruction accepts 4139// multiple operand types with the same basic encoding and format. The classic 4140// case of this is memory operands. 4141// Indirect is not included since its use is limited to Compare & Swap 4142opclass memory( indirect, indOffset13, indIndex ); 4143 4144//----------PIPELINE----------------------------------------------------------- 4145pipeline %{ 4146 4147//----------ATTRIBUTES--------------------------------------------------------- 4148attributes %{ 4149 fixed_size_instructions; // Fixed size instructions 4150 branch_has_delay_slot; // Branch has delay slot following 4151 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4152 instruction_unit_size = 4; // An instruction is 4 bytes long 4153 instruction_fetch_unit_size = 16; // The processor fetches one line 4154 instruction_fetch_units = 1; // of 16 bytes 4155 4156 // List of nop instructions 4157 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4158%} 4159 4160//----------RESOURCES---------------------------------------------------------- 4161// Resources are the functional units available to the machine 4162resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4163 4164//----------PIPELINE DESCRIPTION----------------------------------------------- 4165// Pipeline Description specifies the stages in the machine's pipeline 4166 4167pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4168 4169//----------PIPELINE CLASSES--------------------------------------------------- 4170// Pipeline Classes describe the stages in which input and output are 4171// referenced by the hardware pipeline. 4172 4173// Integer ALU reg-reg operation 4174pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4175 single_instruction; 4176 dst : E(write); 4177 src1 : R(read); 4178 src2 : R(read); 4179 IALU : R; 4180%} 4181 4182// Integer ALU reg-reg long operation 4183pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4184 instruction_count(2); 4185 dst : E(write); 4186 src1 : R(read); 4187 src2 : R(read); 4188 IALU : R; 4189 IALU : R; 4190%} 4191 4192// Integer ALU reg-reg long dependent operation 4193pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4194 instruction_count(1); multiple_bundles; 4195 dst : E(write); 4196 src1 : R(read); 4197 src2 : R(read); 4198 cr : E(write); 4199 IALU : R(2); 4200%} 4201 4202// Integer ALU reg-imm operaion 4203pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4204 single_instruction; 4205 dst : E(write); 4206 src1 : R(read); 4207 IALU : R; 4208%} 4209 4210// Integer ALU reg-reg operation with condition code 4211pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4212 single_instruction; 4213 dst : E(write); 4214 cr : E(write); 4215 src1 : R(read); 4216 src2 : R(read); 4217 IALU : R; 4218%} 4219 4220// Integer ALU reg-imm operation with condition code 4221pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4222 single_instruction; 4223 dst : E(write); 4224 cr : E(write); 4225 src1 : R(read); 4226 IALU : R; 4227%} 4228 4229// Integer ALU zero-reg operation 4230pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4231 single_instruction; 4232 dst : E(write); 4233 src2 : R(read); 4234 IALU : R; 4235%} 4236 4237// Integer ALU zero-reg operation with condition code only 4238pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4239 single_instruction; 4240 cr : E(write); 4241 src : R(read); 4242 IALU : R; 4243%} 4244 4245// Integer ALU reg-reg operation with condition code only 4246pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4247 single_instruction; 4248 cr : E(write); 4249 src1 : R(read); 4250 src2 : R(read); 4251 IALU : R; 4252%} 4253 4254// Integer ALU reg-imm operation with condition code only 4255pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4256 single_instruction; 4257 cr : E(write); 4258 src1 : R(read); 4259 IALU : R; 4260%} 4261 4262// Integer ALU reg-reg-zero operation with condition code only 4263pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4264 single_instruction; 4265 cr : E(write); 4266 src1 : R(read); 4267 src2 : R(read); 4268 IALU : R; 4269%} 4270 4271// Integer ALU reg-imm-zero operation with condition code only 4272pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4273 single_instruction; 4274 cr : E(write); 4275 src1 : R(read); 4276 IALU : R; 4277%} 4278 4279// Integer ALU reg-reg operation with condition code, src1 modified 4280pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4281 single_instruction; 4282 cr : E(write); 4283 src1 : E(write); 4284 src1 : R(read); 4285 src2 : R(read); 4286 IALU : R; 4287%} 4288 4289// Integer ALU reg-imm operation with condition code, src1 modified 4290pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4291 single_instruction; 4292 cr : E(write); 4293 src1 : E(write); 4294 src1 : R(read); 4295 IALU : R; 4296%} 4297 4298pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4299 multiple_bundles; 4300 dst : E(write)+4; 4301 cr : E(write); 4302 src1 : R(read); 4303 src2 : R(read); 4304 IALU : R(3); 4305 BR : R(2); 4306%} 4307 4308// Integer ALU operation 4309pipe_class ialu_none(iRegI dst) %{ 4310 single_instruction; 4311 dst : E(write); 4312 IALU : R; 4313%} 4314 4315// Integer ALU reg operation 4316pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4317 single_instruction; may_have_no_code; 4318 dst : E(write); 4319 src : R(read); 4320 IALU : R; 4321%} 4322 4323// Integer ALU reg conditional operation 4324// This instruction has a 1 cycle stall, and cannot execute 4325// in the same cycle as the instruction setting the condition 4326// code. We kludge this by pretending to read the condition code 4327// 1 cycle earlier, and by marking the functional units as busy 4328// for 2 cycles with the result available 1 cycle later than 4329// is really the case. 4330pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4331 single_instruction; 4332 op2_out : C(write); 4333 op1 : R(read); 4334 cr : R(read); // This is really E, with a 1 cycle stall 4335 BR : R(2); 4336 MS : R(2); 4337%} 4338 4339#ifdef _LP64 4340pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4341 instruction_count(1); multiple_bundles; 4342 dst : C(write)+1; 4343 src : R(read)+1; 4344 IALU : R(1); 4345 BR : E(2); 4346 MS : E(2); 4347%} 4348#endif 4349 4350// Integer ALU reg operation 4351pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4352 single_instruction; may_have_no_code; 4353 dst : E(write); 4354 src : R(read); 4355 IALU : R; 4356%} 4357pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4358 single_instruction; may_have_no_code; 4359 dst : E(write); 4360 src : R(read); 4361 IALU : R; 4362%} 4363 4364// Two integer ALU reg operations 4365pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4366 instruction_count(2); 4367 dst : E(write); 4368 src : R(read); 4369 A0 : R; 4370 A1 : R; 4371%} 4372 4373// Two integer ALU reg operations 4374pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4375 instruction_count(2); may_have_no_code; 4376 dst : E(write); 4377 src : R(read); 4378 A0 : R; 4379 A1 : R; 4380%} 4381 4382// Integer ALU imm operation 4383pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4384 single_instruction; 4385 dst : E(write); 4386 IALU : R; 4387%} 4388 4389// Integer ALU reg-reg with carry operation 4390pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4391 single_instruction; 4392 dst : E(write); 4393 src1 : R(read); 4394 src2 : R(read); 4395 IALU : R; 4396%} 4397 4398// Integer ALU cc operation 4399pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4400 single_instruction; 4401 dst : E(write); 4402 cc : R(read); 4403 IALU : R; 4404%} 4405 4406// Integer ALU cc / second IALU operation 4407pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4408 instruction_count(1); multiple_bundles; 4409 dst : E(write)+1; 4410 src : R(read); 4411 IALU : R; 4412%} 4413 4414// Integer ALU cc / second IALU operation 4415pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4416 instruction_count(1); multiple_bundles; 4417 dst : E(write)+1; 4418 p : R(read); 4419 q : R(read); 4420 IALU : R; 4421%} 4422 4423// Integer ALU hi-lo-reg operation 4424pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4425 instruction_count(1); multiple_bundles; 4426 dst : E(write)+1; 4427 IALU : R(2); 4428%} 4429 4430// Float ALU hi-lo-reg operation (with temp) 4431pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4432 instruction_count(1); multiple_bundles; 4433 dst : E(write)+1; 4434 IALU : R(2); 4435%} 4436 4437// Long Constant 4438pipe_class loadConL( iRegL dst, immL src ) %{ 4439 instruction_count(2); multiple_bundles; 4440 dst : E(write)+1; 4441 IALU : R(2); 4442 IALU : R(2); 4443%} 4444 4445// Pointer Constant 4446pipe_class loadConP( iRegP dst, immP src ) %{ 4447 instruction_count(0); multiple_bundles; 4448 fixed_latency(6); 4449%} 4450 4451// Polling Address 4452pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4453#ifdef _LP64 4454 instruction_count(0); multiple_bundles; 4455 fixed_latency(6); 4456#else 4457 dst : E(write); 4458 IALU : R; 4459#endif 4460%} 4461 4462// Long Constant small 4463pipe_class loadConLlo( iRegL dst, immL src ) %{ 4464 instruction_count(2); 4465 dst : E(write); 4466 IALU : R; 4467 IALU : R; 4468%} 4469 4470// [PHH] This is wrong for 64-bit. See LdImmF/D. 4471pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4472 instruction_count(1); multiple_bundles; 4473 src : R(read); 4474 dst : M(write)+1; 4475 IALU : R; 4476 MS : E; 4477%} 4478 4479// Integer ALU nop operation 4480pipe_class ialu_nop() %{ 4481 single_instruction; 4482 IALU : R; 4483%} 4484 4485// Integer ALU nop operation 4486pipe_class ialu_nop_A0() %{ 4487 single_instruction; 4488 A0 : R; 4489%} 4490 4491// Integer ALU nop operation 4492pipe_class ialu_nop_A1() %{ 4493 single_instruction; 4494 A1 : R; 4495%} 4496 4497// Integer Multiply reg-reg operation 4498pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4499 single_instruction; 4500 dst : E(write); 4501 src1 : R(read); 4502 src2 : R(read); 4503 MS : R(5); 4504%} 4505 4506// Integer Multiply reg-imm operation 4507pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4508 single_instruction; 4509 dst : E(write); 4510 src1 : R(read); 4511 MS : R(5); 4512%} 4513 4514pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4515 single_instruction; 4516 dst : E(write)+4; 4517 src1 : R(read); 4518 src2 : R(read); 4519 MS : R(6); 4520%} 4521 4522pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4523 single_instruction; 4524 dst : E(write)+4; 4525 src1 : R(read); 4526 MS : R(6); 4527%} 4528 4529// Integer Divide reg-reg 4530pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4531 instruction_count(1); multiple_bundles; 4532 dst : E(write); 4533 temp : E(write); 4534 src1 : R(read); 4535 src2 : R(read); 4536 temp : R(read); 4537 MS : R(38); 4538%} 4539 4540// Integer Divide reg-imm 4541pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4542 instruction_count(1); multiple_bundles; 4543 dst : E(write); 4544 temp : E(write); 4545 src1 : R(read); 4546 temp : R(read); 4547 MS : R(38); 4548%} 4549 4550// Long Divide 4551pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4552 dst : E(write)+71; 4553 src1 : R(read); 4554 src2 : R(read)+1; 4555 MS : R(70); 4556%} 4557 4558pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4559 dst : E(write)+71; 4560 src1 : R(read); 4561 MS : R(70); 4562%} 4563 4564// Floating Point Add Float 4565pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4566 single_instruction; 4567 dst : X(write); 4568 src1 : E(read); 4569 src2 : E(read); 4570 FA : R; 4571%} 4572 4573// Floating Point Add Double 4574pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4575 single_instruction; 4576 dst : X(write); 4577 src1 : E(read); 4578 src2 : E(read); 4579 FA : R; 4580%} 4581 4582// Floating Point Conditional Move based on integer flags 4583pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4584 single_instruction; 4585 dst : X(write); 4586 src : E(read); 4587 cr : R(read); 4588 FA : R(2); 4589 BR : R(2); 4590%} 4591 4592// Floating Point Conditional Move based on integer flags 4593pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4594 single_instruction; 4595 dst : X(write); 4596 src : E(read); 4597 cr : R(read); 4598 FA : R(2); 4599 BR : R(2); 4600%} 4601 4602// Floating Point Multiply Float 4603pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4604 single_instruction; 4605 dst : X(write); 4606 src1 : E(read); 4607 src2 : E(read); 4608 FM : R; 4609%} 4610 4611// Floating Point Multiply Double 4612pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4613 single_instruction; 4614 dst : X(write); 4615 src1 : E(read); 4616 src2 : E(read); 4617 FM : R; 4618%} 4619 4620// Floating Point Divide Float 4621pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4622 single_instruction; 4623 dst : X(write); 4624 src1 : E(read); 4625 src2 : E(read); 4626 FM : R; 4627 FDIV : C(14); 4628%} 4629 4630// Floating Point Divide Double 4631pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4632 single_instruction; 4633 dst : X(write); 4634 src1 : E(read); 4635 src2 : E(read); 4636 FM : R; 4637 FDIV : C(17); 4638%} 4639 4640// Floating Point Move/Negate/Abs Float 4641pipe_class faddF_reg(regF dst, regF src) %{ 4642 single_instruction; 4643 dst : W(write); 4644 src : E(read); 4645 FA : R(1); 4646%} 4647 4648// Floating Point Move/Negate/Abs Double 4649pipe_class faddD_reg(regD dst, regD src) %{ 4650 single_instruction; 4651 dst : W(write); 4652 src : E(read); 4653 FA : R; 4654%} 4655 4656// Floating Point Convert F->D 4657pipe_class fcvtF2D(regD dst, regF src) %{ 4658 single_instruction; 4659 dst : X(write); 4660 src : E(read); 4661 FA : R; 4662%} 4663 4664// Floating Point Convert I->D 4665pipe_class fcvtI2D(regD dst, regF src) %{ 4666 single_instruction; 4667 dst : X(write); 4668 src : E(read); 4669 FA : R; 4670%} 4671 4672// Floating Point Convert LHi->D 4673pipe_class fcvtLHi2D(regD dst, regD src) %{ 4674 single_instruction; 4675 dst : X(write); 4676 src : E(read); 4677 FA : R; 4678%} 4679 4680// Floating Point Convert L->D 4681pipe_class fcvtL2D(regD dst, regF src) %{ 4682 single_instruction; 4683 dst : X(write); 4684 src : E(read); 4685 FA : R; 4686%} 4687 4688// Floating Point Convert L->F 4689pipe_class fcvtL2F(regD dst, regF src) %{ 4690 single_instruction; 4691 dst : X(write); 4692 src : E(read); 4693 FA : R; 4694%} 4695 4696// Floating Point Convert D->F 4697pipe_class fcvtD2F(regD dst, regF src) %{ 4698 single_instruction; 4699 dst : X(write); 4700 src : E(read); 4701 FA : R; 4702%} 4703 4704// Floating Point Convert I->L 4705pipe_class fcvtI2L(regD dst, regF src) %{ 4706 single_instruction; 4707 dst : X(write); 4708 src : E(read); 4709 FA : R; 4710%} 4711 4712// Floating Point Convert D->F 4713pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4714 instruction_count(1); multiple_bundles; 4715 dst : X(write)+6; 4716 src : E(read); 4717 FA : R; 4718%} 4719 4720// Floating Point Convert D->L 4721pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4722 instruction_count(1); multiple_bundles; 4723 dst : X(write)+6; 4724 src : E(read); 4725 FA : R; 4726%} 4727 4728// Floating Point Convert F->I 4729pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4730 instruction_count(1); multiple_bundles; 4731 dst : X(write)+6; 4732 src : E(read); 4733 FA : R; 4734%} 4735 4736// Floating Point Convert F->L 4737pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4738 instruction_count(1); multiple_bundles; 4739 dst : X(write)+6; 4740 src : E(read); 4741 FA : R; 4742%} 4743 4744// Floating Point Convert I->F 4745pipe_class fcvtI2F(regF dst, regF src) %{ 4746 single_instruction; 4747 dst : X(write); 4748 src : E(read); 4749 FA : R; 4750%} 4751 4752// Floating Point Compare 4753pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4754 single_instruction; 4755 cr : X(write); 4756 src1 : E(read); 4757 src2 : E(read); 4758 FA : R; 4759%} 4760 4761// Floating Point Compare 4762pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4763 single_instruction; 4764 cr : X(write); 4765 src1 : E(read); 4766 src2 : E(read); 4767 FA : R; 4768%} 4769 4770// Floating Add Nop 4771pipe_class fadd_nop() %{ 4772 single_instruction; 4773 FA : R; 4774%} 4775 4776// Integer Store to Memory 4777pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4778 single_instruction; 4779 mem : R(read); 4780 src : C(read); 4781 MS : R; 4782%} 4783 4784// Integer Store to Memory 4785pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4786 single_instruction; 4787 mem : R(read); 4788 src : C(read); 4789 MS : R; 4790%} 4791 4792// Integer Store Zero to Memory 4793pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4794 single_instruction; 4795 mem : R(read); 4796 MS : R; 4797%} 4798 4799// Special Stack Slot Store 4800pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4801 single_instruction; 4802 stkSlot : R(read); 4803 src : C(read); 4804 MS : R; 4805%} 4806 4807// Special Stack Slot Store 4808pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4809 instruction_count(2); multiple_bundles; 4810 stkSlot : R(read); 4811 src : C(read); 4812 MS : R(2); 4813%} 4814 4815// Float Store 4816pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4817 single_instruction; 4818 mem : R(read); 4819 src : C(read); 4820 MS : R; 4821%} 4822 4823// Float Store 4824pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4825 single_instruction; 4826 mem : R(read); 4827 MS : R; 4828%} 4829 4830// Double Store 4831pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4832 instruction_count(1); 4833 mem : R(read); 4834 src : C(read); 4835 MS : R; 4836%} 4837 4838// Double Store 4839pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4840 single_instruction; 4841 mem : R(read); 4842 MS : R; 4843%} 4844 4845// Special Stack Slot Float Store 4846pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4847 single_instruction; 4848 stkSlot : R(read); 4849 src : C(read); 4850 MS : R; 4851%} 4852 4853// Special Stack Slot Double Store 4854pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4855 single_instruction; 4856 stkSlot : R(read); 4857 src : C(read); 4858 MS : R; 4859%} 4860 4861// Integer Load (when sign bit propagation not needed) 4862pipe_class iload_mem(iRegI dst, memory mem) %{ 4863 single_instruction; 4864 mem : R(read); 4865 dst : C(write); 4866 MS : R; 4867%} 4868 4869// Integer Load from stack operand 4870pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 4871 single_instruction; 4872 mem : R(read); 4873 dst : C(write); 4874 MS : R; 4875%} 4876 4877// Integer Load (when sign bit propagation or masking is needed) 4878pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 4879 single_instruction; 4880 mem : R(read); 4881 dst : M(write); 4882 MS : R; 4883%} 4884 4885// Float Load 4886pipe_class floadF_mem(regF dst, memory mem) %{ 4887 single_instruction; 4888 mem : R(read); 4889 dst : M(write); 4890 MS : R; 4891%} 4892 4893// Float Load 4894pipe_class floadD_mem(regD dst, memory mem) %{ 4895 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 4896 mem : R(read); 4897 dst : M(write); 4898 MS : R; 4899%} 4900 4901// Float Load 4902pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 4903 single_instruction; 4904 stkSlot : R(read); 4905 dst : M(write); 4906 MS : R; 4907%} 4908 4909// Float Load 4910pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 4911 single_instruction; 4912 stkSlot : R(read); 4913 dst : M(write); 4914 MS : R; 4915%} 4916 4917// Memory Nop 4918pipe_class mem_nop() %{ 4919 single_instruction; 4920 MS : R; 4921%} 4922 4923pipe_class sethi(iRegP dst, immI src) %{ 4924 single_instruction; 4925 dst : E(write); 4926 IALU : R; 4927%} 4928 4929pipe_class loadPollP(iRegP poll) %{ 4930 single_instruction; 4931 poll : R(read); 4932 MS : R; 4933%} 4934 4935pipe_class br(Universe br, label labl) %{ 4936 single_instruction_with_delay_slot; 4937 BR : R; 4938%} 4939 4940pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 4941 single_instruction_with_delay_slot; 4942 cr : E(read); 4943 BR : R; 4944%} 4945 4946pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 4947 single_instruction_with_delay_slot; 4948 op1 : E(read); 4949 BR : R; 4950 MS : R; 4951%} 4952 4953pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 4954 single_instruction_with_delay_slot; 4955 cr : E(read); 4956 BR : R; 4957%} 4958 4959pipe_class br_nop() %{ 4960 single_instruction; 4961 BR : R; 4962%} 4963 4964pipe_class simple_call(method meth) %{ 4965 instruction_count(2); multiple_bundles; force_serialization; 4966 fixed_latency(100); 4967 BR : R(1); 4968 MS : R(1); 4969 A0 : R(1); 4970%} 4971 4972pipe_class compiled_call(method meth) %{ 4973 instruction_count(1); multiple_bundles; force_serialization; 4974 fixed_latency(100); 4975 MS : R(1); 4976%} 4977 4978pipe_class call(method meth) %{ 4979 instruction_count(0); multiple_bundles; force_serialization; 4980 fixed_latency(100); 4981%} 4982 4983pipe_class tail_call(Universe ignore, label labl) %{ 4984 single_instruction; has_delay_slot; 4985 fixed_latency(100); 4986 BR : R(1); 4987 MS : R(1); 4988%} 4989 4990pipe_class ret(Universe ignore) %{ 4991 single_instruction; has_delay_slot; 4992 BR : R(1); 4993 MS : R(1); 4994%} 4995 4996pipe_class ret_poll(g3RegP poll) %{ 4997 instruction_count(3); has_delay_slot; 4998 poll : E(read); 4999 MS : R; 5000%} 5001 5002// The real do-nothing guy 5003pipe_class empty( ) %{ 5004 instruction_count(0); 5005%} 5006 5007pipe_class long_memory_op() %{ 5008 instruction_count(0); multiple_bundles; force_serialization; 5009 fixed_latency(25); 5010 MS : R(1); 5011%} 5012 5013// Check-cast 5014pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5015 array : R(read); 5016 match : R(read); 5017 IALU : R(2); 5018 BR : R(2); 5019 MS : R; 5020%} 5021 5022// Convert FPU flags into +1,0,-1 5023pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5024 src1 : E(read); 5025 src2 : E(read); 5026 dst : E(write); 5027 FA : R; 5028 MS : R(2); 5029 BR : R(2); 5030%} 5031 5032// Compare for p < q, and conditionally add y 5033pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5034 p : E(read); 5035 q : E(read); 5036 y : E(read); 5037 IALU : R(3) 5038%} 5039 5040// Perform a compare, then move conditionally in a branch delay slot. 5041pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5042 src2 : E(read); 5043 srcdst : E(read); 5044 IALU : R; 5045 BR : R; 5046%} 5047 5048// Define the class for the Nop node 5049define %{ 5050 MachNop = ialu_nop; 5051%} 5052 5053%} 5054 5055//----------INSTRUCTIONS------------------------------------------------------- 5056 5057//------------Special Stack Slot instructions - no match rules----------------- 5058instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5059 // No match rule to avoid chain rule match. 5060 effect(DEF dst, USE src); 5061 ins_cost(MEMORY_REF_COST); 5062 size(4); 5063 format %{ "LDF $src,$dst\t! stkI to regF" %} 5064 opcode(Assembler::ldf_op3); 5065 ins_encode(form3_mem_reg(src, dst)); 5066 ins_pipe(floadF_stk); 5067%} 5068 5069instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5070 // No match rule to avoid chain rule match. 5071 effect(DEF dst, USE src); 5072 ins_cost(MEMORY_REF_COST); 5073 size(4); 5074 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5075 opcode(Assembler::lddf_op3); 5076 ins_encode(form3_mem_reg(src, dst)); 5077 ins_pipe(floadD_stk); 5078%} 5079 5080instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5081 // No match rule to avoid chain rule match. 5082 effect(DEF dst, USE src); 5083 ins_cost(MEMORY_REF_COST); 5084 size(4); 5085 format %{ "STF $src,$dst\t! regF to stkI" %} 5086 opcode(Assembler::stf_op3); 5087 ins_encode(form3_mem_reg(dst, src)); 5088 ins_pipe(fstoreF_stk_reg); 5089%} 5090 5091instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5092 // No match rule to avoid chain rule match. 5093 effect(DEF dst, USE src); 5094 ins_cost(MEMORY_REF_COST); 5095 size(4); 5096 format %{ "STDF $src,$dst\t! regD to stkL" %} 5097 opcode(Assembler::stdf_op3); 5098 ins_encode(form3_mem_reg(dst, src)); 5099 ins_pipe(fstoreD_stk_reg); 5100%} 5101 5102instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5103 effect(DEF dst, USE src); 5104 ins_cost(MEMORY_REF_COST*2); 5105 size(8); 5106 format %{ "STW $src,$dst.hi\t! long\n\t" 5107 "STW R_G0,$dst.lo" %} 5108 opcode(Assembler::stw_op3); 5109 ins_encode(form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5110 ins_pipe(lstoreI_stk_reg); 5111%} 5112 5113instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5114 // No match rule to avoid chain rule match. 5115 effect(DEF dst, USE src); 5116 ins_cost(MEMORY_REF_COST); 5117 size(4); 5118 format %{ "STX $src,$dst\t! regL to stkD" %} 5119 opcode(Assembler::stx_op3); 5120 ins_encode( form3_mem_reg( dst, src ) ); 5121 ins_pipe(istore_stk_reg); 5122%} 5123 5124//---------- Chain stack slots between similar types -------- 5125 5126// Load integer from stack slot 5127instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5128 match(Set dst src); 5129 ins_cost(MEMORY_REF_COST); 5130 5131 size(4); 5132 format %{ "LDUW $src,$dst\t!stk" %} 5133 opcode(Assembler::lduw_op3); 5134 ins_encode( form3_mem_reg( src, dst ) ); 5135 ins_pipe(iload_mem); 5136%} 5137 5138// Store integer to stack slot 5139instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5140 match(Set dst src); 5141 ins_cost(MEMORY_REF_COST); 5142 5143 size(4); 5144 format %{ "STW $src,$dst\t!stk" %} 5145 opcode(Assembler::stw_op3); 5146 ins_encode( form3_mem_reg( dst, src ) ); 5147 ins_pipe(istore_mem_reg); 5148%} 5149 5150// Load long from stack slot 5151instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5152 match(Set dst src); 5153 5154 ins_cost(MEMORY_REF_COST); 5155 size(4); 5156 format %{ "LDX $src,$dst\t! long" %} 5157 opcode(Assembler::ldx_op3); 5158 ins_encode( form3_mem_reg( src, dst ) ); 5159 ins_pipe(iload_mem); 5160%} 5161 5162// Store long to stack slot 5163instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5164 match(Set dst src); 5165 5166 ins_cost(MEMORY_REF_COST); 5167 size(4); 5168 format %{ "STX $src,$dst\t! long" %} 5169 opcode(Assembler::stx_op3); 5170 ins_encode( form3_mem_reg( dst, src ) ); 5171 ins_pipe(istore_mem_reg); 5172%} 5173 5174#ifdef _LP64 5175// Load pointer from stack slot, 64-bit encoding 5176instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5177 match(Set dst src); 5178 ins_cost(MEMORY_REF_COST); 5179 size(4); 5180 format %{ "LDX $src,$dst\t!ptr" %} 5181 opcode(Assembler::ldx_op3); 5182 ins_encode( form3_mem_reg( src, dst ) ); 5183 ins_pipe(iload_mem); 5184%} 5185 5186// Store pointer to stack slot 5187instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5188 match(Set dst src); 5189 ins_cost(MEMORY_REF_COST); 5190 size(4); 5191 format %{ "STX $src,$dst\t!ptr" %} 5192 opcode(Assembler::stx_op3); 5193 ins_encode( form3_mem_reg( dst, src ) ); 5194 ins_pipe(istore_mem_reg); 5195%} 5196#else // _LP64 5197// Load pointer from stack slot, 32-bit encoding 5198instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5199 match(Set dst src); 5200 ins_cost(MEMORY_REF_COST); 5201 format %{ "LDUW $src,$dst\t!ptr" %} 5202 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5203 ins_encode( form3_mem_reg( src, dst ) ); 5204 ins_pipe(iload_mem); 5205%} 5206 5207// Store pointer to stack slot 5208instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5209 match(Set dst src); 5210 ins_cost(MEMORY_REF_COST); 5211 format %{ "STW $src,$dst\t!ptr" %} 5212 opcode(Assembler::stw_op3, Assembler::ldst_op); 5213 ins_encode( form3_mem_reg( dst, src ) ); 5214 ins_pipe(istore_mem_reg); 5215%} 5216#endif // _LP64 5217 5218//------------Special Nop instructions for bundling - no match rules----------- 5219// Nop using the A0 functional unit 5220instruct Nop_A0() %{ 5221 ins_cost(0); 5222 5223 format %{ "NOP ! Alu Pipeline" %} 5224 opcode(Assembler::or_op3, Assembler::arith_op); 5225 ins_encode( form2_nop() ); 5226 ins_pipe(ialu_nop_A0); 5227%} 5228 5229// Nop using the A1 functional unit 5230instruct Nop_A1( ) %{ 5231 ins_cost(0); 5232 5233 format %{ "NOP ! Alu Pipeline" %} 5234 opcode(Assembler::or_op3, Assembler::arith_op); 5235 ins_encode( form2_nop() ); 5236 ins_pipe(ialu_nop_A1); 5237%} 5238 5239// Nop using the memory functional unit 5240instruct Nop_MS( ) %{ 5241 ins_cost(0); 5242 5243 format %{ "NOP ! Memory Pipeline" %} 5244 ins_encode( emit_mem_nop ); 5245 ins_pipe(mem_nop); 5246%} 5247 5248// Nop using the floating add functional unit 5249instruct Nop_FA( ) %{ 5250 ins_cost(0); 5251 5252 format %{ "NOP ! Floating Add Pipeline" %} 5253 ins_encode( emit_fadd_nop ); 5254 ins_pipe(fadd_nop); 5255%} 5256 5257// Nop using the branch functional unit 5258instruct Nop_BR( ) %{ 5259 ins_cost(0); 5260 5261 format %{ "NOP ! Branch Pipeline" %} 5262 ins_encode( emit_br_nop ); 5263 ins_pipe(br_nop); 5264%} 5265 5266//----------Load/Store/Move Instructions--------------------------------------- 5267//----------Load Instructions-------------------------------------------------- 5268// Load Byte (8bit signed) 5269instruct loadB(iRegI dst, memory mem) %{ 5270 match(Set dst (LoadB mem)); 5271 ins_cost(MEMORY_REF_COST); 5272 5273 size(4); 5274 format %{ "LDSB $mem,$dst" %} 5275 opcode(Assembler::ldsb_op3); 5276 ins_encode( form3_mem_reg( mem, dst ) ); 5277 ins_pipe(iload_mask_mem); 5278%} 5279 5280// Load Byte (8bit UNsigned) into an int reg 5281instruct loadUB(iRegI dst, memory mem, immI_255 bytemask) %{ 5282 match(Set dst (AndI (LoadB mem) bytemask)); 5283 ins_cost(MEMORY_REF_COST); 5284 5285 size(4); 5286 format %{ "LDUB $mem,$dst" %} 5287 opcode(Assembler::ldub_op3); 5288 ins_encode( form3_mem_reg( mem, dst ) ); 5289 ins_pipe(iload_mask_mem); 5290%} 5291 5292// Load Byte (8bit UNsigned) into a Long Register 5293instruct loadUBL(iRegL dst, memory mem, immL_FF bytemask) %{ 5294 match(Set dst (AndL (ConvI2L (LoadB mem)) bytemask)); 5295 ins_cost(MEMORY_REF_COST); 5296 5297 size(4); 5298 format %{ "LDUB $mem,$dst" %} 5299 opcode(Assembler::ldub_op3); 5300 ins_encode( form3_mem_reg( mem, dst ) ); 5301 ins_pipe(iload_mask_mem); 5302%} 5303 5304// Load Char (16bit UNsigned) into a Long Register 5305instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{ 5306 match(Set dst (AndL (ConvI2L (LoadC mem)) bytemask)); 5307 ins_cost(MEMORY_REF_COST); 5308 5309 size(4); 5310 format %{ "LDUH $mem,$dst" %} 5311 opcode(Assembler::lduh_op3); 5312 ins_encode( form3_mem_reg( mem, dst ) ); 5313 ins_pipe(iload_mask_mem); 5314%} 5315 5316// Load Char (16bit unsigned) 5317instruct loadC(iRegI dst, memory mem) %{ 5318 match(Set dst (LoadC mem)); 5319 ins_cost(MEMORY_REF_COST); 5320 5321 size(4); 5322 format %{ "LDUH $mem,$dst" %} 5323 opcode(Assembler::lduh_op3); 5324 ins_encode( form3_mem_reg( mem, dst ) ); 5325 ins_pipe(iload_mask_mem); 5326%} 5327 5328// Load Integer 5329instruct loadI(iRegI dst, memory mem) %{ 5330 match(Set dst (LoadI mem)); 5331 ins_cost(MEMORY_REF_COST); 5332 size(4); 5333 5334 format %{ "LDUW $mem,$dst" %} 5335 opcode(Assembler::lduw_op3); 5336 ins_encode( form3_mem_reg( mem, dst ) ); 5337 ins_pipe(iload_mem); 5338%} 5339 5340// Load Long - aligned 5341instruct loadL(iRegL dst, memory mem ) %{ 5342 match(Set dst (LoadL mem)); 5343 ins_cost(MEMORY_REF_COST); 5344 size(4); 5345 format %{ "LDX $mem,$dst\t! long" %} 5346 opcode(Assembler::ldx_op3); 5347 ins_encode( form3_mem_reg( mem, dst ) ); 5348 ins_pipe(iload_mem); 5349%} 5350 5351// Load Long - UNaligned 5352instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5353 match(Set dst (LoadL_unaligned mem)); 5354 effect(KILL tmp); 5355 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5356 size(16); 5357 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5358 "\tLDUW $mem ,$dst\n" 5359 "\tSLLX #32, $dst, $dst\n" 5360 "\tOR $dst, R_O7, $dst" %} 5361 opcode(Assembler::lduw_op3); 5362 ins_encode( form3_mem_reg_long_unaligned_marshal( mem, dst )); 5363 ins_pipe(iload_mem); 5364%} 5365 5366// Load Aligned Packed Byte into a Double Register 5367instruct loadA8B(regD dst, memory mem) %{ 5368 match(Set dst (Load8B mem)); 5369 ins_cost(MEMORY_REF_COST); 5370 size(4); 5371 format %{ "LDDF $mem,$dst\t! packed8B" %} 5372 opcode(Assembler::lddf_op3); 5373 ins_encode( form3_mem_reg( mem, dst ) ); 5374 ins_pipe(floadD_mem); 5375%} 5376 5377// Load Aligned Packed Char into a Double Register 5378instruct loadA4C(regD dst, memory mem) %{ 5379 match(Set dst (Load4C mem)); 5380 ins_cost(MEMORY_REF_COST); 5381 size(4); 5382 format %{ "LDDF $mem,$dst\t! packed4C" %} 5383 opcode(Assembler::lddf_op3); 5384 ins_encode( form3_mem_reg( mem, dst ) ); 5385 ins_pipe(floadD_mem); 5386%} 5387 5388// Load Aligned Packed Short into a Double Register 5389instruct loadA4S(regD dst, memory mem) %{ 5390 match(Set dst (Load4S mem)); 5391 ins_cost(MEMORY_REF_COST); 5392 size(4); 5393 format %{ "LDDF $mem,$dst\t! packed4S" %} 5394 opcode(Assembler::lddf_op3); 5395 ins_encode( form3_mem_reg( mem, dst ) ); 5396 ins_pipe(floadD_mem); 5397%} 5398 5399// Load Aligned Packed Int into a Double Register 5400instruct loadA2I(regD dst, memory mem) %{ 5401 match(Set dst (Load2I mem)); 5402 ins_cost(MEMORY_REF_COST); 5403 size(4); 5404 format %{ "LDDF $mem,$dst\t! packed2I" %} 5405 opcode(Assembler::lddf_op3); 5406 ins_encode( form3_mem_reg( mem, dst ) ); 5407 ins_pipe(floadD_mem); 5408%} 5409 5410// Load Range 5411instruct loadRange(iRegI dst, memory mem) %{ 5412 match(Set dst (LoadRange mem)); 5413 ins_cost(MEMORY_REF_COST); 5414 5415 size(4); 5416 format %{ "LDUW $mem,$dst\t! range" %} 5417 opcode(Assembler::lduw_op3); 5418 ins_encode( form3_mem_reg( mem, dst ) ); 5419 ins_pipe(iload_mem); 5420%} 5421 5422// Load Integer into %f register (for fitos/fitod) 5423instruct loadI_freg(regF dst, memory mem) %{ 5424 match(Set dst (LoadI mem)); 5425 ins_cost(MEMORY_REF_COST); 5426 size(4); 5427 5428 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5429 opcode(Assembler::ldf_op3); 5430 ins_encode( form3_mem_reg( mem, dst ) ); 5431 ins_pipe(floadF_mem); 5432%} 5433 5434// Load Pointer 5435instruct loadP(iRegP dst, memory mem) %{ 5436 match(Set dst (LoadP mem)); 5437 ins_cost(MEMORY_REF_COST); 5438 size(4); 5439 5440#ifndef _LP64 5441 format %{ "LDUW $mem,$dst\t! ptr" %} 5442 opcode(Assembler::lduw_op3, 0, REGP_OP); 5443#else 5444 format %{ "LDX $mem,$dst\t! ptr" %} 5445 opcode(Assembler::ldx_op3, 0, REGP_OP); 5446#endif 5447 ins_encode( form3_mem_reg( mem, dst ) ); 5448 ins_pipe(iload_mem); 5449%} 5450 5451// Load Compressed Pointer 5452instruct loadN(iRegN dst, memory mem) %{ 5453 match(Set dst (LoadN mem)); 5454 ins_cost(MEMORY_REF_COST); 5455 size(4); 5456 5457 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5458 ins_encode %{ 5459 Register base = as_Register($mem$$base); 5460 Register index = as_Register($mem$$index); 5461 Register dst = $dst$$Register; 5462 if (index != G0) { 5463 __ lduw(base, index, dst); 5464 } else { 5465 __ lduw(base, $mem$$disp, dst); 5466 } 5467 %} 5468 ins_pipe(iload_mem); 5469%} 5470 5471// Load Klass Pointer 5472instruct loadKlass(iRegP dst, memory mem) %{ 5473 match(Set dst (LoadKlass mem)); 5474 ins_cost(MEMORY_REF_COST); 5475 size(4); 5476 5477#ifndef _LP64 5478 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5479 opcode(Assembler::lduw_op3, 0, REGP_OP); 5480#else 5481 format %{ "LDX $mem,$dst\t! klass ptr" %} 5482 opcode(Assembler::ldx_op3, 0, REGP_OP); 5483#endif 5484 ins_encode( form3_mem_reg( mem, dst ) ); 5485 ins_pipe(iload_mem); 5486%} 5487 5488// Load narrow Klass Pointer 5489instruct loadNKlass(iRegN dst, memory mem) %{ 5490 match(Set dst (LoadNKlass mem)); 5491 ins_cost(MEMORY_REF_COST); 5492 size(4); 5493 5494 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5495 5496 ins_encode %{ 5497 Register base = as_Register($mem$$base); 5498 Register index = as_Register($mem$$index); 5499 Register dst = $dst$$Register; 5500 if (index != G0) { 5501 __ lduw(base, index, dst); 5502 } else { 5503 __ lduw(base, $mem$$disp, dst); 5504 } 5505 %} 5506 ins_pipe(iload_mem); 5507%} 5508 5509// Load Short (16bit signed) 5510instruct loadS(iRegI dst, memory mem) %{ 5511 match(Set dst (LoadS mem)); 5512 ins_cost(MEMORY_REF_COST); 5513 5514 size(4); 5515 format %{ "LDSH $mem,$dst" %} 5516 opcode(Assembler::ldsh_op3); 5517 ins_encode( form3_mem_reg( mem, dst ) ); 5518 ins_pipe(iload_mask_mem); 5519%} 5520 5521// Load Double 5522instruct loadD(regD dst, memory mem) %{ 5523 match(Set dst (LoadD mem)); 5524 ins_cost(MEMORY_REF_COST); 5525 5526 size(4); 5527 format %{ "LDDF $mem,$dst" %} 5528 opcode(Assembler::lddf_op3); 5529 ins_encode( form3_mem_reg( mem, dst ) ); 5530 ins_pipe(floadD_mem); 5531%} 5532 5533// Load Double - UNaligned 5534instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5535 match(Set dst (LoadD_unaligned mem)); 5536 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5537 size(8); 5538 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5539 "\tLDF $mem+4,$dst.lo\t!" %} 5540 opcode(Assembler::ldf_op3); 5541 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5542 ins_pipe(iload_mem); 5543%} 5544 5545// Load Float 5546instruct loadF(regF dst, memory mem) %{ 5547 match(Set dst (LoadF mem)); 5548 ins_cost(MEMORY_REF_COST); 5549 5550 size(4); 5551 format %{ "LDF $mem,$dst" %} 5552 opcode(Assembler::ldf_op3); 5553 ins_encode( form3_mem_reg( mem, dst ) ); 5554 ins_pipe(floadF_mem); 5555%} 5556 5557// Load Constant 5558instruct loadConI( iRegI dst, immI src ) %{ 5559 match(Set dst src); 5560 ins_cost(DEFAULT_COST * 3/2); 5561 format %{ "SET $src,$dst" %} 5562 ins_encode( Set32(src, dst) ); 5563 ins_pipe(ialu_hi_lo_reg); 5564%} 5565 5566instruct loadConI13( iRegI dst, immI13 src ) %{ 5567 match(Set dst src); 5568 5569 size(4); 5570 format %{ "MOV $src,$dst" %} 5571 ins_encode( Set13( src, dst ) ); 5572 ins_pipe(ialu_imm); 5573%} 5574 5575instruct loadConP(iRegP dst, immP src) %{ 5576 match(Set dst src); 5577 ins_cost(DEFAULT_COST * 3/2); 5578 format %{ "SET $src,$dst\t!ptr" %} 5579 // This rule does not use "expand" unlike loadConI because then 5580 // the result type is not known to be an Oop. An ADLC 5581 // enhancement will be needed to make that work - not worth it! 5582 5583 ins_encode( SetPtr( src, dst ) ); 5584 ins_pipe(loadConP); 5585 5586%} 5587 5588instruct loadConP0(iRegP dst, immP0 src) %{ 5589 match(Set dst src); 5590 5591 size(4); 5592 format %{ "CLR $dst\t!ptr" %} 5593 ins_encode( SetNull( dst ) ); 5594 ins_pipe(ialu_imm); 5595%} 5596 5597instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5598 match(Set dst src); 5599 ins_cost(DEFAULT_COST); 5600 format %{ "SET $src,$dst\t!ptr" %} 5601 ins_encode %{ 5602 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page()); 5603 __ sethi(polling_page, false ); 5604 %} 5605 ins_pipe(loadConP_poll); 5606%} 5607 5608instruct loadConN0(iRegN dst, immN0 src) %{ 5609 match(Set dst src); 5610 5611 size(4); 5612 format %{ "CLR $dst\t! compressed NULL ptr" %} 5613 ins_encode( SetNull( dst ) ); 5614 ins_pipe(ialu_imm); 5615%} 5616 5617instruct loadConN(iRegN dst, immN src) %{ 5618 match(Set dst src); 5619 ins_cost(DEFAULT_COST * 3/2); 5620 format %{ "SET $src,$dst\t! compressed ptr" %} 5621 ins_encode %{ 5622 Register dst = $dst$$Register; 5623 __ set_narrow_oop((jobject)$src$$constant, dst); 5624 %} 5625 ins_pipe(ialu_hi_lo_reg); 5626%} 5627 5628instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ 5629 // %%% maybe this should work like loadConD 5630 match(Set dst src); 5631 effect(KILL tmp); 5632 ins_cost(DEFAULT_COST * 4); 5633 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} 5634 ins_encode( LdImmL(src, dst, tmp) ); 5635 ins_pipe(loadConL); 5636%} 5637 5638instruct loadConL0( iRegL dst, immL0 src ) %{ 5639 match(Set dst src); 5640 ins_cost(DEFAULT_COST); 5641 size(4); 5642 format %{ "CLR $dst\t! long" %} 5643 ins_encode( Set13( src, dst ) ); 5644 ins_pipe(ialu_imm); 5645%} 5646 5647instruct loadConL13( iRegL dst, immL13 src ) %{ 5648 match(Set dst src); 5649 ins_cost(DEFAULT_COST * 2); 5650 5651 size(4); 5652 format %{ "MOV $src,$dst\t! long" %} 5653 ins_encode( Set13( src, dst ) ); 5654 ins_pipe(ialu_imm); 5655%} 5656 5657instruct loadConF(regF dst, immF src, o7RegP tmp) %{ 5658 match(Set dst src); 5659 effect(KILL tmp); 5660 5661#ifdef _LP64 5662 size(36); 5663#else 5664 size(8); 5665#endif 5666 5667 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" 5668 "LDF [$tmp+lo(&$src)],$dst" %} 5669 ins_encode( LdImmF(src, dst, tmp) ); 5670 ins_pipe(loadConFD); 5671%} 5672 5673instruct loadConD(regD dst, immD src, o7RegP tmp) %{ 5674 match(Set dst src); 5675 effect(KILL tmp); 5676 5677#ifdef _LP64 5678 size(36); 5679#else 5680 size(8); 5681#endif 5682 5683 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" 5684 "LDDF [$tmp+lo(&$src)],$dst" %} 5685 ins_encode( LdImmD(src, dst, tmp) ); 5686 ins_pipe(loadConFD); 5687%} 5688 5689// Prefetch instructions. 5690// Must be safe to execute with invalid address (cannot fault). 5691 5692instruct prefetchr( memory mem ) %{ 5693 match( PrefetchRead mem ); 5694 ins_cost(MEMORY_REF_COST); 5695 5696 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 5697 opcode(Assembler::prefetch_op3); 5698 ins_encode( form3_mem_prefetch_read( mem ) ); 5699 ins_pipe(iload_mem); 5700%} 5701 5702instruct prefetchw( memory mem ) %{ 5703 match( PrefetchWrite mem ); 5704 ins_cost(MEMORY_REF_COST); 5705 5706 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 5707 opcode(Assembler::prefetch_op3); 5708 ins_encode( form3_mem_prefetch_write( mem ) ); 5709 ins_pipe(iload_mem); 5710%} 5711 5712 5713//----------Store Instructions------------------------------------------------- 5714// Store Byte 5715instruct storeB(memory mem, iRegI src) %{ 5716 match(Set mem (StoreB mem src)); 5717 ins_cost(MEMORY_REF_COST); 5718 5719 size(4); 5720 format %{ "STB $src,$mem\t! byte" %} 5721 opcode(Assembler::stb_op3); 5722 ins_encode( form3_mem_reg( mem, src ) ); 5723 ins_pipe(istore_mem_reg); 5724%} 5725 5726instruct storeB0(memory mem, immI0 src) %{ 5727 match(Set mem (StoreB mem src)); 5728 ins_cost(MEMORY_REF_COST); 5729 5730 size(4); 5731 format %{ "STB $src,$mem\t! byte" %} 5732 opcode(Assembler::stb_op3); 5733 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5734 ins_pipe(istore_mem_zero); 5735%} 5736 5737instruct storeCM0(memory mem, immI0 src) %{ 5738 match(Set mem (StoreCM mem src)); 5739 ins_cost(MEMORY_REF_COST); 5740 5741 size(4); 5742 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 5743 opcode(Assembler::stb_op3); 5744 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5745 ins_pipe(istore_mem_zero); 5746%} 5747 5748// Store Char/Short 5749instruct storeC(memory mem, iRegI src) %{ 5750 match(Set mem (StoreC mem src)); 5751 ins_cost(MEMORY_REF_COST); 5752 5753 size(4); 5754 format %{ "STH $src,$mem\t! short" %} 5755 opcode(Assembler::sth_op3); 5756 ins_encode( form3_mem_reg( mem, src ) ); 5757 ins_pipe(istore_mem_reg); 5758%} 5759 5760instruct storeC0(memory mem, immI0 src) %{ 5761 match(Set mem (StoreC mem src)); 5762 ins_cost(MEMORY_REF_COST); 5763 5764 size(4); 5765 format %{ "STH $src,$mem\t! short" %} 5766 opcode(Assembler::sth_op3); 5767 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5768 ins_pipe(istore_mem_zero); 5769%} 5770 5771// Store Integer 5772instruct storeI(memory mem, iRegI src) %{ 5773 match(Set mem (StoreI mem src)); 5774 ins_cost(MEMORY_REF_COST); 5775 5776 size(4); 5777 format %{ "STW $src,$mem" %} 5778 opcode(Assembler::stw_op3); 5779 ins_encode( form3_mem_reg( mem, src ) ); 5780 ins_pipe(istore_mem_reg); 5781%} 5782 5783// Store Long 5784instruct storeL(memory mem, iRegL src) %{ 5785 match(Set mem (StoreL mem src)); 5786 ins_cost(MEMORY_REF_COST); 5787 size(4); 5788 format %{ "STX $src,$mem\t! long" %} 5789 opcode(Assembler::stx_op3); 5790 ins_encode( form3_mem_reg( mem, src ) ); 5791 ins_pipe(istore_mem_reg); 5792%} 5793 5794instruct storeI0(memory mem, immI0 src) %{ 5795 match(Set mem (StoreI mem src)); 5796 ins_cost(MEMORY_REF_COST); 5797 5798 size(4); 5799 format %{ "STW $src,$mem" %} 5800 opcode(Assembler::stw_op3); 5801 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5802 ins_pipe(istore_mem_zero); 5803%} 5804 5805instruct storeL0(memory mem, immL0 src) %{ 5806 match(Set mem (StoreL mem src)); 5807 ins_cost(MEMORY_REF_COST); 5808 5809 size(4); 5810 format %{ "STX $src,$mem" %} 5811 opcode(Assembler::stx_op3); 5812 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5813 ins_pipe(istore_mem_zero); 5814%} 5815 5816// Store Integer from float register (used after fstoi) 5817instruct storeI_Freg(memory mem, regF src) %{ 5818 match(Set mem (StoreI mem src)); 5819 ins_cost(MEMORY_REF_COST); 5820 5821 size(4); 5822 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 5823 opcode(Assembler::stf_op3); 5824 ins_encode( form3_mem_reg( mem, src ) ); 5825 ins_pipe(fstoreF_mem_reg); 5826%} 5827 5828// Store Pointer 5829instruct storeP(memory dst, sp_ptr_RegP src) %{ 5830 match(Set dst (StoreP dst src)); 5831 ins_cost(MEMORY_REF_COST); 5832 size(4); 5833 5834#ifndef _LP64 5835 format %{ "STW $src,$dst\t! ptr" %} 5836 opcode(Assembler::stw_op3, 0, REGP_OP); 5837#else 5838 format %{ "STX $src,$dst\t! ptr" %} 5839 opcode(Assembler::stx_op3, 0, REGP_OP); 5840#endif 5841 ins_encode( form3_mem_reg( dst, src ) ); 5842 ins_pipe(istore_mem_spORreg); 5843%} 5844 5845instruct storeP0(memory dst, immP0 src) %{ 5846 match(Set dst (StoreP dst src)); 5847 ins_cost(MEMORY_REF_COST); 5848 size(4); 5849 5850#ifndef _LP64 5851 format %{ "STW $src,$dst\t! ptr" %} 5852 opcode(Assembler::stw_op3, 0, REGP_OP); 5853#else 5854 format %{ "STX $src,$dst\t! ptr" %} 5855 opcode(Assembler::stx_op3, 0, REGP_OP); 5856#endif 5857 ins_encode( form3_mem_reg( dst, R_G0 ) ); 5858 ins_pipe(istore_mem_zero); 5859%} 5860 5861// Store Compressed Pointer 5862instruct storeN(memory dst, iRegN src) %{ 5863 match(Set dst (StoreN dst src)); 5864 ins_cost(MEMORY_REF_COST); 5865 size(4); 5866 5867 format %{ "STW $src,$dst\t! compressed ptr" %} 5868 ins_encode %{ 5869 Register base = as_Register($dst$$base); 5870 Register index = as_Register($dst$$index); 5871 Register src = $src$$Register; 5872 if (index != G0) { 5873 __ stw(src, base, index); 5874 } else { 5875 __ stw(src, base, $dst$$disp); 5876 } 5877 %} 5878 ins_pipe(istore_mem_spORreg); 5879%} 5880 5881instruct storeN0(memory dst, immN0 src) %{ 5882 match(Set dst (StoreN dst src)); 5883 ins_cost(MEMORY_REF_COST); 5884 size(4); 5885 5886 format %{ "STW $src,$dst\t! compressed ptr" %} 5887 ins_encode %{ 5888 Register base = as_Register($dst$$base); 5889 Register index = as_Register($dst$$index); 5890 if (index != G0) { 5891 __ stw(0, base, index); 5892 } else { 5893 __ stw(0, base, $dst$$disp); 5894 } 5895 %} 5896 ins_pipe(istore_mem_zero); 5897%} 5898 5899// Store Double 5900instruct storeD( memory mem, regD src) %{ 5901 match(Set mem (StoreD mem src)); 5902 ins_cost(MEMORY_REF_COST); 5903 5904 size(4); 5905 format %{ "STDF $src,$mem" %} 5906 opcode(Assembler::stdf_op3); 5907 ins_encode( form3_mem_reg( mem, src ) ); 5908 ins_pipe(fstoreD_mem_reg); 5909%} 5910 5911instruct storeD0( memory mem, immD0 src) %{ 5912 match(Set mem (StoreD mem src)); 5913 ins_cost(MEMORY_REF_COST); 5914 5915 size(4); 5916 format %{ "STX $src,$mem" %} 5917 opcode(Assembler::stx_op3); 5918 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5919 ins_pipe(fstoreD_mem_zero); 5920%} 5921 5922// Store Float 5923instruct storeF( memory mem, regF src) %{ 5924 match(Set mem (StoreF mem src)); 5925 ins_cost(MEMORY_REF_COST); 5926 5927 size(4); 5928 format %{ "STF $src,$mem" %} 5929 opcode(Assembler::stf_op3); 5930 ins_encode( form3_mem_reg( mem, src ) ); 5931 ins_pipe(fstoreF_mem_reg); 5932%} 5933 5934instruct storeF0( memory mem, immF0 src) %{ 5935 match(Set mem (StoreF mem src)); 5936 ins_cost(MEMORY_REF_COST); 5937 5938 size(4); 5939 format %{ "STW $src,$mem\t! storeF0" %} 5940 opcode(Assembler::stw_op3); 5941 ins_encode( form3_mem_reg( mem, R_G0 ) ); 5942 ins_pipe(fstoreF_mem_zero); 5943%} 5944 5945// Store Aligned Packed Bytes in Double register to memory 5946instruct storeA8B(memory mem, regD src) %{ 5947 match(Set mem (Store8B mem src)); 5948 ins_cost(MEMORY_REF_COST); 5949 size(4); 5950 format %{ "STDF $src,$mem\t! packed8B" %} 5951 opcode(Assembler::stdf_op3); 5952 ins_encode( form3_mem_reg( mem, src ) ); 5953 ins_pipe(fstoreD_mem_reg); 5954%} 5955 5956// Convert oop pointer into compressed form 5957instruct encodeHeapOop(iRegN dst, iRegP src) %{ 5958 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 5959 match(Set dst (EncodeP src)); 5960 format %{ "encode_heap_oop $src, $dst" %} 5961 ins_encode %{ 5962 __ encode_heap_oop($src$$Register, $dst$$Register); 5963 %} 5964 ins_pipe(ialu_reg); 5965%} 5966 5967instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 5968 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 5969 match(Set dst (EncodeP src)); 5970 format %{ "encode_heap_oop_not_null $src, $dst" %} 5971 ins_encode %{ 5972 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 5973 %} 5974 ins_pipe(ialu_reg); 5975%} 5976 5977instruct decodeHeapOop(iRegP dst, iRegN src) %{ 5978 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 5979 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 5980 match(Set dst (DecodeN src)); 5981 format %{ "decode_heap_oop $src, $dst" %} 5982 ins_encode %{ 5983 __ decode_heap_oop($src$$Register, $dst$$Register); 5984 %} 5985 ins_pipe(ialu_reg); 5986%} 5987 5988instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 5989 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 5990 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 5991 match(Set dst (DecodeN src)); 5992 format %{ "decode_heap_oop_not_null $src, $dst" %} 5993 ins_encode %{ 5994 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 5995 %} 5996 ins_pipe(ialu_reg); 5997%} 5998 5999 6000// Store Zero into Aligned Packed Bytes 6001instruct storeA8B0(memory mem, immI0 zero) %{ 6002 match(Set mem (Store8B mem zero)); 6003 ins_cost(MEMORY_REF_COST); 6004 size(4); 6005 format %{ "STX $zero,$mem\t! packed8B" %} 6006 opcode(Assembler::stx_op3); 6007 ins_encode( form3_mem_reg( mem, R_G0 ) ); 6008 ins_pipe(fstoreD_mem_zero); 6009%} 6010 6011// Store Aligned Packed Chars/Shorts in Double register to memory 6012instruct storeA4C(memory mem, regD src) %{ 6013 match(Set mem (Store4C mem src)); 6014 ins_cost(MEMORY_REF_COST); 6015 size(4); 6016 format %{ "STDF $src,$mem\t! packed4C" %} 6017 opcode(Assembler::stdf_op3); 6018 ins_encode( form3_mem_reg( mem, src ) ); 6019 ins_pipe(fstoreD_mem_reg); 6020%} 6021 6022// Store Zero into Aligned Packed Chars/Shorts 6023instruct storeA4C0(memory mem, immI0 zero) %{ 6024 match(Set mem (Store4C mem (Replicate4C zero))); 6025 ins_cost(MEMORY_REF_COST); 6026 size(4); 6027 format %{ "STX $zero,$mem\t! packed4C" %} 6028 opcode(Assembler::stx_op3); 6029 ins_encode( form3_mem_reg( mem, R_G0 ) ); 6030 ins_pipe(fstoreD_mem_zero); 6031%} 6032 6033// Store Aligned Packed Ints in Double register to memory 6034instruct storeA2I(memory mem, regD src) %{ 6035 match(Set mem (Store2I mem src)); 6036 ins_cost(MEMORY_REF_COST); 6037 size(4); 6038 format %{ "STDF $src,$mem\t! packed2I" %} 6039 opcode(Assembler::stdf_op3); 6040 ins_encode( form3_mem_reg( mem, src ) ); 6041 ins_pipe(fstoreD_mem_reg); 6042%} 6043 6044// Store Zero into Aligned Packed Ints 6045instruct storeA2I0(memory mem, immI0 zero) %{ 6046 match(Set mem (Store2I mem zero)); 6047 ins_cost(MEMORY_REF_COST); 6048 size(4); 6049 format %{ "STX $zero,$mem\t! packed2I" %} 6050 opcode(Assembler::stx_op3); 6051 ins_encode( form3_mem_reg( mem, R_G0 ) ); 6052 ins_pipe(fstoreD_mem_zero); 6053%} 6054 6055 6056//----------MemBar Instructions----------------------------------------------- 6057// Memory barrier flavors 6058 6059instruct membar_acquire() %{ 6060 match(MemBarAcquire); 6061 ins_cost(4*MEMORY_REF_COST); 6062 6063 size(0); 6064 format %{ "MEMBAR-acquire" %} 6065 ins_encode( enc_membar_acquire ); 6066 ins_pipe(long_memory_op); 6067%} 6068 6069instruct membar_acquire_lock() %{ 6070 match(MemBarAcquire); 6071 predicate(Matcher::prior_fast_lock(n)); 6072 ins_cost(0); 6073 6074 size(0); 6075 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6076 ins_encode( ); 6077 ins_pipe(empty); 6078%} 6079 6080instruct membar_release() %{ 6081 match(MemBarRelease); 6082 ins_cost(4*MEMORY_REF_COST); 6083 6084 size(0); 6085 format %{ "MEMBAR-release" %} 6086 ins_encode( enc_membar_release ); 6087 ins_pipe(long_memory_op); 6088%} 6089 6090instruct membar_release_lock() %{ 6091 match(MemBarRelease); 6092 predicate(Matcher::post_fast_unlock(n)); 6093 ins_cost(0); 6094 6095 size(0); 6096 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6097 ins_encode( ); 6098 ins_pipe(empty); 6099%} 6100 6101instruct membar_volatile() %{ 6102 match(MemBarVolatile); 6103 ins_cost(4*MEMORY_REF_COST); 6104 6105 size(4); 6106 format %{ "MEMBAR-volatile" %} 6107 ins_encode( enc_membar_volatile ); 6108 ins_pipe(long_memory_op); 6109%} 6110 6111instruct unnecessary_membar_volatile() %{ 6112 match(MemBarVolatile); 6113 predicate(Matcher::post_store_load_barrier(n)); 6114 ins_cost(0); 6115 6116 size(0); 6117 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6118 ins_encode( ); 6119 ins_pipe(empty); 6120%} 6121 6122//----------Register Move Instructions----------------------------------------- 6123instruct roundDouble_nop(regD dst) %{ 6124 match(Set dst (RoundDouble dst)); 6125 ins_cost(0); 6126 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6127 ins_encode( ); 6128 ins_pipe(empty); 6129%} 6130 6131 6132instruct roundFloat_nop(regF dst) %{ 6133 match(Set dst (RoundFloat dst)); 6134 ins_cost(0); 6135 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6136 ins_encode( ); 6137 ins_pipe(empty); 6138%} 6139 6140 6141// Cast Index to Pointer for unsafe natives 6142instruct castX2P(iRegX src, iRegP dst) %{ 6143 match(Set dst (CastX2P src)); 6144 6145 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6146 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6147 ins_pipe(ialu_reg); 6148%} 6149 6150// Cast Pointer to Index for unsafe natives 6151instruct castP2X(iRegP src, iRegX dst) %{ 6152 match(Set dst (CastP2X src)); 6153 6154 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6155 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6156 ins_pipe(ialu_reg); 6157%} 6158 6159instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6160 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6161 match(Set stkSlot src); // chain rule 6162 ins_cost(MEMORY_REF_COST); 6163 format %{ "STDF $src,$stkSlot\t!stk" %} 6164 opcode(Assembler::stdf_op3); 6165 ins_encode(form3_mem_reg(stkSlot, src)); 6166 ins_pipe(fstoreD_stk_reg); 6167%} 6168 6169instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6170 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6171 match(Set dst stkSlot); // chain rule 6172 ins_cost(MEMORY_REF_COST); 6173 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6174 opcode(Assembler::lddf_op3); 6175 ins_encode(form3_mem_reg(stkSlot, dst)); 6176 ins_pipe(floadD_stk); 6177%} 6178 6179instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6180 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6181 match(Set stkSlot src); // chain rule 6182 ins_cost(MEMORY_REF_COST); 6183 format %{ "STF $src,$stkSlot\t!stk" %} 6184 opcode(Assembler::stf_op3); 6185 ins_encode(form3_mem_reg(stkSlot, src)); 6186 ins_pipe(fstoreF_stk_reg); 6187%} 6188 6189//----------Conditional Move--------------------------------------------------- 6190// Conditional move 6191instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6192 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6193 ins_cost(150); 6194 format %{ "MOV$cmp $pcc,$src,$dst" %} 6195 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6196 ins_pipe(ialu_reg); 6197%} 6198 6199instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6200 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6201 ins_cost(140); 6202 format %{ "MOV$cmp $pcc,$src,$dst" %} 6203 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6204 ins_pipe(ialu_imm); 6205%} 6206 6207instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6208 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6209 ins_cost(150); 6210 size(4); 6211 format %{ "MOV$cmp $icc,$src,$dst" %} 6212 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6213 ins_pipe(ialu_reg); 6214%} 6215 6216instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6217 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6218 ins_cost(140); 6219 size(4); 6220 format %{ "MOV$cmp $icc,$src,$dst" %} 6221 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6222 ins_pipe(ialu_imm); 6223%} 6224 6225instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6226 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6227 ins_cost(150); 6228 size(4); 6229 format %{ "MOV$cmp $icc,$src,$dst" %} 6230 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6231 ins_pipe(ialu_reg); 6232%} 6233 6234instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6235 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6236 ins_cost(140); 6237 size(4); 6238 format %{ "MOV$cmp $icc,$src,$dst" %} 6239 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6240 ins_pipe(ialu_imm); 6241%} 6242 6243instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6244 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6245 ins_cost(150); 6246 size(4); 6247 format %{ "MOV$cmp $fcc,$src,$dst" %} 6248 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6249 ins_pipe(ialu_reg); 6250%} 6251 6252instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6253 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6254 ins_cost(140); 6255 size(4); 6256 format %{ "MOV$cmp $fcc,$src,$dst" %} 6257 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6258 ins_pipe(ialu_imm); 6259%} 6260 6261// Conditional move for RegN. Only cmov(reg,reg). 6262instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6263 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6264 ins_cost(150); 6265 format %{ "MOV$cmp $pcc,$src,$dst" %} 6266 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6267 ins_pipe(ialu_reg); 6268%} 6269 6270// This instruction also works with CmpN so we don't need cmovNN_reg. 6271instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6272 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6273 ins_cost(150); 6274 size(4); 6275 format %{ "MOV$cmp $icc,$src,$dst" %} 6276 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6277 ins_pipe(ialu_reg); 6278%} 6279 6280instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6281 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6282 ins_cost(150); 6283 size(4); 6284 format %{ "MOV$cmp $fcc,$src,$dst" %} 6285 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6286 ins_pipe(ialu_reg); 6287%} 6288 6289// Conditional move 6290instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6291 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6292 ins_cost(150); 6293 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6294 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6295 ins_pipe(ialu_reg); 6296%} 6297 6298instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6299 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6300 ins_cost(140); 6301 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6302 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6303 ins_pipe(ialu_imm); 6304%} 6305 6306// This instruction also works with CmpN so we don't need cmovPN_reg. 6307instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6308 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6309 ins_cost(150); 6310 6311 size(4); 6312 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6313 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6314 ins_pipe(ialu_reg); 6315%} 6316 6317instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6318 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6319 ins_cost(140); 6320 6321 size(4); 6322 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6323 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6324 ins_pipe(ialu_imm); 6325%} 6326 6327instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6328 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6329 ins_cost(150); 6330 size(4); 6331 format %{ "MOV$cmp $fcc,$src,$dst" %} 6332 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6333 ins_pipe(ialu_imm); 6334%} 6335 6336instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6337 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6338 ins_cost(140); 6339 size(4); 6340 format %{ "MOV$cmp $fcc,$src,$dst" %} 6341 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6342 ins_pipe(ialu_imm); 6343%} 6344 6345// Conditional move 6346instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6347 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6348 ins_cost(150); 6349 opcode(0x101); 6350 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6351 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6352 ins_pipe(int_conditional_float_move); 6353%} 6354 6355instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6356 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6357 ins_cost(150); 6358 6359 size(4); 6360 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6361 opcode(0x101); 6362 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6363 ins_pipe(int_conditional_float_move); 6364%} 6365 6366// Conditional move, 6367instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6368 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6369 ins_cost(150); 6370 size(4); 6371 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6372 opcode(0x1); 6373 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6374 ins_pipe(int_conditional_double_move); 6375%} 6376 6377// Conditional move 6378instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6379 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6380 ins_cost(150); 6381 size(4); 6382 opcode(0x102); 6383 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6384 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6385 ins_pipe(int_conditional_double_move); 6386%} 6387 6388instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6389 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6390 ins_cost(150); 6391 6392 size(4); 6393 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6394 opcode(0x102); 6395 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6396 ins_pipe(int_conditional_double_move); 6397%} 6398 6399// Conditional move, 6400instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6401 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6402 ins_cost(150); 6403 size(4); 6404 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6405 opcode(0x2); 6406 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6407 ins_pipe(int_conditional_double_move); 6408%} 6409 6410// Conditional move 6411instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6412 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6413 ins_cost(150); 6414 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6415 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6416 ins_pipe(ialu_reg); 6417%} 6418 6419instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6420 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6421 ins_cost(140); 6422 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6423 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6424 ins_pipe(ialu_imm); 6425%} 6426 6427instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6428 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6429 ins_cost(150); 6430 6431 size(4); 6432 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6433 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6434 ins_pipe(ialu_reg); 6435%} 6436 6437 6438instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6439 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6440 ins_cost(150); 6441 6442 size(4); 6443 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6444 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6445 ins_pipe(ialu_reg); 6446%} 6447 6448 6449 6450//----------OS and Locking Instructions---------------------------------------- 6451 6452// This name is KNOWN by the ADLC and cannot be changed. 6453// The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6454// for this guy. 6455instruct tlsLoadP(g2RegP dst) %{ 6456 match(Set dst (ThreadLocal)); 6457 6458 size(0); 6459 ins_cost(0); 6460 format %{ "# TLS is in G2" %} 6461 ins_encode( /*empty encoding*/ ); 6462 ins_pipe(ialu_none); 6463%} 6464 6465instruct checkCastPP( iRegP dst ) %{ 6466 match(Set dst (CheckCastPP dst)); 6467 6468 size(0); 6469 format %{ "# checkcastPP of $dst" %} 6470 ins_encode( /*empty encoding*/ ); 6471 ins_pipe(empty); 6472%} 6473 6474 6475instruct castPP( iRegP dst ) %{ 6476 match(Set dst (CastPP dst)); 6477 format %{ "# castPP of $dst" %} 6478 ins_encode( /*empty encoding*/ ); 6479 ins_pipe(empty); 6480%} 6481 6482instruct castII( iRegI dst ) %{ 6483 match(Set dst (CastII dst)); 6484 format %{ "# castII of $dst" %} 6485 ins_encode( /*empty encoding*/ ); 6486 ins_cost(0); 6487 ins_pipe(empty); 6488%} 6489 6490//----------Arithmetic Instructions-------------------------------------------- 6491// Addition Instructions 6492// Register Addition 6493instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6494 match(Set dst (AddI src1 src2)); 6495 6496 size(4); 6497 format %{ "ADD $src1,$src2,$dst" %} 6498 ins_encode %{ 6499 __ add($src1$$Register, $src2$$Register, $dst$$Register); 6500 %} 6501 ins_pipe(ialu_reg_reg); 6502%} 6503 6504// Immediate Addition 6505instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6506 match(Set dst (AddI src1 src2)); 6507 6508 size(4); 6509 format %{ "ADD $src1,$src2,$dst" %} 6510 opcode(Assembler::add_op3, Assembler::arith_op); 6511 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6512 ins_pipe(ialu_reg_imm); 6513%} 6514 6515// Pointer Register Addition 6516instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 6517 match(Set dst (AddP src1 src2)); 6518 6519 size(4); 6520 format %{ "ADD $src1,$src2,$dst" %} 6521 opcode(Assembler::add_op3, Assembler::arith_op); 6522 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6523 ins_pipe(ialu_reg_reg); 6524%} 6525 6526// Pointer Immediate Addition 6527instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 6528 match(Set dst (AddP src1 src2)); 6529 6530 size(4); 6531 format %{ "ADD $src1,$src2,$dst" %} 6532 opcode(Assembler::add_op3, Assembler::arith_op); 6533 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6534 ins_pipe(ialu_reg_imm); 6535%} 6536 6537// Long Addition 6538instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6539 match(Set dst (AddL src1 src2)); 6540 6541 size(4); 6542 format %{ "ADD $src1,$src2,$dst\t! long" %} 6543 opcode(Assembler::add_op3, Assembler::arith_op); 6544 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6545 ins_pipe(ialu_reg_reg); 6546%} 6547 6548instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6549 match(Set dst (AddL src1 con)); 6550 6551 size(4); 6552 format %{ "ADD $src1,$con,$dst" %} 6553 opcode(Assembler::add_op3, Assembler::arith_op); 6554 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6555 ins_pipe(ialu_reg_imm); 6556%} 6557 6558//----------Conditional_store-------------------------------------------------- 6559// Conditional-store of the updated heap-top. 6560// Used during allocation of the shared heap. 6561// Sets flags (EQ) on success. Implemented with a CASA on Sparc. 6562 6563// LoadP-locked. Same as a regular pointer load when used with a compare-swap 6564instruct loadPLocked(iRegP dst, memory mem) %{ 6565 match(Set dst (LoadPLocked mem)); 6566 ins_cost(MEMORY_REF_COST); 6567 6568#ifndef _LP64 6569 size(4); 6570 format %{ "LDUW $mem,$dst\t! ptr" %} 6571 opcode(Assembler::lduw_op3, 0, REGP_OP); 6572#else 6573 format %{ "LDX $mem,$dst\t! ptr" %} 6574 opcode(Assembler::ldx_op3, 0, REGP_OP); 6575#endif 6576 ins_encode( form3_mem_reg( mem, dst ) ); 6577 ins_pipe(iload_mem); 6578%} 6579 6580// LoadL-locked. Same as a regular long load when used with a compare-swap 6581instruct loadLLocked(iRegL dst, memory mem) %{ 6582 match(Set dst (LoadLLocked mem)); 6583 ins_cost(MEMORY_REF_COST); 6584 size(4); 6585 format %{ "LDX $mem,$dst\t! long" %} 6586 opcode(Assembler::ldx_op3); 6587 ins_encode( form3_mem_reg( mem, dst ) ); 6588 ins_pipe(iload_mem); 6589%} 6590 6591instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 6592 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 6593 effect( KILL newval ); 6594 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 6595 "CMP R_G3,$oldval\t\t! See if we made progress" %} 6596 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 6597 ins_pipe( long_memory_op ); 6598%} 6599 6600instruct storeLConditional_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6601 match(Set res (StoreLConditional mem_ptr (Binary oldval newval))); 6602 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6603 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap 6604 format %{ 6605 "MOV $newval,R_O7\n\t" 6606 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t" 6607 "CMP $oldval,R_O7\t\t! See if we made progress\n\t" 6608 "MOV 1,$res\n\t" 6609 "MOVne xcc,R_G0,$res" 6610 %} 6611 ins_encode( enc_casx(mem_ptr, oldval, newval), 6612 enc_lflags_ne_to_boolean(res) ); 6613 ins_pipe( long_memory_op ); 6614%} 6615 6616instruct storeLConditional_flags(iRegP mem_ptr, iRegL oldval, iRegL newval, flagsRegL xcc, o7RegI tmp1, immI0 zero) %{ 6617 match(Set xcc (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero)); 6618 effect( USE mem_ptr, KILL tmp1); 6619 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap 6620 format %{ 6621 "MOV $newval,R_O7\n\t" 6622 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t" 6623 "CMP $oldval,R_O7\t\t! See if we made progress" 6624 %} 6625 ins_encode( enc_casx(mem_ptr, oldval, newval)); 6626 ins_pipe( long_memory_op ); 6627%} 6628 6629// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 6630 6631instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6632 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 6633 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6634 format %{ 6635 "MOV $newval,O7\n\t" 6636 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6637 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6638 "MOV 1,$res\n\t" 6639 "MOVne xcc,R_G0,$res" 6640 %} 6641 ins_encode( enc_casx(mem_ptr, oldval, newval), 6642 enc_lflags_ne_to_boolean(res) ); 6643 ins_pipe( long_memory_op ); 6644%} 6645 6646 6647instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6648 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 6649 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6650 format %{ 6651 "MOV $newval,O7\n\t" 6652 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6653 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6654 "MOV 1,$res\n\t" 6655 "MOVne icc,R_G0,$res" 6656 %} 6657 ins_encode( enc_casi(mem_ptr, oldval, newval), 6658 enc_iflags_ne_to_boolean(res) ); 6659 ins_pipe( long_memory_op ); 6660%} 6661 6662instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6663 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 6664 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6665 format %{ 6666 "MOV $newval,O7\n\t" 6667 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6668 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6669 "MOV 1,$res\n\t" 6670 "MOVne xcc,R_G0,$res" 6671 %} 6672#ifdef _LP64 6673 ins_encode( enc_casx(mem_ptr, oldval, newval), 6674 enc_lflags_ne_to_boolean(res) ); 6675#else 6676 ins_encode( enc_casi(mem_ptr, oldval, newval), 6677 enc_iflags_ne_to_boolean(res) ); 6678#endif 6679 ins_pipe( long_memory_op ); 6680%} 6681 6682instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6683 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 6684 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6685 format %{ 6686 "MOV $newval,O7\n\t" 6687 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6688 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6689 "MOV 1,$res\n\t" 6690 "MOVne icc,R_G0,$res" 6691 %} 6692 ins_encode( enc_casi(mem_ptr, oldval, newval), 6693 enc_iflags_ne_to_boolean(res) ); 6694 ins_pipe( long_memory_op ); 6695%} 6696 6697//--------------------- 6698// Subtraction Instructions 6699// Register Subtraction 6700instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6701 match(Set dst (SubI src1 src2)); 6702 6703 size(4); 6704 format %{ "SUB $src1,$src2,$dst" %} 6705 opcode(Assembler::sub_op3, Assembler::arith_op); 6706 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6707 ins_pipe(ialu_reg_reg); 6708%} 6709 6710// Immediate Subtraction 6711instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6712 match(Set dst (SubI src1 src2)); 6713 6714 size(4); 6715 format %{ "SUB $src1,$src2,$dst" %} 6716 opcode(Assembler::sub_op3, Assembler::arith_op); 6717 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6718 ins_pipe(ialu_reg_imm); 6719%} 6720 6721instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 6722 match(Set dst (SubI zero src2)); 6723 6724 size(4); 6725 format %{ "NEG $src2,$dst" %} 6726 opcode(Assembler::sub_op3, Assembler::arith_op); 6727 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6728 ins_pipe(ialu_zero_reg); 6729%} 6730 6731// Long subtraction 6732instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6733 match(Set dst (SubL src1 src2)); 6734 6735 size(4); 6736 format %{ "SUB $src1,$src2,$dst\t! long" %} 6737 opcode(Assembler::sub_op3, Assembler::arith_op); 6738 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6739 ins_pipe(ialu_reg_reg); 6740%} 6741 6742// Immediate Subtraction 6743instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6744 match(Set dst (SubL src1 con)); 6745 6746 size(4); 6747 format %{ "SUB $src1,$con,$dst\t! long" %} 6748 opcode(Assembler::sub_op3, Assembler::arith_op); 6749 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6750 ins_pipe(ialu_reg_imm); 6751%} 6752 6753// Long negation 6754instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 6755 match(Set dst (SubL zero src2)); 6756 6757 size(4); 6758 format %{ "NEG $src2,$dst\t! long" %} 6759 opcode(Assembler::sub_op3, Assembler::arith_op); 6760 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6761 ins_pipe(ialu_zero_reg); 6762%} 6763 6764// Multiplication Instructions 6765// Integer Multiplication 6766// Register Multiplication 6767instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6768 match(Set dst (MulI src1 src2)); 6769 6770 size(4); 6771 format %{ "MULX $src1,$src2,$dst" %} 6772 opcode(Assembler::mulx_op3, Assembler::arith_op); 6773 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6774 ins_pipe(imul_reg_reg); 6775%} 6776 6777// Immediate Multiplication 6778instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6779 match(Set dst (MulI src1 src2)); 6780 6781 size(4); 6782 format %{ "MULX $src1,$src2,$dst" %} 6783 opcode(Assembler::mulx_op3, Assembler::arith_op); 6784 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6785 ins_pipe(imul_reg_imm); 6786%} 6787 6788instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6789 match(Set dst (MulL src1 src2)); 6790 ins_cost(DEFAULT_COST * 5); 6791 size(4); 6792 format %{ "MULX $src1,$src2,$dst\t! long" %} 6793 opcode(Assembler::mulx_op3, Assembler::arith_op); 6794 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6795 ins_pipe(mulL_reg_reg); 6796%} 6797 6798// Immediate Multiplication 6799instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 6800 match(Set dst (MulL src1 src2)); 6801 ins_cost(DEFAULT_COST * 5); 6802 size(4); 6803 format %{ "MULX $src1,$src2,$dst" %} 6804 opcode(Assembler::mulx_op3, Assembler::arith_op); 6805 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6806 ins_pipe(mulL_reg_imm); 6807%} 6808 6809// Integer Division 6810// Register Division 6811instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 6812 match(Set dst (DivI src1 src2)); 6813 ins_cost((2+71)*DEFAULT_COST); 6814 6815 format %{ "SRA $src2,0,$src2\n\t" 6816 "SRA $src1,0,$src1\n\t" 6817 "SDIVX $src1,$src2,$dst" %} 6818 ins_encode( idiv_reg( src1, src2, dst ) ); 6819 ins_pipe(sdiv_reg_reg); 6820%} 6821 6822// Immediate Division 6823instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 6824 match(Set dst (DivI src1 src2)); 6825 ins_cost((2+71)*DEFAULT_COST); 6826 6827 format %{ "SRA $src1,0,$src1\n\t" 6828 "SDIVX $src1,$src2,$dst" %} 6829 ins_encode( idiv_imm( src1, src2, dst ) ); 6830 ins_pipe(sdiv_reg_imm); 6831%} 6832 6833//----------Div-By-10-Expansion------------------------------------------------ 6834// Extract hi bits of a 32x32->64 bit multiply. 6835// Expand rule only, not matched 6836instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 6837 effect( DEF dst, USE src1, USE src2 ); 6838 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 6839 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 6840 ins_encode( enc_mul_hi(dst,src1,src2)); 6841 ins_pipe(sdiv_reg_reg); 6842%} 6843 6844// Magic constant, reciprical of 10 6845instruct loadConI_x66666667(iRegIsafe dst) %{ 6846 effect( DEF dst ); 6847 6848 size(8); 6849 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 6850 ins_encode( Set32(0x66666667, dst) ); 6851 ins_pipe(ialu_hi_lo_reg); 6852%} 6853 6854// Register Shift Right Arithmatic Long by 32-63 6855instruct sra_31( iRegI dst, iRegI src ) %{ 6856 effect( DEF dst, USE src ); 6857 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 6858 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 6859 ins_pipe(ialu_reg_reg); 6860%} 6861 6862// Arithmetic Shift Right by 8-bit immediate 6863instruct sra_reg_2( iRegI dst, iRegI src ) %{ 6864 effect( DEF dst, USE src ); 6865 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 6866 opcode(Assembler::sra_op3, Assembler::arith_op); 6867 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 6868 ins_pipe(ialu_reg_imm); 6869%} 6870 6871// Integer DIV with 10 6872instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 6873 match(Set dst (DivI src div)); 6874 ins_cost((6+6)*DEFAULT_COST); 6875 expand %{ 6876 iRegIsafe tmp1; // Killed temps; 6877 iRegIsafe tmp2; // Killed temps; 6878 iRegI tmp3; // Killed temps; 6879 iRegI tmp4; // Killed temps; 6880 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 6881 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 6882 sra_31( tmp3, src ); // SRA src,31 -> tmp3 6883 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 6884 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 6885 %} 6886%} 6887 6888// Register Long Division 6889instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6890 match(Set dst (DivL src1 src2)); 6891 ins_cost(DEFAULT_COST*71); 6892 size(4); 6893 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 6894 opcode(Assembler::sdivx_op3, Assembler::arith_op); 6895 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6896 ins_pipe(divL_reg_reg); 6897%} 6898 6899// Register Long Division 6900instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 6901 match(Set dst (DivL src1 src2)); 6902 ins_cost(DEFAULT_COST*71); 6903 size(4); 6904 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 6905 opcode(Assembler::sdivx_op3, Assembler::arith_op); 6906 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6907 ins_pipe(divL_reg_imm); 6908%} 6909 6910// Integer Remainder 6911// Register Remainder 6912instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 6913 match(Set dst (ModI src1 src2)); 6914 effect( KILL ccr, KILL temp); 6915 6916 format %{ "SREM $src1,$src2,$dst" %} 6917 ins_encode( irem_reg(src1, src2, dst, temp) ); 6918 ins_pipe(sdiv_reg_reg); 6919%} 6920 6921// Immediate Remainder 6922instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 6923 match(Set dst (ModI src1 src2)); 6924 effect( KILL ccr, KILL temp); 6925 6926 format %{ "SREM $src1,$src2,$dst" %} 6927 ins_encode( irem_imm(src1, src2, dst, temp) ); 6928 ins_pipe(sdiv_reg_imm); 6929%} 6930 6931// Register Long Remainder 6932instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 6933 effect(DEF dst, USE src1, USE src2); 6934 size(4); 6935 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 6936 opcode(Assembler::sdivx_op3, Assembler::arith_op); 6937 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6938 ins_pipe(divL_reg_reg); 6939%} 6940 6941// Register Long Division 6942instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 6943 effect(DEF dst, USE src1, USE src2); 6944 size(4); 6945 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 6946 opcode(Assembler::sdivx_op3, Assembler::arith_op); 6947 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6948 ins_pipe(divL_reg_imm); 6949%} 6950 6951instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 6952 effect(DEF dst, USE src1, USE src2); 6953 size(4); 6954 format %{ "MULX $src1,$src2,$dst\t! long" %} 6955 opcode(Assembler::mulx_op3, Assembler::arith_op); 6956 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6957 ins_pipe(mulL_reg_reg); 6958%} 6959 6960// Immediate Multiplication 6961instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 6962 effect(DEF dst, USE src1, USE src2); 6963 size(4); 6964 format %{ "MULX $src1,$src2,$dst" %} 6965 opcode(Assembler::mulx_op3, Assembler::arith_op); 6966 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6967 ins_pipe(mulL_reg_imm); 6968%} 6969 6970instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 6971 effect(DEF dst, USE src1, USE src2); 6972 size(4); 6973 format %{ "SUB $src1,$src2,$dst\t! long" %} 6974 opcode(Assembler::sub_op3, Assembler::arith_op); 6975 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6976 ins_pipe(ialu_reg_reg); 6977%} 6978 6979instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 6980 effect(DEF dst, USE src1, USE src2); 6981 size(4); 6982 format %{ "SUB $src1,$src2,$dst\t! long" %} 6983 opcode(Assembler::sub_op3, Assembler::arith_op); 6984 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6985 ins_pipe(ialu_reg_reg); 6986%} 6987 6988// Register Long Remainder 6989instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6990 match(Set dst (ModL src1 src2)); 6991 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 6992 expand %{ 6993 iRegL tmp1; 6994 iRegL tmp2; 6995 divL_reg_reg_1(tmp1, src1, src2); 6996 mulL_reg_reg_1(tmp2, tmp1, src2); 6997 subL_reg_reg_1(dst, src1, tmp2); 6998 %} 6999%} 7000 7001// Register Long Remainder 7002instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7003 match(Set dst (ModL src1 src2)); 7004 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7005 expand %{ 7006 iRegL tmp1; 7007 iRegL tmp2; 7008 divL_reg_imm13_1(tmp1, src1, src2); 7009 mulL_reg_imm13_1(tmp2, tmp1, src2); 7010 subL_reg_reg_2 (dst, src1, tmp2); 7011 %} 7012%} 7013 7014// Integer Shift Instructions 7015// Register Shift Left 7016instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7017 match(Set dst (LShiftI src1 src2)); 7018 7019 size(4); 7020 format %{ "SLL $src1,$src2,$dst" %} 7021 opcode(Assembler::sll_op3, Assembler::arith_op); 7022 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7023 ins_pipe(ialu_reg_reg); 7024%} 7025 7026// Register Shift Left Immediate 7027instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7028 match(Set dst (LShiftI src1 src2)); 7029 7030 size(4); 7031 format %{ "SLL $src1,$src2,$dst" %} 7032 opcode(Assembler::sll_op3, Assembler::arith_op); 7033 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7034 ins_pipe(ialu_reg_imm); 7035%} 7036 7037// Register Shift Left 7038instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7039 match(Set dst (LShiftL src1 src2)); 7040 7041 size(4); 7042 format %{ "SLLX $src1,$src2,$dst" %} 7043 opcode(Assembler::sllx_op3, Assembler::arith_op); 7044 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7045 ins_pipe(ialu_reg_reg); 7046%} 7047 7048// Register Shift Left Immediate 7049instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7050 match(Set dst (LShiftL src1 src2)); 7051 7052 size(4); 7053 format %{ "SLLX $src1,$src2,$dst" %} 7054 opcode(Assembler::sllx_op3, Assembler::arith_op); 7055 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7056 ins_pipe(ialu_reg_imm); 7057%} 7058 7059// Register Arithmetic Shift Right 7060instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7061 match(Set dst (RShiftI src1 src2)); 7062 size(4); 7063 format %{ "SRA $src1,$src2,$dst" %} 7064 opcode(Assembler::sra_op3, Assembler::arith_op); 7065 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7066 ins_pipe(ialu_reg_reg); 7067%} 7068 7069// Register Arithmetic Shift Right Immediate 7070instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7071 match(Set dst (RShiftI src1 src2)); 7072 7073 size(4); 7074 format %{ "SRA $src1,$src2,$dst" %} 7075 opcode(Assembler::sra_op3, Assembler::arith_op); 7076 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7077 ins_pipe(ialu_reg_imm); 7078%} 7079 7080// Register Shift Right Arithmatic Long 7081instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7082 match(Set dst (RShiftL src1 src2)); 7083 7084 size(4); 7085 format %{ "SRAX $src1,$src2,$dst" %} 7086 opcode(Assembler::srax_op3, Assembler::arith_op); 7087 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7088 ins_pipe(ialu_reg_reg); 7089%} 7090 7091// Register Shift Left Immediate 7092instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7093 match(Set dst (RShiftL src1 src2)); 7094 7095 size(4); 7096 format %{ "SRAX $src1,$src2,$dst" %} 7097 opcode(Assembler::srax_op3, Assembler::arith_op); 7098 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7099 ins_pipe(ialu_reg_imm); 7100%} 7101 7102// Register Shift Right 7103instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7104 match(Set dst (URShiftI src1 src2)); 7105 7106 size(4); 7107 format %{ "SRL $src1,$src2,$dst" %} 7108 opcode(Assembler::srl_op3, Assembler::arith_op); 7109 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7110 ins_pipe(ialu_reg_reg); 7111%} 7112 7113// Register Shift Right Immediate 7114instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7115 match(Set dst (URShiftI src1 src2)); 7116 7117 size(4); 7118 format %{ "SRL $src1,$src2,$dst" %} 7119 opcode(Assembler::srl_op3, Assembler::arith_op); 7120 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7121 ins_pipe(ialu_reg_imm); 7122%} 7123 7124// Register Shift Right 7125instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7126 match(Set dst (URShiftL src1 src2)); 7127 7128 size(4); 7129 format %{ "SRLX $src1,$src2,$dst" %} 7130 opcode(Assembler::srlx_op3, Assembler::arith_op); 7131 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7132 ins_pipe(ialu_reg_reg); 7133%} 7134 7135// Register Shift Right Immediate 7136instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7137 match(Set dst (URShiftL src1 src2)); 7138 7139 size(4); 7140 format %{ "SRLX $src1,$src2,$dst" %} 7141 opcode(Assembler::srlx_op3, Assembler::arith_op); 7142 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7143 ins_pipe(ialu_reg_imm); 7144%} 7145 7146// Register Shift Right Immediate with a CastP2X 7147#ifdef _LP64 7148instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7149 match(Set dst (URShiftL (CastP2X src1) src2)); 7150 size(4); 7151 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7152 opcode(Assembler::srlx_op3, Assembler::arith_op); 7153 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7154 ins_pipe(ialu_reg_imm); 7155%} 7156#else 7157instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7158 match(Set dst (URShiftI (CastP2X src1) src2)); 7159 size(4); 7160 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7161 opcode(Assembler::srl_op3, Assembler::arith_op); 7162 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7163 ins_pipe(ialu_reg_imm); 7164%} 7165#endif 7166 7167 7168//----------Floating Point Arithmetic Instructions----------------------------- 7169 7170// Add float single precision 7171instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7172 match(Set dst (AddF src1 src2)); 7173 7174 size(4); 7175 format %{ "FADDS $src1,$src2,$dst" %} 7176 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7177 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7178 ins_pipe(faddF_reg_reg); 7179%} 7180 7181// Add float double precision 7182instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7183 match(Set dst (AddD src1 src2)); 7184 7185 size(4); 7186 format %{ "FADDD $src1,$src2,$dst" %} 7187 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7188 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7189 ins_pipe(faddD_reg_reg); 7190%} 7191 7192// Sub float single precision 7193instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7194 match(Set dst (SubF src1 src2)); 7195 7196 size(4); 7197 format %{ "FSUBS $src1,$src2,$dst" %} 7198 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7199 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7200 ins_pipe(faddF_reg_reg); 7201%} 7202 7203// Sub float double precision 7204instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7205 match(Set dst (SubD src1 src2)); 7206 7207 size(4); 7208 format %{ "FSUBD $src1,$src2,$dst" %} 7209 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7210 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7211 ins_pipe(faddD_reg_reg); 7212%} 7213 7214// Mul float single precision 7215instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7216 match(Set dst (MulF src1 src2)); 7217 7218 size(4); 7219 format %{ "FMULS $src1,$src2,$dst" %} 7220 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7221 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7222 ins_pipe(fmulF_reg_reg); 7223%} 7224 7225// Mul float double precision 7226instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7227 match(Set dst (MulD src1 src2)); 7228 7229 size(4); 7230 format %{ "FMULD $src1,$src2,$dst" %} 7231 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7232 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7233 ins_pipe(fmulD_reg_reg); 7234%} 7235 7236// Div float single precision 7237instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7238 match(Set dst (DivF src1 src2)); 7239 7240 size(4); 7241 format %{ "FDIVS $src1,$src2,$dst" %} 7242 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7243 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7244 ins_pipe(fdivF_reg_reg); 7245%} 7246 7247// Div float double precision 7248instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7249 match(Set dst (DivD src1 src2)); 7250 7251 size(4); 7252 format %{ "FDIVD $src1,$src2,$dst" %} 7253 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7254 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7255 ins_pipe(fdivD_reg_reg); 7256%} 7257 7258// Absolute float double precision 7259instruct absD_reg(regD dst, regD src) %{ 7260 match(Set dst (AbsD src)); 7261 7262 format %{ "FABSd $src,$dst" %} 7263 ins_encode(fabsd(dst, src)); 7264 ins_pipe(faddD_reg); 7265%} 7266 7267// Absolute float single precision 7268instruct absF_reg(regF dst, regF src) %{ 7269 match(Set dst (AbsF src)); 7270 7271 format %{ "FABSs $src,$dst" %} 7272 ins_encode(fabss(dst, src)); 7273 ins_pipe(faddF_reg); 7274%} 7275 7276instruct negF_reg(regF dst, regF src) %{ 7277 match(Set dst (NegF src)); 7278 7279 size(4); 7280 format %{ "FNEGs $src,$dst" %} 7281 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7282 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7283 ins_pipe(faddF_reg); 7284%} 7285 7286instruct negD_reg(regD dst, regD src) %{ 7287 match(Set dst (NegD src)); 7288 7289 format %{ "FNEGd $src,$dst" %} 7290 ins_encode(fnegd(dst, src)); 7291 ins_pipe(faddD_reg); 7292%} 7293 7294// Sqrt float double precision 7295instruct sqrtF_reg_reg(regF dst, regF src) %{ 7296 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7297 7298 size(4); 7299 format %{ "FSQRTS $src,$dst" %} 7300 ins_encode(fsqrts(dst, src)); 7301 ins_pipe(fdivF_reg_reg); 7302%} 7303 7304// Sqrt float double precision 7305instruct sqrtD_reg_reg(regD dst, regD src) %{ 7306 match(Set dst (SqrtD src)); 7307 7308 size(4); 7309 format %{ "FSQRTD $src,$dst" %} 7310 ins_encode(fsqrtd(dst, src)); 7311 ins_pipe(fdivD_reg_reg); 7312%} 7313 7314//----------Logical Instructions----------------------------------------------- 7315// And Instructions 7316// Register And 7317instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7318 match(Set dst (AndI src1 src2)); 7319 7320 size(4); 7321 format %{ "AND $src1,$src2,$dst" %} 7322 opcode(Assembler::and_op3, Assembler::arith_op); 7323 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7324 ins_pipe(ialu_reg_reg); 7325%} 7326 7327// Immediate And 7328instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7329 match(Set dst (AndI src1 src2)); 7330 7331 size(4); 7332 format %{ "AND $src1,$src2,$dst" %} 7333 opcode(Assembler::and_op3, Assembler::arith_op); 7334 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7335 ins_pipe(ialu_reg_imm); 7336%} 7337 7338// Register And Long 7339instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7340 match(Set dst (AndL src1 src2)); 7341 7342 ins_cost(DEFAULT_COST); 7343 size(4); 7344 format %{ "AND $src1,$src2,$dst\t! long" %} 7345 opcode(Assembler::and_op3, Assembler::arith_op); 7346 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7347 ins_pipe(ialu_reg_reg); 7348%} 7349 7350instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7351 match(Set dst (AndL src1 con)); 7352 7353 ins_cost(DEFAULT_COST); 7354 size(4); 7355 format %{ "AND $src1,$con,$dst\t! long" %} 7356 opcode(Assembler::and_op3, Assembler::arith_op); 7357 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7358 ins_pipe(ialu_reg_imm); 7359%} 7360 7361// Or Instructions 7362// Register Or 7363instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7364 match(Set dst (OrI src1 src2)); 7365 7366 size(4); 7367 format %{ "OR $src1,$src2,$dst" %} 7368 opcode(Assembler::or_op3, Assembler::arith_op); 7369 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7370 ins_pipe(ialu_reg_reg); 7371%} 7372 7373// Immediate Or 7374instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7375 match(Set dst (OrI src1 src2)); 7376 7377 size(4); 7378 format %{ "OR $src1,$src2,$dst" %} 7379 opcode(Assembler::or_op3, Assembler::arith_op); 7380 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7381 ins_pipe(ialu_reg_imm); 7382%} 7383 7384// Register Or Long 7385instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7386 match(Set dst (OrL src1 src2)); 7387 7388 ins_cost(DEFAULT_COST); 7389 size(4); 7390 format %{ "OR $src1,$src2,$dst\t! long" %} 7391 opcode(Assembler::or_op3, Assembler::arith_op); 7392 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7393 ins_pipe(ialu_reg_reg); 7394%} 7395 7396instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7397 match(Set dst (OrL src1 con)); 7398 ins_cost(DEFAULT_COST*2); 7399 7400 ins_cost(DEFAULT_COST); 7401 size(4); 7402 format %{ "OR $src1,$con,$dst\t! long" %} 7403 opcode(Assembler::or_op3, Assembler::arith_op); 7404 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7405 ins_pipe(ialu_reg_imm); 7406%} 7407 7408// Xor Instructions 7409// Register Xor 7410instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7411 match(Set dst (XorI src1 src2)); 7412 7413 size(4); 7414 format %{ "XOR $src1,$src2,$dst" %} 7415 opcode(Assembler::xor_op3, Assembler::arith_op); 7416 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7417 ins_pipe(ialu_reg_reg); 7418%} 7419 7420// Immediate Xor 7421instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7422 match(Set dst (XorI src1 src2)); 7423 7424 size(4); 7425 format %{ "XOR $src1,$src2,$dst" %} 7426 opcode(Assembler::xor_op3, Assembler::arith_op); 7427 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7428 ins_pipe(ialu_reg_imm); 7429%} 7430 7431// Register Xor Long 7432instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7433 match(Set dst (XorL src1 src2)); 7434 7435 ins_cost(DEFAULT_COST); 7436 size(4); 7437 format %{ "XOR $src1,$src2,$dst\t! long" %} 7438 opcode(Assembler::xor_op3, Assembler::arith_op); 7439 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7440 ins_pipe(ialu_reg_reg); 7441%} 7442 7443instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7444 match(Set dst (XorL src1 con)); 7445 7446 ins_cost(DEFAULT_COST); 7447 size(4); 7448 format %{ "XOR $src1,$con,$dst\t! long" %} 7449 opcode(Assembler::xor_op3, Assembler::arith_op); 7450 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7451 ins_pipe(ialu_reg_imm); 7452%} 7453 7454//----------Convert to Boolean------------------------------------------------- 7455// Nice hack for 32-bit tests but doesn't work for 7456// 64-bit pointers. 7457instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7458 match(Set dst (Conv2B src)); 7459 effect( KILL ccr ); 7460 ins_cost(DEFAULT_COST*2); 7461 format %{ "CMP R_G0,$src\n\t" 7462 "ADDX R_G0,0,$dst" %} 7463 ins_encode( enc_to_bool( src, dst ) ); 7464 ins_pipe(ialu_reg_ialu); 7465%} 7466 7467#ifndef _LP64 7468instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 7469 match(Set dst (Conv2B src)); 7470 effect( KILL ccr ); 7471 ins_cost(DEFAULT_COST*2); 7472 format %{ "CMP R_G0,$src\n\t" 7473 "ADDX R_G0,0,$dst" %} 7474 ins_encode( enc_to_bool( src, dst ) ); 7475 ins_pipe(ialu_reg_ialu); 7476%} 7477#else 7478instruct convP2B( iRegI dst, iRegP src ) %{ 7479 match(Set dst (Conv2B src)); 7480 ins_cost(DEFAULT_COST*2); 7481 format %{ "MOV $src,$dst\n\t" 7482 "MOVRNZ $src,1,$dst" %} 7483 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 7484 ins_pipe(ialu_clr_and_mover); 7485%} 7486#endif 7487 7488instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 7489 match(Set dst (CmpLTMask p q)); 7490 effect( KILL ccr ); 7491 ins_cost(DEFAULT_COST*4); 7492 format %{ "CMP $p,$q\n\t" 7493 "MOV #0,$dst\n\t" 7494 "BLT,a .+8\n\t" 7495 "MOV #-1,$dst" %} 7496 ins_encode( enc_ltmask(p,q,dst) ); 7497 ins_pipe(ialu_reg_reg_ialu); 7498%} 7499 7500instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7501 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 7502 effect(KILL ccr, TEMP tmp); 7503 ins_cost(DEFAULT_COST*3); 7504 7505 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7506 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7507 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7508 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 7509 ins_pipe( cadd_cmpltmask ); 7510%} 7511 7512instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7513 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); 7514 effect( KILL ccr, TEMP tmp); 7515 ins_cost(DEFAULT_COST*3); 7516 7517 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7518 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7519 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7520 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 7521 ins_pipe( cadd_cmpltmask ); 7522%} 7523 7524//----------Arithmetic Conversion Instructions--------------------------------- 7525// The conversions operations are all Alpha sorted. Please keep it that way! 7526 7527instruct convD2F_reg(regF dst, regD src) %{ 7528 match(Set dst (ConvD2F src)); 7529 size(4); 7530 format %{ "FDTOS $src,$dst" %} 7531 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 7532 ins_encode(form3_opf_rs2D_rdF(src, dst)); 7533 ins_pipe(fcvtD2F); 7534%} 7535 7536 7537// Convert a double to an int in a float register. 7538// If the double is a NAN, stuff a zero in instead. 7539instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 7540 effect(DEF dst, USE src, KILL fcc0); 7541 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7542 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7543 "FDTOI $src,$dst\t! convert in delay slot\n\t" 7544 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7545 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7546 "skip:" %} 7547 ins_encode(form_d2i_helper(src,dst)); 7548 ins_pipe(fcvtD2I); 7549%} 7550 7551instruct convD2I_reg(stackSlotI dst, regD src) %{ 7552 match(Set dst (ConvD2I src)); 7553 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7554 expand %{ 7555 regF tmp; 7556 convD2I_helper(tmp, src); 7557 regF_to_stkI(dst, tmp); 7558 %} 7559%} 7560 7561// Convert a double to a long in a double register. 7562// If the double is a NAN, stuff a zero in instead. 7563instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 7564 effect(DEF dst, USE src, KILL fcc0); 7565 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7566 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7567 "FDTOX $src,$dst\t! convert in delay slot\n\t" 7568 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 7569 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 7570 "skip:" %} 7571 ins_encode(form_d2l_helper(src,dst)); 7572 ins_pipe(fcvtD2L); 7573%} 7574 7575 7576// Double to Long conversion 7577instruct convD2L_reg(stackSlotL dst, regD src) %{ 7578 match(Set dst (ConvD2L src)); 7579 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7580 expand %{ 7581 regD tmp; 7582 convD2L_helper(tmp, src); 7583 regD_to_stkL(dst, tmp); 7584 %} 7585%} 7586 7587 7588instruct convF2D_reg(regD dst, regF src) %{ 7589 match(Set dst (ConvF2D src)); 7590 format %{ "FSTOD $src,$dst" %} 7591 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 7592 ins_encode(form3_opf_rs2F_rdD(src, dst)); 7593 ins_pipe(fcvtF2D); 7594%} 7595 7596 7597instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 7598 effect(DEF dst, USE src, KILL fcc0); 7599 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 7600 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7601 "FSTOI $src,$dst\t! convert in delay slot\n\t" 7602 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7603 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7604 "skip:" %} 7605 ins_encode(form_f2i_helper(src,dst)); 7606 ins_pipe(fcvtF2I); 7607%} 7608 7609instruct convF2I_reg(stackSlotI dst, regF src) %{ 7610 match(Set dst (ConvF2I src)); 7611 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7612 expand %{ 7613 regF tmp; 7614 convF2I_helper(tmp, src); 7615 regF_to_stkI(dst, tmp); 7616 %} 7617%} 7618 7619 7620instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 7621 effect(DEF dst, USE src, KILL fcc0); 7622 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 7623 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7624 "FSTOX $src,$dst\t! convert in delay slot\n\t" 7625 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 7626 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 7627 "skip:" %} 7628 ins_encode(form_f2l_helper(src,dst)); 7629 ins_pipe(fcvtF2L); 7630%} 7631 7632// Float to Long conversion 7633instruct convF2L_reg(stackSlotL dst, regF src) %{ 7634 match(Set dst (ConvF2L src)); 7635 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7636 expand %{ 7637 regD tmp; 7638 convF2L_helper(tmp, src); 7639 regD_to_stkL(dst, tmp); 7640 %} 7641%} 7642 7643 7644instruct convI2D_helper(regD dst, regF tmp) %{ 7645 effect(USE tmp, DEF dst); 7646 format %{ "FITOD $tmp,$dst" %} 7647 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 7648 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 7649 ins_pipe(fcvtI2D); 7650%} 7651 7652instruct convI2D_reg(stackSlotI src, regD dst) %{ 7653 match(Set dst (ConvI2D src)); 7654 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7655 expand %{ 7656 regF tmp; 7657 stkI_to_regF( tmp, src); 7658 convI2D_helper( dst, tmp); 7659 %} 7660%} 7661 7662instruct convI2D_mem( regD_low dst, memory mem ) %{ 7663 match(Set dst (ConvI2D (LoadI mem))); 7664 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7665 size(8); 7666 format %{ "LDF $mem,$dst\n\t" 7667 "FITOD $dst,$dst" %} 7668 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 7669 ins_encode( form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 7670 ins_pipe(floadF_mem); 7671%} 7672 7673 7674instruct convI2F_helper(regF dst, regF tmp) %{ 7675 effect(DEF dst, USE tmp); 7676 format %{ "FITOS $tmp,$dst" %} 7677 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 7678 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 7679 ins_pipe(fcvtI2F); 7680%} 7681 7682instruct convI2F_reg( regF dst, stackSlotI src ) %{ 7683 match(Set dst (ConvI2F src)); 7684 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7685 expand %{ 7686 regF tmp; 7687 stkI_to_regF(tmp,src); 7688 convI2F_helper(dst, tmp); 7689 %} 7690%} 7691 7692instruct convI2F_mem( regF dst, memory mem ) %{ 7693 match(Set dst (ConvI2F (LoadI mem))); 7694 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7695 size(8); 7696 format %{ "LDF $mem,$dst\n\t" 7697 "FITOS $dst,$dst" %} 7698 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 7699 ins_encode( form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 7700 ins_pipe(floadF_mem); 7701%} 7702 7703 7704instruct convI2L_reg(iRegL dst, iRegI src) %{ 7705 match(Set dst (ConvI2L src)); 7706 size(4); 7707 format %{ "SRA $src,0,$dst\t! int->long" %} 7708 opcode(Assembler::sra_op3, Assembler::arith_op); 7709 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 7710 ins_pipe(ialu_reg_reg); 7711%} 7712 7713// Zero-extend convert int to long 7714instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 7715 match(Set dst (AndL (ConvI2L src) mask) ); 7716 size(4); 7717 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 7718 opcode(Assembler::srl_op3, Assembler::arith_op); 7719 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 7720 ins_pipe(ialu_reg_reg); 7721%} 7722 7723// Zero-extend long 7724instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 7725 match(Set dst (AndL src mask) ); 7726 size(4); 7727 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 7728 opcode(Assembler::srl_op3, Assembler::arith_op); 7729 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 7730 ins_pipe(ialu_reg_reg); 7731%} 7732 7733instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 7734 match(Set dst (MoveF2I src)); 7735 effect(DEF dst, USE src); 7736 ins_cost(MEMORY_REF_COST); 7737 7738 size(4); 7739 format %{ "LDUW $src,$dst\t! MoveF2I" %} 7740 opcode(Assembler::lduw_op3); 7741 ins_encode( form3_mem_reg( src, dst ) ); 7742 ins_pipe(iload_mem); 7743%} 7744 7745instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 7746 match(Set dst (MoveI2F src)); 7747 effect(DEF dst, USE src); 7748 ins_cost(MEMORY_REF_COST); 7749 7750 size(4); 7751 format %{ "LDF $src,$dst\t! MoveI2F" %} 7752 opcode(Assembler::ldf_op3); 7753 ins_encode(form3_mem_reg(src, dst)); 7754 ins_pipe(floadF_stk); 7755%} 7756 7757instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 7758 match(Set dst (MoveD2L src)); 7759 effect(DEF dst, USE src); 7760 ins_cost(MEMORY_REF_COST); 7761 7762 size(4); 7763 format %{ "LDX $src,$dst\t! MoveD2L" %} 7764 opcode(Assembler::ldx_op3); 7765 ins_encode( form3_mem_reg( src, dst ) ); 7766 ins_pipe(iload_mem); 7767%} 7768 7769instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 7770 match(Set dst (MoveL2D src)); 7771 effect(DEF dst, USE src); 7772 ins_cost(MEMORY_REF_COST); 7773 7774 size(4); 7775 format %{ "LDDF $src,$dst\t! MoveL2D" %} 7776 opcode(Assembler::lddf_op3); 7777 ins_encode(form3_mem_reg(src, dst)); 7778 ins_pipe(floadD_stk); 7779%} 7780 7781instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 7782 match(Set dst (MoveF2I src)); 7783 effect(DEF dst, USE src); 7784 ins_cost(MEMORY_REF_COST); 7785 7786 size(4); 7787 format %{ "STF $src,$dst\t!MoveF2I" %} 7788 opcode(Assembler::stf_op3); 7789 ins_encode(form3_mem_reg(dst, src)); 7790 ins_pipe(fstoreF_stk_reg); 7791%} 7792 7793instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 7794 match(Set dst (MoveI2F src)); 7795 effect(DEF dst, USE src); 7796 ins_cost(MEMORY_REF_COST); 7797 7798 size(4); 7799 format %{ "STW $src,$dst\t!MoveI2F" %} 7800 opcode(Assembler::stw_op3); 7801 ins_encode( form3_mem_reg( dst, src ) ); 7802 ins_pipe(istore_mem_reg); 7803%} 7804 7805instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 7806 match(Set dst (MoveD2L src)); 7807 effect(DEF dst, USE src); 7808 ins_cost(MEMORY_REF_COST); 7809 7810 size(4); 7811 format %{ "STDF $src,$dst\t!MoveD2L" %} 7812 opcode(Assembler::stdf_op3); 7813 ins_encode(form3_mem_reg(dst, src)); 7814 ins_pipe(fstoreD_stk_reg); 7815%} 7816 7817instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 7818 match(Set dst (MoveL2D src)); 7819 effect(DEF dst, USE src); 7820 ins_cost(MEMORY_REF_COST); 7821 7822 size(4); 7823 format %{ "STX $src,$dst\t!MoveL2D" %} 7824 opcode(Assembler::stx_op3); 7825 ins_encode( form3_mem_reg( dst, src ) ); 7826 ins_pipe(istore_mem_reg); 7827%} 7828 7829 7830//----------- 7831// Long to Double conversion using V8 opcodes. 7832// Still useful because cheetah traps and becomes 7833// amazingly slow for some common numbers. 7834 7835// Magic constant, 0x43300000 7836instruct loadConI_x43300000(iRegI dst) %{ 7837 effect(DEF dst); 7838 size(4); 7839 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 7840 ins_encode(SetHi22(0x43300000, dst)); 7841 ins_pipe(ialu_none); 7842%} 7843 7844// Magic constant, 0x41f00000 7845instruct loadConI_x41f00000(iRegI dst) %{ 7846 effect(DEF dst); 7847 size(4); 7848 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 7849 ins_encode(SetHi22(0x41f00000, dst)); 7850 ins_pipe(ialu_none); 7851%} 7852 7853// Construct a double from two float halves 7854instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 7855 effect(DEF dst, USE src1, USE src2); 7856 size(8); 7857 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 7858 "FMOVS $src2.lo,$dst.lo" %} 7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 7860 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 7861 ins_pipe(faddD_reg_reg); 7862%} 7863 7864// Convert integer in high half of a double register (in the lower half of 7865// the double register file) to double 7866instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 7867 effect(DEF dst, USE src); 7868 size(4); 7869 format %{ "FITOD $src,$dst" %} 7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 7871 ins_encode(form3_opf_rs2D_rdD(src, dst)); 7872 ins_pipe(fcvtLHi2D); 7873%} 7874 7875// Add float double precision 7876instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 7877 effect(DEF dst, USE src1, USE src2); 7878 size(4); 7879 format %{ "FADDD $src1,$src2,$dst" %} 7880 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7881 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7882 ins_pipe(faddD_reg_reg); 7883%} 7884 7885// Sub float double precision 7886instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 7887 effect(DEF dst, USE src1, USE src2); 7888 size(4); 7889 format %{ "FSUBD $src1,$src2,$dst" %} 7890 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7891 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7892 ins_pipe(faddD_reg_reg); 7893%} 7894 7895// Mul float double precision 7896instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 7897 effect(DEF dst, USE src1, USE src2); 7898 size(4); 7899 format %{ "FMULD $src1,$src2,$dst" %} 7900 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7901 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7902 ins_pipe(fmulD_reg_reg); 7903%} 7904 7905instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 7906 match(Set dst (ConvL2D src)); 7907 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 7908 7909 expand %{ 7910 regD_low tmpsrc; 7911 iRegI ix43300000; 7912 iRegI ix41f00000; 7913 stackSlotL lx43300000; 7914 stackSlotL lx41f00000; 7915 regD_low dx43300000; 7916 regD dx41f00000; 7917 regD tmp1; 7918 regD_low tmp2; 7919 regD tmp3; 7920 regD tmp4; 7921 7922 stkL_to_regD(tmpsrc, src); 7923 7924 loadConI_x43300000(ix43300000); 7925 loadConI_x41f00000(ix41f00000); 7926 regI_to_stkLHi(lx43300000, ix43300000); 7927 regI_to_stkLHi(lx41f00000, ix41f00000); 7928 stkL_to_regD(dx43300000, lx43300000); 7929 stkL_to_regD(dx41f00000, lx41f00000); 7930 7931 convI2D_regDHi_regD(tmp1, tmpsrc); 7932 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 7933 subD_regD_regD(tmp3, tmp2, dx43300000); 7934 mulD_regD_regD(tmp4, tmp1, dx41f00000); 7935 addD_regD_regD(dst, tmp3, tmp4); 7936 %} 7937%} 7938 7939// Long to Double conversion using fast fxtof 7940instruct convL2D_helper(regD dst, regD tmp) %{ 7941 effect(DEF dst, USE tmp); 7942 size(4); 7943 format %{ "FXTOD $tmp,$dst" %} 7944 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 7945 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 7946 ins_pipe(fcvtL2D); 7947%} 7948 7949instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ 7950 predicate(VM_Version::has_fast_fxtof()); 7951 match(Set dst (ConvL2D src)); 7952 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 7953 expand %{ 7954 regD tmp; 7955 stkL_to_regD(tmp, src); 7956 convL2D_helper(dst, tmp); 7957 %} 7958%} 7959 7960//----------- 7961// Long to Float conversion using V8 opcodes. 7962// Still useful because cheetah traps and becomes 7963// amazingly slow for some common numbers. 7964 7965// Long to Float conversion using fast fxtof 7966instruct convL2F_helper(regF dst, regD tmp) %{ 7967 effect(DEF dst, USE tmp); 7968 size(4); 7969 format %{ "FXTOS $tmp,$dst" %} 7970 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 7971 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 7972 ins_pipe(fcvtL2F); 7973%} 7974 7975instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ 7976 match(Set dst (ConvL2F src)); 7977 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 7978 expand %{ 7979 regD tmp; 7980 stkL_to_regD(tmp, src); 7981 convL2F_helper(dst, tmp); 7982 %} 7983%} 7984//----------- 7985 7986instruct convL2I_reg(iRegI dst, iRegL src) %{ 7987 match(Set dst (ConvL2I src)); 7988#ifndef _LP64 7989 format %{ "MOV $src.lo,$dst\t! long->int" %} 7990 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 7991 ins_pipe(ialu_move_reg_I_to_L); 7992#else 7993 size(4); 7994 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 7995 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 7996 ins_pipe(ialu_reg); 7997#endif 7998%} 7999 8000// Register Shift Right Immediate 8001instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8002 match(Set dst (ConvL2I (RShiftL src cnt))); 8003 8004 size(4); 8005 format %{ "SRAX $src,$cnt,$dst" %} 8006 opcode(Assembler::srax_op3, Assembler::arith_op); 8007 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8008 ins_pipe(ialu_reg_imm); 8009%} 8010 8011// Replicate scalar to packed byte values in Double register 8012instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8013 effect(DEF dst, USE src); 8014 format %{ "SLLX $src,56,$dst\n\t" 8015 "SRLX $dst, 8,O7\n\t" 8016 "OR $dst,O7,$dst\n\t" 8017 "SRLX $dst,16,O7\n\t" 8018 "OR $dst,O7,$dst\n\t" 8019 "SRLX $dst,32,O7\n\t" 8020 "OR $dst,O7,$dst\t! replicate8B" %} 8021 ins_encode( enc_repl8b(src, dst)); 8022 ins_pipe(ialu_reg); 8023%} 8024 8025// Replicate scalar to packed byte values in Double register 8026instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8027 match(Set dst (Replicate8B src)); 8028 expand %{ 8029 iRegL tmp; 8030 Repl8B_reg_helper(tmp, src); 8031 regL_to_stkD(dst, tmp); 8032 %} 8033%} 8034 8035// Replicate scalar constant to packed byte values in Double register 8036instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ 8037 match(Set dst (Replicate8B src)); 8038#ifdef _LP64 8039 size(36); 8040#else 8041 size(8); 8042#endif 8043 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" 8044 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} 8045 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); 8046 ins_pipe(loadConFD); 8047%} 8048 8049// Replicate scalar to packed char values into stack slot 8050instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8051 effect(DEF dst, USE src); 8052 format %{ "SLLX $src,48,$dst\n\t" 8053 "SRLX $dst,16,O7\n\t" 8054 "OR $dst,O7,$dst\n\t" 8055 "SRLX $dst,32,O7\n\t" 8056 "OR $dst,O7,$dst\t! replicate4C" %} 8057 ins_encode( enc_repl4s(src, dst) ); 8058 ins_pipe(ialu_reg); 8059%} 8060 8061// Replicate scalar to packed char values into stack slot 8062instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8063 match(Set dst (Replicate4C src)); 8064 expand %{ 8065 iRegL tmp; 8066 Repl4C_reg_helper(tmp, src); 8067 regL_to_stkD(dst, tmp); 8068 %} 8069%} 8070 8071// Replicate scalar constant to packed char values in Double register 8072instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ 8073 match(Set dst (Replicate4C src)); 8074#ifdef _LP64 8075 size(36); 8076#else 8077 size(8); 8078#endif 8079 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" 8080 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8081 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8082 ins_pipe(loadConFD); 8083%} 8084 8085// Replicate scalar to packed short values into stack slot 8086instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8087 effect(DEF dst, USE src); 8088 format %{ "SLLX $src,48,$dst\n\t" 8089 "SRLX $dst,16,O7\n\t" 8090 "OR $dst,O7,$dst\n\t" 8091 "SRLX $dst,32,O7\n\t" 8092 "OR $dst,O7,$dst\t! replicate4S" %} 8093 ins_encode( enc_repl4s(src, dst) ); 8094 ins_pipe(ialu_reg); 8095%} 8096 8097// Replicate scalar to packed short values into stack slot 8098instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8099 match(Set dst (Replicate4S src)); 8100 expand %{ 8101 iRegL tmp; 8102 Repl4S_reg_helper(tmp, src); 8103 regL_to_stkD(dst, tmp); 8104 %} 8105%} 8106 8107// Replicate scalar constant to packed short values in Double register 8108instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ 8109 match(Set dst (Replicate4S src)); 8110#ifdef _LP64 8111 size(36); 8112#else 8113 size(8); 8114#endif 8115 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" 8116 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8117 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8118 ins_pipe(loadConFD); 8119%} 8120 8121// Replicate scalar to packed int values in Double register 8122instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8123 effect(DEF dst, USE src); 8124 format %{ "SLLX $src,32,$dst\n\t" 8125 "SRLX $dst,32,O7\n\t" 8126 "OR $dst,O7,$dst\t! replicate2I" %} 8127 ins_encode( enc_repl2i(src, dst)); 8128 ins_pipe(ialu_reg); 8129%} 8130 8131// Replicate scalar to packed int values in Double register 8132instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8133 match(Set dst (Replicate2I src)); 8134 expand %{ 8135 iRegL tmp; 8136 Repl2I_reg_helper(tmp, src); 8137 regL_to_stkD(dst, tmp); 8138 %} 8139%} 8140 8141// Replicate scalar zero constant to packed int values in Double register 8142instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ 8143 match(Set dst (Replicate2I src)); 8144#ifdef _LP64 8145 size(36); 8146#else 8147 size(8); 8148#endif 8149 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" 8150 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} 8151 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); 8152 ins_pipe(loadConFD); 8153%} 8154 8155//----------Control Flow Instructions------------------------------------------ 8156// Compare Instructions 8157// Compare Integers 8158instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8159 match(Set icc (CmpI op1 op2)); 8160 effect( DEF icc, USE op1, USE op2 ); 8161 8162 size(4); 8163 format %{ "CMP $op1,$op2" %} 8164 opcode(Assembler::subcc_op3, Assembler::arith_op); 8165 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8166 ins_pipe(ialu_cconly_reg_reg); 8167%} 8168 8169instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8170 match(Set icc (CmpU op1 op2)); 8171 8172 size(4); 8173 format %{ "CMP $op1,$op2\t! unsigned" %} 8174 opcode(Assembler::subcc_op3, Assembler::arith_op); 8175 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8176 ins_pipe(ialu_cconly_reg_reg); 8177%} 8178 8179instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8180 match(Set icc (CmpI op1 op2)); 8181 effect( DEF icc, USE op1 ); 8182 8183 size(4); 8184 format %{ "CMP $op1,$op2" %} 8185 opcode(Assembler::subcc_op3, Assembler::arith_op); 8186 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8187 ins_pipe(ialu_cconly_reg_imm); 8188%} 8189 8190instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8191 match(Set icc (CmpI (AndI op1 op2) zero)); 8192 8193 size(4); 8194 format %{ "BTST $op2,$op1" %} 8195 opcode(Assembler::andcc_op3, Assembler::arith_op); 8196 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8197 ins_pipe(ialu_cconly_reg_reg_zero); 8198%} 8199 8200instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8201 match(Set icc (CmpI (AndI op1 op2) zero)); 8202 8203 size(4); 8204 format %{ "BTST $op2,$op1" %} 8205 opcode(Assembler::andcc_op3, Assembler::arith_op); 8206 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8207 ins_pipe(ialu_cconly_reg_imm_zero); 8208%} 8209 8210instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8211 match(Set xcc (CmpL op1 op2)); 8212 effect( DEF xcc, USE op1, USE op2 ); 8213 8214 size(4); 8215 format %{ "CMP $op1,$op2\t\t! long" %} 8216 opcode(Assembler::subcc_op3, Assembler::arith_op); 8217 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8218 ins_pipe(ialu_cconly_reg_reg); 8219%} 8220 8221instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8222 match(Set xcc (CmpL op1 con)); 8223 effect( DEF xcc, USE op1, USE con ); 8224 8225 size(4); 8226 format %{ "CMP $op1,$con\t\t! long" %} 8227 opcode(Assembler::subcc_op3, Assembler::arith_op); 8228 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8229 ins_pipe(ialu_cconly_reg_reg); 8230%} 8231 8232instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8233 match(Set xcc (CmpL (AndL op1 op2) zero)); 8234 effect( DEF xcc, USE op1, USE op2 ); 8235 8236 size(4); 8237 format %{ "BTST $op1,$op2\t\t! long" %} 8238 opcode(Assembler::andcc_op3, Assembler::arith_op); 8239 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8240 ins_pipe(ialu_cconly_reg_reg); 8241%} 8242 8243// useful for checking the alignment of a pointer: 8244instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8245 match(Set xcc (CmpL (AndL op1 con) zero)); 8246 effect( DEF xcc, USE op1, USE con ); 8247 8248 size(4); 8249 format %{ "BTST $op1,$con\t\t! long" %} 8250 opcode(Assembler::andcc_op3, Assembler::arith_op); 8251 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8252 ins_pipe(ialu_cconly_reg_reg); 8253%} 8254 8255instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8256 match(Set icc (CmpU op1 op2)); 8257 8258 size(4); 8259 format %{ "CMP $op1,$op2\t! unsigned" %} 8260 opcode(Assembler::subcc_op3, Assembler::arith_op); 8261 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8262 ins_pipe(ialu_cconly_reg_imm); 8263%} 8264 8265// Compare Pointers 8266instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8267 match(Set pcc (CmpP op1 op2)); 8268 8269 size(4); 8270 format %{ "CMP $op1,$op2\t! ptr" %} 8271 opcode(Assembler::subcc_op3, Assembler::arith_op); 8272 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8273 ins_pipe(ialu_cconly_reg_reg); 8274%} 8275 8276instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8277 match(Set pcc (CmpP op1 op2)); 8278 8279 size(4); 8280 format %{ "CMP $op1,$op2\t! ptr" %} 8281 opcode(Assembler::subcc_op3, Assembler::arith_op); 8282 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8283 ins_pipe(ialu_cconly_reg_imm); 8284%} 8285 8286// Compare Narrow oops 8287instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8288 match(Set icc (CmpN op1 op2)); 8289 8290 size(4); 8291 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8292 opcode(Assembler::subcc_op3, Assembler::arith_op); 8293 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8294 ins_pipe(ialu_cconly_reg_reg); 8295%} 8296 8297instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8298 match(Set icc (CmpN op1 op2)); 8299 8300 size(4); 8301 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8302 opcode(Assembler::subcc_op3, Assembler::arith_op); 8303 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8304 ins_pipe(ialu_cconly_reg_imm); 8305%} 8306 8307//----------Max and Min-------------------------------------------------------- 8308// Min Instructions 8309// Conditional move for min 8310instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8311 effect( USE_DEF op2, USE op1, USE icc ); 8312 8313 size(4); 8314 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8315 opcode(Assembler::less); 8316 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8317 ins_pipe(ialu_reg_flags); 8318%} 8319 8320// Min Register with Register. 8321instruct minI_eReg(iRegI op1, iRegI op2) %{ 8322 match(Set op2 (MinI op1 op2)); 8323 ins_cost(DEFAULT_COST*2); 8324 expand %{ 8325 flagsReg icc; 8326 compI_iReg(icc,op1,op2); 8327 cmovI_reg_lt(op2,op1,icc); 8328 %} 8329%} 8330 8331// Max Instructions 8332// Conditional move for max 8333instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8334 effect( USE_DEF op2, USE op1, USE icc ); 8335 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8336 opcode(Assembler::greater); 8337 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8338 ins_pipe(ialu_reg_flags); 8339%} 8340 8341// Max Register with Register 8342instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8343 match(Set op2 (MaxI op1 op2)); 8344 ins_cost(DEFAULT_COST*2); 8345 expand %{ 8346 flagsReg icc; 8347 compI_iReg(icc,op1,op2); 8348 cmovI_reg_gt(op2,op1,icc); 8349 %} 8350%} 8351 8352 8353//----------Float Compares---------------------------------------------------- 8354// Compare floating, generate condition code 8355instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8356 match(Set fcc (CmpF src1 src2)); 8357 8358 size(4); 8359 format %{ "FCMPs $fcc,$src1,$src2" %} 8360 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8361 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8362 ins_pipe(faddF_fcc_reg_reg_zero); 8363%} 8364 8365instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8366 match(Set fcc (CmpD src1 src2)); 8367 8368 size(4); 8369 format %{ "FCMPd $fcc,$src1,$src2" %} 8370 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8371 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8372 ins_pipe(faddD_fcc_reg_reg_zero); 8373%} 8374 8375 8376// Compare floating, generate -1,0,1 8377instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8378 match(Set dst (CmpF3 src1 src2)); 8379 effect(KILL fcc0); 8380 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8381 format %{ "fcmpl $dst,$src1,$src2" %} 8382 // Primary = float 8383 opcode( true ); 8384 ins_encode( floating_cmp( dst, src1, src2 ) ); 8385 ins_pipe( floating_cmp ); 8386%} 8387 8388instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8389 match(Set dst (CmpD3 src1 src2)); 8390 effect(KILL fcc0); 8391 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8392 format %{ "dcmpl $dst,$src1,$src2" %} 8393 // Primary = double (not float) 8394 opcode( false ); 8395 ins_encode( floating_cmp( dst, src1, src2 ) ); 8396 ins_pipe( floating_cmp ); 8397%} 8398 8399//----------Branches--------------------------------------------------------- 8400// Jump 8401// (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8402instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8403 match(Jump switch_val); 8404 8405 ins_cost(350); 8406 8407 format %{ "SETHI [hi(table_base)],O7\n\t" 8408 "ADD O7, lo(table_base), O7\n\t" 8409 "LD [O7+$switch_val], O7\n\t" 8410 "JUMP O7" 8411 %} 8412 ins_encode( jump_enc( switch_val, table) ); 8413 ins_pc_relative(1); 8414 ins_pipe(ialu_reg_reg); 8415%} 8416 8417// Direct Branch. Use V8 version with longer range. 8418instruct branch(label labl) %{ 8419 match(Goto); 8420 effect(USE labl); 8421 8422 size(8); 8423 ins_cost(BRANCH_COST); 8424 format %{ "BA $labl" %} 8425 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond 8426 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); 8427 ins_encode( enc_ba( labl ) ); 8428 ins_pc_relative(1); 8429 ins_pipe(br); 8430%} 8431 8432// Conditional Direct Branch 8433instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8434 match(If cmp icc); 8435 effect(USE labl); 8436 8437 size(8); 8438 ins_cost(BRANCH_COST); 8439 format %{ "BP$cmp $icc,$labl" %} 8440 // Prim = bits 24-22, Secnd = bits 31-30 8441 ins_encode( enc_bp( labl, cmp, icc ) ); 8442 ins_pc_relative(1); 8443 ins_pipe(br_cc); 8444%} 8445 8446// Branch-on-register tests all 64 bits. We assume that values 8447// in 64-bit registers always remains zero or sign extended 8448// unless our code munges the high bits. Interrupts can chop 8449// the high order bits to zero or sign at any time. 8450instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 8451 match(If cmp (CmpI op1 zero)); 8452 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8453 effect(USE labl); 8454 8455 size(8); 8456 ins_cost(BRANCH_COST); 8457 format %{ "BR$cmp $op1,$labl" %} 8458 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8459 ins_pc_relative(1); 8460 ins_pipe(br_reg); 8461%} 8462 8463instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 8464 match(If cmp (CmpP op1 null)); 8465 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8466 effect(USE labl); 8467 8468 size(8); 8469 ins_cost(BRANCH_COST); 8470 format %{ "BR$cmp $op1,$labl" %} 8471 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8472 ins_pc_relative(1); 8473 ins_pipe(br_reg); 8474%} 8475 8476instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 8477 match(If cmp (CmpL op1 zero)); 8478 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8479 effect(USE labl); 8480 8481 size(8); 8482 ins_cost(BRANCH_COST); 8483 format %{ "BR$cmp $op1,$labl" %} 8484 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8485 ins_pc_relative(1); 8486 ins_pipe(br_reg); 8487%} 8488 8489instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8490 match(If cmp icc); 8491 effect(USE labl); 8492 8493 format %{ "BP$cmp $icc,$labl" %} 8494 // Prim = bits 24-22, Secnd = bits 31-30 8495 ins_encode( enc_bp( labl, cmp, icc ) ); 8496 ins_pc_relative(1); 8497 ins_pipe(br_cc); 8498%} 8499 8500instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 8501 match(If cmp pcc); 8502 effect(USE labl); 8503 8504 size(8); 8505 ins_cost(BRANCH_COST); 8506 format %{ "BP$cmp $pcc,$labl" %} 8507 // Prim = bits 24-22, Secnd = bits 31-30 8508 ins_encode( enc_bpx( labl, cmp, pcc ) ); 8509 ins_pc_relative(1); 8510 ins_pipe(br_cc); 8511%} 8512 8513instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 8514 match(If cmp fcc); 8515 effect(USE labl); 8516 8517 size(8); 8518 ins_cost(BRANCH_COST); 8519 format %{ "FBP$cmp $fcc,$labl" %} 8520 // Prim = bits 24-22, Secnd = bits 31-30 8521 ins_encode( enc_fbp( labl, cmp, fcc ) ); 8522 ins_pc_relative(1); 8523 ins_pipe(br_fcc); 8524%} 8525 8526instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 8527 match(CountedLoopEnd cmp icc); 8528 effect(USE labl); 8529 8530 size(8); 8531 ins_cost(BRANCH_COST); 8532 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8533 // Prim = bits 24-22, Secnd = bits 31-30 8534 ins_encode( enc_bp( labl, cmp, icc ) ); 8535 ins_pc_relative(1); 8536 ins_pipe(br_cc); 8537%} 8538 8539instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8540 match(CountedLoopEnd cmp icc); 8541 effect(USE labl); 8542 8543 size(8); 8544 ins_cost(BRANCH_COST); 8545 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8546 // Prim = bits 24-22, Secnd = bits 31-30 8547 ins_encode( enc_bp( labl, cmp, icc ) ); 8548 ins_pc_relative(1); 8549 ins_pipe(br_cc); 8550%} 8551 8552// ============================================================================ 8553// Long Compare 8554// 8555// Currently we hold longs in 2 registers. Comparing such values efficiently 8556// is tricky. The flavor of compare used depends on whether we are testing 8557// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 8558// The GE test is the negated LT test. The LE test can be had by commuting 8559// the operands (yielding a GE test) and then negating; negate again for the 8560// GT test. The EQ test is done by ORcc'ing the high and low halves, and the 8561// NE test is negated from that. 8562 8563// Due to a shortcoming in the ADLC, it mixes up expressions like: 8564// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 8565// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 8566// are collapsed internally in the ADLC's dfa-gen code. The match for 8567// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 8568// foo match ends up with the wrong leaf. One fix is to not match both 8569// reg-reg and reg-zero forms of long-compare. This is unfortunate because 8570// both forms beat the trinary form of long-compare and both are very useful 8571// on Intel which has so few registers. 8572 8573instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 8574 match(If cmp xcc); 8575 effect(USE labl); 8576 8577 size(8); 8578 ins_cost(BRANCH_COST); 8579 format %{ "BP$cmp $xcc,$labl" %} 8580 // Prim = bits 24-22, Secnd = bits 31-30 8581 ins_encode( enc_bpl( labl, cmp, xcc ) ); 8582 ins_pc_relative(1); 8583 ins_pipe(br_cc); 8584%} 8585 8586// Manifest a CmpL3 result in an integer register. Very painful. 8587// This is the test to avoid. 8588instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 8589 match(Set dst (CmpL3 src1 src2) ); 8590 effect( KILL ccr ); 8591 ins_cost(6*DEFAULT_COST); 8592 size(24); 8593 format %{ "CMP $src1,$src2\t\t! long\n" 8594 "\tBLT,a,pn done\n" 8595 "\tMOV -1,$dst\t! delay slot\n" 8596 "\tBGT,a,pn done\n" 8597 "\tMOV 1,$dst\t! delay slot\n" 8598 "\tCLR $dst\n" 8599 "done:" %} 8600 ins_encode( cmpl_flag(src1,src2,dst) ); 8601 ins_pipe(cmpL_reg); 8602%} 8603 8604// Conditional move 8605instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 8606 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 8607 ins_cost(150); 8608 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 8609 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8610 ins_pipe(ialu_reg); 8611%} 8612 8613instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 8614 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 8615 ins_cost(140); 8616 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 8617 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 8618 ins_pipe(ialu_imm); 8619%} 8620 8621instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 8622 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 8623 ins_cost(150); 8624 format %{ "MOV$cmp $xcc,$src,$dst" %} 8625 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8626 ins_pipe(ialu_reg); 8627%} 8628 8629instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 8630 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 8631 ins_cost(140); 8632 format %{ "MOV$cmp $xcc,$src,$dst" %} 8633 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 8634 ins_pipe(ialu_imm); 8635%} 8636 8637instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 8638 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 8639 ins_cost(150); 8640 format %{ "MOV$cmp $xcc,$src,$dst" %} 8641 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8642 ins_pipe(ialu_reg); 8643%} 8644 8645instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 8646 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 8647 ins_cost(150); 8648 format %{ "MOV$cmp $xcc,$src,$dst" %} 8649 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 8650 ins_pipe(ialu_reg); 8651%} 8652 8653instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 8654 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 8655 ins_cost(140); 8656 format %{ "MOV$cmp $xcc,$src,$dst" %} 8657 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 8658 ins_pipe(ialu_imm); 8659%} 8660 8661instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 8662 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 8663 ins_cost(150); 8664 opcode(0x101); 8665 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 8666 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 8667 ins_pipe(int_conditional_float_move); 8668%} 8669 8670instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 8671 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 8672 ins_cost(150); 8673 opcode(0x102); 8674 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 8675 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 8676 ins_pipe(int_conditional_float_move); 8677%} 8678 8679// ============================================================================ 8680// Safepoint Instruction 8681instruct safePoint_poll(iRegP poll) %{ 8682 match(SafePoint poll); 8683 effect(USE poll); 8684 8685 size(4); 8686#ifdef _LP64 8687 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 8688#else 8689 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 8690#endif 8691 ins_encode %{ 8692 __ relocate(relocInfo::poll_type); 8693 __ ld_ptr($poll$$Register, 0, G0); 8694 %} 8695 ins_pipe(loadPollP); 8696%} 8697 8698// ============================================================================ 8699// Call Instructions 8700// Call Java Static Instruction 8701instruct CallStaticJavaDirect( method meth ) %{ 8702 match(CallStaticJava); 8703 effect(USE meth); 8704 8705 size(8); 8706 ins_cost(CALL_COST); 8707 format %{ "CALL,static ; NOP ==> " %} 8708 ins_encode( Java_Static_Call( meth ), call_epilog ); 8709 ins_pc_relative(1); 8710 ins_pipe(simple_call); 8711%} 8712 8713// Call Java Dynamic Instruction 8714instruct CallDynamicJavaDirect( method meth ) %{ 8715 match(CallDynamicJava); 8716 effect(USE meth); 8717 8718 ins_cost(CALL_COST); 8719 format %{ "SET (empty),R_G5\n\t" 8720 "CALL,dynamic ; NOP ==> " %} 8721 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 8722 ins_pc_relative(1); 8723 ins_pipe(call); 8724%} 8725 8726// Call Runtime Instruction 8727instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 8728 match(CallRuntime); 8729 effect(USE meth, KILL l7); 8730 ins_cost(CALL_COST); 8731 format %{ "CALL,runtime" %} 8732 ins_encode( Java_To_Runtime( meth ), 8733 call_epilog, adjust_long_from_native_call ); 8734 ins_pc_relative(1); 8735 ins_pipe(simple_call); 8736%} 8737 8738// Call runtime without safepoint - same as CallRuntime 8739instruct CallLeafDirect(method meth, l7RegP l7) %{ 8740 match(CallLeaf); 8741 effect(USE meth, KILL l7); 8742 ins_cost(CALL_COST); 8743 format %{ "CALL,runtime leaf" %} 8744 ins_encode( Java_To_Runtime( meth ), 8745 call_epilog, 8746 adjust_long_from_native_call ); 8747 ins_pc_relative(1); 8748 ins_pipe(simple_call); 8749%} 8750 8751// Call runtime without safepoint - same as CallLeaf 8752instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 8753 match(CallLeafNoFP); 8754 effect(USE meth, KILL l7); 8755 ins_cost(CALL_COST); 8756 format %{ "CALL,runtime leaf nofp" %} 8757 ins_encode( Java_To_Runtime( meth ), 8758 call_epilog, 8759 adjust_long_from_native_call ); 8760 ins_pc_relative(1); 8761 ins_pipe(simple_call); 8762%} 8763 8764// Tail Call; Jump from runtime stub to Java code. 8765// Also known as an 'interprocedural jump'. 8766// Target of jump will eventually return to caller. 8767// TailJump below removes the return address. 8768instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 8769 match(TailCall jump_target method_oop ); 8770 8771 ins_cost(CALL_COST); 8772 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 8773 ins_encode(form_jmpl(jump_target)); 8774 ins_pipe(tail_call); 8775%} 8776 8777 8778// Return Instruction 8779instruct Ret() %{ 8780 match(Return); 8781 8782 // The epilogue node did the ret already. 8783 size(0); 8784 format %{ "! return" %} 8785 ins_encode(); 8786 ins_pipe(empty); 8787%} 8788 8789 8790// Tail Jump; remove the return address; jump to target. 8791// TailCall above leaves the return address around. 8792// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 8793// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 8794// "restore" before this instruction (in Epilogue), we need to materialize it 8795// in %i0. 8796instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 8797 match( TailJump jump_target ex_oop ); 8798 ins_cost(CALL_COST); 8799 format %{ "! discard R_O7\n\t" 8800 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 8801 ins_encode(form_jmpl_set_exception_pc(jump_target)); 8802 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 8803 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 8804 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 8805 ins_pipe(tail_call); 8806%} 8807 8808// Create exception oop: created by stack-crawling runtime code. 8809// Created exception is now available to this handler, and is setup 8810// just prior to jumping to this handler. No code emitted. 8811instruct CreateException( o0RegP ex_oop ) 8812%{ 8813 match(Set ex_oop (CreateEx)); 8814 ins_cost(0); 8815 8816 size(0); 8817 // use the following format syntax 8818 format %{ "! exception oop is in R_O0; no code emitted" %} 8819 ins_encode(); 8820 ins_pipe(empty); 8821%} 8822 8823 8824// Rethrow exception: 8825// The exception oop will come in the first argument position. 8826// Then JUMP (not call) to the rethrow stub code. 8827instruct RethrowException() 8828%{ 8829 match(Rethrow); 8830 ins_cost(CALL_COST); 8831 8832 // use the following format syntax 8833 format %{ "Jmp rethrow_stub" %} 8834 ins_encode(enc_rethrow); 8835 ins_pipe(tail_call); 8836%} 8837 8838 8839// Die now 8840instruct ShouldNotReachHere( ) 8841%{ 8842 match(Halt); 8843 ins_cost(CALL_COST); 8844 8845 size(4); 8846 // Use the following format syntax 8847 format %{ "ILLTRAP ; ShouldNotReachHere" %} 8848 ins_encode( form2_illtrap() ); 8849 ins_pipe(tail_call); 8850%} 8851 8852// ============================================================================ 8853// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 8854// array for an instance of the superklass. Set a hidden internal cache on a 8855// hit (cache is checked with exposed code in gen_subtype_check()). Return 8856// not zero for a miss or zero for a hit. The encoding ALSO sets flags. 8857instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 8858 match(Set index (PartialSubtypeCheck sub super)); 8859 effect( KILL pcc, KILL o7 ); 8860 ins_cost(DEFAULT_COST*10); 8861 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 8862 ins_encode( enc_PartialSubtypeCheck() ); 8863 ins_pipe(partial_subtype_check_pipe); 8864%} 8865 8866instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 8867 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 8868 effect( KILL idx, KILL o7 ); 8869 ins_cost(DEFAULT_COST*10); 8870 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 8871 ins_encode( enc_PartialSubtypeCheck() ); 8872 ins_pipe(partial_subtype_check_pipe); 8873%} 8874 8875 8876// ============================================================================ 8877// inlined locking and unlocking 8878 8879instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 8880 match(Set pcc (FastLock object box)); 8881 8882 effect(KILL scratch, TEMP scratch2); 8883 ins_cost(100); 8884 8885 size(4*112); // conservative overestimation ... 8886 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 8887 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 8888 ins_pipe(long_memory_op); 8889%} 8890 8891 8892instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 8893 match(Set pcc (FastUnlock object box)); 8894 effect(KILL scratch, TEMP scratch2); 8895 ins_cost(100); 8896 8897 size(4*120); // conservative overestimation ... 8898 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 8899 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 8900 ins_pipe(long_memory_op); 8901%} 8902 8903// Count and Base registers are fixed because the allocator cannot 8904// kill unknown registers. The encodings are generic. 8905instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 8906 match(Set dummy (ClearArray cnt base)); 8907 effect(TEMP temp, KILL ccr); 8908 ins_cost(300); 8909 format %{ "MOV $cnt,$temp\n" 8910 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 8911 " BRge loop\t\t! Clearing loop\n" 8912 " STX G0,[$base+$temp]\t! delay slot" %} 8913 ins_encode( enc_Clear_Array(cnt, base, temp) ); 8914 ins_pipe(long_memory_op); 8915%} 8916 8917instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, 8918 o7RegI tmp3, flagsReg ccr) %{ 8919 match(Set result (StrComp str1 str2)); 8920 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); 8921 ins_cost(300); 8922 format %{ "String Compare $str1,$str2 -> $result" %} 8923 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) ); 8924 ins_pipe(long_memory_op); 8925%} 8926 8927// ============================================================================ 8928//------------Bytes reverse-------------------------------------------------- 8929 8930instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 8931 match(Set dst (ReverseBytesI src)); 8932 effect(DEF dst, USE src); 8933 8934 // Op cost is artificially doubled to make sure that load or store 8935 // instructions are preferred over this one which requires a spill 8936 // onto a stack slot. 8937 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 8938 size(8); 8939 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 8940 opcode(Assembler::lduwa_op3); 8941 ins_encode( form3_mem_reg_little(src, dst) ); 8942 ins_pipe( iload_mem ); 8943%} 8944 8945instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 8946 match(Set dst (ReverseBytesL src)); 8947 effect(DEF dst, USE src); 8948 8949 // Op cost is artificially doubled to make sure that load or store 8950 // instructions are preferred over this one which requires a spill 8951 // onto a stack slot. 8952 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 8953 size(8); 8954 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 8955 8956 opcode(Assembler::ldxa_op3); 8957 ins_encode( form3_mem_reg_little(src, dst) ); 8958 ins_pipe( iload_mem ); 8959%} 8960 8961// Load Integer reversed byte order 8962instruct loadI_reversed(iRegI dst, memory src) %{ 8963 match(Set dst (ReverseBytesI (LoadI src))); 8964 8965 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8966 size(8); 8967 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 8968 8969 opcode(Assembler::lduwa_op3); 8970 ins_encode( form3_mem_reg_little( src, dst) ); 8971 ins_pipe(iload_mem); 8972%} 8973 8974// Load Long - aligned and reversed 8975instruct loadL_reversed(iRegL dst, memory src) %{ 8976 match(Set dst (ReverseBytesL (LoadL src))); 8977 8978 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8979 size(8); 8980 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 8981 8982 opcode(Assembler::ldxa_op3); 8983 ins_encode( form3_mem_reg_little( src, dst ) ); 8984 ins_pipe(iload_mem); 8985%} 8986 8987// Store Integer reversed byte order 8988instruct storeI_reversed(memory dst, iRegI src) %{ 8989 match(Set dst (StoreI dst (ReverseBytesI src))); 8990 8991 ins_cost(MEMORY_REF_COST); 8992 size(8); 8993 format %{ "STWA $src, $dst\t!asi=primary_little" %} 8994 8995 opcode(Assembler::stwa_op3); 8996 ins_encode( form3_mem_reg_little( dst, src) ); 8997 ins_pipe(istore_mem_reg); 8998%} 8999 9000// Store Long reversed byte order 9001instruct storeL_reversed(memory dst, iRegL src) %{ 9002 match(Set dst (StoreL dst (ReverseBytesL src))); 9003 9004 ins_cost(MEMORY_REF_COST); 9005 size(8); 9006 format %{ "STXA $src, $dst\t!asi=primary_little" %} 9007 9008 opcode(Assembler::stxa_op3); 9009 ins_encode( form3_mem_reg_little( dst, src) ); 9010 ins_pipe(istore_mem_reg); 9011%} 9012 9013//----------PEEPHOLE RULES----------------------------------------------------- 9014// These must follow all instruction definitions as they use the names 9015// defined in the instructions definitions. 9016// 9017// peepmatch ( root_instr_name [preceeding_instruction]* ); 9018// 9019// peepconstraint %{ 9020// (instruction_number.operand_name relational_op instruction_number.operand_name 9021// [, ...] ); 9022// // instruction numbers are zero-based using left to right order in peepmatch 9023// 9024// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 9025// // provide an instruction_number.operand_name for each operand that appears 9026// // in the replacement instruction's match rule 9027// 9028// ---------VM FLAGS--------------------------------------------------------- 9029// 9030// All peephole optimizations can be turned off using -XX:-OptoPeephole 9031// 9032// Each peephole rule is given an identifying number starting with zero and 9033// increasing by one in the order seen by the parser. An individual peephole 9034// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 9035// on the command-line. 9036// 9037// ---------CURRENT LIMITATIONS---------------------------------------------- 9038// 9039// Only match adjacent instructions in same basic block 9040// Only equality constraints 9041// Only constraints between operands, not (0.dest_reg == EAX_enc) 9042// Only one replacement instruction 9043// 9044// ---------EXAMPLE---------------------------------------------------------- 9045// 9046// // pertinent parts of existing instructions in architecture description 9047// instruct movI(eRegI dst, eRegI src) %{ 9048// match(Set dst (CopyI src)); 9049// %} 9050// 9051// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 9052// match(Set dst (AddI dst src)); 9053// effect(KILL cr); 9054// %} 9055// 9056// // Change (inc mov) to lea 9057// peephole %{ 9058// // increment preceeded by register-register move 9059// peepmatch ( incI_eReg movI ); 9060// // require that the destination register of the increment 9061// // match the destination register of the move 9062// peepconstraint ( 0.dst == 1.dst ); 9063// // construct a replacement instruction that sets 9064// // the destination to ( move's source register + one ) 9065// peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 9066// %} 9067// 9068 9069// // Change load of spilled value to only a spill 9070// instruct storeI(memory mem, eRegI src) %{ 9071// match(Set mem (StoreI mem src)); 9072// %} 9073// 9074// instruct loadI(eRegI dst, memory mem) %{ 9075// match(Set dst (LoadI mem)); 9076// %} 9077// 9078// peephole %{ 9079// peepmatch ( loadI storeI ); 9080// peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 9081// peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 9082// %} 9083 9084//----------SMARTSPILL RULES--------------------------------------------------- 9085// These must follow all instruction definitions as they use the names 9086// defined in the instructions definitions. 9087// 9088// SPARC will probably not have any of these rules due to RISC instruction set. 9089 9090//----------PIPELINE----------------------------------------------------------- 9091// Rules which define the behavior of the target architectures pipeline. 9092